Display device and electronic device

Abstract

A display device and an electronic device are provided, the display device comprising: a base substrate including a display area and a non-display area positioned at a side of the display area; at least one transistor and a wire, the at least one transistor being located in the display area of ​​the base substrate, and the wire being located in the non-display area of ​​the base substrate; at least one light-emitting element being located in the display area and coupled to the at least one transistor; an encapsulation layer covering the light-emitting element; a sensing electrode and a sensing line, the sensing electrode being located on the encapsulation layer, and the sensing line being located on the encapsulation layer and coupled to the sensing electrode; and an alignment mark being located on the encapsulation layer and at least partially overlapping with some of the wires in the non-display area in a plan view.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0056485, filed on May 14, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0002] The present invention relates generally to a display device and, more particularly, to a display device having alignment marks to facilitate assembly of layers of the device during manufacturing. Background Art

[0003] The display device may include a display panel on which an image is displayed, and a window disposed on the display panel to protect the display panel.

[0004] In order to identify the position of the display panel in a process of coupling the window to the display panel, the display panel includes an alignment mark for position recognition.

[0005] Such an alignment mark is disposed in a non-display region (ie, a region in which an image is not displayed) of a display panel, and an ineffective area may occur in the non-display region due to design limitations of the alignment mark.

[0006] Recently, there has been an increasing demand for reducing the size of a bezel corresponding to a non-display area and maximizing the available space for a display area of ​​a display panel. Therefore, a great deal of research has been conducted on various schemes for minimizing an ineffective area due to an alignment mark.

[0007] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0008] Applicants have recognized that by adjusting the spacing of the signal lines relative to the alignment marks, the amount of dead space in the non-display area of ​​the display device can be minimized.

[0009] Electronic devices and display devices constructed according to the principles and exemplary embodiments of the invention have reduced dead zones in the border area surrounding the display area. The reduced dead zones can be achieved by positioning the alignment marks to overlap at least some of the outermost lines or to be disposed adjacent to the outermost lines. The outermost lines can have reduced density (pitch) to allow greater light transmittance.

[0010] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0011] According to one aspect of the invention, a display device includes: a base substrate including a display area and a non-display area positioned at a side of the display area; at least one transistor and a wire, the at least one transistor is located in the display area of ​​the base substrate, and the wire is located in the non-display area of ​​the base substrate; at least one light-emitting element is located in the display area and is coupled to the at least one transistor; an encapsulation layer covering the light-emitting element; a sensing electrode and a sensing line, the sensing electrode is located on the encapsulation layer, and the sensing line is located on the encapsulation layer and is coupled to the sensing electrode; and an alignment mark is located on the encapsulation layer and at least partially overlaps with some of the wires in the non-display area in a plan view.

[0012] Some of the conductive lines may be disposed in a first region of the base substrate, the remaining conductive lines may be disposed in a second region of the base substrate, and transmittance at the first region may be higher than transmittance at the second region.

[0013] The spacing between some of the conductive lines may be larger than the spacing between the remaining conductive lines.

[0014] In a plan view, a shortest distance from one of the conductive lines to an edge of the base substrate may be shorter than a shortest distance from the alignment mark to an edge of the base substrate.

[0015] The alignment mark may include alignment patterns, the alignment patterns may be spaced apart from each other, and adjacent alignment patterns may have different planar shapes.

[0016] The alignment patterns may be arranged sequentially along a first direction, a length of each of the alignment patterns in the first direction may be greater than a width of each of the alignment patterns in a second direction, the second direction may be substantially perpendicular to the first direction, and a spacing between the alignment patterns in the first direction may be less than a length.

[0017] The length in the first direction may be in the range of about 100 μm to about 500 μm, and the width in the second direction may be in the range of about 30 μm to about 150 μm.

[0018] The length in the first direction may be approximately 3 to 6 times the width in the second direction.

[0019] One of the alignment patterns may have a substantially rectangular planar shape, and the other of the alignment patterns may have a substantially triangular planar shape.

[0020] The alignment mark may include first, second, and third alignment patterns that are sequentially arranged, and the first and third alignment patterns may have substantially the same planar shape.

[0021] Some of the conductive lines may include a crack detection line extending along an edge of the display area, and the crack detection line may be electrically isolated from the at least one transistor.

[0022] A side surface of the display device may form an acute angle with a line substantially parallel to a thickness direction of the base substrate.

[0023] The at least one transistor may include: a semiconductor pattern disposed on a base substrate; a gate electrode on and overlapping the semiconductor pattern; a first insulating layer on the gate electrode; and a source electrode and a drain electrode on the first insulating layer.

[0024] Some of the conductive lines may be provided on the same layer as the gate electrode.

[0025] Some of the wires may be provided on the same layer as the source electrode and the drain electrode.

[0026] The alignment mark may include sub-alignment marks, and the sub-alignment marks may be separated from each other and disposed in different layers.

[0027] The alignment mark may be closer to the edge of the base substrate than the conductive line.

[0028] According to another aspect of the invention, a display device includes: a base substrate including a display area and a non-display area positioned at a side of the display area; at least one transistor and a wire, the at least one transistor is located in the display area of ​​the base substrate, and the wire is arranged in the non-display area of ​​the base substrate; at least one light emitting element is located in the display area and is coupled to the at least one transistor; an encapsulation layer covering the light emitting element; a sensing electrode and a sensing line, the sensing electrode is located on the encapsulation layer, the sensing line is located on the encapsulation layer and is coupled to the sensing electrode; and an alignment mark is located on the encapsulation layer and is arranged to be adjacent to the wire at a distance smaller than the spacing between the wires.

[0029] According to other aspects of the invention, an electronic device includes: a base substrate; a semiconductor pattern disposed on the base substrate; a first conductive pattern disposed on the semiconductor pattern; a first insulating layer disposed on the first conductive pattern; and a second conductive pattern disposed on the first insulating layer, wherein one of the first conductive pattern and the second conductive pattern includes an alignment mark, wherein the alignment mark at least partially overlaps with at least one conductive pattern of the other conductive pattern among the first conductive pattern and the second conductive pattern.

[0030] The alignment mark may be included in the first conductive pattern, and the alignment mark may overlap at least one of the second conductive patterns.

[0031] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the inventive concept. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification.

[0033] Figure 1 is a perspective view showing an exemplary embodiment of a display device constructed according to the principles of the invention.

[0034] Figure 2 It is shown Figure 1 1 is an exploded perspective view of an exemplary embodiment of a display device.

[0035] Figure 3 It is shown that the Figure 2 FIG. 1 is a plan view of an exemplary embodiment of a display module in a display device of FIG. 1 .

[0036] Figure 4A and Figure 4B It is shown Figure 3 sectional view of an exemplary embodiment of a display module.

[0037] Figure 5 It is shown that the Figure 4A FIG. 1 is a plan view of an exemplary embodiment of a display unit in a display module.

[0038] Figure 6 It is shown Figure 5 An exemplary embodiment of a sensing unit in a display module of FIG. 1 and includes a plan view of an enlarged portion.

[0039] Figure 7 is a diagram showing a display module Figure 6 FIG. 1 is a plan view of an exemplary embodiment in which the first detection area is enlarged.

[0040] Figure 8 is used to explain the Figure 2 An exploded perspective view of an exemplary process of aligning a display module and a window with each other in a display device.

[0041] Fig. 9 It is shown by shooting Figure 7 A plan view of an exemplary embodiment of an image obtained in the first detection area.

[0042] Fig.10 is a diagram showing a display module Figure 6 FIG. 1 is a plan view of an exemplary embodiment in which the first detection area is enlarged.

[0043] Fig.11 It is shown along Figure 22 is a cross-sectional view of an exemplary embodiment of a display module taken along line AA′.

[0044] Figures 12 to 15 It is shown along Figure 2 2 is a cross-sectional view of various exemplary embodiments of a display module taken along line AA′.

[0045] Fig.16 It is shown along Figure 2 FIG. 1 is a cross-sectional view of another exemplary embodiment of a display module taken along line AA′.

[0046] Fig.17 It is shown Fig.16 1 is a plan view of an exemplary embodiment of a display module.

[0047] Fig.18 It is shown along Figure 2 FIG. 1 is a cross-sectional view of another exemplary embodiment of a display module taken along line AA′.

[0048] Fig.19 It is shown Fig.18 1 is a plan view of an exemplary embodiment of a display module.

[0049] Fig. 20 It is shown that the Figure 2 FIG. 1 is a plan view of another exemplary embodiment of a display module in a display device of FIG. 1 .

[0050] Fig.21 It is shown Fig. 20 sectional view of an exemplary embodiment of a display module.

[0051] Fig. 22 It is shown Fig. 20 sectional view of an exemplary embodiment of a display module. DETAILED DESCRIPTION

[0052] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments or implementations of the invention. "Embodiment" and "implementation" as used herein are interchangeable words as non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid making various exemplary embodiments unnecessarily obscure. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, construction and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0053] Unless otherwise specified, the illustrated exemplary embodiments will be understood as providing exemplary features of the details of variations of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, exchanged and / or rearranged without departing from the inventive concept.

[0054] The use of cross hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments may be implemented differently, a specific process sequence may be performed in a sequence different from that described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to that described. In addition, the same reference numerals represent the same elements.

[0055] When an element or layer is referred to as being "on", "connected to" or "bonded to" another element or layer, the element or layer may be directly on, directly connected to or directly bonded to the other element or layer, or there may be intermediate elements or layers. However, when an element or layer is referred to as being "directly on", "directly connected to" or "directly bonded to" another element or layer, there are no intermediate elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without intermediate elements. In addition, the DR1 axis, the DR2 axis and the DR3 axis are not limited to three axes of a rectangular coordinate system such as the x-axis, the y-axis and the z-axis, but may be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis and the DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ for example. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0056] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be named a second element without departing from the disclosed teachings.

[0057] For descriptive purposes, spatially relative terms such as "under," "below," "below," "down," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein and thereby describe the relationship of one element to another (or multiple) elements as shown in the accompanying drawings. Spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements or features would subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "under" can include both above and below orientations. In addition, the device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein are interpreted accordingly.

[0058] The terms used here are for the purpose of describing specific embodiments, and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one (kind / person)" and "said / the" as used here are also intended to include plural forms. In addition, when the terms "comprising", "including" and / or its variations are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, elements, components and / or their groups, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It is also noted that, as used here, the terms "substantially", "about" and other similar terms are used as approximate terms and not as degree terms, and are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0059] Various exemplary embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected to occur. Therefore, the exemplary embodiments disclosed herein should not necessarily be interpreted as limitations on the shapes of the specifically illustrated regions, but will include deviations in shape due to, for example, manufacturing. In this manner, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and as such, are not necessarily intended to be limiting.

[0060] As used herein, the terms “display device” and “electronic device” may be used interchangeably, may refer to different versions of the exemplary embodiments disclosed herein, and may have layers defined by different ordinal numbers.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which this disclosure is a part. Unless explicitly defined as such herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an ideal or overly formal sense.

[0062] Figure 1 is a perspective view showing an exemplary embodiment of a display device constructed according to the principles of the invention.

[0063] Reference Figure 1 , the display device 1 can display an image. The display device 1 may be a portable terminal such as a tablet PC, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a game console, or a wristwatch-type electronic device. However, the type of the display device 1 is not limited thereto. For example, the display device 1 may be a large electronic device such as a TV or an outdoor billboard or a small or medium-sized electronic device such as a personal computer, a notebook computer, a vehicle navigation device, or a camera.

[0064] The display device 1 may have a substantially planar rectangular shape. The display device 1 may include two long sides (eg, a first long side LS1 and a second long side LS2) and two short sides (eg, a first short side SS1 and a second short side SS2). Figure 1 As shown in FIG, the angle where the long sides LS1 and LS2 of the display device 1 meet the short sides SS1 and SS2 can be maintained at a right angle, but a curved surface can also be formed. The substantially planar shape of the display device 1 is not limited to the illustrated shape, but can be a substantially circular shape or any other shape.

[0065] Figure 2 It is shown Figure 1 1 is an exploded perspective view of an exemplary embodiment of a display device.

[0066] Reference Figure 2 The display device 1 may include a display module 10 , a functional module 20 and a window (or window module) 30 .

[0067] The display module 10 may display an image. For example, the display module 10 may be an organic light emitting display panel. Hereinafter, a case where the display module 10 is an organic light emitting display panel is exemplified, but the display module of the exemplary embodiment is not limited thereto. For example, the display module 10 may be another type of display panel such as a liquid crystal display panel, an electrophoretic display panel, or a plasma display panel.

[0068] In addition, the display module 10 can sense touch input. Figure 3 A detailed configuration of the display module 10 is described.

[0069] The display module 10 may include a display area DA and a non-display area NDA. The display area DA may be defined as a portion in which an image is displayed and the non-display area NDA may be defined as a portion in which an image is not displayed.

[0070] The display area DA may be disposed in (or located at) a central portion of the display module 10 and may be larger than the non-display area NDA. In the display area DA, a plurality of pixels PXL (see FIG. 1 ) to be described later may be arranged. Figure 5 ). The display area DA may have a substantially rectangular shape or a rectangular shape with rounded corners. However, the shape of the display area DA is not limited thereto, and the display area DA may have various shapes such as a substantially square shape, a substantially polygonal shape, a substantially circular shape, or a substantially elliptical shape. In addition, the display area DA may include a plurality of sub-display areas spaced apart from each other.

[0071] The non-display area NDA may be disposed on at least one side of the display area DA or around the display area DA. The non-display area NDA may be an area extending from the outer edge of the display area DA to the boundary (or edge) of the display module 10. A signal line or a driving circuit for applying a signal to the display area DA (or the pixel PXL arranged in the display area DA) may be disposed in the non-display area NDA. In addition, the outermost black matrix may be disposed in the non-display area NDA.

[0072] In addition, the display module 10 may include a main region MR, a bending region BR, and a sub-region SR. The main region MR may include a display region DA and may form a display surface of the display device 1. The bending region BR may extend from the main region MR in a first direction DR1 and may be bendable. The sub-region SR may extend from the bending region BR and may overlap with the main region MR according to a bending state of the bending region BR.

[0073] Later, we will refer to Figure 2 The cross-sectional view taken along the line A-A' Fig.11 The detailed configuration of the display module 10 will be described.

[0074] Unless otherwise defined, the terms "upper", "top" or "top surface" here refer to the display surface on which the display module 10 displays an image, and the terms "lower", "bottom" or "bottom surface" may refer to the side of the display module 10 facing away from the display surface.

[0075] The functional module 20 may be disposed on top of the display module 10. The functional module 20 may include at least one functional layer. The functional layer may be a layer on which a color filter function, a color conversion function, a polarization function, etc. are performed. The functional layer may be implemented as a sheet layer formed by a sheet, a film layer formed by a film, a thin film layer, a coating layer, a panel or a plate. A single functional layer may be constructed using a single layer, or may be constructed using a plurality of stacked thin films or coating layers. For example, the functional layer may be a color filter, an optical film, etc. The functional module 20 may be omitted.

[0076] The window 30 may be provided on the top of the functional module 20 (or the display module 10). The window 30 may overlap the display module 10 and substantially cover the entire surface of the display module 10. The window 30 may be larger than the display module 10. For example, on the two short sides SS1 and SS2 of the display device 1, the window 30 may protrude outward from the display module 10. Even on the two long sides LS1 and LS2 of the display device 1, the window 30 may protrude from the display module 10. The window 30 may protrude from the two long sides LS1 and LS2 of the display device 1, and may also protrude from the two short sides SS1 and SS2 of the display module 10.

[0077] The window 30 may include a central portion and a shielding pattern. The central portion may overlap the display area DA of the display module 10 to transmit light emitted from the display area DA. The shielding pattern may be located on a boundary of the window 30. The shielding pattern may overlap the non-display area NDA of the display module 10 and may prevent the non-display area NDA from being perceived.

[0078] The functional module 20 and the window 30 may be bonded to the display module 10 by an optically clear adhesive (OCA) or an optically clear resin (OCR).

[0079] Figure 3 It is shown that the Figure 2 FIG. 1 is a plan view of an exemplary embodiment of a display module in a display device of FIG. 1 .

[0080] Reference Figure 3 , the display module 10 may include one or more alignment marks AM (or alignment marks, alignment keys).

[0081] The alignment mark AM may be used as an identification mark for alignment during a process for attaching the window 30 (or the functional module 20, OCA, or OCR) to the display module 10. In addition, the alignment mark AM may be used in a process for checking the result of laser cutting (or checking a cut portion of the display module 10 resulting from laser cutting performed on the display module 10 having a substantially planar shape) after the display module 10 coupled to the window 30 has been cut with a laser beam. In addition, the alignment mark AM may be used to define a frame of the display module 10 (or the display device 1).

[0082] The alignment mark AM may be disposed in the non-display area NDA of the display module 10 .

[0083] In an embodiment, the non-display area NDA may include first to fourth detection areas AMA1 to AMA4 respectively based on four corners of the display area DA, and the alignment mark AM may include first to fourth alignment marks AM1 to AM4 respectively disposed in the first to fourth detection areas AMA1 to AMA4. For example, the first detection area AMA1 may be disposed adjacent to an upper portion of the first long side LS1, and the first alignment mark AM1 may be disposed in the first detection area AMA1. The second detection area AMA2 may be disposed adjacent to a lower portion of the first long side LS1, and the second alignment mark AM2 may be disposed in the second detection area AMA2. The third and fourth detection areas AMA3 and AMA4 may be disposed on the second long side LS2 to be symmetrical with the first and second detection areas AMA1 and AMA2 with respect to the display area DA, and the third and fourth alignment marks AM3 and AM4 may be disposed in the third and fourth detection areas AMA3 and AMA4, respectively.

[0084] In an embodiment, the non-display area NDA may further include fifth to tenth detection areas AMA5 to AMA10, and the alignment mark AM may include fifth to tenth alignment marks AM5 to AM10 respectively disposed in the fifth to tenth detection areas AMA5 to AMA10. For example, the fifth and sixth detection areas AMA5 and AMA6 may be disposed adjacent to the first short side SS1, the seventh and eighth detection areas AMA7 and AMA8 may be disposed at the left / right edge of the sub-area SR in which the drive circuit (e.g., the drive integrated circuit D_IC) is disposed, and the ninth and tenth detection areas AMA9 and AMA10 may be disposed in a portion adjacent to the bending area BR among portions of the main area MR. The fifth to tenth alignment marks AM5 to AM10 may be disposed in the fifth to tenth detection areas AMA5 to AMA10, respectively. The fifth to tenth alignment marks AM5 to AM10 may be used to check the width of the invalid area (e.g., the distance from the fifth to tenth alignment marks AM5 to AM10 to the edge of the display module 10) after the process of laser cutting for the display module 10 has been performed.

[0085] Since the first to tenth alignment marks AM1 to AM10 are substantially the same as or similar to one another, the first alignment mark AM1 will be described as a representative alignment mark among the first to tenth alignment marks AM1 to AM10.

[0086] In an embodiment, the first alignment mark AM1 may include alignment patterns AMP1, AMP2, and AMP3. For example, the first alignment mark AM1 may be sequentially arranged along the first direction DR1 and may include first to third alignment patterns AMP1 to AMP3 spaced apart from each other.

[0087] As will be described later, two adjacent patterns among the first to third alignment patterns AMP1 to AMP3 can be used as identification marks for alignment. For example, when the first alignment pattern AMP1 and the second alignment pattern AMP2 are used as identification marks but do not function properly, the second alignment pattern AMP2 and the third alignment pattern AMP3 (or the first alignment pattern AMP1 and the third alignment pattern AMP3) can be used as identification marks.

[0088] In an embodiment, among the first to third alignment patterns AMP1 to AMP3, adjacent alignment patterns may have different planar shapes. Figure 7 The plane shapes of the first to third alignment patterns AMP1 to AMP3 are described in detail.

[0089] Each of the fifth alignment mark AM5 and the sixth alignment mark AM6 may include three alignment patterns sequentially arranged in the second direction DR2, each of the seventh alignment mark AM7 and the eighth alignment mark AM8 may include two alignment patterns, and each of the ninth alignment mark AM9 and the tenth alignment mark AM10 may include a single alignment mark. That is, considering the function of the alignment mark AM (e.g., an identification mark for alignment, an identification mark for defining a frame, etc.), each of the first alignment mark AM1 to the tenth alignment mark AM10 may include various numbers of alignment patterns.

[0090] In an embodiment, the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 may be made of an opaque material (e.g., metal). For example, when light is irradiated to the first detection area AMA1 in a direction from the bottom of the display module 10 to the top of the display module 10, the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 block the light, so that shadows (or shadow images) of the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 are generated, and thus the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 can be identified based on the shadow images. This will be referred to later. Figure 8 A configuration for identifying the first to third alignment patterns AMP1 to AMP3 is described in detail.

[0091] Figure 4A and Figure 4B It is shown Figure 3 sectional view of an exemplary embodiment of a display module.

[0092] Reference Figure 4A , the display module 10 may include a base substrate SUB (or substrate), a display unit DISP, and a sensing unit TSP.

[0093] The base substrate SUB may be made of an insulating material such as glass or resin. The base substrate SUB may be made of a material having flexibility to be bendable or foldable, and may have a single-layer structure or a multi-layer structure.

[0094] The display unit DISP may be formed on the base substrate SUB. The display unit DISP may include pixels PXL (see FIG. 1 ) disposed in a display area DA of the base substrate SUB. Figure 5) and lines DLS (or signal lines) disposed in the non-display area NDA of the base substrate SUB. The pixel PXL may include a light emitting element and at least one transistor coupled to the light emitting element to provide a driving current to the light emitting element, and at least some of the lines DLS may be directly / indirectly coupled to the pixel PXL and may transmit a required driving signal to drive the pixel PXL (or transistor).

[0095] The sensing unit TSP may be disposed on the display unit DISP, and may include a sensing electrode disposed in the display area DA (or sensing area), a sensing line disposed in the non-display area NDA (or non-sensing area) and coupled to the sensing electrode, and an alignment mark AM. For example, the sensing unit TSP may sense an external touch input, etc., by using a capacitive sensing technology using the sensing electrode, in which case the sensing unit TSP may be specifically referred to as a touch sensing unit.

[0096] The sensing unit TSP may be integrated with the display unit DISP. That is, the sensing unit TSP may be directly formed on the display unit DISP, and a separate adhesive layer (eg, OCR, OCA, etc.) may not be interposed between the display unit DISP and the sensing unit TSP.

[0097] As mentioned above Figure 3 As described, the align mark AM may be disposed in the non-display area NDA, and may overlap some of the lines DLS in the display unit DISP.

[0098] Although in Figure 4A In the description, the sensing unit TSP has been described as being integrated with the display unit DISP, but exemplary embodiments are not limited thereto.

[0099] Reference Figure 4B , another exemplary embodiment of the display module 10_0 may further include an adhesive layer ADH, and the sensing unit TSP may be bonded to the display unit DISP through the adhesive layer ADH. For example, the display unit DISP and the sensing unit TSP may both be implemented as panels and may be manufactured independently of each other, and the sensing unit TSP may be attached to the display unit DISP through the adhesive layer ADH (e.g., OCA). In addition to the presence of the adhesive layer ADH, the display module 10_0 may be Figure 4A The display modules 10 are substantially the same or similar. Therefore, repeated descriptions thereof will be omitted to avoid redundancy.

[0100] Figure 5 It is shown that the Figure 4A A plan view of an exemplary embodiment of a display unit in a display module of FIG. Figure 5 Based on the above reference Figure 4A The depicted line DLS schematically illustrates the display unit DISP.

[0101] Reference Figures 3 to 5 , the lines DLS may be arranged to be spaced apart from each other at a constant or variable pitch (interval) along an edge of the display area DA (or an edge of the display module) in the non-display area NDA. At least some of the lines DLS may be electrically coupled to a driving integrated circuit ("IC") D_IC, but exemplary embodiments are not limited thereto.

[0102] In an embodiment, the line DLS may include a signal line DL and detection lines (or referred to as crack detection lines) MCD1 and MCD2.

[0103] In an embodiment, the line DLS may include a first detection line MCD1 and a second detection line MCD2. In a plan view, the first detection line MCD1 may extend along an edge of the display device 1 and may be disposed to be closest to one side edge of the display device 1 among the line DLS. Similarly, in a plan view, the second detection line MCD2 may extend along an edge of the display device 1 and may be disposed to be closest to the other side edge of the display device 1 among the line DLS. The first detection line MCD1 and the second detection line MCD2 may be electrically isolated from the pixel PXL and may be electrically coupled to the drive IC D_IC, but exemplary embodiments are not limited thereto.

[0104] The first detection line MCD1 and the second detection line MCD2 may be fault detection lines (i.e., module crack detection lines) for detecting faults (e.g., line cracks) in the display device 1, may be disposed in the outermost portion of the display device 1 in a plan view, and may have a line width narrower than that of other lines (e.g., the signal line DL).

[0105] Although the display unit DISP Figure 5 2 and 3. In the embodiment of the present invention, the display unit DISP is shown as including two detection lines MCD1 and MCD2, but the exemplary embodiment of the display unit DISP is not limited thereto. For example, the display unit DISP may have five or more detection lines on one side of the display unit DISP, wherein attenuation of the detected signal can be mitigated and the location of the fault area in the display unit DISP can be detected.

[0106] The signal line DL may extend from the driving IC D_IC along at least a portion of an edge of the display area DA, may be coupled to the pixel PXL, and may transmit a driving signal required for driving of the pixel PXL.

[0107] Although the signal line DL Figure 5, but this structure is only exemplary, and exemplary embodiments are not limited thereto. For example, the display unit DISP may include a scan driver (or a scan drive circuit including a shift register) disposed on the left and right sides of the display unit DISP and configured to sequentially generate scan signals, wherein the signal line DL is coupled to the scan driver and is capable of transmitting a clock signal.

[0108] Figure 6 It is shown that the Figure 5 For ease of description, Figure 6 The alignment mark AM is shown as included in the above reference Figure 3 Representative first to fourth alignment marks AM1 to AM4 among the first to tenth alignment marks AM1 to AM10 are described.

[0109] Reference Figure 3 , Figure 4A and Figure 6 The sensing unit TSP may include a sensing area SA and a non-sensing area NSA. The sensing area SA may correspond to the display area DA of the display device 1 (or the display module 10 or the base substrate SUB), and the non-sensing area NSA may correspond to the non-display area NDA of the display device 1 .

[0110] In the sensing area SA, the sensing electrode TE may be arranged, and the non-sensing area NSA may include a sensing line SL, a pad (or pad) unit PD, and an alignment mark AM.

[0111] The sensing electrode TE may include a first sensing electrode TE1 and a second sensing electrode TE2. The first sensing electrode TE1 and the second sensing electrode TE2 may be arranged alternately (or by turns), and may be coupled in different directions, respectively.

[0112] The first sensing electrodes TE1 may be arranged in a matrix, may be electrically coupled to each other along the second direction DR2, and may constitute sensing electrode rows substantially parallel to each other. In one sensing electrode row, each of the first sensing electrodes TE1 may be electrically coupled to an adjacent sensing electrode through a first connection pattern CNP1 (or bridge pattern).

[0113] The second sensing electrodes TE2 may be arranged in a matrix, may be electrically coupled to each other along the first direction DR1, and may constitute sensing electrode columns substantially parallel to each other. In one sensing electrode column, each of the second sensing electrodes TE2 may be electrically coupled to an adjacent sensing electrode through a second connection pattern CNP2.

[0114] Each of the first sensing electrode TE1 (or sensing electrode row) and the second sensing electrode TE2 (or sensing electrode column) may be electrically coupled to a sensing pad included in the pad unit PD through a sensing line SL.

[0115] In an embodiment, each of the connection patterns CNP1 and CNP2 and the sensing electrode TE may include a plurality of fine wires. For example, as enlarged and shown in the area EA, each of the connection patterns CNP1 and CNP2 and the sensing electrode TE may include a plurality of first fine wires extending in one direction and substantially parallel to each other and a plurality of second fine wires extending in a direction crossing the first fine wires and substantially parallel to each other. In an embodiment, each of the connection patterns CNP1 and CNP2 and the sensing electrode TE may have a mesh structure.

[0116] The sensing line SL may electrically couple the sensing electrode TE to the driving circuit. The sensing line SL may transmit a sensing input signal from the driving circuit to the sensing electrode TE or transmit a sensing output signal from the sensing electrode TE to the driving circuit.

[0117] As mentioned above Figure 3 As described, the alignment mark AM may include alignment marks AM1 to AM4 arranged in the corresponding inspection areas AMA1 to AMA4.

[0118] The first alignment mark AM1 (or each of the first to fourth alignment marks AM1 to AM4) may include a first alignment pattern AMP1, a second alignment pattern AMP2 and a third alignment pattern AMP3, and the first alignment pattern AMP1, the second alignment pattern AMP2 and the third alignment pattern AMP3 may be positioned independently of each other like island patterns, may be spaced apart from the sensing line SL, may be electrically isolated from the sensing line SL, or may be insulated from the sensing line SL.

[0119] The first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 may be arranged in the outermost portion of the non-sensing area NSA (or the non-display area NDA) of the sensing unit TSP. For example, the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 of the first alignment mark AM1 may be arranged closer to the first side of the sensing unit TSP (e.g., the first long side LS1 of the display module 10, see FIG. 1 ) than the sensing line SL. Figure 3 )’s outermost edge.

[0120] Figure 7 is a diagram showing a display module Figure 6 A plan view of an exemplary embodiment in which the first detection area is enlarged. Figure 7, the display module 10 is briefly shown based on the alignment mark AM and the line DLS set in the first detection area AMA1. Since the first detection area AMA1 to the fourth detection area AMA4 (or the first detection area AMA1 to the tenth detection area AMA10) are Figure 3 ) may be substantially the same or similar to the relationship between the alignment mark AM and the line DLS in the first detection area AMA1, so the following description based on the first detection area AMA1 is representative of the first to fourth detection areas AMA1 to AMA4.

[0121] Reference FIG. 4A to FIG. 7 , the lines DLS may include first to eighth lines DL1 to DL8 which may extend along the first direction DR1 and be arranged to be spaced apart from each other along the second direction DR2 (or the horizontal direction).

[0122] In an embodiment, the display device 1 may include a first area A1 in which some of the lines DLS are disposed and a second area A2 in which the remaining lines other than the lines of the first area A1 are disposed, wherein the transmittance (i.e., light transmittance) of the first area A1 may be higher than the transmittance of the second area A2. The alignment mark AM may overlap with the first area A1 in a plan view. For example, the lines DLS may include first lines DLS1 (e.g., first lines DL1 to fifth lines DL5) disposed in the first area A1 and second lines DLS2 (e.g., sixth lines DL6 to eighth lines DL8) disposed in the second area A2. Here, at least some of the first lines DLS1 may be the lines described above with reference to Figure 5 The first detection line MCD1 is described.

[0123] In an embodiment, the first interval D1 between the first lines DLS1 (i.e., some lines in the lines DLS and lines adjacent thereto) may be larger than the second interval D2 between the second lines DLS2 (i.e., the remaining lines in the lines DLS). For example, the first interval D1 between the fourth line DL4 and the fifth line DL5 among the first lines DLS1 may be larger than the second interval D2 between the sixth line DL6 and the seventh line DL7 among the second lines DLS2. For example, the second interval D2 may be 2 μm or less, and the first interval D1 may be about 20 μm to about 30 μm. That is, the wiring density of the first line DLS1 in the first area A1 may be lower than the wiring density of the second line DLS2 in the second area A2. Since the lines DLS may be made of an opaque material (e.g., a metal material) that reflects or absorbs light, the transmittance of the first area A1 may be different from the transmittance of the second area A2 according to the different intervals of the lines DLS.

[0124] In an example, the line width of the first line DLS1 may be smaller than the line width of the second line DLS2. Even if the wiring density (or number of lines) of the first line DLS1 in the first area A1 is equal to the wiring density (or number of lines) of the second line DLS2 in the second area A2, the transmittance of the first area A1 may be increased according to the line width of the first line DLS1.

[0125] Since the transmittance of the first area A1 is relatively large (eg, 90% or more), the alignment mark AM overlapped with the first line DLS1 in the first area A1 can be aligned by an alignment device (eg, a visual camera VCM, see Figure 8 ) is recognized.

[0126] The alignment mark AM may include a first alignment pattern AMP1, a second alignment pattern AMP2, and a third alignment pattern AMP3, wherein the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 may be arranged to be spaced apart from each other along the first direction DR1, and may overlap with at least some of the first lines DLS1. For example, the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 may overlap with the second line DL2 and the third line DL3, but they are not limited thereto.

[0127] In the embodiment, in a plan view, from one of the lines DLS to the display module 10 (or base substrate SUB, see Figure 4A ) may be shorter than the first shortest distance WD1 from the alignment mark AM to the edge of the display module 10 (or the base substrate SUB, see Figure 4A ). For example, the first shortest distance WD1 from the first line DL1 arranged in the outermost part among the lines DLS to the first long side LS1 of the display module 10 (or the edge EDGE of the display module 10) may be smaller than the second shortest distance WD2 from the alignment mark AM (or the first alignment pattern AMP1) to the first long side LS1 of the display module 10 (or the edge EDGE of the display module 10). However, exemplary embodiments are not limited thereto. For example, in a range in which the alignment mark AM overlaps with the first line DLS1, the first shortest distance WD1 may be equal to the second shortest distance WD2, or may be greater than the second shortest distance WD2.

[0128] In an embodiment, among the first, second, and third alignment patterns AMP1, AMP2, and AMP3, adjacent alignment patterns may have different plane shapes.

[0129] For example, the first alignment pattern AMP1 may have a substantially rectangular planar shape (or a substantially elongated strip shape), and the second alignment pattern AMP2 adjacent to the first alignment pattern AMP1 may have a substantially triangular planar shape. Similarly, the third alignment pattern AMP3 adjacent to the second alignment pattern AMP2 may have a substantially rectangular planar shape. The third alignment pattern AMP3 may have a substantially planar shape that is the same as the planar shape of the first alignment pattern AMP1. The alignment system (or visual camera VCM) that recognizes the alignment mark AM may detect the position of the display module 10 based on the first alignment pattern AMP1 and the second alignment pattern AMP2, and may also detect the position of the display module 10 based on the second alignment pattern AMP2 and the third alignment pattern AMP3. However, when all of the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 have substantially the same shape, an error may occur in determining whether the two detected alignment patterns are the first alignment pattern AMP1 and the second alignment pattern AMP2 or the second alignment pattern AMP2 and the third alignment pattern AMP3, and therefore two adjacent patterns among the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 may have different planar shapes.

[0130] However, the planar shapes of the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 are not limited thereto. For example, the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 may have various planar shapes (such as, approximately semicircular shape, approximately trapezoidal shape, approximately "C" shape, approximately "L" shape, and approximately star shape), and may have different planar shapes.

[0131] In an embodiment, the lengths L1, L2, and L3 of the first, second, and third alignment patterns AMP1, AMP2, and AMP3 in the first direction DR1 may be greater than the width W1 of each alignment pattern in the second direction DR2. In addition, in the first direction DR1, the intervals GAP1 and GAP2 between the first, second, and third alignment patterns AMP1, AMP2, and AMP3 may be smaller than the lengths L1, L2, and L3 of the alignment patterns.

[0132] In an embodiment, the lengths L1, L2, and L3 of the first, second, and third alignment patterns AMP1, AMP2, and AMP3, respectively, may be in the range of about 100 μm to about 500 μm, and the width W1 of each of the first, second, and third alignment patterns AMP1, AMP2, and AMP3 may be in the range of about 30 μm to about 150 μm. In this case, the lengths L1, L2, and L3 of the first, second, and third alignment patterns AMP1, AMP2, and AMP3, respectively, may be about three to six times the width W1.

[0133] In embodiments, lengths L1, L2, and L3 of the first, second, and third alignment patterns AMP1, AMP2, and AMP3 may be about 200 μm, and a width W1 of each of the first, second, and third alignment patterns AMP1, AMP2, and AMP3 may be about 40 μm or about 50 μm.

[0134] Since the invalid area of ​​the display module 10 corresponds to or is proportional to the first shortest distance WD1 or the second shortest distance WD2, the width W1 of each of the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 may be more restrictive than the lengths L1, L2, and L3.

[0135] Since the width W1 of each of the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 is reduced, the width of the first area A1 in which the first line DLS1 overlapping the alignment mark AM is arranged can be reduced, and thus the invalid area can be further reduced. In addition, as the respective lengths L1, L2, and L3 of the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 increase (that is, as the respective areas of the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 increase), the recognition rate of the alignment mark AM can be prevented from being reduced due to the reduction in the width W1.

[0136] As the performance of the alignment system for recognizing the alignment mark AM (e.g., the resolution of the visual camera VCM) improves, the alignment mark AM can be recognized even if the width W1 of each of the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 is reduced. However, when the first line DLS1 overlapping the alignment mark AM is recognized, the alignment mark AM may not be recognized as expected due to the first line DLS1. Therefore, considering the visibility of the alignment mark AM and the invisibility of the first line DLS1, the width W1 of each of the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 may be set to about 40μm or 50μm.

[0137] Although in Figure 7 , the first length L1 of the first alignment pattern AMP1, the second length L2 of the second alignment pattern AMP2, and the third length L3 of the third alignment pattern AMP3 are shown to be substantially equal to each other, but the lengths of the alignment patterns are not limited thereto, and the first length L1, the second length L2, and the third length L3 may be different from each other. Similarly, the widths of the first alignment pattern AMP1, the second alignment pattern AMP2, and the third alignment pattern AMP3 may be equal to or different from each other.

[0138] Figure 8 is used to explain the Figure 2 An exploded perspective view of an exemplary process of aligning a display module and a window with each other in a display device.

[0139] Reference Figure 8 , the visual camera VCM may be arranged on one surface (eg, a surface displaying an image) of the display module 10. In addition, the visual camera VCM may be arranged on the top of the window 30. The visual camera VCM may be arranged to correspond to the non-display area NDA of the display module 10.

[0140] The visual camera VCM may acquire an image (or an alignment mark image) of the alignment mark AM (or the detection area AMA) of the display module 10 by light emitted from the light source. The alignment device may detect the alignment mark AM based on the image acquired by the visual camera VCM, may determine whether the alignment between the display module 10 and the window 30 has been performed based on the detected alignment mark AM, and may couple the window 30 to the display module 10 when it is determined that the alignment between the display module 10 and the window 30 has been performed.

[0141] The light source may be disposed on the bottom of the display module 10 (e.g., on the rear surface of the display module 10), and each visual camera VCM may acquire an alignment mark image including a shadow of the alignment mark AM, that is, an alignment mark image matching the alignment mark AM. However, exemplary embodiments are not limited thereto, and the light source may be disposed on one surface of the display module 10 (e.g., the display surface), and each visual camera VCM may also acquire an alignment mark image due to reflected light that has been reflected by the alignment mark AM.

[0142] The alignment device can extract feature points (e.g., inflection points or the shape of inflection points) of each alignment mark image and match the extracted feature points with preset feature points, or can match the alignment mark image with a preset reference alignment mark image, calculate the matching score, and then identify the alignment mark AM based on the matching score.

[0143] Fig. 9 is shown by capturing Figure 7 A plan view of an exemplary embodiment of an image obtained in the first detection area.

[0144] exist Fig. 9 In the Figure 8 The visual camera VCM acquires an image IMAGE1 of the first detection area AMA1.

[0145] Reference Figure 7 and Fig. 9 , the alignment mark AM (or the first, second, and third alignment patterns AMP1, AMP2, and AMP3) may be made of an opaque material and may be indicated in black in the image IMAGE1.

[0146] Similarly, since the transmittance of the second area A2 of the display device 1 is relatively low, that is, since the second line DLS2 (see Figure 7 ) has a high wiring density, so most of the light irradiated to the second area A2 will be blocked. In addition, the resolution (or resolving power) of the visual camera VCM may be greater than the second interval D2 between the second lines DLS2. That is, according to the viewing angle and resolution (or resolving power) of the visual camera VCM, the second lines DLS2 in the second area A2 may be identified as a single surface. For example, when the visual camera VCM separated from the display module 10 by a certain distance has a resolution of a maximum of 3μm, the second lines DLS2 may be arranged to be spaced apart from each other at intervals smaller than the resolution of the visual camera VCM, for example, 2μm intervals. In this case, the second lines DLS2 can be identified as a single surface by the visual camera VCM. In this case, the second area A2 can be displayed completely in black.

[0147] Since the transmittance of the first area A1 of the display device 1 is relatively high, that is, since the first line DLS1 (see Figure 7 ) has a low wiring density, so most of the light irradiated to the first area A1 may not be blocked. In this case, the first area A1 (i.e., the first area A1 excluding the alignment mark AM) may be displayed brighter than the second area A2 in a manner that the first area A1 is displayed in light gray.

[0148] Even if the second line DLS2 in the second area A2 is partially sensed, an image corresponding to the second line DLS2 (ie, the second line DLS2 having the relatively large second interval D2) may be removed by image processing (eg, image smoothing technique) on the image IMAGE1.

[0149] Since no separate wire is arranged in the region defined by the first shortest distance WD1 extending from the edge of the first region A1 to the edge of the display module 10 , all light may pass through this region and this region may appear brighter than the first region A1 , for example, by being displayed in white.

[0150] Therefore, even if the alignment mark AM is disposed in the first area A1 and aligned with the first line DLS1 (see Figure 7 ) are overlapped, the alignment mark AM can also be accurately detected or identified.

[0151] Fig.10 is a diagram showing a display module Figure 6 A plan view of an exemplary embodiment in which the first detection area is enlarged. Fig.10 In the figure, it is shown that Figure 7 The display module 10 corresponds to the alignment mark AM and the line DSL.

[0152] Reference Figure 6 , Figure 7 and Fig.10 , except for the shape of the second alignment pattern AMP2, Fig.10 The display module 10 and Figure 7 The display modules 10 are substantially the same or similar, and thus a repeated description thereof will be omitted to avoid redundancy.

[0153] The second alignment pattern AMP2 may have a substantially double triangle planar shape. Fig.10 As shown in , the second alignment pattern AMP2 can have a planar shape of a roughly double triangle implemented as two triangles arranged symmetrically to each other. Since the double triangle includes a larger number of feature points than an ordinary triangle, the error recognition rate of the second alignment pattern AMP2 (or alignment mark AM) can be further reduced compared to a rectangle or a single triangle.

[0154] Fig.11 It is shown along Figure 2 2 is a cross-sectional view of an exemplary embodiment of a display module taken along line AA′.

[0155] Reference Figures 2 to 6 and Fig.11 The display module 10 may include a base substrate SUB, at least one transistor TR, a line DLS (or a conductive line), a light emitting element EL and an encapsulation layer TFE (or a display unit DISP), sensing electrodes TE1 and TE2 and a sensing line SL (or a sensing unit TSP), and an alignment mark AM.

[0156] The base substrate SUB may be made of an insulating material such as glass or resin. The base substrate SUB may be made of a material having flexibility to be bendable or foldable, and may have a single-layer structure or a multi-layer structure.

[0157] For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the material used to form the base substrate SUB is not limited thereto. For example, the base substrate SUB may also be made of fiberglass reinforced plastic (FRP) or the like.

[0158] The base substrate SUB may include a display area DA and a non-display area NDA disposed on one side of the display area DA.

[0159] The transistor TR (or the pixel circuit (or the pixel circuit layer) PCL) may be disposed on the base substrate SUB, the transistor TR may be disposed in the display area DA of the base substrate SUB, and the line DLS may be disposed in the non-display area NDA of the base substrate SUB.

[0160] The transistor TR (or pixel circuit layer PCL) may include a semiconductor pattern (or semiconductor layer) disposed between the buffer layer BUF and the insulating layers INS1 , INS2 , and INS3 , a gate electrode GE (or first conductive layer GAT), a source electrode SE, and a drain electrode DE (or second conductive layer SD).

[0161] The buffer layer BUF may be disposed on the entire surface of the base substrate SUB. The buffer layer BUF may prevent the diffusion of impurity ions, may prevent water or external air from penetrating into the display module, and may perform a surface flattening function. The buffer layer BUF may include silicon nitride, silicon oxide, or silicon oxynitride. The buffer layer BUF may be omitted based on the type or processing conditions of the base substrate SUB.

[0162] The semiconductor pattern may be disposed on the buffer layer BUF (or the base substrate SUB). The semiconductor pattern may be an active layer forming a channel of the transistor TR. The semiconductor pattern may include a source region and a drain region respectively contacting a source electrode SE and a drain electrode DE to be described later. The region between the source region and the drain region may be a channel region ACT.

[0163] The semiconductor pattern may include polysilicon, amorphous silicon, oxide semiconductor, etc. The channel region ACT of the semiconductor pattern may be a semiconductor pattern not doped with impurities, and thus may be an intrinsic semiconductor. Each of the source region and the drain region may be a semiconductor pattern doped with impurities. Impurities such as n-type impurities, p-type impurities, or other metals may be used as impurities.

[0164] The first insulating layer INS1 (or gate insulating layer) may be disposed on the semiconductor pattern and the buffer layer BUF (or base substrate SUB). The first insulating layer INS1 may be disposed on the entire surface of the base substrate SUB. The first insulating layer INS1 may be a gate insulating layer having a gate insulating function.

[0165] The first insulating layer INS1 may include an inorganic insulating material such as a silicon compound or a metal oxide. For example, the first insulating layer INS1 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a mixture thereof. The first insulating layer INS1 may have a single-layer structure, or may have a multi-layer structure consisting of a plurality of stacked layers made of different materials.

[0166] The gate electrode GE (or the first conductive layer GAT) may be disposed on the first insulating layer INS1. The gate electrode GE may be disposed to overlap the semiconductor layer (or the channel region ACT of the semiconductor layer).

[0167] The gate electrode GE may include a metal corresponding to one or more selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The gate electrode GE may have a single-layer structure or a multi-layer structure.

[0168] The display module 10 may further include a gate line formed in the same layer as the gate electrode GE. The gate line may be electrically coupled to the gate electrode GE, may extend to the non-display area NDA in a plan view, and may be electrically coupled to the driving integrated circuit D_IC. The gate line may transmit a gate signal provided from the driving integrated circuit D_IC to the gate electrode GE of the transistor TR.

[0169] The second insulating layer INS2 (or interlayer insulating layer) may be disposed on the gate electrode GE and may be disposed on the entire surface of the base substrate SUB. The second insulating layer INS2 may function to insulate the gate electrode GE from the source electrode SE and the drain electrode DE and may be an interlayer insulating layer.

[0170] The second insulating layer INS2 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide, or an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene oxide resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The second insulating layer INS2 may have a single-layer structure, or may have a multi-layer structure consisting of a plurality of stacked layers made of different materials.

[0171] The source electrode SE and the drain electrode DE (or the second conductive layer SD) may be disposed on the second insulating layer INS2. The line DLS may be disposed in the same layer as the source electrode SE and the drain electrode DE.

[0172] The source electrode SE and the drain electrode DE may respectively contact the source region and the drain region of the semiconductor pattern through contact holes formed through the second insulating layer INS2 and the first insulating layer INS1 .

[0173] The lines DLS may include a first line DLS1 and a second line DLS2 .

[0174] Some of the second lines DLS2 may be electrically coupled to the source electrode SE, may extend to the non-display area NDA in a plan view, and may be electrically coupled to the driving integrated circuit D_IC (see Figure 3 ). As reference has been made to Figure 7 The second line DLS2 is described, and thus a repeated description thereof will be omitted to avoid redundancy.

[0175] The first line DLS1 may include the above reference Figure 5 The first detection line MCD1 (or the second detection line MCD2) described above. Figure 7 The first shortest distance WD1 and the first interval D1 of the first line DLS1 are described, and thus a repeated description thereof will be omitted to avoid redundancy.

[0176] Similar to the gate electrode GE, the source electrode SE and the drain electrode DE and the line DLS may include a metal corresponding to one or more selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The source electrode SE and the drain electrode DE and the line DLS may have a single-layer structure or a multi-layer structure.

[0177] A third insulating layer INS3 (or a passivation layer) may be disposed on the source and drain electrodes SE and DE and the line DLS.

[0178] The light emitting element unit LDL may be disposed on the pixel circuit PCL. The light emitting element unit LDL may include at least one light emitting element EL disposed in the display area DA and coupled to at least one transistor TR, and an encapsulation layer TFE.

[0179] The light emitting element EL (or light emitting element unit LDL) may include a first electrode LE (or lower electrode), a second electrode UE (or upper electrode) and an emission layer IL (or intermediate layer). In addition, the light emitting element EL may further include a pixel defining layer PDL. Any one of the first electrode LE and the second electrode UE may be an anode electrode, and the other may be a cathode electrode. For example, the first electrode LE may be an anode electrode, and the second electrode UE may be a cathode electrode.

[0180] The first electrode LE may be electrically coupled to the drain electrode DE of the transistor TR through a contact hole formed through the third insulating layer INS3 .

[0181] The pixel defining layer PDL may be disposed along the edge of the first electrode LE, and may include an organic insulating material.

[0182] The emission layer IL may be disposed on the top of the first electrode LE exposed by the pixel defining layer PDL. The emission layer IL may include a low molecular substance or a high molecular substance.

[0183] The second electrode UE may be disposed on the emission layer IL. The second electrode UE may be a common electrode formed on the entire surface of the emission layer IL and the pixel defining layer PDL. The second electrode UE may be a transparent electrode or a semi-transparent electrode.

[0184] The encapsulation layer TFE may be disposed on the second electrode UE. The encapsulation layer TFE may prevent water and air that may come from the outside from penetrating into the light emitting element EL. The encapsulation layer TFE may be formed by thin film encapsulation and may include one or more organic layers and one or more inorganic layers. For example, the organic layer may be formed to include any one selected from the group consisting of epoxy resin, acrylate, and polyurethane acrylate, and the inorganic layer may be formed to include a silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiON x ) is one or more of the group consisting of ).

[0185] Although in Fig.12 The light emitting element unit LDL is illustrated as including an organic light emitting element, but the light emitting element unit LDL is not limited thereto and may include an inorganic light emitting element or the like.

[0186] The sensing electrode TE, the sensing line SL, and the alignment mark AM may be disposed on the encapsulation layer TFE. The sensing electrode TE may be disposed in the display area DA (or the sensing area SA), and the sensing line SL may be disposed in the non-display area NDA and coupled to the sensing electrode TE.

[0187] The sensing unit TSP may include a first sensing electrode TE1 and first and second connection patterns CNP1 and CNP2 (or third and fourth conductive layers YTML1 and YTML2 ) disposed between the encapsulation layer TFE and fourth and fifth insulating layers INS4 and INS5 .

[0188] The first connection pattern CNP1 (or the third conductive layer YTML1) may be disposed on the encapsulation layer TFE. The sensing line SL and the alignment mark AM may be disposed in the same layer as the first connection pattern CNP1. The alignment mark AM may be directly disposed on the encapsulation layer TFE.

[0189] The sensing line SL and the align mark AM may be arranged in the non-display area NDA (or the non-sensing area NSA of the sensing unit TSP).

[0190] The alignment mark AM may be disposed in the first area A1 and may overlap some of the lines DLS (ie, the first line DLS1). Figure 7 The second shortest distance WD2 and the size of the alignment mark AM are described, and thus repeated descriptions thereof will be omitted to avoid redundancy.

[0191] The fourth insulating layer INS4 may be disposed on and cover the first connection pattern CNP1, the sensing line SL, and the alignment mark AM. In addition, the fourth insulating layer INS4 may be disposed on the encapsulation layer TFE partially exposed by the first connection pattern CNP1, the sensing line SL, and the alignment mark AM.

[0192] The first sensing electrode TE1 and the second connection pattern CNP2 may be disposed on the fourth insulating layer INS4, and the second sensing electrode TE2 (see Figure 6 ) can also be disposed on the fourth insulating layer INS4. Figure 6 As described, the first sensing electrode TE1, the second connection pattern CNP2 and the second sensing electrode TE2 may be disposed in the display area DA (or the sensing area SA of the sensing unit TSP). The first sensing electrode TE1 may be electrically coupled to the first connection pattern CNP1 and the sensing line SL through contact holes formed through the fourth insulating layer INS4, respectively.

[0193] The fifth insulating layer INS5 may be disposed on the first sensing electrode TE1 and the second connection pattern CNP2 , and may be formed on the entire surface of the encapsulation layer TFE.

[0194] As mentioned above Fig.11 As described, the alignment mark AM may be disposed on the encapsulation layer TFE, and may be disposed to overlap the first line DLS1.

[0195] Figures 12 to 15 It is shown along Figure 2 A cross-sectional view of various exemplary embodiments of a display module taken along line AA'. Figures 12 to 15 , the cross-sectional views of the display modules 10_1 to 10_4 may be substantially similar to those of Fig.11 The corresponding display module 10. Therefore, repeated descriptions of common elements will be omitted to avoid redundancy.

[0196] First, refer to Fig.11 and Fig.12 , display module 10_1 and Fig.11 The display module 10_1 is different from the display module 10_1 in that the display module 10_1 includes an inclined side surface SIDE.

[0197] The display module 10_1 (or the display device 1 ) may be processed (or cut) using laser.

[0198] The laser beam may be irradiated to the rear surface of the display module 10_1 along the third direction DR3 or the fourth direction DR4. Here, the third direction DR3 may be the same as the direction in which light is emitted from the display module 10_1, and the fourth direction DR4 may form a first specific angle θ1 toward the outside of the display module 10_1 relative to the third direction DR3. For example, the first specific angle θ1 may fall within a range of about 0.1 degrees to about 5 degrees, within a range of about 0.3 degrees to about 3 degrees, or within a range of about 0.5 degrees to about 2 degrees. When the laser beam is irradiated along the third direction DR3 or the fourth direction DR4, even if the laser beam is reflected by the first electrode LE or the second electrode UE included in the display module 10_1, the display area DA of the display module 10_1 may not be damaged.

[0199] When the display module 10_1 is cut by a laser beam, a laser beam traveling along the third direction DR3 or the fourth direction DR4 is used, and a relatively large amount of energy is applied to the rear surface of the display module 10_1, so the side surface SIDE (or laser etching surface) of the display module 10_1 may have a reverse tilt structure. The side surface SIDE of the display module 10_1 may form a second specific angle θ2 toward the outside of the display module 10_1 relative to the third direction DR3. For example, the second specific angle θ2 may fall within a range of about 3 degrees to about 5 degrees.

[0200] Since the side surface SIDE of the display module 10_1 is processed by laser processing, the side surface of the display unit DISP and the side surface of the sensing unit TSP can both form an acute angle with the thickness direction of the display unit DISP (i.e., the third direction DR3), wherein the side surface of the display unit DISP and the side surface of the sensing unit TSP can be located in the same or same plane (coplanar).

[0201] Since the alignment mark AM is formed on the encapsulation layer TFE, the side surface SIDE of the display module 10_1 may be located further inward from the display module 10_1 compared to a typical display module (e.g., a display module including an alignment mark formed in the same layer as the transistor TR). Therefore, the ineffective area of ​​the display module 10_1 may be further reduced.

[0202] Reference Fig.11 and Fig.13 , display module 10_2 and Fig.11 The display module 10_2 is different from the display module 10_2 in that the display module 10_2 includes an alignment mark AM formed in the same layer as the first sensing electrode TE1 (or, the fourth conductive layer YTML2 ).

[0203] The alignment mark AM may be disposed in the first area A1 and may overlap some of the lines DLS (ie, the first line DLS1). Figure 7The shortest distance WD2 and the size of the alignment mark AM are described, and thus repeated descriptions thereof will be omitted to avoid redundancy.

[0204] That is, the alignment mark AM may be included in the sensing unit TSP, and may be formed in the same layer as the first connection pattern CNP1 or the first sensing electrode TE1.

[0205] Reference Fig.11 and Fig.14 , display module 10_3 and Fig.11 The display module 10_3 is different from the display module 10_3 in that the display module 10_3 includes a first sub-alignment mark AM_S1 and a second sub-alignment mark AM_S2.

[0206] The first sub-alignment mark AM_S1 and the second sub-alignment mark AM_S2 may be vertically separated from each other and may be disposed on different layers. Fig.14 As shown in FIG. 1 , the first sub-alignment mark AM_S1 may be formed in the same layer as the first connection pattern CNP1 , and the second sub-alignment mark AM_S2 may be formed in the same layer as the first sensing electrode TE1 .

[0207] In embodiments, the first and second sub-alignment marks AM_S1 and AM_S2 may be included in a single alignment mark AM (eg, first alignment mark AM1 ) or may constitute a single alignment mark AM.

[0208] For example, the first sub-alignment mark AM_S1 may be Figure 6 The first alignment pattern AMP1 (or the third alignment pattern AMP3 ) described above, the second sub-alignment mark AM_S2 may be a second alignment pattern AMP2 .

[0209] In an example, the first sub-alignment mark AM_S1 and the second sub-alignment mark AM_S2 may overlap each other and may constitute a single alignment pattern (eg, refer to Figure 6 In this case, the shape of the alignment mark AM (eg, a more complicated shape) can be more easily realized.

[0210] Reference Fig.11 and Fig.15 , display module 10_4 and Fig.11 The display module 10_4 is different from the display module 10_4 in that the display module 10_4 includes a line DLS formed in the same layer as the gate electrode GE (or the first conductive layer GAT) of the transistor TR.

[0211] In addition to the layer on which the wired DLS is provided, Fig.15 The line DLS is the same as above. Fig.11The described lines DLS are substantially the same or similar, and thus repeated descriptions thereof will be omitted to avoid redundancy.

[0212] That is, the alignment mark AM may be aligned with some of the lines DLS (ie, the first line DLS1 disposed in the outermost portion in a plan view among the lines DLS, for example, as described above with reference to FIG. Figure 5 The first detection line MCD1 and the second detection line MCD2 described above are overlapped, and some of the lines DLS may be disposed in the same layer as the gate electrode GE or the source electrode SE and the drain electrode DE of the transistor TR. In addition, when the display module 10_4 further includes an additional conductive layer different from the gate electrode GE or the source electrode SE and the drain electrode DE of the transistor TR, the first line DLS1 may be included in the additional conductive layer.

[0213] Fig.16 It is shown along Figure 2 A cross-sectional view of another exemplary embodiment of a display module taken along line AA' of FIG. Fig.16 , the display module 10_5 is shown with Fig.11 The corresponding cross-sectional view.

[0214] Fig.17 It is shown Fig.16 A plan view of an exemplary embodiment of a display module. Fig.17 , the display module 10_5 is shown with Figure 6 The part corresponding to the first detection area AMA1.

[0215] Reference Figure 7 , Fig.11 , Fig.16 and Fig.17 , in addition to the arrangement position of the alignment mark AM, Fig.16 The display module 10_5 can be compared with the above reference Figure 7 and Fig.11 The display modules 10 described are substantially the same or similar. Therefore, repeated descriptions thereof will be omitted to avoid redundancy.

[0216] The alignment mark AM may be disposed in the same layer as the first connection pattern CNP1 (or the third conductive layer YTML1 ), and may partially overlap the first line DLS1 (or the first area A1 in which the first line DLS1 is disposed).

[0217] For example, when the first area A1 in which the first line DLS1 is arranged is not sufficiently defined due to the specifications required for the line DLS, for example, when the width of the first area A1 in the second direction DR2 is smaller than the first width W1 of the first alignment pattern AMP1, the alignment mark AM may partially overlap with the line DLS.

[0218] In this case, the third shortest distance WD3 from one of the lines DLS to the side surface SIDE of the display module 10_5 (or the edge of the display module 10_5) may be greater than the second shortest distance WD2 from the alignment mark AM to the side surface SIDE of the display module 10_5 (or the edge of the display module 10_5).

[0219] like Fig.17 As shown in the figure, the third shortest distance WD3 from the first line DL1 set in the outermost part among the lines DLS to the first long side LS1 of the display module 10_5 (or the edge of the display module 10_5) can be greater than the second shortest distance WD2 from the alignment mark AM (or the first alignment pattern AMP1) to the first long side LS1 of the display module 10_5 (or the edge of the display module 10_5).

[0220] In addition to the arrangement position of the alignment mark AM or the arrangement relationship between the alignment mark AM and the first line DLS1, Fig.16 and Fig.17 The alignment mark AM shown in FIG. Figure 7 and Fig.11 The described alignment marks AM are substantially the same or similar, and thus a repeated description thereof will be omitted to avoid redundancy.

[0221] As mentioned above Fig.16 and Fig.17 As described, the alignment mark AM may partially overlap the line DLS (or the first line DLS1 ).

[0222] Fig.18 It is shown along Figure 2 A cross-sectional view of another exemplary embodiment of a display module taken along line AA' of FIG. Fig.18 , the display module 10_6 is shown with Fig.11 Corresponding sectional view and not described Fig.11 All elements are depicted in order to avoid redundancy. Fig.19 It is shown Fig.18 A plan view of an exemplary embodiment of a display module. Fig.19 , the display module 10_6 is shown with Figure 6 The part corresponding to the first detection area AMA1.

[0223] Reference Figure 7 , Fig.11 , Fig.18 and Fig.19 , Fig.18 The display module 10_6 is similar to the above reference Figure 7 and Fig.11 The display module 10 described is different in that the alignment mark AM does not overlap the line DLS.

[0224] The alignment mark AM may be disposed in the same layer as the first connection pattern CNP1 (or the third conductive layer YTML1 ), and may not overlap the first line DLS1 (or the first area A1 in which the first line DLS1 is disposed).

[0225] For example, when the first area A1 in which the first line DLS1 is arranged cannot be defined due to required specifications of the line DLS, the alignment mark AM may not overlap the line DLS.

[0226] In this case, the third shortest distance WD3 from one of the lines DLS to the side surface SIDE of the display module 10_6 (or the edge of the display module 10_6) may be greater than the second shortest distance WD2 from the alignment mark AM to the side surface SIDE of the display module 10_6 (or the edge of the display module 10_6).

[0227] In an embodiment, in a plan view (or in a horizontal direction), a third interval D3 between the alignment mark AM and the line DLS may be smaller than the first interval D1 (or the second interval D2 ) between the lines DLS.

[0228] For example, Fig.18 As shown in FIG. 1 , the third interval D3 between the alignment mark AM and the line DLS in the horizontal direction may be smaller than the first interval D1 between the first lines DLS1. In addition, the third interval D3 may be larger than the second interval D2. The reason for this is that, as described above with reference to FIG. Fig. 9 Described, according to Figure 8 The second interval D2 may not be recognized due to the resolution of the visual camera VCM, and when the alignment mark AM is spaced apart from the line DLS by an interval smaller than the second interval D2, the alignment mark AM may not be recognized from the line DLS. Therefore, the third interval D3 may also be larger than the second interval D2.

[0229] In an embodiment, Fig.19 As shown in FIG. , in the plan view, the alignment mark AM and the line DLS may actually contact each other, in which case, as shown in FIG. Fig.18 The third interval D3 depicted in the figure can be substantially 0, for example. The portion where the alignment mark AM contacts the line DLS can be set as a feature point. Optionally, the entire plane shape (or an image corresponding to the entire plane shape, for example, a roughly “╞” shape) of the line DLS in the first detection area AMA1 and the alignment patterns AMP1, AMP2, and AMP3 protruding from the line DLS in the second direction DR2 can be set as the alignment mark AM. Therefore, even if the alignment mark AM and the line DLS are recognized as a single shape without being individually distinguished from each other, the alignment patterns AMP1, AMP2, and AMP3 can also be used as the alignment mark AM.

[0230] As mentioned above Fig.18 and Fig.19 As described, the alignment mark AM may not overlap with the line DLS but may be arranged as close as possible to the line DSL or in contact with the line DLS in a plan view.

[0231] Fig. 20 It is shown that the Figure 2 A plan view of another embodiment of a display module in a display device. Fig. 20 In the figure, it is shown that Figure 5 The display unit DISP corresponds to the display module 10_7.

[0232] Reference Figure 2 , Figure 5 and Fig. 20 , Fig. 20 The display module 10_7 (or display unit) and Figure 5 The display unit DISP is different in that the display module 10_7 further includes an alignment mark AM.

[0233] The alignment mark AM may be disposed in the non-display area NDA and may overlap some of the lines DLS. Figure 3 , Figure 5 , Figure 6 , Figure 7 and Fig.10 The described alignment mark AM (and the alignment patterns AMP1 , AMP2 , and AMP3 ) are substantially the same or similar, and thus repeated descriptions thereof will be omitted to avoid redundancy.

[0234] Fig.21 It is shown Fig. 20 A cross-sectional view of an exemplary embodiment of a display module. Fig.21 , the display module 10_7 is shown Fig.11 The cross section of the display module 10 corresponds to FIG. Fig.11 , Fig. 20 and Fig.21 , display module 10_7 and Fig.11 The display module 10_7 is different from the display module 10_7 in that the display module 10_7 does not include the sensing unit TSP.

[0235] The display module 10_7 may include a base substrate SUB (or a pixel circuit PCL), a line DLS, an alignment mark AM, and a light emitting element EL (or a light emitting unit LDL). Fig.11 (or Fig.15) are substantially the same or similar to the base substrate SUB, lines DLS, and light emitting elements EL described herein, and thus repeated descriptions thereof will be omitted to avoid redundancy.

[0236] The line DLS may be disposed in the same layer as the gate electrode GE of the transistor TR, and the alignment mark AM may be disposed in the same layer as the source electrode SE and the drain electrode DE of the transistor TR.

[0237] The alignment mark AM may be aligned with some of the lines DLS (ie, the first line DLS1 disposed in the outermost portion in a plan view among the lines DLS, for example, as described above with reference to FIG. Figure 5 The first detection line MCD1 and the second detection line MCD2 are described as overlapping.

[0238] The first shortest distance WD1 from one of the lines DLS to the side surface SIDE of the display module 10_7 may be less than or equal to the second shortest distance WD2 from the alignment mark AM to the side surface SIDE of the display module 10_7. Figure 8 ), the display module 10_7 can be obtained with reference to the above Fig. 9 The image described is essentially the same as image IMAGE1.

[0239] Although the alignment mark AM and the first line DSL1 are described as overlapping each other, exemplary embodiments are not limited thereto. Fig.16 and Fig.18 As described above, the alignment mark AM may be arranged to partially overlap the first line DSL1 (or the first area A1) or to be arranged adjacent to the first line DSL1 (or the first area A1). In this case, similar to the third shortest distance WD3 (see Fig.16 or Fig.18 ), the first shortest distance WD1 can be greater than the second shortest distance WD2.

[0240] In addition, despite the Fig.21 The alignment mark AM is illustrated as being disposed on the top of the first line DSL1 in FIG. 1 , but the alignment mark AM is not limited thereto.

[0241] Fig. 22 It is shown Fig. 20 A cross-sectional view of an exemplary embodiment of a display module. Fig. 22 In the figure, it is shown that Fig.21 The display module 10_7 corresponds to the display module 10_8.

[0242] Reference Figure 20 to Figure 22 , except for the arrangement positions of the line DLS and the alignment mark AM, the display module 10_8 may be Fig.21The display modules 10_7 are substantially the same or similar. Therefore, repeated descriptions thereof will be omitted to avoid redundancy.

[0243] The alignment mark AM may be disposed in the same layer as the gate electrode GE of the transistor TR, and the line DLS may be disposed in the same layer as the source electrode SE and the drain electrode DE of the transistor TR. That is, the alignment mark AM may be disposed under the line DLS (or under the first line DSL1).

[0244] As mentioned above Figure 20 to Figure 22 As described, the alignment mark AM may be disposed on a layer different from a layer on which some of the lines DLS (eg, the first line DSL1 or the outermost lines) are disposed, and the alignment mark AM may overlap some of the lines DLS.

[0245] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those of ordinary skill in the art.

Claims

1. A display device, the display device include: a base substrate including a display area and a non-display area positioned at a side of the display area; At least one transistor and a conductive line, wherein the at least one transistor is located in the display area of ​​the base substrate, and the conductive line is located in the non-display area of ​​the base substrate; at least one light emitting element located in the display area and coupled to the at least one transistor; An encapsulation layer, covering the light emitting element; a sensing electrode and a sensing line, wherein the sensing electrode is located on the packaging layer, and the sensing line is located on the packaging layer and coupled to the sensing electrode; as well as an alignment mark located on the encapsulation layer and at least partially overlapping some of the conductive lines in the non-display area in a plan view, Some of the wires are arranged in a first region of the base substrate, and the remaining wires are arranged in a second region of the base substrate, and The transmittance at the first region is higher than the transmittance at the second region.

2. The display device according to claim 1, in, The spacing between some of the conductive lines is larger than the spacing between the remaining conductive lines.

3. The display device according to claim 1, in, In the plan view, a shortest distance from one of the conductive lines to an edge of the base substrate is shorter than a shortest distance from the alignment mark to the edge of the base substrate.

4. The display device according to claim 1, in: The alignment mark includes an alignment pattern, and The alignment patterns are spaced apart from each other, and adjacent alignment patterns have different planar shapes.

5. The display device according to claim 4, in: The alignment patterns are sequentially arranged along a first direction, The length of each of the alignment patterns in the first direction is greater than the width of each of the alignment patterns in the second direction, The second direction is perpendicular to the first direction, and A spacing between the alignment patterns in the first direction is smaller than the length.

6. The display device according to claim 5, in: The length in the first direction is in the range of 100 μm to 500 μm, and The width in the second direction is in a range of 30 μm to 150 μm.

7. The display device according to claim 5, in, The length in the first direction is 3 to 6 times the width in the second direction.

8. The display device according to claim 5, in: One of the alignment patterns has a rectangular planar shape, and Another one of the alignment patterns has a triangular planar shape.

9. The display device according to claim 4, in: The alignment mark includes a first alignment pattern, a second alignment pattern, and a third alignment pattern that are sequentially arranged, and The first alignment pattern and the third alignment pattern have the same planar shape.

10. The display device according to claim 1, in: Some of the conductive lines include crack detection lines extending along an edge of the display area, and The crack detection line is electrically isolated from the at least one transistor.

11. The display device according to claim 1, in: A side surface of the display device forms an acute angle with a line parallel to a thickness direction of the base substrate.

12. The display device according to claim 11, in, The at least one transistor comprises: A semiconductor pattern is disposed on the base substrate; a gate electrode, located on the semiconductor pattern and overlapping the semiconductor pattern; A first insulating layer is disposed on the gate electrode; and The source electrode and the drain electrode are located on the first insulating layer.

13. The display device according to claim 12, in, The some of the conductive lines are disposed on the same layer as the gate electrode.

14. The display device according to claim 12, in, The some of the wires are disposed on the same layer as the source electrode and the drain electrode.

15. The display device according to claim 1, in: The alignment mark includes a sub-alignment mark, and The sub-alignment marks are separated from each other and disposed in different layers.

16. The display device according to claim 1, in, The alignment mark is closer to an edge of the base substrate than the conductive line.

17. An electronic device, the electronic device include: base substrate; A semiconductor pattern is disposed on the base substrate; A first conductive pattern, disposed on the semiconductor pattern; a first insulating layer, disposed on the first conductive pattern; as well as a second conductive pattern, disposed on the first insulating layer, wherein one of the first conductive pattern and the second conductive pattern comprises an alignment mark, and wherein the alignment mark at least partially overlaps at least one conductive pattern of the other conductive pattern among the first conductive pattern and the second conductive pattern, wherein some of the other conductive patterns among the first conductive pattern and the second conductive pattern are arranged in the first region of the base substrate, and the remaining conductive patterns of the other conductive pattern are arranged in the second region of the base substrate, and The transmittance at the first region is higher than the transmittance at the second region.

18. The electronic device according to claim 17, in: The alignment mark is included in the first conductive pattern, and The alignment mark overlaps at least one of the second conductive patterns.

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