A Quad-CAP high-voltage isolation capacitor and digital isolator

Abstract

In an embodiment of the present disclosure, a Quad-CAP high-voltage isolation capacitor and a digital isolator are provided, which include two interconnected isolation capacitor units. Each isolation capacitor unit includes a lower electrode plate, an upper electrode plate, and an SiO2 dielectric layer and a Polyimide dielectric layer sequentially arranged between the lower electrode plate and the upper electrode plate. The thickness of the SiO2 dielectric layer is 9-11 um, and the thickness of the Polyimide dielectric layer is 18-22 um. The isolation capacitor of the present disclosure can effectively increase the isolation breakdown voltage value of the digital isolator chip, thereby improving the reliability of the isolator chip and meeting the requirements of some high-voltage applications at the same time.

Description

Technical Field

[0001] The present disclosure relates to the technical field of digital isolators, and in particular to a Quad-CAP high-voltage isolation capacitor and a digital isolator. Background Art

[0002] Capacitor isolators are becoming the mainstream application in the isolator market due to their compatibility with standard CMOS processes, low cost, and high voltage resistance. The isolation capacitors in conventional digital isolators are based on standard CMOS processes. 2 The lower plate is the second metal layer M2, the upper plate is the top metal layer M6, and the isolation gate is composed of the metal and via layers between VIA2 and VIA5. The thickness of the standard process is about 6-7um, and after improvement, it can be achieved to a thickness of about 10um. The gate SiO 2 The density is relatively good, the withstand voltage is about 500Vrms / um, and the isolation withstand voltage of a single capacitor is about 5000Vrms. The earliest capacitive digital isolator was implemented with a single capacitor, with low isolation withstand voltage and poor reliability. The mainstream capacitive digital isolator on the market is dual-capacitor isolation, with improved isolation withstand voltage, reaching 5000-10000Vrms withstand voltage, and improved reliability. However, the isolation withstand voltage of the isolator still needs to be improved to meet the needs of some high-voltage applications. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a Quad-CAP high-voltage isolation capacitor and a digital isolator. The isolation capacitor can effectively improve the isolation voltage resistance value of the digital isolator chip. The theoretical isolation voltage resistance value can reach 20,000 Vrms, thereby improving the reliability of the isolator chip and meeting the needs of some high-voltage applications.

[0004] In order to meet the above technical objectives, the present invention provides the following technical solutions:

[0005] A Quad-CAP high withstand voltage isolation capacitor comprises two isolation capacitor units connected to each other, each of the isolation capacitor units comprises a lower plate, an upper plate and a SiO2 2 dielectric layer and Polyimide dielectric layer, the SiO 2 The thickness of the dielectric layer is 9-11um, and the thickness of the Polyimide dielectric layer is 18-22um.

[0006] In a preferred embodiment, the SiO 2 The thickness of the dielectric layer is 10um, and the thickness of the Polyimide dielectric layer is 20um.

[0007] In a preferred embodiment, the upper electrode plate is made of metal Cu.

[0008] In a preferred embodiment, the Polyimide dielectric layer is processed by a wafer back-end process.

[0009] The present invention also provides a digital isolator, comprising a signal transmitting module, a signal receiving module, and the Quad-CAP high-voltage isolation capacitor as described above; the signal transmitting module modulates the input signal and transmits the modulated signal to the isolation capacitor, and the signal passing through the isolation capacitor is demodulated by the signal receiving module and then output.

[0010] The invention discloses a Quad-CAP (Quad-Capacitor) high withstand voltage isolation capacitor and a digital isolator, and has the beneficial effects that: the invention proposes a new Quad-CAP isolation withstand voltage capacitor, which is composed of four capacitors to form an isolation gate, and can further improve the isolation withstand voltage value of the digital isolator chip. The theoretical isolation withstand voltage value can reach 20000Vrms, thereby improving the reliability of the isolator chip, and can also meet the needs of some high withstand voltage occasions. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 It is the basic structure of the isolation capacitor in the conventional capacitive digital isolator;

[0013] Figure 2 The basic structure of the high withstand voltage isolation capacitor of the present invention;

[0014] Figure 3 The digital isolator circuit diagram of the present invention uses a high-voltage isolation capacitor. DETAILED DESCRIPTION

[0015] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0016] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0017] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0018] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The drawings only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0019] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0020] refer to Figure 1 , Figure 1The basic structure of the isolation capacitor in a conventional digital isolator is shown in the figure. It is obtained by improving the thickness of the vias using the standard CMOS process. The lower plate is the second metal layer M2, the upper plate is the top metal layer M6, and the isolation gate is composed of the metal and via layers between VIA2 and VIA5. The thickness of the standard process is about 6 to 7um, and after improvement, it can achieve a thickness of about 10um. The density of the gate SiO2 is relatively good, the unit withstand voltage value is about 500Vrms / um, and the isolation withstand voltage value of a single capacitor is about 5000Vrms. Each isolator consists of two bare cores, which are connected by bonding wires. Therefore, the isolation gate of the isolator is composed of two isolation capacitors in series, and the overall withstand voltage is the sum of the two isolation capacitors, which is about 10000Vrms.

[0021] Next, refer to Figure 2 , attached Figure 2 The basic structure of the Quad-CAP (Quad-Capacitor) high withstand voltage isolation capacitor of the present invention is shown in FIG. It includes two isolation capacitor units connected to each other, and the figure shows two isolation capacitor dielectrics connected in series on a single bare core of the isolation capacitor unit, one of which is C sio2 SiO obtained by CMOS process 2 The dielectric isolation capacitor has a thickness of about 9-11um, preferably 10um; PI The isolation capacitor is a Polyimide medium formed by the post-processing of the wafer, with a capacitor thickness of about 18-22um, preferably 20um, and a unit withstand voltage of 250Vrms / um. The lower plate of the capacitor is the second layer of metal M2, and the upper plate is thick copper formed by the post-processing of the wafer. The upper plate also serves as a pad PAD, and is interconnected with another identical isolation capacitor unit bare core by bonding. Similarly, each isolator is composed of two bare cores, which are connected to each other by bonding wires. Therefore, the isolation gate of the Quad-CAP (quad capacitor) isolator is composed of four isolation capacitors connected in series, and the overall withstand voltage is the sum of the withstand voltages of the four isolation capacitors, which is about 20,000Vrms.

[0022] The isolator capacitor of Quad-CAP is composed of 4 isolation capacitors connected in series. The isolation withstand voltage is the sum of the isolation withstand voltage of the 4 isolation capacitors. The digital isolator used is composed of two bare cores sealed together. Each bare core has two isolation capacitors connected in series, namely SiO 2 Capacitors and Polyimide capacitors. Using special isolator process technology, SiO 2 The dielectric thickness of the capacitor can be as low as 10um, and the unit withstand voltage is 500Vrms / um. 2The withstand voltage of the capacitor is about 5000Vrms; Polyimide capacitors are manufactured in the wafer back-end processing, with a thickness of preferably 20um and a unit withstand voltage of 250Vrms / um. Therefore, the withstand voltage of a single Polyimide capacitor is about 5000Vrms. Therefore, the overall withstand voltage of the isolator is about Viso = 2*(5000+5000) = 20000Vrms.

[0023] Attached Figure 3 The circuit diagram of the digital isolator using the above-mentioned high-voltage isolation capacitor in the present invention is shown in FIG. The isolator circuit is based on OOK modulation and demodulation technology, and adopts the Quad-CAP isolation capacitor circuit proposed in the present invention. It includes a signal transmitter 100, a signal receiver 200, and a capacitive isolation gate 300 between the signal transmitter 100 and the signal receiver 200, that is, the above-mentioned high-voltage isolation capacitor. The input signal VIN is connected to the Schmitt trigger 101 to realize the shaping of the input signal to obtain a clean square wave signal, which is then sent to the OOK modulator 102. The high-frequency clock signal generated by the high-frequency carrier generator 103 is also sent to the OOK modulator 102, and OOK modulation is performed with the input signal in the OOK modulator 102 to obtain a differential OOK modulated signal. The modulated differential OOK signal is transmitted to the capacitive isolation gate 300, and after the differential Quad-CAP isolation gate, it is connected to the signal receiver 200. The preamplifier 201 is arranged in the signal receiver 200, linearly amplifies the weak OOK modulated signal after the isolation barrier, sends it to the OOK demodulator 202 for demodulation, restores it to the initial square wave signal, and then drives and amplifies it through the driver 203 and sends it to VOUT output.

[0024] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A Quad-CAP high withstand voltage isolation capacitor, It is characterized in that The invention comprises two isolated capacitor units connected to each other, each of which comprises a lower plate, an upper plate and a SiO2 film disposed between the lower plate and the upper plate. 2 The lower plate is the second metal layer M2, the upper plate is thick copper formed by wafer post-processing, and the upper plate is also used as a PAD to interconnect with another isolation capacitor unit bare core. 2 The thickness of the dielectric layer is 9-11um, the thickness of the Polyimide dielectric layer is 18-22um, a single bare core of the isolation capacitor unit has two isolation capacitor dielectrics connected in series, each isolator is composed of two bare cores, and the isolation gate of the Quad-CAP isolator is composed of four isolation capacitors connected in series.

2. The Quad-CAP high withstand voltage isolation capacitor according to claim 1, It is characterized in that The SiO 2 The thickness of the dielectric layer is 10um, and the thickness of the Polyimide dielectric layer is 20um.

3. The Quad-CAP high withstand voltage isolation capacitor according to claim 1, It is characterized in that The Polyimide dielectric layer is processed through a wafer back-end process.

4. A digital isolator, It is characterized in that It comprises a signal transmitting module, a signal receiving module, and the Quad-CAP high withstand voltage isolation capacitor according to any one of claims 1 to 3; the signal transmitting module modulates the input signal and transmits the modulated signal to the Quad-CAP high withstand voltage isolation capacitor, and the signal passing through the Quad-CAP high withstand voltage isolation capacitor is demodulated by the signal receiving module and then output.

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