A CPU network interface performance test board, test system and test method

Abstract

The embodiments of the present application disclose a CPU network interface performance test board, test system and test method, which relate to the field of board technology and are invented to improve the accuracy of testing the performance of the CPU network interface. The CPU network interface performance test board includes: a printed circuit board, on which a first gold finger, a secondary drive unit and a first group of optical modules are provided; wherein a first group of network pins are provided on the first gold finger, the first group of network pins are connected to the first row of terminals, the secondary drive unit is respectively connected to the second row of terminals and the third row of terminals, and the first group of optical modules is connected to the fourth row of terminals; the first row of terminals is arranged adjacent to the second row of terminals, and the third row of terminals is arranged adjacent to the fourth row of terminals. The present application is suitable for testing the performance of the CPU network interface.

Description

Technical Field

[0001] The present application relates to the field of board technology, and in particular to a CPU network interface performance test board, a test system and a test method. Background Art

[0002] With the technological development of CPU chip design, the high-speed interface integrated on the CPU can be configured into different protocol types through software to achieve different interface functions. That is, the same signal can be configured into PCIe, network (SFI, KR, etc.), or SATA storage interface, etc.

[0003] In the final product, the hardware is generally designed with a fixed interface function and the software is configured with a corresponding interface protocol. However, in the development of the CPU, multiple tests need to be performed on the CPU network interface to evaluate the performance of the CPU network interface. In the existing testing technology, the CPU network interface is connected to the PCIe slot and tested with the help of a PCIe standard test fixture. However, the PCIe standard test fixture only has an SMA interface. Signal quality testing and loopback testing can be performed through the SMA, but since there is no optical module on the PCIe test fixture, it is impossible to use the optical module test fixture to perform signal quality testing and loopback testing when there is an optical module on the test link, and it is also impossible to perform business stress testing. To evaluate the performance of the CPU network interface, the above multiple tests need to be performed to obtain corresponding signal quality and network performance indicators, and then a comprehensive evaluation is performed. Obviously, since there are fewer test items in the existing testing technology, the accuracy of testing the CPU network interface performance in the existing technology is low. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a CPU network interface performance test board, a test system and a test method to improve the accuracy of testing the CPU network interface performance.

[0005] An embodiment of the present application provides a CPU network interface performance test board, including: a printed circuit board, on which a first gold finger, a secondary drive unit and a first group of optical modules are arranged; wherein a first group of network pins are arranged on the first gold finger, the first group of network pins are connected to a first row of terminals, the secondary drive unit is respectively connected to a second row of terminals and a third row of terminals, and the first group of optical modules is connected to a fourth row of terminals; the first row of terminals is adjacent to the second row of terminals, and the third row of terminals is adjacent to the fourth row of terminals.

[0006] According to a specific implementation method of an embodiment of the present application, the first group of network pins includes N groups of sub-network pins, and the two input pins of each group of sub-network pins are respectively connected to the first terminal and the second terminal in the first row of terminals, and the two output pins of each group of sub-network pins are respectively connected to the third terminal and the fourth terminal in the first row of terminals; wherein N is an integer greater than or equal to 1.

[0007] According to a specific implementation method of the embodiment of the present application, the secondary drive unit includes a first secondary drive unit and a second secondary drive unit, the first secondary drive unit and the second secondary drive unit are arranged side by side on the printed circuit board, the input pin of the first secondary drive unit and the output pin of the second secondary drive unit are connected to the second row of terminals; the output pin of the first secondary drive unit and the input pin of the second secondary drive unit are connected to the third row of terminals.

[0008] According to a specific implementation of the embodiment of the present application, the secondary drive unit also includes a third secondary drive unit and a fourth secondary drive unit, and the third secondary drive unit and the fourth secondary drive unit are arranged side by side with the first secondary drive unit on the printed circuit board, and the input pin of the third secondary drive unit and the output pin of the fourth secondary drive unit are connected to the second row of terminals; the output pin of the third secondary drive unit and the input pin of the fourth secondary drive unit are connected to the third row of terminals.

[0009] According to a specific implementation method of an embodiment of the present application, the first group of optical modules includes K optical modules, and the K optical modules are arranged side by side on the printed circuit board, and the two input ends of each optical module are respectively connected to the first terminal and the second terminal in the fourth row of terminals, and the two output ends of each optical module are respectively connected to the third terminal and the fourth terminal in the fourth row of terminals; wherein K is an integer greater than or equal to 1.

[0010] According to a specific implementation method of an embodiment of the present application, a first system management bus is also provided on the printed circuit board, and a first conversion chip is connected to the first system management bus. After the first conversion chip divides the first system management bus into N paths, the first conversion chip is respectively connected to each optical module in the first group of optical modules.

[0011] According to a specific implementation method of an embodiment of the present application, a first I / O interface chip and a second I / O interface chip are also connected to the first system management bus; the I / O interface of the first I / O interface chip is connected to the in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and / or the reception loss indication signal terminal of the first group of optical modules; the I / O interface of the second I / O interface chip is connected to the LED indicator light.

[0012] According to a specific implementation manner of the embodiment of the present application, the secondary drive unit is also connected to the first system management bus.

[0013] According to a specific implementation method of the embodiment of the present application, one end of the first system management bus close to the first gold finger is connected to a first jump cap optional connector; on the printed circuit board, a second jump cap optional connector and a third jump cap optional connector are arranged adjacent to the first jump cap optional connector; wherein, the second jump cap optional connector is connected to the first pin of the first gold finger, the third jump cap optional connector is connected to the second pin of the first gold finger, the first pin of the first gold finger is used to connect to the baseboard management controller on the mainboard, and the second pin of the first gold finger is used to connect to the CPU on the mainboard.

[0014] According to a specific implementation of the embodiment of the present application, a second gold finger and a second group of optical modules are provided on the printed circuit board; wherein a second group of network pins is provided on the second gold finger, and the second group of network pins is connected to the second group of optical modules.

[0015] According to a specific implementation method of an embodiment of the present application, the second group of network pins includes Q groups of sub-network pins, the second group of optical modules includes Q optical modules, each group of sub-network pins is connected to each optical module, wherein the two input pins of each group of sub-network pins are respectively connected to the two output ends of the corresponding optical module, and the two output pins of each group of sub-network pins are respectively connected to the two input ends of the corresponding optical module; wherein Q is an integer greater than or equal to 1.

[0016] According to a specific implementation method of an embodiment of the present application, a second system management bus is also provided on the printed circuit board, and a second conversion chip is connected to the second system management bus. After the second conversion chip divides the second system management bus into N paths, the second conversion chip is respectively connected to each optical module in the second group of optical modules.

[0017] According to a specific implementation method of an embodiment of the present application, a third I / O interface chip and a fourth I / O interface chip are also connected to the second system management bus; the I / O interface of the third I / O interface chip is connected to the in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and / or the reception loss indication signal terminal of the second group of optical modules; the I / O interface of the fourth I / O interface chip is connected to the LED indicator light.

[0018] According to a specific implementation method of the embodiment of the present application, one end of the second system management bus close to the second gold finger is connected to a fourth jumper optional connector; on the printed circuit board, a fifth jumper optional connector and a sixth jumper optional connector are arranged adjacent to the fourth jumper optional connector; wherein the fifth jumper optional connector is connected to the first pin of the second gold finger, the sixth jumper optional connector is connected to the second pin of the second gold finger, the first pin of the second gold finger is used to connect to the baseboard management controller on the mainboard, and the second pin of the second gold finger is used to connect to the CPU on the mainboard.

[0019] According to a specific implementation manner of the embodiment of the present application, the first group of optical modules and the second group of optical modules are respectively a plurality of SFP+ optical modules arranged side by side.

[0020] The present application also provides a CPU network interface performance test system, comprising: a mainboard and a CPU network interface performance test board, wherein the mainboard is provided with a CPU chip and a PCIE slot connected to the CPU chip, and the CPU network interface performance test board is inserted into the PCIE slot, wherein the CPU network interface performance test board is the CPU network interface performance test board described in any of the aforementioned implementation methods.

[0021] The present application also provides a CPU network interface performance testing method, comprising: a CPU network port on a mainboard sends network test data to a first group of optical modules on a test board inserted in a PCIE slot on the mainboard to perform a service stress test, a loopback test and / or a signal quality test; wherein the test board is the CPU network interface performance test board described in any of the aforementioned implementations; wherein the first row of terminals and the fourth row of terminals on the test board are connected so that the first group of network pins are connected to the first group of optical modules; and the CPU network interface performance is determined based on the test results.

[0022] According to a specific implementation method of an embodiment of the present application, it also includes: the first row of terminals and the second row of terminals on the test board are connected, and the third row of terminals and the fourth row of terminals are connected, so that the secondary drive unit is connected between the first group of network pins and the first group of optical modules to perform service stress testing, loopback testing and / or signal quality testing with the secondary drive unit.

[0023] According to a specific implementation manner of the embodiment of the present application, it also includes: monitoring status information of the first group of optical modules or the second group of optical modules.

[0024] The embodiment of the present application provides a CPU network interface performance test board, test system and test method, by providing a first gold finger, a secondary drive unit and a first group of optical modules on a printed circuit board; wherein, a first group of network pins is provided on the first gold finger, the first group of network pins is connected to a first row of terminals, the secondary drive unit is respectively connected to a second row of terminals and a third row of terminals, and the first group of optical modules is connected to a fourth row of terminals; the first row of terminals is adjacent to the second row of terminals, and the third row of terminals is adjacent to the fourth row of terminals. By connecting the first group of network pins of the test board of this embodiment to corresponding pins on a mainboard and the first group of network pins to the first group of optical modules, signal quality testing, loopback testing and service stress testing can be implemented when there are optical modules on the test link. The first row of terminals can also be used to perform loopback testing and signal quality testing. According to the test results of multiple test items, the performance of the CPU network interface is evaluated, thereby facilitating the improvement of the accuracy of testing the performance of the CPU network interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 This is a structural diagram of a CPU network interface performance test board according to an embodiment of the present application;

[0027] Figure 2 This is a schematic diagram of the CPU network interface performance test board link connection according to an embodiment of the present application;

[0028] Figure 3 This is a SMBus link topology diagram in a test board according to an embodiment of the present application;

[0029] Figure 4 This is a SMBus link topology diagram in a test board in another embodiment of the present application;

[0030] Figure 5 A flowchart of a CPU network interface performance testing method according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0032] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0033] See also Figure 1 and Figure 2 The CPU network interface performance test board of this embodiment may include:

[0034] A printed circuit board 1 is provided with a first gold finger 2, a secondary drive unit 3 and a first group of optical modules 4; wherein, a first group of network pins 5 are provided on the first gold finger 2, the first group of network pins 5 are connected to a first row of terminals 6, the secondary drive unit 3 is respectively connected to a second row of terminals 7 and a third row of terminals 8, the first group of optical modules 4 is connected to a fourth row of terminals 9, the first row of terminals 6 is adjacent to the second row of terminals 7, and the third row of terminals 8 is adjacent to the fourth row of terminals 9.

[0035] The CPU network interface performance may include the driving capability of the CPU network interface.

[0036] Printed circuit boards (PCB boards), also known as printed circuit boards, are providers of electrical connections for electronic components. Printed circuit boards usually refer to bare boards, i.e. circuit boards without components installed.

[0037] The first gold finger 2 can be composed of a plurality of golden conductive contacts. Because its surface is gold-plated and the conductive contacts are arranged like fingers, it is called a "gold finger" or Finger, and the conductive contacts can also be called pins. The size and shape of the gold finger can be determined according to actual conditions. In one example, the gold finger 2 is a standard PCIE Finger gold finger shape. The conductive contacts on the first gold finger 2 can be set as network pins, which can transmit high-speed network data. In one example, the first group of network pins 5 on the gold finger 2 can be XGBE pins.

[0038] The first group of network pins 5 may include a group of sub-network pins, or may include multiple groups of network pins. In one example, the first group of network pins includes N groups of sub-network pins, and the two input pins of each group of sub-network pins are respectively connected to the first terminal and the second terminal in the first row of terminals, and the two output pins of each group of sub-network pins are respectively connected to the third terminal and the fourth terminal in the first row of terminals; wherein N is an integer greater than or equal to 1.

[0039] The secondary driving unit 3 may include a re-timer Re-timer and a driver Re-driver; in the signal transmission of the high-speed serial channel, the Re-driver and the Re-timer can be used to ensure the quality of signal transmission; the Re-timer reconstructs the signal of the previous stage and then sends it out, generates a clock, and recovers the data; the role of the Re-driver is only to enhance the original signal and replenish energy at the physical layer.

[0040] The first group of optical modules 4 is used to transmit data sent by the mainboard CPU to an external device, or receive data sent by an external device, and can also be used to transfer data sent by the mainboard CPU to the test board of this embodiment. The first group of optical modules may include one or more than two optical modules.

[0041] The first row of terminals 6, the second row of terminals 7, the third row of terminals 8 and / or the fourth row of terminals 9 may be connection terminals on a connector. In an example, the first row of terminals 6, the second row of terminals 7, the third row of terminals 8 and / or the fourth row of terminals 9 may be terminals on a RF connector, specifically terminals of an SMA RF coaxial connector.

[0042] The CPU network interface can be configured to the corresponding network protocol for testing. In this embodiment, the CPU network interface is configured to the network protocol corresponding to the optical module. Specifically, the PU network interface can be tested as an SFP+ network interface. The performance of the CPU network interface can be determined by signal quality and network performance indicators. Specifically, it can be divided into the following situations: 1. Performance test of a network interface of a CPU when receiving and sending data; 2. Performance test of receiving and sending data between two network interfaces of a CPU; 3. Performance test of a network interface of a CPU sending data and a network interface of another CPU receiving data; 4. Performance test of a network interface of a CPU sending data and evaluating the sent data can also be performed.

[0043] In this embodiment, a first gold finger, a secondary drive unit and a first group of optical modules are provided on a printed circuit board; wherein a first group of network pins are provided on the first gold finger, the first group of network pins are connected to a first row of terminals, the secondary drive unit is respectively connected to a second row of terminals and a third row of terminals, and the first group of optical modules is connected to a fourth row of terminals; the first row of terminals is adjacent to the second row of terminals, and the third row of terminals is adjacent to the fourth row of terminals. By connecting the first group of network pins of the test board of this embodiment to corresponding pins on the mainboard and the first group of network pins to the first group of optical modules, a signal quality test, a loopback test and a service stress test can be implemented in the case where there is an optical module on the test link. The first row of terminals can also be used to perform loopback tests and signal quality tests. According to the test results of multiple test items, the performance of the CPU network interface is evaluated, thereby facilitating the improvement of the accuracy of testing the performance of the CPU network interface. In addition, in addition to being configured as a C protocol corresponding to the optical module, this embodiment can also be used to perform In addition to the performance test of the PU network interface, other network interface protocols can also be tested through the first row of terminals. In this way, a test board in this embodiment can perform multiple test items under the same protocol (network interface protocol corresponding to the optical module) to evaluate the performance of the CPU network interface, and can also perform test items configured with other network protocols, that is, a test board supports multiple test items, thereby enriching the function of the test board. In addition, since the first group of network pins are connected to the first row of terminals, the secondary drive unit is respectively connected to the third row of terminals and the fourth row of terminals, and the first group of optical modules is connected to the fourth row of terminals, in this way, the functional modular design of the first group of network pins, the secondary drive unit and the first group of optical modules is realized, so that the above modules can be flexibly combined according to the test items, and since the secondary drive unit is integrated, when testing, it can be selected to string the secondary drive unit into the test link or not according to the test needs, so that it can facilitate the early evaluation of the server whole machine product.

[0044] Another embodiment of the present application is basically the same as the above embodiment, except that the secondary drive unit of this embodiment includes a first secondary drive unit and a second secondary drive unit, the first secondary drive unit and the second secondary drive unit are arranged side by side on the printed circuit board, the input pin of the first secondary drive unit and the output pin of the second secondary drive unit are connected to the second row of terminals; the output pin of the first secondary drive unit and the input pin of the second secondary drive unit are connected to the third row of terminals.

[0045] The first secondary driving unit and the second secondary driving unit may be chips of the same type, such as a re-timer or a driver.

[0046] In this embodiment, the secondary drive unit includes a first secondary drive unit and a second secondary drive unit, the first secondary drive unit and the second secondary drive unit are arranged side by side on the printed circuit board, the input pin of the first secondary drive unit and the output pin of the second secondary drive unit are connected to the second row of terminals; the output pin of the first secondary drive unit and the input pin of the second secondary drive unit are connected to the third row of terminals. When the test board of this embodiment is used to perform a loopback test of the secondary drive units in series, the two secondary drive units can flexibly process their respective input signals separately.

[0047] Another embodiment of the present application is basically the same as the above embodiment, except that the secondary drive unit of this embodiment further includes: a third secondary drive unit and a fourth secondary drive unit, the third secondary drive unit and the fourth secondary drive unit are arranged side by side with the first secondary drive unit on the printed circuit board, the input pin of the third secondary drive unit and the output pin of the fourth secondary drive unit are connected to the second row of terminals; the output pin of the third secondary drive unit and the input pin of the fourth secondary drive unit are connected to the third row of terminals.

[0048] The third secondary driving unit and the fourth secondary driving unit may be the same type of chip, such as both may be re-timers Re-timers or both may be drivers Re-drivers. In one example, the first secondary driving unit and the second secondary driving unit may both be re-timers Re-timers, and the third secondary driving unit and the fourth secondary driving unit may both be drivers Re-drivers.

[0049] In this embodiment, by setting the third secondary drive unit and the fourth secondary drive unit, when testing, the type of secondary drive unit for realizing specific functions can be selected according to actual conditions, such as selecting a suitable solution of Re-timer and Re-driver.

[0050] Another embodiment of the present application is basically the same as the above embodiment, except that the first group of optical modules 4 of this embodiment includes K optical modules 40, and the K optical modules are arranged side by side on the printed circuit board 1, and the two input ends of each optical module 40 are respectively connected to the first terminal and the second terminal in the fourth row of terminals 9, and the two output ends of each optical module 40 are respectively connected to the third terminal and the fourth terminal in the fourth row of terminals 9; wherein K is an integer greater than or equal to 1.

[0051] By correspondingly connecting the two input ends of each optical module to the first terminal and the second terminal in the fourth row of terminals, and correspondingly connecting the two output ends of each optical module to the third terminal and the fourth terminal in the fourth row of terminals, the test board of this embodiment can realize the transmission of differential signals. Specifically, each optical module may include pins for receiving and sending signals, wherein both the received signal and the sent signal are differential signals.

[0052] See also Figure 3 In order to facilitate the acquisition of internal information of the first group of optical modules, another embodiment of the present application is basically the same as the above embodiment, except that the test board of this embodiment is further provided with a first system management bus on the printed circuit board 1, and the first system management bus is connected to a first conversion chip 10. The first conversion chip 10 divides the first system management bus into N paths and is respectively connected to each optical module in the first group of optical modules 4.

[0053] The first system management bus (SMBus) provides a control bus for system and power management tasks. In a system using SMBus, messages are sent and received between devices through SMBus instead of using separate control lines, which saves the number of device pins. In addition, using SMBus, the device can also provide its production information, tell the system its model, part number, etc., save its status for suspend events, report different types of errors, receive control parameters, and return its status, etc.

[0054] The first conversion chip 10 can divide the first system management bus into N paths, where N is greater than or equal to 2; after being divided into N paths, they are respectively connected to the corresponding optical modules in the first group of optical modules 4, so that when in use, the internal data of each optical module, such as the operating temperature of the optical module and other information, can be easily obtained.

[0055] In one example, the first conversion chip may be a system management bus expansion chip, and the specific model may be 9546.

[0056] In order to facilitate monitoring the status of the first group of optical modules and to facilitate intuitive understanding of the status of the test board, another embodiment of the present application is basically the same as the above embodiment, except that, in the test board of this embodiment, a first I / O interface chip 11 and a second I / O interface chip 12 are also connected to the first system management bus; the I / O interface of the first I / O interface chip 11 is connected to the in-place signal terminal, the transmission enable control signal terminal, the transmission failure signal terminal, and / or the reception loss signal terminal of the first group of optical modules 4; the I / O interface of the second I / O interface chip 12 is connected to the LED indicator light 13.

[0057] The first I / O interface chip 11 can be a chip with input and output expansion functions, specifically a 9555 chip. The I / O interface of the first I / O interface chip can be connected to the in-place (MODABS), transmit enable control (TXDIS), transmit failure indication (TXFAULT) and receive loss indication (RXLOS) signal pins of the first group of optical modules 4 to monitor the status of the first group of optical modules 4.

[0058] The second I / O interface chip 12 can be a chip with input and output expansion functions, specifically a 9555 chip; the I / O interface of the second I / O interface chip 12 is connected to the LED indicator light 13, and the working status of the test board can be indicated by the on and off, color of one LED indicator light or the on and off, color of more than two LED indicator lights and their different combination states, such as whether the board is working properly and what fault occurs when a fault occurs. These states can be associated with the state of the indicator light, such as green when working normally, red when abnormal, or it can flash to indicate normal, and not flash to indicate abnormal.

[0059] In order to facilitate the storage and reading of test information, in one example, a first electrically erasable programmable read-only memory is also connected to the first system management bus.

[0060] The first electrically erasable programmable read only memory (EEPROM) is a storage chip in which data is not lost after power failure. The board information can be stored in the EEPROM to facilitate reading the board information. Furthermore, the CPU network interface protocol can be configured as the interface protocol supported by the board according to the board information.

[0061] In order to configure the secondary drive unit conveniently and flexibly, in one example, the first system management bus is further connected to a secondary drive unit 3 .

[0062] In this embodiment, the performance of the secondary drive unit can be configured by connecting the secondary drive unit 3 to the first system management bus.

[0063] In order to flexibly select whether the CPU or the baseboard management controller performs configuration management on the devices connected to the first system management bus, the end of the first system management bus close to the first gold finger 2 is connected to the first jumper cap optional connector 13; on the printed circuit board 1, a second jumper cap optional connector 15 and a third jumper cap optional connector 16 are arranged adjacent to the first jumper cap optional connector 14; wherein, the second jumper cap optional connector 15 is connected to the first pin 2a of the first gold finger 2, the third jumper cap optional connector 16 is connected to the second pin 2b of the first gold finger 3, the first pin 2a of the first gold finger 2 is used to connect to the baseboard management controller on the mainboard, and the second pin 2b of the first gold finger 3 is used to connect to the CPU on the mainboard.

[0064] The PCIE Finger standard defines only one set of SMBUS signals, which can be connected to the CPU or the BMC. There are also multiple reserved (RSVD) but undefined pins on the PCIE Finger, and some motherboards define some RSVD pins as SMBUS. In one example, the first pin 2a and the second pin 2b on the test board of this embodiment can define the RSVD pin on the gold finger as SMBUS signal pins.

[0065] The first jumper cap optional connector 14, the second jumper cap optional connector 15 and / or the second jumper cap optional connector 16 may be 3-pin connectors.

[0066] The Baseboard Manager Controller (BMC) has monitoring and control functions. It operates on system hardware, such as monitoring the system's temperature, voltage, fan, power supply, etc., and making corresponding adjustments to ensure that the system is in a healthy state. It can also record various hardware information and log records to prompt users and locate subsequent problems; BMC is an independent system that does not rely on other hardware on the system (such as CPU, memory, etc.), nor does it rely on BIOS, OS, etc. (but BMC can interact with BIOS and OS, which can play a better role in platform management. There is system management software under OS that can work with BMC to achieve better management results).

[0067] When in use, the first jump cap optional connector 14 and the second jump cap optional connector 15 can be connected through a jump cap as needed, and the first jump cap optional connector 14 and the third jump cap optional connector 16 can also be connected through a jump cap.

[0068] The test board of this embodiment can be in the form of a PCIE plug-in card. In order to facilitate application inside a standard chassis, the test board of this embodiment can be designed according to the standard PCIE card size, such as the same size as a standard PCIE full-height half-length card. Further, in order to save costs and be closer to the actual situation, see Figure 1 An embodiment of the present application is basically the same as the above embodiment, except that a second gold finger 17 and a second group of optical modules 18 are provided on the printed circuit board 1; wherein a second group of network pins 19 are provided on the second gold finger 17, and the second group of network pins 19 are connected to the second group of optical modules 18.

[0069] The second group of network pins may include Q groups of sub-network pins, and the second group of optical modules includes Q optical modules 180, each group of sub-network pins is connected to each optical module, wherein the two input pins of each group of sub-network pins are respectively connected to the two output ends of the corresponding optical module, and the two output pins of each group of sub-network pins are respectively connected to the two input ends of the corresponding optical module; wherein Q is an integer greater than or equal to 1.

[0070] The second group of network pins 19 can be XGBE high-speed pins. By connecting the two input pins of each group of sub-network pins to the two output ends of the corresponding optical module, and the two output pins of each group of sub-network pins to the two input ends of the corresponding optical module, the test board of this embodiment can realize the transmission of differential signals. Specifically, each group of sub-network pins includes pins for receiving and sending signals, wherein both the received signal and the sent signal are differential signals.

[0071] See also Figure 4 In order to facilitate the acquisition of internal information of the second group of optical modules, another embodiment of the present application is basically the same as the above embodiment, except that the test board of this embodiment is also provided with a second system management bus on the printed circuit board 1, and the second system management bus is connected to a second conversion chip 20. The second conversion chip 20 divides the second system management bus into N paths and is respectively connected to each optical module in the second group of optical modules 18.

[0072] The second system management bus (SMBus) provides a control bus for system and power management tasks. In systems using SMBus, messages are sent and received between devices through SMBus instead of using separate control lines, which saves the number of device pins. In addition, using SMBus, the device can also provide its production information, tell the system its model, part number, etc., save its status for suspend events, report different types of errors, receive control parameters, and return its status, etc.

[0073] The second conversion chip 20 can divide the second system management bus into N paths, where N is greater than or equal to 2; after being divided into N paths, they are respectively connected to the corresponding optical modules in the second group of optical modules 18, so that when in use, the internal data of each optical module, such as the operating temperature of the optical module and other information, can be easily obtained.

[0074] In one example, the second conversion chip 20 may be a system management bus expansion chip, and the specific model may be 9546.

[0075] In order to facilitate monitoring the status of the second group of optical modules 18 and to facilitate intuitive understanding of the status of the test board, another embodiment of the present application is basically the same as the above embodiment, except that, in the test board of this embodiment, a third I / O interface chip 21 and a fourth I / O interface chip 22 are also connected to the second system management bus; the I / O interface of the third I / O interface chip 21 is connected to the in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and the reception loss indication signal terminal of the second group of optical modules 18; the I / O interface of the fourth I / O interface chip 22 is connected to the LED indicator light 23.

[0076] The third I / O interface chip 21 can be a chip with input and output expansion functions, specifically a 9555 chip. The IO interface of the third I / O interface chip 21 can be connected to the in-place (MODABS), transmit enable control (TXDIS), transmit failure (TXFAULT) and receive loss (RXLOS) signal pins of the second group of optical modules 18 to monitor the status of the second group of optical modules 18.

[0077] The fourth I / O interface chip 22 can be a chip with input and output expansion functions, specifically a 9555 chip; the I / O interface of the fourth I / O interface chip 22 is connected to the LED indicator light 23, and the working status of the test board can be indicated by the on and off, color of one LED indicator light or the on and off, color of more than two LED indicator lights and their different combination states, such as whether the board is working properly and what fault occurs when a fault occurs. These states can be associated with the state of the indicator light, such as green when working normally, red when abnormal, or flashing to indicate normal, and non-flashing to indicate abnormal.

[0078] In order to facilitate the storage and reading of test information, in one example, a second electrically erasable programmable read-only memory is also connected to the second system management bus.

[0079] The second electrically erasable programmable read only memory (EEPROM) is a storage chip in which data is not lost after power failure. The board information can be stored in the EEPROM to facilitate reading the board information. Furthermore, the CPU network interface protocol can be configured as the interface protocol supported by the board according to the board information.

[0080] In order to flexibly select whether the CPU or the baseboard management controller performs configuration management on the devices connected to the second system management bus, the end of the second system management bus close to the second gold finger 17 is connected to the fourth jumper optional connector 24; on the printed circuit board 1, a fifth jumper optional connector 25 and a sixth jumper optional connector 26 are arranged adjacent to the fourth jumper optional connector 24; wherein, the fifth jumper optional connector 25 is connected to the first pin 17a of the second gold finger 17, the sixth jumper optional connector 26 is connected to the second pin 17b of the second gold finger 17, the first pin 17a of the second gold finger 17 is used to connect to the baseboard management controller on the mainboard, and the second pin 17b of the second gold finger 17 is used to connect to the CPU on the mainboard.

[0081] The fourth jumper optional connector 24, the fifth jumper optional connector 25 and / or the sixth jumper optional connector 26 may be 3-pin connectors.

[0082] In one example, the first group of optical modules and the second group of optical modules are respectively a plurality of SFP+ optical modules arranged side by side.

[0083] The SFP+ optical module is an enhanced small pluggable transceiver optical module. The SFP+ optical module has an interface for plugging in an optical cable, and an optical cable can be inserted into the interface to perform a CPU network interface performance test.

[0084] See also Figure 1 The embodiment of the present application also provides a CPU network interface performance test system, including: a mainboard and a CPU network interface performance test board, the mainboard is provided with a CPU chip and a PCIE slot connected to the CPU chip, the CPU network interface performance test board is inserted into the PCIE slot, wherein the CPU network interface performance test board is the CPU network interface performance test board in the aforementioned embodiment.

[0085] The motherboard is also called the mainboard, system board, or motherboard. The motherboard is generally a rectangular circuit board on which the main circuit systems that make up the computer are installed, generally including the BIOS chip, I / O control chip, keyboard and panel control switch interface, indicator light connectors, expansion slots, DC power supply connectors for the motherboard and plug-in cards, and CPU chip socket and other components; the CPU is installed in the CPU chip socket.

[0086] In one example, the PCIE slot on the motherboard can be configured as a PCIe slot corresponding to the protocol of the CPU network interface; in another example, the BIOS configures the signal of the corresponding PCIe slot to the protocol corresponding to the optical module, specifically the protocol corresponding to SFP+.

[0087] In this embodiment, a CPU chip and a PCIE slot connected to the CPU chip are provided on the mainboard, and the CPU network interface adaptability test board is inserted into the PCIE slot, wherein the CPU network interface performance test board is the CPU network interface performance test board described in the aforementioned embodiment, and the first group of network pins is connected to the first group of optical modules, so that signal quality testing, loopback testing and service stress testing can be implemented when there are optical modules on the test link, and loopback testing and signal quality testing can also be performed by the first row of terminals. According to the test results of multiple test items, the performance of the CPU network interface is evaluated, thereby facilitating improving the accuracy of testing the CPU network interface performance.

[0088] See also Figure 2 and Figure 5 The present application also provides a CPU network interface performance testing method, including:

[0089] Step 101, the CPU network interface on the mainboard sends network test data to a test board inserted in a PCIE slot on the mainboard to perform service stress testing, loopback testing and signal quality testing; wherein the test board is the CPU network interface performance test board in the aforementioned embodiment; wherein the first row of terminals and the fourth row of terminals on the test board are connected so that the first group of network pins and the first group of optical modules are connected.

[0090] The CPU network interface may be a CPU network interface configured with a network protocol corresponding to the optical module; the network test data may include multiple data packets; the network test data sent by the CPU network interface of this embodiment may be data sent at a certain rate, such as 100M, 1000M, 10G, etc.

[0091] When performing a business stress test, the first group of optical modules in this embodiment receives network test data sent from the CPU network interface, and sends the received network test data sent from the CPU network interface to a test system having a third group of optical modules and a CPU connected to the third group of SFP+ optical modules. According to the above process, at a certain transmission rate and after a predetermined time, network performance indicators such as bit error rate, delay and / or packet loss rate are determined based on the test data sent by the CPU network interface and the test data received by another CPU network interface.

[0092] When performing a loopback test, the external input and output ports of one optical module in the first group of optical modules are connected through an optical fiber or a copper cable. The CPU network interface on the mainboard sends network test data to the test board, the optical module receives the network test data sent from the CPU network interface, and sends the network test data to the CPU network interface via the optical fiber or copper cable and the first golden finger, the CPU network interface receives the returned network test data, and determines network performance indicators such as bit error rate, delay and / or packet loss rate according to the network test data sent by the CPU network interface and the network test data received by the CPU network interface, and then determines the performance of the CPU network interface according to the network performance indicators; the external input port of an optical module A in the first group of optical modules can also be connected to the external output interface of another optical module B through the optical fiber or copper cable, the CPU network interface on the mainboard sends network test data to the test board, the optical module A receives the network test data sent from the CPU network interface, and the optical module B receives the test data sent from the optical module A via the optical fiber or copper cable, and then sends it to the CPU network interface, the CPU network interface receives the network test data sent from the optical module B, and determines network performance indicators such as bit error rate, delay and / or packet loss rate according to the network test data sent by the CPU network interface and the network test data received by the CPU network interface.

[0093] The loopback test can also be: (1) performing a near-end loopback test on a CPU network interface, correspondingly connecting the first row of terminals on the test board that are connected to the CPU network interface, the CPU network interface sends network test data, and after passing through the first gold finger and the first row of terminals, the CPU receives the network test data, and determines network performance indicators such as bit error rate, delay and / or packet loss rate based on the network test data sent and received by the CPU network interface; (2) performing a near-end loopback test on two CPU network interfaces, correspondingly connecting the first row of terminals on the test board that are connected to the CPU network interface, the CPU network interface a sends network test data, and after passing through the first gold finger and the first row of terminals, the CPU network interface b receives the network test data, and determines network performance indicators such as bit error rate, delay and / or packet loss rate based on the network test data sent by the CPU network interface a and the network test data received by the CPU network interface b.

[0094] When performing a signal quality test, the optical module test fixture is installed in an optical module in the first group of optical modules, the optical module test fixture is connected to an oscilloscope, the CPU network interface on the mainboard sends network test data to the test board, the optical module receives the network test data sent from the CPU network interface, the network test data is input into the oscilloscope through the optical module test fixture, and the high-speed oscilloscope performs eye diagram test analysis to determine the signal quality. In one example, the optical module test fixture is an SFP+ test fixture.

[0095] The signal quality test can also be performed by connecting the first row of terminals connected to the CPU network interface to an oscilloscope, and performing eye diagram test analysis on the high-speed oscilloscope to determine the signal quality.

[0096] Step 102: Determine the performance of the CPU network interface according to the test result.

[0097] The performance of the CPU network interface can be comprehensively verified or evaluated based on the results of business stress testing, loopback testing, and signal quality testing.

[0098] Another embodiment of the present application is basically the same as the above embodiment, except that the testing method of this embodiment further includes: the first row of terminals and the second row of terminals on the test board are connected, and the third row of terminals and the fourth row of terminals are connected, so that the secondary drive unit is connected between the first group of network pins and the first group of optical modules, so as to perform service stress testing, loopback testing and signal quality testing with the secondary drive unit according to the method of the above embodiment.

[0099] In the case that the CPU network interface performance is insufficient, a secondary driver chip can be added to conduct relevant tests. Based on the test data and the performance of the secondary driver chip in the test, the performance of the CPU network interface can be improved accordingly, or a reference for the motherboard design can be provided, as well as convenience for the early evaluation of the server product.

[0100] In order to monitor the optical modules when performing the CPU network interface performance test, the method of this embodiment further includes: monitoring the status information of the first group of optical modules or the second group of optical modules.

[0101] The in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and / or the reception loss indication signal terminal of the first group of optical modules or the second network interface can be monitored, and the internal state of the first group of optical modules or the second network interface can also be monitored; specifically, the monitoring can be performed through the first conversion chip or the second conversion chip.

[0102] The CPU network interface can also be configured to other network protocols (protocols other than the protocols corresponding to the optical module) to perform loopback tests and signal quality tests: (1) Perform a near-end loopback test on the CPU network interface, connect the first row of terminals on the test board that are connected to the CPU network interface, and the CPU network interface sends network test data. After passing through the first gold finger and the first row of terminals, the CPU receives the network test data. Based on the network test data sent and received by the CPU network interface, determine network performance indicators such as bit error rate, delay and / or packet loss rate, etc.; (2) Perform two The near-end loopback test of the CPU network interface is to connect the first row of terminals connected to the CPU network interface on the test board to the corresponding connection, and the CPU network interface a sends the network test data. After passing through the first gold finger and the first row of terminals, the CPU network interface b receives the network test data. According to the network test data sent by the CPU network interface a and the network test data received by the CPU network interface b, the network performance indicators such as bit error rate, delay and / or packet loss rate, etc. are determined; (3) the first row of terminals connected to the CPU network interface is connected to an oscilloscope, and the high-speed oscilloscope performs eye diagram test analysis to determine the signal quality.

[0103] Based on the above test results, the performance of the CPU network interface is verified and evaluated.

[0104] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0105] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0106] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A CPU network interface performance test board, characterized in that: The CPU network interface performance includes the driving capability of the CPU network interface; the CPU network interface performance test board includes: a printed circuit board, on which a first gold finger, a secondary drive unit and a first group of optical modules are arranged; wherein a first group of network pins are arranged on the first gold finger, the first group of network pins are connected to a first row of terminals, the secondary drive unit is respectively connected to a second row of terminals and a third row of terminals, and the first group of optical modules is connected to a fourth row of terminals; wherein the first row of terminals is adjacent to the second row of terminals, and the third row of terminals is adjacent to the fourth row of terminals; The printed circuit board is also provided with a first system management bus, to which a first conversion chip is connected. The first conversion chip divides the first system management bus into N paths, and the N paths are respectively connected to each optical module in the first group of optical modules; wherein N is greater than or equal to 2.

2. The test board according to claim 1, characterized in that: The first group of network pins includes N groups of sub-network pins, the two input pins of each group of sub-network pins are respectively connected to the first terminal and the second terminal in the first row of terminals, and the two output pins of each group of sub-network pins are respectively connected to the third terminal and the fourth terminal in the first row of terminals; wherein N is an integer greater than or equal to 1.

3. The test board according to claim 1, characterized in that: The secondary drive unit includes a first secondary drive unit and a second secondary drive unit, the first secondary drive unit and the second secondary drive unit are arranged side by side on the printed circuit board, the input pin of the first secondary drive unit and the output pin of the second secondary drive unit are respectively connected to the second row of terminals; the output pin of the first secondary drive unit and the input pin of the second secondary drive unit are respectively connected to the third row of terminals.

4. The test board according to claim 3, characterized in that: The secondary drive unit also includes a third secondary drive unit and a fourth secondary drive unit, which are arranged side by side with the first secondary drive unit on the printed circuit board, and the input pin of the third secondary drive unit and the output pin of the fourth secondary drive unit are respectively connected to the second row of terminals; the output pin of the third secondary drive unit and the input pin of the fourth secondary drive unit are respectively connected to the third row of terminals.

5. The test board according to claim 1, characterized in that: The first group of optical modules includes K optical modules, which are arranged side by side on the printed circuit board, and the two input ends of each optical module are respectively connected to the first terminal and the second terminal in the fourth row of terminals, and the two output ends of each optical module are respectively connected to the third terminal and the fourth terminal in the fourth row of terminals; wherein K is an integer greater than or equal to 1.

6. The test board according to claim 1, characterized in that: The first system management bus is also connected to a first I / O interface chip and a second I / O interface chip; The I / O interface of the first I / O interface chip is connected to a presence signal terminal, a transmission enable control signal terminal, a transmission failure indication signal terminal, and / or a reception loss indication signal terminal of the first group of optical modules; The I / O interface of the second I / O interface chip is connected to the LED indicator light.

7. The test board according to claim 1, characterized in that: The secondary driving unit is also connected to the first system management bus.

8. The test board according to claim 1, characterized in that: An end of the first system management bus close to the first gold finger is connected to a first jumper cap optional connector; On the printed circuit board, a second jumper cap optional connector and a third jumper cap optional connector are arranged adjacent to the first jumper cap optional connector; wherein the second jumper cap optional connector is connected to the first pin of the first gold finger, and the third jumper cap optional connector is connected to the second pin of the first gold finger, the first pin of the first gold finger is used to connect to the baseboard management controller on the mainboard, and the second pin of the first gold finger is used to connect to the CPU on the mainboard.

9. The test board according to claim 1, characterized in that: A second gold finger and a second group of optical modules are arranged on the printed circuit board; wherein a second group of network pins are arranged on the second gold finger, and the second group of network pins are connected to the second group of optical modules.

10. The test board according to claim 9, characterized in that: The second group of network pins includes Q groups of sub-network pins, and the second group of optical modules includes Q optical modules. Each group of sub-network pins is connected to each optical module, wherein the two input pins of each group of sub-network pins are respectively connected to the two output ends of the corresponding optical module, and the two output pins of each group of sub-network pins are respectively connected to the two input ends of the corresponding optical module; wherein Q is an integer greater than or equal to 1.

11. The test board according to claim 9, characterized in that: The printed circuit board is also provided with a second system management bus, to which a second conversion chip is connected. The second conversion chip divides the second system management bus into N paths, and the N paths are respectively connected to the respective optical modules in the second group of optical modules.

12. The test board according to claim 11, characterized in that: The second system management bus is also connected to a third I / O interface chip and a fourth I / O interface chip; The I / O interface of the third I / O interface chip is connected to the in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and / or the reception loss indication signal terminal of the second group of optical modules; The I / O interface of the fourth I / O interface chip is connected to the LED indicator light.

13. The test board according to claim 11, characterized in that: An end of the second system management bus close to the second gold finger is connected to a fourth jumper optional connector; On the printed circuit board, a fifth jumper optional connector and a sixth jumper optional connector are arranged adjacent to the fourth jumper optional connector; wherein the fifth jumper optional connector is connected to the first pin of the second gold finger, and the sixth jumper optional connector is connected to the second pin of the second gold finger, the first pin of the second gold finger is used to connect to the baseboard management controller on the mainboard, and the second pin of the second gold finger is used to connect to the CPU on the mainboard.

14. The test board according to claim 9, characterized in that: The first group of optical modules and the second group of optical modules are respectively a plurality of SFP+ optical modules arranged side by side.

15. A CPU network interface performance test system, characterized in that: include: A main board and a CPU network interface performance test board, wherein the main board is provided with a CPU chip and a PCIE slot connected to the CPU chip, and the CPU network interface performance test board is inserted into the PCIE slot, wherein the CPU network interface performance test board is the CPU network interface performance test board as described in any one of claims 1-14.

16. A CPU network interface performance testing method, characterized in that: include: The CPU network port on the mainboard sends network test data to the first group of optical modules on the test board inserted in the PCIE slot on the mainboard to perform service stress testing, loopback testing and / or signal quality testing; wherein the test board is the CPU network interface performance test board according to any one of claims 1 to 14; wherein the first row of terminals and the fourth row of terminals on the test board are connected so that the first group of network pins are connected to the first group of optical modules; Based on the test results, determine the CPU network interface performance.

17. The testing method according to claim 16, characterized in that: Also includes: The first row of terminals on the test board is connected to the second row of terminals, and the third row of terminals is connected to the fourth row of terminals, so that the secondary drive unit is connected between the first group of network pins and the first group of optical modules to perform service stress testing, loopback testing and / or signal quality testing with the secondary drive unit.

18. The testing method according to claim 16, characterized in that: Also includes: Monitor status information of the first group of optical modules.

19. The testing method according to claim 16, characterized in that: The test board is the CPU network interface performance test board according to any one of claims 9 to 14; The method further includes: monitoring status information of the second group of optical modules.

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