Semiconductor device with embedded magnetic flux concentrator

Abstract

Semiconductor devices with embedded magnetic flux concentrators are disclosed. The invention relates to a magnetic flux concentrator (MFC) structure comprising a substrate, a first metal layer disposed on or above the substrate, and a second metal layer disposed on or above the first metal layer. Each metal layer comprises (i) a first wire layer comprising first wires that conduct an electrical signal, and (ii) a first dielectric layer disposed on the first wire layer. The magnetic flux concentrator is at least partially disposed in the first metal layer, the second metal layer, or both the first and second metal layers. The structure can comprise an electronic circuit or a magnetic sensor with a sense plate. The structure can comprise a transformer or an electromagnet with suitable control circuitry. The magnetic flux concentrator can comprise a metal stress reduction layer in the first or second wire layer and a core formed by electroplating onto the stress reduction layer.

Description

Technical Field

[0001] This invention generally relates to the field of semiconductor devices having magnetic flux concentrators and magnetic sensors. Background Technology

[0002] Sensors are widely used in electronic devices to measure environmental properties and report measured sensor values. Specifically, magnetic sensors are used, for example, in transportation systems such as automobiles to measure magnetic fields. Magnetic sensors can comprise Hall effect sensors that generate an output voltage proportional to the applied magnetic field, or they can comprise magnetoresistive materials whose resistance changes in response to an external magnetic field. In many applications, it is desirable for magnetic sensors to be small and sensitive and integrated with electronic processing circuitry to reduce the overall size of the magnetic sensor and provide improved measurement and integration into external electronic systems.

[0003] US9857437 B2 describes a Hall effect magnetic sensor for measuring magnetic fields, comprising an integrated circuit formed of a semiconductor material on a substrate, an insulating layer, and an adhesive layer. The adhesive layer and insulating layer are formed on the integrated circuit substrate, and a Hall effect sensing element is located on the adhesive layer. A passivation layer is formed above the Hall effect sensing element. JP2017166926 teaches a magnetic flux converging plate on an adhesive layer coated on a semiconductor substrate, the semiconductor substrate having a magnetic sensor located on opposite sides of the semiconductor substrate. US9018028 B2 discloses a magnetic sensor having a substrate with a Hall sensor element, a protective layer disposed on the substrate, a base layer on the protective layer, and an integrated magnetic converging element on the base layer.

[0004] US6545462B2 describes a sensor for detecting the direction of a magnetic field, comprising a magnetic flux concentrator and a Hall element. The magnetic flux concentrator is a metallic structure with soft magnetic properties that can amplify a magnetic field (such as a planar magnetic field) and can be used to convert the field into a differential vertical field. The Hall element is arranged in a region near the edge of the magnetic flux concentrator. The magnetic flux concentrator is disposed on a semiconductor die (e.g., a CMOS integrated circuit), in which the Hall effect sensor is formed in a vertical or horizontal configuration. The magnetic flux concentrator is positioned above the semiconductor die.

[0005] US7358724B2 describes a substrate with a recess in which a magnetic material is disposed. The magnetic material forms a magnetic flux concentrator, and a magnetic field sensing element can be positioned close to the recess.

[0006] Integrated circuits can have very small components or structures, for example, with dimensions of tens of micrometers or even smaller. Therefore, it is also desirable to reduce the size of integrated magnetic sensors, but it may be difficult to combine magnetic sensing structures with magnetic flux concentrators to provide sufficient sensitivity.

[0007] Magnetic flux concentrators (MFCs) are also known as integrated magnetic concentrators (IMCs).

[0008] Therefore, there is a need for space-efficient and small structures and effective methods to provide magnetic flux concentrators for a variety of purposes, including magnetic field sensing. Summary of the Invention

[0009] The purpose of embodiments of the present invention is to provide a structure and method for embedding a magnetic flux concentrator in an integrated circuit in a space-efficient manner.

[0010] The above objectives are achieved by the solution according to the present invention.

[0011] According to some embodiments of the present invention, a magnetic flux concentrator structure includes: a substrate; a first metal layer comprising: (i) a first conductive layer disposed on or above the substrate, the first conductive layer including a first conductive line for conducting electrical signals; and (ii) a first dielectric layer disposed on the first conductive layer; a second metal layer comprising: (i) a second conductive layer disposed on or above the first metal layer, the second conductive layer including a second conductive line for conducting electrical signals; and (ii) a second dielectric layer disposed on the second conductive layer; and a magnetic flux concentrator (MFC) at least partially disposed in the first metal layer, at least partially disposed in the second metal layer, or at least partially disposed in both the first metal layer and the second metal layer. The MFC may be disposed on the first conductive line or the second conductive line, or may include the first conductive line or the second conductive line.

[0012] According to some embodiments of the present invention, the magnetic flux concentrator is at least partially disposed in the first conductive layer of the first metal layer, at least partially disposed in the second conductive layer of the second metal layer, or at least partially disposed in both the first conductive layer and the second conductive layer.

[0013] According to some embodiments, (i) the flux concentrator has a lateral dimension of 130 micrometers or less, 100 micrometers or less, or 50 micrometers or less, (ii) the flux concentrator has a thickness of 15 micrometers or less, 10 micrometers or less, or 5 micrometers or less, or (iii) both of (i) and (ii).

[0014] According to some embodiments of the present invention, the second dielectric layer includes an MFC via, and a magnetic flux concentrator is at least partially disposed in the MFC via.

[0015] According to some embodiments of the invention, one or more wires are disposed in or on a substrate, forming one or more coils surrounding a magnetic flux concentrator. The one or more coils surrounding the magnetic flux concentrator may form a transformer or an electromagnet.

[0016] According to some embodiments of the present invention, the substrate is a semiconductor substrate, the semiconductor substrate including electronic circuitry disposed in or on the semiconductor substrate, and wherein the electronic circuitry has a feature size less than or equal to 200 nm, less than or equal to 180 nm, or less than or equal to 110 nm. According to some embodiments of the present invention, (i) a first wire is electrically connected to the electronic circuitry, (ii) a second wire is electrically connected to the electronic circuitry, or (iii) both of (i) and (ii).

[0017] According to some embodiments of the present invention, the magnetic flux concentrator structure includes a magnetic sensor that is at least partially disposed in a first metal layer, at least partially disposed between a substrate and the first metal layer, at least partially disposed in the substrate, or at least partially disposed on a side of the substrate opposite to the magnetic flux concentrator. According to some embodiments of the present invention, (i) a first wire is electrically connected to the magnetic sensor, (ii) a second wire is electrically connected to the magnetic sensor, or (iii) both of (i) and (ii). According to some embodiments of the present invention, at least a portion of the magnetic sensor is within the range of 10 micrometers, 8 micrometers, 5 micrometers, 3 micrometers, 2 micrometers, or 1 micrometer of the magnetic flux concentrator. According to some embodiments of the present invention, the magnetic sensor is a Hall effect sensor including a sensing plate. The sensing plate may be disposed in a doped semiconductor region of the substrate, for example, disposed below the first metal layer as an n-doped diffusion portion of the substrate in a CMOS circuit or magnetic sensor circuit. This portion of the substrate may include other dielectric and conductive layers.

[0018] According to some embodiments of the present invention, a magnetic flux concentrator includes a core at least partially disposed in a second dielectric layer and a stress-reducing layer disposed in a second conductive layer. According to some embodiments of the present invention, the stress-reducing layer has greater ductility than the magnetic flux concentrator, and is conductive, or is a ductile metal (e.g., aluminum) found in CMOS or magnetic sensor circuits, or includes a ductile metal (e.g., aluminum) found in CMOS or magnetic sensor circuits, or any combination thereof. According to some embodiments, the stress-reducing layer is multilayered, comprising a conductive and ductile first layer and a second layer as a seed layer disposed on the first layer. The seed layer can provide a compatible surface for electroplating the core and can be electrically connected to the substrate to provide electroplating current.

[0019] According to some embodiments of the present invention, the magnetic flux concentrator is electrically connected to an electrical connector in the first metal layer or electrically connected to a substrate, for example, the stress reduction layer is electrically contacted with the core and is in electrical contact with a first wire in the substrate or the first metal layer for electroplating the core.

[0020] According to some embodiments of the present invention, the magnetic flux concentrator is mechanically isolated from the dielectric layer(s) formed therein.

[0021] According to some embodiments of the present invention, a magnetic flux concentrator structure is constructed by providing a substrate, forming one or more metal layers (each metal layer including a conductive layer and a dielectric layer disposed above the conductive layer) on or over the substrate, forming an MFC via in one or more dielectric layers, and disposing a magnetic flux concentrator in the MFC via. According to embodiments of the present invention, the magnetic flux concentrator includes a stress-reducing layer and a core, and the magnetic flux concentrator is disposed in the MFC via by etching one or more dielectric layers to expose conductive lines having two-dimensional regions (e.g., contact regions or contact pads) in the conductive layer. The exposed conductive lines are electrically connected to a current source, and the core is electroplated on the two-dimensional regions of the exposed conductive lines. A stress-reducing layer may be formed between the core and the substrate in the region of the exposed conductive lines.

[0022] According to some embodiments of this disclosure, the electrical connection between the current source and the exposed wires can be electrically connected to a sealing ring for controlling a CMOS circuitry of the MFC. Thus, the exposed areas are in electrical contact with the wafer substrate, and the sealing ring provides substrate contact for all metal layers, through which plating current is supplied to all exposed areas by simply connecting the wafer edge to the current source. The substrate distributes the plating current to all sealing rings, and then from the sealing rings to all exposed areas. Because the sealing rings have high conductivity and a relatively large contact area, they reduce the resistance of the substrate. Therefore, according to some embodiments, the magnetic flux concentrator structure includes electronic circuitry and a sealing ring disposed around the electronic circuitry, and the seed layer is electrically connected to the substrate through the sealing ring.

[0023] According to some embodiments of this disclosure, a method of manufacturing a magnetic flux concentrator structure includes: providing a substrate; disposing a first metal layer on or above the substrate, the first metal layer comprising: (i) a first conductive layer disposed on or above the substrate, the first conductive layer including a first conductive line for conducting electrical signals, and (ii) a first dielectric layer disposed on the first conductive layer; disposing a second metal layer on or above the first metal layer, the second metal layer comprising: (i) a second conductive layer disposed on or above the first metal layer, the second conductive layer including a second conductive line for conducting electrical signals, and (ii) a second dielectric layer disposed on the second conductive layer; and disposing the magnetic flux concentrator at least partially in the first metal layer, at least partially in the second metal layer, or at least partially in both the first metal layer and the second metal layer. Some embodiments include disposing an electroplated seed layer on the second conductive layer prior to disposing the second dielectric layer.

[0024] In embodiments of the present invention, the magnetic flux concentrator is at least partially disposed in the first conductive layer of the first metal layer, at least partially disposed in the second conductive layer of the second metal layer, or at least partially disposed in both the first conductive layer and the second conductive layer.

[0025] Embodiments of the present invention provide a spatially efficient and small magnetic sensor with an integrated magnetic flux concentrator that provides improved sensitivity in a semiconductor device.

[0026] For the purpose of summarizing the invention and the advantages achieved beyond those of the prior art, certain objects and advantages of the invention have been described above. It should be understood, of course, that not all such objects or advantages can be achieved according to any particular embodiment of the invention. Therefore, for example, those skilled in the art will recognize that the invention can be embodied or practiced in a manner that achieves or optimizes one or more advantages as taught herein, without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0027] The above and other aspects of the invention will be apparent from the embodiments described herein(s) ...)(s)(s)(s))(s)(s))(s)(s)( Attached Figure Description

[0028] The foregoing and other objects, aspects, features and advantages of this disclosure will become more apparent and better understood by referring to the following description taken in conjunction with the accompanying drawings.

[0029] Figure 1 This is a cross-sectional view including a magnetic sensor according to an illustrative embodiment of the present invention.

[0030] Figure 2 It is based on something like Figure 1 Partial plan view of an illustrative embodiment of the present invention.

[0031] Figure 3 A cross-sectional view showing a coil and a conductor redistribution layer according to an illustrative embodiment of the present invention.

[0032] Figure 4 A cross-sectional view showing an illustrative embodiment of the present invention, including an encapsulation layer and a wire redistribution layer.

[0033] Figure 5 A cross-sectional view showing a coil and transformer / electromagnetic circuit according to an illustrative embodiment of the present invention.

[0034] Figure 6 Indicates according to something like Figure 5 Partial plan view of an illustrative embodiment of the present invention.

[0035] Figure 7 A cross-sectional view including a coil, showing an illustrative embodiment of the present invention.

[0036] Figure 8 A cross-sectional view showing a magnetic flux concentrator and a conductive stress reduction layer according to an illustrative embodiment of the present invention.

[0037] Figure 9 and Figure 10 A flowchart illustrating a method according to an illustrative embodiment of the present invention.

[0038] Figure 11 A detailed cross-sectional view showing the magnetic flux concentrator and through-hole according to an illustrative embodiment of the present invention.

[0039] Figure 12 The diagram shows a cross-sectional view that is useful for understanding the prior art and embodiments of the present invention. Detailed Implementation

[0040] The invention will be described with reference to specific embodiments and particular drawings, but the invention is not limited thereto but is defined only by the claims.

[0041] Furthermore, the terms "first," "second," etc., used in the specification and claims are used to distinguish between similar elements and are not necessarily used to describe an order in time, space, rank, or any other way. It should be understood that the terms thus used are interchangeable where appropriate, and the embodiments of the invention described herein can be operated in an order different from that described or illustrated herein.

[0042] It should be noted that the term "comprising" as used in the claims should not be construed as limiting oneself to the means listed thereafter; it does not exclude other elements or steps. Therefore, the term should be interpreted as specifying the presence of the features, integers, steps, or components stated as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps, or components, or groups thereof. Thus, the scope of the statement "an apparatus comprising means A and B" should not be limited to an apparatus consisting solely of components A and B. This means that for the purposes of this invention, the only relevant components of the apparatus are A and B.

[0043] Throughout this specification, the reference to "an embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the phrase "in an embodiment" or "in an embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, but may refer to the same embodiment. Furthermore, in one or more embodiments, as will be obvious to those skilled in the art according to this disclosure, particular features, structures, or characteristics can be combined in any suitable manner.

[0044] Similarly, it should be understood that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, drawing, or description for the purpose of simplification and to aid in understanding one or more of the various inventive aspects. However, this method of disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the appended claims, inventive aspects lie in fewer features than all the features of a single foregoing disclosed embodiment. Therefore, the claims appended to the detailed description are thus explicitly incorporated into that detailed description, wherein each claim itself represents a separate embodiment of the invention.

[0045] Furthermore, while some embodiments described herein include features that are included in other embodiments but not others, it will be understood by those skilled in the art that combinations of features from different embodiments are intended to fall within the scope of the invention and form different embodiments. For example, any embodiment of the claimed embodiments in the appended claims can be used in any combination.

[0046] It should be noted that the use of specific terms in describing certain features or aspects of the invention should not be construed as implying that the term is redefined herein to be limited to any particular characteristic of the invention that includes the term and is associated with it.

[0047] Numerous specific details are set forth in the description provided herein. However, it should be understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.

[0048] Embodiments of the present invention provide structures and methods for integrating a magnetic flux concentrator (MFC) or integrated magnetic concentrator (IMC) within a metal layer disposed in an integrated circuit structure. The integrated circuit may include a semiconductor substrate and a patterned metal layer in which active electronic components are formed, the patterned metal layer interconnecting the electronic components on or above the semiconductor substrate. The MFC in the metal layer can be used for a variety of purposes, including, for example, magnetic field sensing, alternating current voltage conversion (transformer), voltage conversion, and active magnetic field generation. Circuitry and wiring may be provided with the MFC to control the integrated circuit structure, for example, to sense magnetic fields or otherwise employ magnetic fields in electronic or magnetic systems. Some embodiments of this disclosure may use a Hall effect magnetic sensor.

[0049] By integrating MFCs into the integrated circuit structure within the conventional integrated circuit workflow, smaller and more sensitive devices can be provided at a reduced manufacturing cost. Embodiments of the present invention provide a structure and method for embedding a magnetic flux concentrator within a metal layer stack of an integrated circuit, thereby reducing the distance between the magnetic flux concentrator and the magnetic sensor beneath or within the metal stack, resulting in a smaller device size, increased device sensitivity, and fewer manufacturing steps. Embodiments of the present invention also enable inductors or wire coils to be formed within the metal layers of the integrated circuit.

[0050] Integrated circuits are widely used in electronic systems to control or operate systems or to sense, respond to, or influence environmental properties. These integrated circuits are typically formed in semiconductor substrates. With appropriate processing, semiconductor substrates can provide sensing and operating electronic circuits (e.g., control circuits and Hall effect magnetic sensors). In a typical integrated circuit manufacturing process, transistors are first formed directly in a semiconductor substrate (e.g., a silicon substrate) using front-end processes. These processes, for example, form doped transistor sources and drains and form dielectric gate structures on the processing side of the semiconductor substrate. Hall effect plates are also typically formed on the processing side of the semiconductor substrate. Once the various semiconductor devices have been fabricated, they are electrically connected to form electrically connected circuits by wires formed in one or more patterned metal layers, which are stacked on the semiconductor processing side. The metal layers are typically constructed using back-end processes by blanket deposition of metal layers and then using photoresist patterned through a mask that can be etched to form patterned wires. Multiple metal layers with patterned wires are typically required. For complex circuits, four or more layers may be used. The wires in each metal layer can be isolated from the wires in the layers above or below using dielectric layers. Electrical interconnections between layers are formed by etching and filling or coating vias with conductive metal in intermediate dielectric layers. Typically, the individual layers are planarized to provide flat surfaces, allowing photolithography equipment to maintain precise focus on large areas of the current semiconductor wafer. Conductors within the metal layers can electrically conduct power and ground signals, as well as analog or digital information signals, such as control or data signals. These conductors can be information signal conductors, or they can form ground or power planes, or they can have effective two-dimensional regions as contact pads or contact areas.

[0051] refer to Figure 12 A conventional magnetic flux concentrator (MFC) 51 includes a core 53 disposed on a polyimide layer 55, which is disposed on a semiconductor substrate 20. A magnetic sensor 60 may include a Hall effect plate through which current is conducted in the magnetic field concentrated by the MFC 51, and the voltage across the Hall effect plate is measured to determine the magnetic field strength. The Hall effect plate is typically disposed at the edge of the core 53. The MFC 51 and an external ambient magnetic field or a generated magnetic field can be combined to provide circuitry (e.g., analog or digital circuitry, CMOS circuitry, bipolar circuitry, or mixed-signal circuitry) to control, sense, or otherwise employ electrical signals or currents. Such circuitry may also include dielectric layers and conductive layers.

[0052] Because the core 53 typically comprises a magnetic metal (such as iron or cobalt) or an iron alloy (such as nickel-iron) and has a coefficient of thermal expansion (CTE) that is completely different from that of the substrate 20 (e.g., a semiconductor substrate) on which the MFC 51 is disposed, the mechanical stress generated by the difference between the CTE of the MFC 51 and the CTE of the substrate 20 can cause the device to malfunction when the device is operated and heated. To help mitigate such mechanical stress, a stress-reducing layer, such as an organic material (e.g., polyimide) layer 55, can be provided between the MFC 51 and the substrate 20. Typical integrated circuits in the prior art employ one or more protective passivation layers and stress buffers (such as polyimide layer 55) placed between the flux concentrator core 53 and the passivation elements to ensure that the thermal expansion of the flux concentrator core 53 relative to the substrate 20 does not damage the passivation elements of the circuit.

[0053] The magnetic gain of the flux concentrator is proportional to the ratio of its diameter to its thickness and the distance from the edge of the flux concentrator to the magnetic sensor. Therefore, in a conventional structure, the distance between the surface of the substrate 20 with the Hall effect plate and the edge of the flux concentrator 53 is determined by the thickness of the metal layer stack 48 of the integrated circuit and the stress buffer layer (e.g., polyimide layer 55), which is, for example, 12 micrometers or greater in a CMOS integrated circuit having more than four metal layers and a polyimide stress reduction layer.

[0054] therefore, Figure 12 The conventional structure illustrated herein (and cited, for example, in US6545462) has limitations, particularly in the context of small integrated circuits. Integrated circuits typically employ passivation and dielectric layers between interconnect layers (e.g., wire layers with patterned conductors) and active element layers (e.g., transistors). These passivation and dielectric layers do not shrink in size as interconnect and active elements decrease due to improvements in photolithography, and the number of metal layers 48 in integrated circuits tends to increase due to the increasing number of transistors. Consequently, the distance between the Hall effect plate and the flux concentrator 51 increases, thus requiring a relatively large Hall effect plate. Therefore, the Hall effect plate cannot be made smaller due to improvements in circuit and wire resolution, and ultimately becomes too large to be cost-effective in integrated circuits and too far from the flux concentrator 50 to provide sufficient sensitivity. This problem becomes increasingly severe as the resolution (feature size) of integrated circuits reaches 200 nm or smaller, such as 180 nm or smaller, or 110 nm or smaller, especially for digital CMOS integrated circuits.

[0055] In order to overcome this problem, and according to Figure 1 and Figure 2As illustrated in the embodiment of this disclosure, the magnetic flux concentrator (MFC) structure 10 includes a magnetic flux concentrator 50 disposed within a metal layer 48, which is disposed on or above an integrated circuit substrate 20. The substrate 20 may be a semiconductor substrate and may include integrated electronic circuitry 22 and other electronic components (such as a Hall effect plate), the integrated electronic circuitry 22 including active transistors and diodes. The metal layer 48 includes at least a first metal layer 41 disposed on or above the substrate 20 and a second metal layer 42 disposed on or above the first metal layer 41. The first metal layer 41 includes (i) a first conductive layer 31 disposed on or above the substrate 20, the first conductive layer 31 including patterned first conductive lines 71 for conducting electrical signals, and (ii) a first dielectric layer 81 disposed on the first conductive layer 31 on the side of the first conductive layer opposite to the substrate 20. The first conductive layer 31 can be directly disposed on the substrate 20 or disposed on a layer disposed on the substrate 20. For example, the substrate 20 can be coated with a planarized dielectric layer 80 or include a planarized dielectric layer 80 as the surface of the substrate 20. The dielectric layer 80 may also include additional conductors or conductor connections. The first conductor 71 conducts electrical signals, such as power, ground, or information signals. The second metal layer 42 is disposed on the first metal layer 41 and includes (i) the second conductive layer 32, which includes second conductors 72 for conducting electrical signals, and (ii) the second dielectric layer 82 disposed on the second conductive layer, which is disposed on the side of the second conductive layer 32 opposite to the substrate 20, the first conductive layer 31, and the first dielectric layer 81. Like the first conductive layer 31, the second conductive layer 32 conducts electrical signals, such as power, ground, or information signals. The second conductive layer 32 can be patterned and can include individual conductors 78 or electrical buses. Generally, the conductor 78 shown in the figure can be a single conductor 78 conducting a single signal or multiple conductors conducting multiple signals (e.g., a bus including multiple conductors connected in parallel). The flux concentrator 50 is at least partially disposed in the first metal layer 41, at least partially disposed in the second metal layer 42, or at least partially disposed in both the first metal layer 41 and the second metal layer 42. In some embodiments, additional metal layers 48 (each additional metal layer 48 includes a dielectric layer 88 above the conductor layer 38) are disposed in a layer above the second metal layer 42 such that the flux concentrator 50 extends through the additional metal layers 48. In some embodiments, the flux concentrator 50 exists only in some of the metal layers 48, such as the first metal layer 41, or as... Figure 3As shown, there are a second metal layer 42 and a third metal layer 43. The magnetic flux concentrator 50 can be disposed on a conductor 78 in any conductor layer 38 of the metal layer 48 or on a conductor 78 in any conductor layer 38 of the metal layer 48.

[0056] As described herein, (multiple) conductor layers 38 generally refer to any conductor layer in the flux concentrator structure 10 (e.g., first conductor layer 31 and second conductor layer 32). (Multiple) metal layers 48 generally refer to any metal layer in the flux concentrator structure 10 (e.g., first metal layer 41 and second metal layer 42). (Multiple) dielectric layers 88 generally refer to any dielectric layer in the flux concentrator structure 10 (e.g., planarized dielectric layer 80, first dielectric layer 81, and second dielectric layer 82). (Multiple) conductors 78 generally refer to any conductor or combination of conductors such as an electrical bus formed by patterning any conductor layer 38. (e.g., first conductor 71 or second conductor 72) The conductors 78 in the different conductor layers 38 can be electrically connected via vias 70. The via 70 is a conductive connection between any dielectric layer 88 of conductors 78 in different conductor layers 38. The via 70 can be formed by etching holes in the dielectric layers 88 using photolithography and coating or filling the holes with conductive metals such as tungsten, titanium, copper or aluminum.

[0057] Conventionally, "metal layer" may refer only to the patterned conductive layer 38, but as used herein, "metal layer 48" refers to both the conductive layer 38 and the dielectric layer 88 coated on the conductive layer 38 (e.g., the first conductive layer 31 and the first dielectric layer 81 form the first metal layer 41, and the second conductive layer 32 and the second dielectric layer 82 form the second metal layer 42, and so on), such that... Figure 1 As shown, the magnetic flux concentrator 50 is disposed in at least one of the second conductive layer 32 and the second dielectric layer 82, or in both the second conductive layer 32 and the second dielectric layer 82, such that the magnetic flux concentrator 50 is at least partially located in the second metal layer 42. According to some embodiments of this disclosure, the magnetic flux concentrator 50 is also at least partially located in the first metal layer 41 (e.g., Figure 8 (as shown in the diagram). In some embodiments, the top dielectric layer 88 or the encapsulation layer 92 forms the surface of the substrate 20.

[0058] The magnetic flux concentrator 50 is used to concentrate a magnetic field and make the concentrated magnetic field easier to detect and measure. In some embodiments, the magnetic flux concentrator 50 may include a core 52 at least partially disposed in the first metal layer 41 or the second metal layer 42 or both the first metal layer 41 and the second metal layer 42, for example, comprising a magnetic metal (such as iron or cobalt), or a metal alloy comprising a magnetic metal (such as nickel-iron). The second dielectric layer 82 may include an MFC via 56 (a hole in the second dielectric layer 82), in which the magnetic flux concentrator 50 may be at least partially disposed. For example, the core 52 may be disposed in the MFC via 56. The magnetic flux concentrator 50 may also include, for example, a stress reduction layer 54 disposed in contact with the core 52. The stress reduction layer 54 may be disposed in the second metal layer 42, and specifically in the second conductive layer 32 (such as...). Figure 1 (as shown) or in the first conductor layer 31 (as shown) Figure 8 As shown in the following discussion, the magnetic flux concentrator 50 can also be disposed in the MFC via 56, for example at the bottom of the MFC via 56 (the bottom of the MFC via 56 is the portion of the MFC via 56 closest to the substrate 20). Therefore, in some embodiments of this disclosure, the magnetic flux concentrator 50 is at least partially present in the second metal layer 42 (and thus in both the second conductive layer 32 and the second dielectric layer 82, including the second metal layer 42). In some embodiments of this disclosure, the magnetic flux concentrator 50 is at least partially present in the first metal layer 41 and the second metal layer 42 (and thus in the first conductive layer 31 and the first dielectric layer 81 including the first metal layer 41, and in the second conductive layer 32 and the second dielectric layer 82 including the second metal layer 42). In some embodiments, since the additional metal layer 48 is disposed above the second metal layer 42, the MFC via 56 can extend through the additional metal layer 48. The additional metal layer 48 can also be disposed below the first metal layer 41.

[0059] The stress-reducing layer 54 reduces the stress caused by any difference in the coefficients of thermal expansion between the core 52 and the substrate 20. For this purpose, the stress-reducing layer 54 can have a greater ductility than the core 52. In some embodiments, the stress-reducing layer 54 is conductive, can be in electrical and physical contact with the core 52, and the stress-reducing layer 54 can comprise aluminum or may be aluminum. By providing a conductive stress-reducing layer 54 of a metal with greater ductility than the core 52 that is in electrical and physical contact with the core 52, the core 52 can be manufactured using electroplating techniques without the need for sputtering and patterned seed layers formed on top of the substrate 20, as discussed further below.

[0060] Therefore, according to some embodiments of this disclosure, a magnetic flux concentrator structure 10 can be constructed by providing a substrate 20, forming one or more metal layers 48 (each metal layer 48 including a conductive layer 38 and a dielectric layer 88 disposed above the conductive layer 38) on or over the substrate 20, forming an MFC via 56 in one or more dielectric layers 88, and disposing a magnetic flux concentrator 50 in the MFC via 56. According to an embodiment of the invention, the magnetic flux concentrator 50 includes a stress reduction layer 54 and a core 52, and is disposed in the MFC via 56 by etching one or more dielectric layers 88 to expose conductive lines 78 having effective two-dimensional regions (e.g., contact regions or contact pads) in the conductive layer 38. The effective two-dimensional region of the stress reduction layer 54 may extend across the entire bottom of the MFC via 56, or vice versa. In some embodiments, the stress-reducing layer 54 extends beyond the MFC via 56 and beyond the core 52 to reduce the stress gradient present at the edge of the core 52 and to reduce cracking in the substrate 20 layer (e.g., a dielectric layer or a semiconductor layer) adjacent to or beneath the core 52. Figure 4 and Figure 8 As shown in the diagram, the exposed wires 78 are electrically connected to an external current source, and the core 52 is electroplated on the area of ​​the exposed wires 78. According to some embodiments of the invention, the exposed wires 78 can serve as an etching stop for etching the MFC via 56, provide a conductive region for providing current to electroplat the core 52 in the MFC via 56, provide a sublayer for depositing the seed layer 57 to achieve electroplating, and can serve as a stress-reducing layer 54.

[0061] According to some embodiments of this disclosure, the substrate 20 of the magnetic flux concentrator structure 10 is a semiconductor substrate including electronic circuitry 22, which is, for example, an integrated circuit disposed in or on the semiconductor substrate using photolithography methods and materials. Electronic circuitry 22 may include doped or implanted semiconductor structures having feature sizes less than or equal to 200 nm, less than or equal to 180 nm, or less than or equal to 110 nm. Electronic circuitry 22 may be digital circuitry, analog circuitry, or mixed-signal circuitry, and may be configured as CMOS circuitry in the silicon substrate 20. As described above, conventional methods and equipment for measuring magnetic fields become less efficient or more expensive when the resolution (feature size) of integrated circuits reaches these dimensions, thus providing an advantage for the present invention.

[0062] The conductor 78 may be a patterned metal line deposited by evaporation and patterned using photolithography methods and materials, such as silver, aluminum, titanium, tungsten, copper, or other metals. The dielectric layer 88 may include a dielectric material 89, such as inorganic materials like oxides (e.g., silicon dioxide) and nitrides (e.g., silicon nitride), or organic polymers, resins, and epoxy resins. The dielectric layer 88 may be coated by plasma-enhanced chemical vapor deposition (PECVD), spraying, slot coating, spin coating, or other methods known in photolithography techniques.

[0063] According to some embodiments of this disclosure, a first wire 71 is electrically connected to electronic circuit 22, a second wire 72 is electrically connected to electronic circuit 22, or both are connected to electronic circuit 22. Electrically connecting the first wire 71 and the second wire 72 to electronic circuit 22 provides a system that operates, controls, or responds to electrical or magnetic signals or electric or magnetic fields and can respond to an external controller or other external system.

[0064] The embodiments of this disclosure offer advantages in small devices and systems, and achieve core 52 structures with reduced dimensions that would otherwise be difficult to achieve with conventional means in similar implementations. According to some embodiments, (i) the flux concentrator 50 has a lateral dimension of 130 micrometers or less, 100 micrometers or less, or 50 micrometers or less, (ii) the flux concentrator 50 has a thickness of 15 micrometers or less, 10 micrometers or less, or 5 micrometers or less, or (iii) both (i) and (ii). When such small flux concentrators 50 are provided on a thin stress-reducing layer 54 (such as a ductile metal like aluminum), such small flux concentrators 50 can tolerate mechanical stresses from heat relative to the substrate 20. In contrast, prior art devices are larger and require thicker stress-reducing layers (such as... Figure 12 The polyimide layer 55 in the middle increases the size of existing devices and the distance between the MFC and the Hall effect plate.

[0065] According to some embodiments of this disclosure, the magnetic flux concentrator structure 10 includes a magnetic sensor 60 at least partially disposed in a first metal layer 41, such as disposed in a first conductive layer 31, a first dielectric layer 81, or both the first conductive layer 31 and the first dielectric layer 81. The magnetic sensor 60 may include a magnetic sensor circuit 64 electrically connected to one or more sensing plates 62 (such as Hall effect plates). The magnetic sensor circuit 64 may include a doped or implanted semiconductor structure having a feature size less than or equal to 200 nm, less than or equal to 180 nm, or less than or equal to 110 nm, the semiconductor structure being fabricated using photolithography and materials, and may be a mixed-signal circuit or an analog circuit. The magnetic sensor 60 may be a Hall effect sensor including one or more Hall effect sensing plates 62. In some embodiments, the magnetic sensor may be a magnetoresistor or other material having electronic properties modulated by a magnetic field. The sensing plate 62 may be movable a distance from the magnetic sensor circuit 64. In some embodiments, the magnetic sensor 60 is disposed between the substrate 20 and the first metal layer 41, disposed within the substrate 20, or disposed on the side of the substrate 20 opposite to the magnetic flux concentrator 50. A first wire 71 may be electrically connected to the magnetic sensor circuit 64 or the electronic circuit 22, and a second wire 72 may be electrically connected to the magnetic sensor circuit 64 or the electronic circuit 22, or both, for example, electrically connected to both the magnetic sensor circuit 64 and the electronic circuit 22. The sensing plate 62 may be electrically connected to the magnetic sensor circuit 64 using four electrical connections, for example, to provide current through the sensing plate 62 and sense the corresponding voltage difference across the sensing plate 62 when a magnetic field is present. Therefore, in Figure 2 and Figure 6 In some embodiments, the wires 78 electrically connecting each sensing plate 62 to a circuit (e.g., magnetic sensor circuit 64) can be a bus comprising at least four individual wires. In some embodiments, at least a portion of the magnetic sensor 60 or sensing plate 62 is within the range of 10 micrometers, 8 micrometers, 5 micrometers, 3 micrometers, 2 micrometers, or 1 micrometer of the magnetic flux concentrator 50. The sensing plate 62 can be disposed in a doped semiconductor region of the substrate 20, for example, in the same layer as the CMOS circuit or in the same layer as the magnetic sensor circuit 64. Although in Figure 1 The magnetic sensor circuit 64 is shown as a separate circuit from the electronic circuit 22, but it can be incorporated into the electronic circuit 22, or the electronic circuit 22 and the magnetic sensor circuit 64 can be a common circuit. The magnetic flux concentrator 50 can be at least partially disposed above the sensing plate 62 in a direction orthogonal to the surface of the substrate 20, for example, the sensing plate 62 can be disposed directly below the edge of the core 52.

[0066] A highly integrated and sensitive magnetic sensor 60 is provided by electrically connecting the first wire 71 or the second wire 72 to the magnetic sensor 60 (or electronic circuit 22, or both the magnetic sensor 60 and electronic circuit 22) and disposing the Hall effect sensing plate 62 in the doped semiconductor region of the substrate 20. In integrated circuit manufacturing, the individual wires 78 in the metal layer 48 can be separated by only a few micrometers or less, such that disposing the sensing plate 62 adjacent to the magnetic flux concentrator 50 in the second metal layer 42 in the doped semiconductor region of the substrate 20 provides a highly integrated and sensitive magnetic sensor 60.

[0067] refer to Figures 3-6 According to some embodiments, the flux concentrator structure 10 includes more than two metal layers 48 (e.g., a first metal layer 41 and a second metal layer 42). For example, the flux concentrator structure 10 may include a third metal layer 43 and a fourth metal layer 44, the third metal layer 43 including a third conductor layer 33, the fourth metal layer 44 including a fourth conductor layer 34, the third conductor layer 33 including a third conductor 73, and the fourth conductor layer 34 including a fourth conductor 74. In some embodiments, the flux concentrator structure 10 may include a fifth metal layer 45 and a sixth metal layer 46, the fifth metal layer 45 including a fifth conductor layer 35, the sixth metal layer 46 including a sixth conductor layer 36, the fifth conductor layer 35 including a fifth conductor 75, and the sixth conductor layer 36 including a sixth conductor 76 (e.g., ...). Figure 5 (as shown in the image).

[0068] like Figure 3 As shown, the flux concentrator structure 10 may include one or more wires 78 in a coil 58 surrounding the flux concentrator 50 (e.g., surrounding the core 52), disposed in or on the substrate 20. The wires 78 in the coil 58 may be a first wire 71 disposed in a first wire layer 31 of a first metal layer 41, a second wire 72 disposed in a second wire layer 32 of a second metal layer 42, a third wire 73 disposed in a third wire layer 33 of a third metal layer 43, or a fourth wire 74 disposed in a fourth wire layer 34 of a fourth metal layer 43 (and in some embodiments may include additional wires 78 in an additional wire layer 38 of an additional metal layer 48, such as...). Figure 5 (As shown). The wires 78 in the different wire layers 38 of the coil 58 can be electrically connected through the through-hole 70 and are arranged in a circular or arc shape, as shown. Figure 6As shown in the diagram. The wires 78 in coil 58 can form one or more windings around core 52 to provide an electromagnet or transformer, and can be controlled or responsive to the transformer / electromagnetic circuit 90. For example, the wires 78 in coil 58 can form a single winding around core 52 or a primary winding and a secondary winding. The transformer / electromagnetic circuit 90 can include a doped or implanted semiconductor structure having feature dimensions less than or equal to 200 nm, less than or equal to 180 nm, or less than or equal to 110 nm, fabricated using photolithography and materials, and the transformer / electromagnetic circuit 90 can be a digital circuit (such as a CMOS circuit), a mixed-signal circuit, or an analog circuit. In some such embodiments, the magnetic field in MFC via 56 is perpendicular to substrate 20, eliminating the need for wires 78 positioned below MFC via 56 to influence or control the performance of flux concentrator structure 10.

[0069] like Figure 3 As shown, the flux concentrator structure 10 may include a conductor redistribution layer containing coil conductors 59 or a conductor redistribution layer disposed in a top conductor layer 91 (e.g., disposed on a top dielectric layer in a stack of dielectric layers 88). In some embodiments, and for this application, the magnetic field is ideally parallel to the substrate 20. Therefore, for each coil conductor 59 above the core 52, at least one coil conductor 59 may be disposed in a conductor layer 38 below the core 52, preferably disposed in a first metal layer 41 (or, if present, in a metal layer 48 below the first metal layer 41), wherein a stress-reducing layer 54 is disposed in a second metal layer 42.

[0070] Such coil conductors 59 can be part of the coil 58, or they can form a redistribution layer that provides point contacts to external devices or electrical connections with a lower resolution than the flux concentrator structure 10 itself. Because the flux concentrator 50 is relatively small and can have a low profile above the substrate 20, the conductor redistribution layer can be positioned above the flux concentrator 50. This makes the fabrication of the coil 58 with the magnetic core 52 cost-effective, thereby allowing transformers, voltage converters, and the generation of active magnetic fields in the flux concentrator 50 for electromagnet and magnetic feedback control to be implemented on a chip.

[0071] Similarly, Figure 3As shown, the conductors 78 (e.g., first to fourth conductors 71-74) in the conductor layers 38 (e.g., first to fourth conductor layers 31-34) separated by the dielectric layers 88 (e.g., first dielectric layer 81, second dielectric layer 82, third dielectric layer 83, and fourth dielectric layer 84) on the planar dielectric layer 80 (forming metal layers 48 (e.g., first metal layer 41, second metal layer 42, third metal layer 43, and fourth metal layer 44)) can be electrically connected to the electronic circuit 22 and the transformer / electromagnetic circuit 90 in the substrate 20, or to the portion forming the coil 58, through the via 70.

[0072] refer to Figure 4 The core 52 may extend beyond the MFC via 56 and into or above the top dielectric layer in the stack of dielectric layers 88, or beyond the passivation layer of substrate 20, for example, forming a mushroom shape. If present, the encapsulation layer 92 may protect the core 52 from environmental stresses and contaminants, and if present, coil leads 59 or lead redistribution layers may be disposed on the encapsulation layer 92, or directly above the core 52 (e.g., ...). Figure 4 (as shown), or disposed above other portions of the substrate 20, or directly on top of the top dielectric layer in the stack of dielectric layers 88.

[0073] Figure 5 Some embodiments of this disclosure are illustrated, wherein the core 52 extends into the encapsulation layer 92 but does not extend beyond a portion of the substrate 20 beyond the MFC via 56, thereby forming a cylindrical shape with a rounded top. Figure 5 As shown, the conductors 78 (e.g., first to sixth conductors 71-76) in the conductor layers 38 (e.g., first to sixth conductor layers 31-36) separated by dielectric layers 88 (e.g., first to sixth dielectric layers 81-86) (forming metal layers 48 (e.g., first to sixth metal layers 41-46)) can be electrically connected to the electronic circuit 22 and the transformer / electromagnetic circuit 90 through the vias 70, or form a portion of the coil 58.

[0074] Figure 6 A plan view of a magnetic flux concentrator structure 10 with a modified layout is provided, the modified layout including a coil 58 arranged around a core 52 and a stress reduction layer 54 in an MFC via 56. Figure 6 (not shown in the image), and Figure 3 and Figure 5 Correspondingly, and optionally partially formed in the conductor redistribution layer having coil conductors 59, the transformer / electromagnetic circuit 90, and the electronic circuit 22. The core 52 may be continuous, or may have one or more gaps, such as... Figure 6 The right side of the central ring is shown.

[0075] refer to Figure 7 Some embodiments of this disclosure may include a plurality of magnetic flux concentrators 50 and a magnetic sensor 60. The plurality of magnetic flux concentrators 50 include cores 52 physically contacted in a substrate 20 and a stress layer 54 via first to fifth conductors 71-75 in first to fifth conductor layers 31-35, respectively. The first to fifth conductor layers 31-35 form coils 58 in an active electromagnetic field generating device. The magnetic sensor 60 has a sensing plate 62 and a magnetic sensor circuit 64. Optionally, it may include an encapsulation layer 92 and coil conductors, a conductor redistribution layer, or a top conductor layer 91. Figure 7 (Not shown in the image). In some embodiments, the core 52 may include a shape such as a ring or a circle (e.g., Figure 7 The two cores 52 shown in the cross section can be physically connected (e.g., in a ring) to form a single core 52.

[0076] refer to Figure 9 The flowchart illustrates a method for constructing a magnetic flux concentrator structure 10 according to some embodiments of this disclosure, which may include providing a substrate 20 in step 100 and forming circuitry (e.g., any combination of electronic circuitry 22, magnetic sensor circuitry 64, and transformer / electromagnetic circuitry 90) in or on the substrate 20 in step 110. In step 120, an optional planarized dielectric layer 80 is disposed on the substrate 20 along with any circuitry formed thereon and any vias 70. In embodiments, the substrate 20 is provided with circuitry and an optional planarized dielectric layer 80 formed in or on the substrate 20, such that steps 110 and 120 are incorporated into step 100. A metal layer is formed in steps 130 and 140 by coating and patterning a conductive layer 38 in step 130 to form conductive lines 78 and subsequently disposing a dielectric layer 88 on the conductive layer 38 in step 140. The successive steps 130 and 140 of forming wires and dielectric layers 88 in the patterned wire layer 38 can be iteratively repeated to form as many metal layers 48 as desired, such as a first metal layer 41 and a second metal layer 42 (e.g., ...). Figure 1 (as shown), first to fourth metal layers 41-44 (as shown) Figure 3 (as shown), or the first to sixth metal layers 41-46 (as shown) Figure 5 (as shown in the diagram). In some embodiments, the plating current passes through the substrate 20, for example, through a silicon wafer including the substrate 20. Optionally, a first conductive line 71, a second conductive line 72, or a first conductive line 71 electrically accessible externally, which can be used as an electroplating electrode, is formed in the first conductive layer 31 or the second conductive layer 32. In some embodiments of this disclosure, a sealing ring 49 (in the diagram) surrounds the electronic circuit 22 or the magnetic flux concentrator structure 10. Figure 1 and Figure 2(As shown in the diagram) can be used as an electrical contact between the substrate 20 and the second metal layer 42. According to some embodiments, a sealing ring 49 is composed of all the metal layers 48 (e.g., forming a metal wall around the flux concentrator structure 10), and the sealing ring 49 is provided to prevent ions and moisture from entering from the sides of the structure 10. The sealing ring 49 can be formed around the electronic circuitry 22 and the substrate 20, can be highly conductive, has a large contact area, and therefore provides very low contact resistance and can provide a large current to the plating core 52. The flux concentrator structure 10 can be disposed on a wafer having many such structures. The sealing ring 49 can then also distribute the plating current from the wafer edge to all the individual flux concentrator structures 10, specifically to the seed layer 57.

[0077] Once the final dielectric layer 88 is disposed above the substrate 20, an MFC via 56 can be formed in one or more dielectric layers 88 in step 150, for example, by etching down in a pattern to the second conductive layer 32 or to the first conductive layer 31. Figure 1 , Figure 3 , Figure 5 , Figure 7 and Figure 8 As shown in some embodiments, such as Figure 8 As shown, the MFC via 56 extends into the first conductor 71 in the first conductor layer 31. For clarity, Figure 8 No other conductive layer 38 or metal layer 48 is shown. When etching the MFC via 56, the metal (e.g., aluminum) forming the first conductive layer 31 or the second conductive layer 32 or the stress reduction layer 54 can be used as an etching stop.

[0078] In some embodiments of the present invention, such as Figure 1 , Figure 3 , Figure 5 , Figure 7 and Figure 8 As illustrated, the stress-reducing layer 54 is at least partially disposed at the bottom of the MFC via 56 and is a conductive wire 78, such as a first wire 71 in the first conductive layer 31 or a second wire 72 in the second conductive layer 32. The stress-reducing layer 54 has an area as large as or larger than the bottom area of ​​the MFC via 56. (Reference) Figure 10 Detailed flowchart and Figure 11The detailed structure includes the following steps: after forming the planarized dielectric layer 80 in step 120, forming the first conductive line 71 in the conductive layer 31 in step 131, forming the first dielectric layer 81 in step 141, forming the second conductive line 72 in step 132, and depositing a seed layer 57 on the second conductive line 72 in step 134, such that the stress reduction layer 54 (second conductive line 72) is coated with an additional seed layer to facilitate electroplating on the portion of the stress reduction layer 54 exposed in the MFC via 56. This additional seed layer comprises, for example, a metal (e.g., 50 nm to 200 nm) patterned by sputtering or evaporation and subsequently by patterning a relatively thin layer of material useful for electrodeposition, such as copper, nickel, TiW, TiN, gold, or platinum, or combinations thereof. The additional seed layer material may be present on the entire first conductive line 31 or the second conductive line 32, or may not be present on either the first conductive line 31 or the second conductive line 32. The seed layer 57 and the final conductive layer 38 (e.g., the second conductive line 72 in the second conductive layer 32) can be patterned in a common step. Therefore, according to some embodiments, the stress reduction layer 54 is multilayered, comprising a conductive and ductile first layer (e.g., the second conductive line 72) and a second layer serving as the seed layer 57. The second layer (seed layer 57) is disposed on the first layer (second conductive line 72). The seed layer 57 can be electrically connected to the substrate 20 to provide current for electroplating the core 52 on the seed layer 57.

[0079] Once the final planarized dielectric layer (e.g., the second dielectric layer 82 formed in step 142) is formed in step 150, an MFC via 56 is formed over the stress reduction layer 54 such that only the bottom of the MFC via has an exposed seed layer 57, thereby forming an electroplating electrode at the bottom of the MFC via 56. The stress reduction layer 54 may be electrically connected to an external power source that provides current for electroplating the stress reduction layer 54 to form the core 52 in step 160 by electrolytically depositing metal or metal alloy from a solution immersed in the substrate 20. In some embodiments, the electroplating current is provided by the semiconductor substrate 20 material itself, and only at the wafer edges. Because only the bottom of the MFC via 56 has an exposed seed layer 57 (forming an electroplating electrode), and the walls of the MFC via 56 consist only of the dielectric material etched to form the MFC via 56, no metal or alloy is directly electrodeposited on the walls of the MFC via 56, and any mechanical connection between the core 52 and the dielectric layer (e.g., the second dielectric layer 82) is reduced or eliminated.

[0080] To electrodeposit relatively large or thick cores as seen in the prior art, a seed layer is disposed on one side of the MFC via 56, and a mold (typically a resin material) is disposed above the dielectric layer. In contrast, because embodiments of the present invention include small, relatively thin cores 52, this type of electrodeposition, instead of the seed layer deposition of such prior art, is practical, thus reducing the number of steps required to form the core 52. For example, after forming the MFC via 56, no additional deposition or patterning steps for the seed layer are required, as patterning the conductive layer 38 can also pattern the stress-reducing layer 54 and the seed layer 57. Furthermore, forming the core 52 by electroplating from the stress-reducing layer 54 at the bottom of the MFC via 56, rather than using a patterned seed layer deposited on one side of the MFC via 56, reduces the adhesion between the core 52 and structures in the substrate 20 (e.g., passivation layers or dielectric layers 88). Reduced lateral adhesion consequently reduces passivation fracture in the substrate 20 due to thermal stress; the core 52 can expand and contract to some extent independently of the substrate 20, particularly in the vertical direction. Electroplating the core 52 also improves its uniformity. Furthermore, since there is no seed layer or mold material above the dielectric layer, it is not necessary to remove such materials after electrodeposition. Avoiding such removal steps provides another advantage to the embodiments of this disclosure, as removing seed and mold layer materials would cause processing problems.

[0081] Optionally, in step 170, an encapsulation layer 92 is provided on the core 52, and in step 180, any top conductor layer 91 or conductor redistribution layer is formed.

[0082] The stress reduction layer 54 can be a metal pad with an effective area and various shapes, and when the stress reduction layer 54 is used as an electroplating electrode, it can be formed into various core 52 shapes, such as a cylinder (using a disc-shaped stress reduction layer 54), a cube (using a square stress reduction layer 54), or a ring (using an annular stress reduction layer 54).

[0083] Embodiments of the present invention can conduct or respond to signals in the conductor 78 by providing power, grounding, and control signals to electronic circuit 22 and any magnetic sensor circuit 64 or transformer / electromagnetic circuit 90. In some embodiments, the magnetic sensor 60 can detect and measure the ambient magnetic field, or the transformer / electromagnetic circuit 90 can, under the control of electronic circuit 22, communicate with an external system to generate a magnetic field or transform the voltage of an AC signal.

[0084] It will be apparent to those skilled in the art of electromagnetics that the designations of the various metal layers 48, dielectric layers 88, conductive layers 38, and conductive lines 78 are arbitrary and can be provided in any order. For example, the topmost metal layer 48 furthest from the substrate 20 may be the first metal layer 41, rather than the metal layer 48 closest to the substrate 20 as illustrated in the figure.

[0085] Parts list:

[0086] 10. Magnetic flux concentrator structure

[0087] 20 substrates

[0088] 22 Electronic Circuits

[0089] 31 First Conductor Layer

[0090] 32 Second Conductor Layer

[0091] 33 Third Conductor Layer

[0092] 34 Fourth Conductor Layer

[0093] 35 Fifth Conductor Layer

[0094] 36 Sixth Conductor Layer

[0095] 38 (multiple) conductor layers

[0096] 41 First metal layer

[0097] 42 Second metal layer

[0098] 43 Third metal layer

[0099] 44 Fourth metal layer

[0100] 45 Fifth metal layer

[0101] 46 Sixth Metal Layer

[0102] 48 (multiple) metal layers

[0103] 49 Sealing ring

[0104] 50 Magnetic Flux Concentrator

[0105] 51 Magnetic Flux Concentrator

[0106] 52 cores

[0107] 53 cores

[0108] 54 Stress Reduction Layer

[0109] 55 Polyimide layer

[0110] 56 MFC Through Holes

[0111] 57 Seed Crystal Layer

[0112] 58 coils

[0113] 59 Coil wires

[0114] 60 Magnetic Sensor

[0115] 62 sensing boards

[0116] 64 Magnetic Sensor Circuit

[0117] 70 through-hole

[0118] 71 First Conductor

[0119] 72 Second conductor

[0120] 73 Third conductor

[0121] 74 Fourth conductor

[0122] 75 Fifth conductor

[0123] 76 Sixth conductor

[0124] 78 (multiple) wires

[0125] 80 Planarized Dielectric Layer

[0126] 81 First dielectric layer

[0127] 82 Second dielectric layer

[0128] 83 Third dielectric layer

[0129] 84 Fourth dielectric layer

[0130] 85 Fifth dielectric layer

[0131] 86 Fifth dielectric layer

[0132] 88 (multiple) dielectric layers

[0133] 89 Dielectric Materials

[0134] 90 Transformer / Electromagnetic Circuit

[0135] 91 Top Conductor Layer

[0136] 92 encapsulation layer

[0137] 100 Substrate provision step

[0138] 110 Circuit Formation Steps

[0139] 120 Dielectric Coating Step

[0140] 130. Steps to pattern the conductor layer

[0141] 131. Step to pattern the first conductor layer

[0142] 132. Step to pattern the second conductor layer

[0143] 134. Steps for patterning the seed crystal layer

[0144] 140 Dielectric layer coating step

[0145] 141 Step of coating the first dielectric layer

[0146] 142. Step of coating the second dielectric layer

[0147] 150 Steps to Build MFC

[0148] 160 Electroplating Core Steps

[0149] 170 Packaging Steps

[0150] 180 Optional steps for forming top metal / RDL

[0151] Although the invention has been illustrated and described in detail in the accompanying drawings and the foregoing description, such illustrations and descriptions should be considered illustrative or exemplary rather than limiting. The foregoing description details certain embodiments of the invention. However, it should be understood that, however detailed the foregoing may appear in the text, the invention can be practiced in many ways. The invention is not limited to the disclosed embodiments.

[0152] In implementing the claimed invention, other variations of the disclosed embodiments may be understood and implemented by those skilled in the art from a study of the drawings, this disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a / an" does not exclude a plural. A single processor or other unit may perform the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that combinations of these measures cannot be advantageously used. Computer programs may be stored / distributed on suitable media (such as optical storage media or solid-state media supplied together with or as part of other hardware), but may also be distributed in other forms (such as via the Internet or other wired or wireless telecommunications systems). Any reference numerals in the claims should not be construed as limiting the scope.

Claims

1. A magnetic flux concentrator (MFC) structure, comprising: Substrate, A first metal layer, comprising: (i) a first conductive layer disposed on or above the substrate, the first conductive layer comprising a first conductive line for conducting electrical signals; and (ii) a first dielectric layer disposed on the first conductive layer. A second metal layer, comprising: (i) a second conductive layer disposed on or above the first metal layer, the second conductive layer including second conductive lines for conducting electrical signals; and (ii) a second dielectric layer disposed on the second conductive layer. A magnetic flux concentrator, wherein the magnetic flux concentrator is at least partially disposed in the second metal layer, or at least partially disposed in both the first metal layer and the second metal layer. The magnetic flux concentrator includes a core that is at least partially disposed in the second dielectric layer and a stress reduction layer disposed in the second conductive layer.

2. The magnetic flux concentrator structure as described in claim 1, characterized in that, The second dielectric layer includes an MFC via, wherein the magnetic flux concentrator is at least partially disposed in the MFC via.

3. The magnetic flux concentrator structure as claimed in claim 1, wherein the magnetic flux concentrator structure includes one or more wires disposed in or on the substrate, the wires forming one or more coils surrounding the magnetic flux concentrator.

4. The magnetic flux concentrator structure as described in claim 1, characterized in that, The substrate is a semiconductor substrate, the semiconductor substrate includes electronic circuits disposed in or on the semiconductor substrate, and wherein the electronic circuits have feature dimensions of less than or equal to 200 nm, less than or equal to 180 nm, or less than or equal to 110 nm.

5. The magnetic flux concentrator structure as described in claim 1, characterized in that, (i) The magnetic flux concentrator has a lateral dimension of 130 micrometers or less, 100 micrometers or less, or 50 micrometers or less, (ii) The magnetic flux concentrator has a thickness of 15 micrometers or less, 10 micrometers or less, or 5 micrometers or less, or (iii) both of (i) and (ii).

6. The magnetic flux concentrator structure as claimed in claim 1, wherein the magnetic flux concentrator structure includes a magnetic sensor, the magnetic sensor being at least partially disposed in the first metal layer, at least partially disposed between the substrate and the first metal layer, at least partially disposed in the substrate, or at least partially disposed on the side of the substrate opposite to the magnetic flux concentrator.

7. The magnetic flux concentrator structure as described in claim 6, characterized in that, At least a portion of the magnetic sensor is within the range of 10 micrometers, 8 micrometers, 5 micrometers, 3 micrometers, 2 micrometers, or 1 micrometer of the magnetic flux concentrator.

8. The magnetic flux concentrator structure as described in claim 1, characterized in that, The stress-reducing layer has greater ductility than the magnetic flux concentrator, wherein the stress-reducing layer is conductive.

9. The magnetic flux concentrator structure as described in claim 1, characterized in that, The stress reduction layer is a multilayer structure, comprising a first conductive and ductile layer and a second layer serving as a seed layer, wherein the second layer is disposed on the first layer.

10. The magnetic flux concentrator structure as described in claim 9, characterized in that, The seed layer is electrically connected to the substrate.

11. The magnetic flux concentrator structure of claim 10, comprising electronic circuitry and a sealing ring disposed around the electronic circuitry, wherein, The seed crystal layer is electrically connected to the substrate through the sealing ring.

12. The magnetic flux concentrator structure as described in claim 1, characterized in that, The magnetic flux concentrator is mechanically isolated from the second dielectric layer.

13. A method for manufacturing a magnetic flux concentrator structure, the method comprising: Provide substrate, A first metal layer is disposed on or above the substrate, the first metal layer comprising: (i) a first conductive layer disposed on or above the substrate, the first conductive layer comprising a first conductive line for conducting electrical signals, and (ii) a first dielectric layer disposed on the first conductive layer; A second metal layer is disposed on or above the first metal layer, the second metal layer comprising: (i) a second conductive layer disposed on or above the first metal layer, the second conductive layer comprising second conductive lines for conducting electrical signals; and (ii) a second dielectric layer disposed on the second conductive layer; and The magnetic flux concentrator is disposed at least partially in the second metal layer, or at least partially in both the first metal layer and the second metal layer. The magnetic flux concentrator includes a core that is at least partially disposed in the second dielectric layer and a stress reduction layer disposed in the second conductive layer.

14. The method of claim 13, further comprising depositing an electroplated seed layer on the second conductive layer prior to depositing the second dielectric layer.

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