Circuit and method including configuration terminals

Abstract

Embodiments of the present disclosure generally relate to circuits and methods including configuration terminals. Circuits and methods are provided wherein a configuration terminal (12) of a circuit (10) is coupled to an internal node (15) during a configuration phase and is decoupled from the internal node (15) during normal operation.

Description

Technical Field

[0001] The present application relates to a circuit comprising a configuration terminal and to a corresponding method. Background Art

[0002] An electronic circuit comprises terminals for communicating with other entities, for example to receive a supply voltage, receive an input signal or output an output signal. Where the circuit is provided in a package, such terminals may be provided as pins of the package.

[0003] Such terminals (such as pins) are usually protected against electrostatic discharge (ESD) by an ESD protection circuit, which can be implemented by coupling a diode between the corresponding terminal and a reference potential. In normal operation, the diode is non-conductive. In the event of an electrostatic discharge that causes a high voltage, the diode becomes conductive, thereby reducing the charge generated by the electrostatic discharge to the reference potential.

[0004] One type of terminal is a configuration terminal for configuring a circuit. For example, using such a configuration terminal, an operating mode for a circuit can be selected, or an address can be provided for a circuit when multiple circuits are connected to a common communication environment (such as a bus).

[0005] To give a more specific example, for radio frequency (RF) circuits such as power amplifiers, low noise amplifiers, and RF switches, such configuration terminals can be used to set or configure current mode or one or more low power modes, or to provide a logical address like a USID (unique slave identifier) ​​in a MIPI radio frequency front end (RFFE). However, in some cases, during normal operation, the configuration terminals and the associated ESD circuits may interfere with normal operation. For example, in a radio interface circuit, if the pads associated with the configuration terminals are close to high amplitude RF pins with high overlap capacitance to the configuration terminals, the ESD circuits and readout logic associated with the configuration terminals may cause spurious radiation of nonlinear signals. This is caused at least in part by the rectification of the RF signal at the diodes of the ESD circuits, and may result in higher order harmonics. This in turn may result in a violation of RF specifications, and the rectified RF signal also results in an increase in current consumption.

[0006] Various approaches have been made to overcome this problem, which may have various disadvantages. Summary of the Invention

[0007] There is provided a circuit as defined in claim 1 and a method as defined in claim 10. The dependent claims define further embodiments.

[0008] According to an embodiment, there is provided a circuit comprising:

[0009] a configuration terminal configured to receive a configuration signal in a configuration phase of the circuit,

[0010] internal nodes that are coupled to the internal circuitry of the circuit and

[0011] A switch is coupled between the configuration terminal and the internal node, wherein the switch is configured to couple the configuration terminal to the internal node during the configuration phase and to decouple the configuration terminal from the internal node during normal operation of the circuit.

[0012] According to another embodiment, a method is provided, comprising:

[0013] coupling a configuration terminal of the circuit to an internal node of the circuit during a configuration phase of the circuit and

[0014] The configuration terminal is decoupled from the internal node during normal operation of the circuit.

[0015] The above summary is intended only to give a brief overview of some embodiments and should not be construed as limiting in any way. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1A is a diagram illustrating a circuit in a configuration stage according to an embodiment.

[0017] Figure 1B is shown in normal operation Figure 1A Schematic diagram of the circuit.

[0018] Figure 2 is a diagram illustrating a circuit according to an embodiment.

[0019] Figure 3 is a flow chart illustrating a method according to an embodiment. DETAILED DESCRIPTION

[0020] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. These embodiments should be considered merely as illustrative examples and should not be construed as limiting. For example, although an embodiment may be described as including many features, in other embodiments, some of these features may be omitted or replaced by alternative features. In addition to the features explicitly shown in the drawings or described herein, additional features may be provided, such as features provided in conventional circuits.

[0021] For example, the embodiments described below relate to coupling and decoupling configuration terminals with other portions of the circuit (e.g., internal nodes). In addition to the described coupling and decoupling and circuitry associated therewith, in some embodiments, the circuit can be implemented in a conventional manner and can include additional terminals, additional circuit components, etc., for providing various functions.

[0022] Variations and modifications described with respect to one embodiment may also be applied to other embodiments and will not be described again. Features from different embodiments may be combined to form further embodiments.

[0023] As used herein, configuration refers to the process of configuring a circuit to adjust certain functions before normal operation or in a configuration phase between stages of normal operation. For example, a value can be written to a configuration register and then used in normal operation. As previously mentioned, such a configuration can be used to set certain modes for normal operation (e.g., current mode or low power mode), or to set an address for communication via a bus. These are just some examples, and any type of configuration can be used. In contrast, normal operation refers to any operation in which a circuit provides a function that is designed to function as, for example, a power amplifier, a low noise amplifier, a radio frequency switch, etc.

[0024] As used herein, a terminal is a contact point where a circuit interfaces with the outside world (e.g., with another circuit). In the case of an integrated circuit provided in a package, such a terminal can be implemented as a pin. Such a terminal is typically associated with an electrostatic discharge (ESD) protection circuit system to prevent or mitigate damage to the circuit in the event of an electrostatic discharge, which can be caused, for example, by a person touching the circuit.

[0025] Some embodiments use switches. The switches can be implemented using one or more transistors such as field effect transistors, insulated gate bipolar transistors, or bipolar junction transistors. When the switch is substantially non-conductive (except for possible leakage current, which may occur depending on the implementation of the switch), the switch is said to be "open" or "off," and if the switch provides a low-ohmic electrical connection, the switch is said to be "closed" or "on."

[0026] Figure 1A shows the circuit 10 in a configuration phase according to an embodiment, and Figure 1B Normal operation of the circuit 10 is shown.

[0027] like Figure 1A As shown, the circuit 10 may be provided in a package as indicated by the dotted line 11 in a chip housing. The configuration terminal 12 enables the circuit 10 to be configured during a configuration phase. The configuration terminal 12 may be a configuration pin. The configuration terminal 12 is coupled to an internal node 15 via a switch 13. Figure 1A In the configuration phase, switch 13 is closed. In addition, internal node 15 is coupled to the reference potential via switch 14. Figure 1A In the example, the reference potential is ground (GND). Figure 1AIn the configuration phase shown in , the switch 14 is open, so that the internal node 15 is decoupled from the reference potential.

[0028] In other embodiments, switch 14 and the coupling of internal node 15 to ground may be omitted.

[0029] Internal node 15 is coupled to ESD protection circuitry 16 and sensing circuitry / additional internal circuitry 17 of circuit 10. ESD protection circuitry 16 can be implemented in any conventional manner, such as using a diode that couples internal node 15 to a reference potential (such as ground and / or a positive reference potential) and protects circuitry 17 from electrostatic discharge at configuration terminal 12 by deflecting the electrostatic discharge away from the reference potential(s). Circuitry 17 senses the signal at configuration terminal 12 and configures the internal circuitry of circuit 10 accordingly. This configuration can be accomplished in any conventional manner and can be the configuration described above.

[0030] In some embodiments, control circuitry 18 may also be provided as part of circuit 10 to control the switching of switches 13, 14, or in other words, the switching of switches 13, 14. Figure 1A The configuration phase shown below will refer to Figure 1B Further discussion of normal operation of the switching circuit 10. In other embodiments, the control signal can be applied to additional terminals, such as additional pins (not shown) Figure 1A ), to control switches 13 and 14.

[0031] Reference numeral 19 indicates another terminal of the circuit 10, which may be a radio frequency (RF) terminal, to which RF signals with high signal swings may be applied. In this context, radio frequency may refer to frequencies above 1 MHz, for example 100 MHz or higher or in the gigahertz range. High signal swings may, for example, mean signal swings of up to 14 V for a GSM (Global System for Mobile Communications) signal loaded with 50 Ω, and signal swings of up to 100 V for antenna tuning applications. These values ​​are merely examples, and in other applications, other values ​​may be applied.

[0032] Figure 1A The configuration phase may be applied, for example, at startup of the circuit 10 to configure the circuit 10 at startup.

[0033] Figure 1B The circuit 10 is shown in normal operation, for example after startup. Figure 1B In, only Figure 1AThe portion of the circuit 10 that changes between the configuration phase and normal operation. In normal operation, switch 13 is open and switch 14 is closed. Thus, configuration terminal 12 is decoupled from circuit 10 (by opening switch 13), and internal node 15 is decoupled and thus switch 14 is coupled to a reference potential (e.g., ground) by closing switch 14.

[0034] In some embodiments, decoupling by switch 13 reduces interference that may be caused, for example, by RF signals applied to terminals adjacent to terminal 12 (e.g., terminal 19), and can help meet RF regulations and reduce current consumption. In addition, by closing switch 14, residual voltage caused by and stored in the parasitic capacitance of switch 13 can be shorted to ground. Figure 1A and Figure 1B In the embodiment shown in FIG, switch 14 is coupled between internal node 15 and ground to discharge the residual voltage. In other embodiments, switch 14 can be coupled between terminal 12 and ground. In some implementations, if a voltage is applied to terminal 12 when switch 13 is open and switch 14 is closed, the coupling shown between internal node 15 and ground may reduce the current flow compared to an implementation in which switch 14 is coupled between terminal 12 and ground.

[0035] Figure 2 is a circuit diagram showing another embodiment. In order to avoid repetition, when describing Figure 2 Reference will be made to the embodiments of Figure 1A and Figure 1B The previous description of the embodiments.

[0036] Figure 2 The circuit includes a configuration terminal 20, which is coupled to an internal node 21 via a transmission gate formed by a PMOS transistor 22 and an NMOS transistor 23. The configuration terminal 20 may be a configuration pin of the package circuit, as shown in FIG. Figure 1A and Figure 1B Internal node 21 may be coupled to ESD protection circuitry and readout circuitry and internal configuration circuitry, as described for Figure 1A The internal node 15 is described.

[0037] PMOS transistor 22 is controlled by signal PFC, and NMOS transistor 23 is controlled by signal NFC. In the configuration phase, transistors 22 and 23 are turned on so that configuration terminal 20 is electrically coupled to internal node 21. Therefore, the transmission gate formed by transistors 22 and 23 is Figure 1A The exemplary implementation of switch 13 has similar functionality.

[0038] Furthermore, the internal node 21 is coupled to a reference potential SS_ANA (analog ground) via an NMOS transistor 24. The NMOS transistor 24 is controlled by a signal NFPDC. During the configuration phase, the NMOS transistor 24 is switched off.

[0039] The NMOS transistor 24 is Figure 1A and Figure 1B An exemplary implementation of the switch 14 is shown.

[0040] The signal PFC, the signal NFC and the signal NFPDC can be generated by Figure 1A The internal control circuitry of the control circuitry 18 may be generated, or may be supplied externally via corresponding terminals. In some embodiments, the signals PFC and NFC may be generated based on a common control signal because the PMOS transistor 22 and the NMOS transistor 23 are turned on and off simultaneously.

[0041] In normal operation, as referenced Figure 1B As explained, transistors 22, 23 are turned off and NMOS transistor 24 is turned on. By turning on NMOS transistor 24, any remaining voltage caused by the parasitic capacitances of transistors 22, 23 at internal node 21 is shorted to the reference potential.

[0042] In some embodiments, the parasitic capacitance of such transistors 22 and 23 can be relatively high to prevent electrostatic discharge (ESD). Transistors 22 and 23 can have relatively high gate widths and can use self-aligned silicide blocking (SABL). The self-aligned silicide process is a conventional process for reducing the gate resistance in MOS transistors. In ESD devices, the process is blocked to obtain a higher "pre" resistance, so that the voltage diffusion becomes more uniform and avoids hot spots. Such a design allows self-conduction of transistors 22 and 23 during ESD pulses. This self-conduction limits the voltage at the configuration terminal 20, and therefore limits the drain-gate voltage of transistors 22 and 23. For NMOS transistor 23, an example gate width can be on the order of about 500μm, and for PMOS transistor 22, an example gate width can be about 1mm. It should be noted that Figure 2 The transistor implementation is only an example and other switches can also be used.

[0043] In addition, Figure 2In the circuit, capacitor 27 couples the configuration terminal 20 to the reference potential SS_ANA. In some embodiments, this can help suppress ultra-high frequency RF signals. Ultra-high frequency can refer to frequencies in the GHz range, for example above about 3 GHz, where the shunt transistor 24 is limited by the inductance of the SS_ANA line. Using high external capacitors may instead lead to self-resonance, while small internal capacitors such as capacitor 27 inside the chip can more effectively avoid self-resonance. In addition, in the case of a triple-well implementation of the transistors shown, additional RC filters can be provided for the corresponding wells (well_VP and well_VN in Figure 1), which additional RC filters include capacitor 25 and resistor 26 for the PMOS transistor and resistor 212 and capacitor 211 for the NMOS transistor. In this regard, VSSN is the negative bias voltage for the RF switching transistors 23, 24, well-VP is the positive supply voltage for the RC filtering and well-NP is the VSSN for the RC filtering. Reference numerals 28, 29 and 210 represent diodes, and in Figure 3 Additional terminals, such as RF terminals, are shown passing through element 213.

[0044] Figure 3 is a flow chart illustrating a method according to an embodiment. Figure 3 The method can be used Figure 1A 、 Figure 1B circuit or Figure 2 The present invention is implemented with circuits of and will be described with reference to them, but may also be implemented with other circuits.

[0045] At 30, the method includes coupling a configuration terminal to an internal node during a configuration phase (eg, startup). For example, the coupling Figure 1A 、 Figure 1B 1 is achieved by closing switch 13 and Figure 2 The function is achieved by turning on the transistors 22 and 23 of the transmission gate.

[0046] At 31, the method includes decoupling the configuration terminal from the internal node during normal operation (e.g., by opening switch 13 or by turning off transistors 22, 23). Optionally, at 32, the method may also include decoupling the configuration terminal from the internal node during normal operation (e.g., by closing Figure 1A and Figure 1B The switch 14) couples the internal node to the reference potential or by turning on Figure 2 The method may further comprise providing a capacitor coupling, such as for example for Figure 2 As explained above, capacitor 27, capacitor 25, and capacitor 211.

[0047] Some embodiments are defined by the following examples:

[0048] Example 1. A circuit comprising:

[0049] a configuration terminal configured to receive a configuration signal in a configuration phase of the circuit,

[0050] internal nodes that couple to the internal circuitry of the circuit and

[0051] A switch is coupled between the configuration terminal and the internal node, wherein the switch is configured to couple the configuration terminal with the internal node during the configuration phase and to decouple the configuration terminal from the internal node during normal operation of the circuit.

[0052] Example 2. The circuit of Example 1, wherein the switch comprises a transmission gate comprising a PMOS transistor and an NMOS transistor.

[0053] Example 3. The circuit of Example 2, further comprising an RC filter configured to couple the well of the PMOS transistor to a reference potential, and / or an RC filter configured to couple the well of the NMOS transistor to a reference potential.

[0054] Example 4. The circuit of Examples 1 to 3, further comprising a further switch, wherein the further switch is configured to couple the internal node to a reference potential during the normal operating mode and to decouple the internal node from the reference potential in the configuration phase.

[0055] Example 5. The circuit of Example 4, wherein the reference potential is ground.

[0056] Example 6. The circuit of any of Examples 1 to 5, further comprising ESD protection circuitry coupled to the internal node.

[0057] Example 7. The circuit of any of Examples 1 to 6, further comprising control circuitry configured to control the switch and / or the additional switch.

[0058] Example 8. The circuit of any of Examples 1 to 6, further comprising a further terminal configured to control the switch and / or the further switch.

[0059] Example 9. The circuit of any of Examples 1 to 8, further comprising a capacitor coupled between a terminal of the switch and a reference potential.

[0060] Example 10. The circuit according to any one of Examples 1 to 9 further includes a radio frequency terminal configured to receive a radio frequency signal adjacent to the configuration terminal.

[0061] Example 11. The circuit of any of Examples 1 to 10, wherein the circuit is provided in a package, and wherein the configuration terminal is a configuration pin of the package.

[0062] Example 12. A method comprising:

[0063] coupling the configuration terminal to an internal node of the circuit during the configuration phase and

[0064] This configuration terminal is decoupled from the internal nodes during normal operation.

[0065] Example 13. The method of Example 12, further comprising coupling the internal node to a reference potential during normal operation and decoupling the internal node from the reference potential during the configuration phase.

[0066] Example 14. The method of Example 12 or Example 13, further comprising capacitively coupling the configuration terminal or the internal node to a reference potential.

[0067] Example 15. The method of any of Examples 12 to 14, further comprising applying a radio frequency signal to a further terminal of the circuit during normal operation.

[0068] Example 16. The method of any of Examples 12 to 15, wherein the ESD protection circuitry is coupled to the internal node.

[0069] Example 17. The method of any of Examples 12 to 16, wherein the method is performed using the circuit of any of Examples 1 to 11.

[0070] Although specific embodiments have been shown and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the present invention is limited only by the claims and their equivalents.

Claims

1. A circuit comprising a configuration terminal, comprising: the configuration terminal being configured to receive a configuration signal during a configuration phase of the circuit, an internal node coupled to the internal circuitry of the circuit, a first switch coupled between the configuration terminal and the internal node, wherein the first switch is configured to couple the configuration terminal to the internal node during the configuration phase and to decouple the configuration terminal from the internal node during normal operation of the circuit; a capacitor coupled between the configuration terminal and a reference potential; as well as A second switch is coupled directly between the internal node and the reference potential, wherein the second switch is configured to couple the internal node to the reference potential during the normal operation and to decouple the internal node from the reference potential in the configuration phase. 2 . The circuit of claim 1 , wherein the first switch comprises a transmission gate including a PMOS transistor and an NMOS transistor.

3. The circuit according to claim 2, further comprising an RC filter configured to couple the well of the PMOS transistor to the reference potential and / or an RC filter configured to couple the well of the NMOS transistor to the reference potential.

4. The circuit of claim 1 further comprising ESD protection circuitry coupled to the internal node. 5 . The circuit of claim 1 , further comprising control circuitry configured to control the first switch and / or the second switch. 6 . The circuit of claim 1 , further comprising a further terminal configured to control the first switch and / or the second switch. 7 . The circuit of claim 1 , further comprising a radio frequency terminal configured to receive a radio frequency signal adjacent to the configuration terminal.

8. The circuit of claim 1, wherein the capacitor comprises an integrated circuit capacitor.

9. A method for operating a configuration terminal, comprising: coupling the configuration terminal to an internal node of the circuit during a configuration phase, decoupling the configuration terminal from the internal node during normal operation; as well as capacitively coupling the configuration terminal to a reference potential, wherein the method is performed using a circuit comprising a first switch coupled between the configuration terminal and the internal node and a second switch coupled directly between the internal node and the reference potential, and Wherein the method further comprises coupling the internal node to a reference potential during the normal operation and decoupling the internal node from the reference potential during the configuration phase.

10. The method of claim 9, further comprising applying a radio frequency signal to another terminal of the circuit during normal operation.

11. The method of claim 9, further comprising coupling ESD protection circuitry to the internal node.

12. The method of claim 9, wherein capacitively coupling the configuration terminal or the internal node to a reference potential comprises capacitively coupling the configuration terminal or the internal node to the reference potential with an integrated circuit capacitor.

13. A circuit comprising a configuration terminal, comprising: the configuration terminal; an internal node coupled to internal circuitry of the circuit; a first switch having a current path and a first control node, wherein the current path is coupled directly between the configuration terminal and the internal node, wherein the first switch is configured to couple the configuration terminal with the internal node during a configuration phase of the circuit and to decouple the configuration terminal from the internal node during normal operation of the circuit; as well as a capacitor coupled between the configuration terminal and a reference potential; as well as a second switch having a current path and a second control node, the second control node not directly connected to the first control node, wherein the current path is directly coupled between the internal node and the reference potential, wherein the second switch is configured to couple the internal node to the reference potential during the normal operation and to decouple the internal node from the reference potential in the configuration phase.

14. The circuit of claim 13, wherein the first switch comprises a transmission gate including a PMOS transistor and an NMOS transistor. 15 . The circuit of claim 14 , further comprising an RC filter configured to couple the well of the PMOS transistor to a reference potential and / or an RC filter configured to couple the well of the NMOS transistor to the reference potential.

16. The circuit of claim 13, further comprising ESD protection circuitry coupled to the internal node. 17 . The circuit of claim 13 , further comprising control circuitry configured to control the first switch and / or the second switch.

18. The circuit of claim 13, further comprising a radio frequency terminal adjacent to the configuration terminal.

19. The circuit of claim 15, wherein the capacitor comprises an integrated circuit capacitor.

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