Front-end circuitry that performs analog-to-digital conversion and touch processing circuitry that includes it.

Abstract

This disclosure relates to a front-end circuit for performing analog-to-digital conversion and a touch processing circuit including the same. The touch processing circuit includes: a front-end circuit comprising an amplifier, a first capacitor, a second capacitor, a third capacitor, and a plurality of switches, each switch having two ends selectively connected to each other, the front-end circuit being configured to process an input signal that varies according to a touch; and a controller that controls the plurality of switches such that the front-end circuit is configured as a first circuit to accumulate a deviation of the input signal between a first stage and a second stage during an integration period, and a second circuit to convert the accumulated deviation into a digital signal during a conversion period.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0059700, filed on May 21, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Background Technology

[0003] Example embodiments of the inventive concept relate to signal processing. For example, at least some example embodiments relate to front-end circuitry that performs analog-to-digital conversion and / or touch processing circuitry that includes the front-end circuitry.

[0004] Touch systems that receive user input based on touch events are already used in a variety of applications. For example, a touch system may include an array of sensors arranged on a display panel and can detect the coordinates of objects (such as a part of a user's body or a stylus) that approach or touch the sensor array. Touch systems can be used as components for receiving user input in mobile applications such as mobile phones, as well as in fixed applications such as self-service kiosks. Therefore, touch systems may need to have reduced costs (e.g., reduced power consumption and smaller footprint) and accurate touch event detection. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a signal processing method for detecting touch events is provided, and more specifically, a front-end circuit for performing analog-to-digital conversion and a touch processing circuit including the front-end circuit are provided.

[0006] According to an exemplary embodiment of the present invention, a front-end circuit can be configured to process an input signal that varies according to a touch. The front-end circuit may include a plurality of switches, each configured to selectively form a closed circuit; an amplifier configured to operate during an integration period and a conversion period, wherein during the integration period, a deviation of the input signal between a first stage and a second stage is accumulated as a cumulative deviation, and during the conversion period, the cumulative deviation is converted into a digital signal; a first capacitor configured to sample the input signal during the integration period through at least some of the plurality of switches and to sample the output voltage of the amplifier during the conversion period; a second capacitor configured to provide a common-mode voltage to the amplifier as a virtual ground during the integration period through at least some of the plurality of switches and to serve as a feedback capacitor for the amplifier during the conversion period; and a third capacitor configured to serve as a feedback capacitor during the integration period through at least some of the plurality of switches and to sample the output voltage during the conversion period.

[0007] According to an exemplary embodiment of the present invention, a touch processing circuit includes: a front-end circuit comprising an amplifier, a first capacitor, a second capacitor, a third capacitor, and a plurality of switches, each switch being configured to selectively form a closed circuit, the front-end circuit being configured to process an input signal that varies according to a touch; and a controller configured to control the plurality of switches such that the front-end circuit is configured to: a first circuit for accumulating a deviation of the input signal between a first stage and a second stage as an accumulated deviation during an integration period; and a second circuit for converting the accumulated deviation into a digital signal during a conversion period.

[0008] According to an exemplary embodiment of the present invention, a touch processing circuit is configured to detect a touch based on capacitance that varies according to the touch. The touch processing circuit includes: a front-end circuit comprising an amplifier, a first capacitor, a second capacitor, a third capacitor, and a plurality of switches; the front-end circuit is configured to: generate an input signal based on the capacitance change; accumulate a deviation of the input signal between a first stage and a second stage as a cumulative deviation during an integration period; and convert the cumulative deviation into a digital signal during a conversion period; and a controller configured to control the plurality of switches to operate the amplifier, the first capacitor, the second capacitor, and the third capacitor during the integration period and the conversion period. Attached Figure Description

[0009] Exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0010] Figure 1A and 1B This is a block diagram illustrating an example of a touch system according to one or more example embodiments;

[0011] Figure 2 This is a block diagram illustrating an example of a front-end circuit according to an exemplary embodiment;

[0012] Figure 3 This is a block diagram illustrating an example of a circuit configured by a reconfigurable circuit according to an operating cycle, based on an exemplary embodiment;

[0013] Figure 4 This illustrates an example embodiment. Figure 2 Timing diagram of an example of the input signal;

[0014] Figure 5 This is a flowchart illustrating an example of an operation of a touch processing circuit according to an example embodiment;

[0015] Figure 6 This is a circuit diagram of an example of a reconfigurable circuit according to an example embodiment;

[0016] Figure 7 This illustrates an example embodiment. Figure 6 Timing diagram of the operation of the reconfigurable circuit during the integration period;

[0017] Figure 8A and 8B According to one or more example embodiments Figure 6 The equivalent circuit diagram of the reconfigurable circuit during the integration period;

[0018] Figure 9A and 9B According to one or more example embodiments Figure 6 The equivalent circuit diagram of the reconfigurable circuit during the sampling period;

[0019] Figure 10 This illustrates an example embodiment. Figure 6 Timing diagram of the operation of the reconfigurable circuit during the switching cycle;

[0020] Figure 11A and 11B According to one or more example embodiments Figure 6 The equivalent circuit diagram of the reconfigurable circuit during the switching cycle;

[0021] Figure 12 This is a circuit diagram of an example of a reconfigurable circuit according to an example embodiment;

[0022] Figure 13 This is a circuit diagram of an example of a reconfigurable circuit according to an example embodiment;

[0023] Figure 14 This illustrates an example embodiment. Figure 13 Timing diagram of the operation of the reconfigurable circuit during the integration period;

[0024] Figure 15A and 15B According to one or more example embodiments Figure 13 The equivalent circuit diagram of the reconfigurable circuit during the integration period;

[0025] Figure 16 This is a block diagram of the front-end circuit according to an example embodiment;

[0026] Figure 17 This illustrates an example embodiment. Figure 16 A timing diagram illustrating an example of the operation of the front-end circuitry;

[0027] Figure 18 This is a flowchart illustrating an example of an operational touch processing circuit according to an example embodiment; and

[0028] Figure 19 This is a block diagram of a system according to an example embodiment. Detailed Implementation

[0029] Figure 1A and 1B This is a block diagram illustrating examples of touch systems 10a and 10b according to one or more example embodiments. In detail, Figure 1A This is a block diagram of a touch system 10a including a sensor array 11a, the sensor array 11a including electrodes extending intersecting each other, and Figure 1B This is a block diagram of a touch system 10b including a sensor array 11b with a dot structure. In the following text, details will be omitted. Figure 1A and 1B The superfluous description.

[0030] refer to Figure 1A The touch system 10a may include a sensor array 11a and touch processing circuitry 12a. The touch system 10a can detect the touch (or touch event) of an object on the sensor array 11a. The object can refer to any object that the sensor array 11a can sense its touch. For example, the object can refer to a part of a user's body (e.g., a finger), an object worn or used by the user (e.g., a glove, pen, etc.), or a component of another system that has a variable position depending on its operation. The touch system 10a can be used as a component for receiving input from the outside in various applications. In some example embodiments, the sensor array 11a may be arranged on a display panel, and the touch system 10a can be used to receive user input in response to a display provided to the user on the display panel. For example, the touch system 10a can be used as a component of a fixed electronic system such as a self-service terminal or a mobile electronic system such as a mobile phone. In some example embodiments, the sensor array 11a may be arranged independently on a display panel, similar to a touchpad, writing pad, smartpad, etc. In the description of the inventive concept, a touch or touch event can collectively refer to an object approaching and contacting the sensor array 11a.

[0031] Sensor array 11a may include multiple sensors arranged on the touch area to detect the location of a touch and whether a touch has occurred. For example, sensor array 11a may include multiple capacitive sensors and / or multiple resistive sensors, each capacitive sensor having a variable capacitance depending on the touch, and each resistive sensor having a variable resistance depending on the touch. Figure 1AAs shown, sensor array 11a can receive multiple transmit signals TXs from touch processing circuit 12a through multiple first channels CH1s, and can provide multiple receive signals RXs to touch processing circuit 12a through multiple second channels CH2s. In some example embodiments, the multiple first channels CH1s can be activated sequentially, and when a touch is detected based on the multiple receive signals RXs, sensor array 11a can detect the X coordinate of the touch based on the activated first channels. Furthermore, sensor array 11a can detect the Y coordinate of the touch based on the receive signal indicating the touch among the multiple receive signals RXs. In this specification, the multiple first channels CH1s may be referred to as multiple transmit channels, and the multiple second channels CH2s may be referred to as multiple receive channels.

[0032] The touch processing circuit 12a can provide multiple transmit signals TXs to the sensor array 11a and can receive multiple receive signals RXs from the sensor array 11a. Furthermore, the touch processing circuit 12a may include first front-end circuits to m-th front-end circuits FE1, ..., FEm, first digital error compensation circuits to m-th digital error compensation circuits DEC1, ..., DECm, and a controller 12_1a (where m is an integer greater than 1), and the first front-end circuits to m-th front-end circuits FE1, ..., FEm may each correspond to multiple second channels CH2s. For example, as... Figure 1A As shown, the multiple second channels CH2s may include m channels, and the multiple received signals RXs may include first received signal RX1 to m-th received signal RXm. The first front-end circuits to the m-th front-end circuits FE1, ..., FEm can respectively receive the first received signal to the m-th received signal RX1, ..., RXm, and can respectively output first digital signals to the m-th digital signals D1, ..., Dm. The first digital error compensation circuits to the m-th digital error compensation circuits DEC1, ..., DECm can receive the first digital signal to the m-th digital signal D1, ..., Dm, and can generate first digital output signals to the m-th digital output signals DO1, ..., DOm indicating whether a touch has occurred and / or the touch intensity. For example, see reference later. Figure 3 The first digital signal to the m-th digital signal D1, ..., Dm can be digital signals used for digital-to-analog conversion via a cyclic analog-to-digital converter, and the first digital error compensation circuit to the m-th digital error compensation circuit DEC1, ..., DECm can perform digital error correction logic (DCL) functions in the cyclic analog-to-digital converter. In some example embodiments, the first digital error compensation circuit to the m-th digital error compensation circuit DEC1, ..., DECm can be spaced apart from each other to be adjacent to the first front-end circuit to the m-th front-end circuit FE1, ..., FEm respectively, as will be referred to later. Figure 1BThe touch processing circuit 12a may include a single digital error compensation circuit DEC that receives the first digital output signal to the m-th digital output signals DO1, ..., DOm.

[0033] Please refer to later. Figure 2 The first front-end circuit to the m-th front-end circuits FE1, ..., FEm may each include a reconfigurable circuit based on the control signal CTR sent from the controller 12_1a, and thus can process the first received signal to the m-th received signal RX1, ..., RXm respectively with a reduced area to generate the first digital signal to the m-th digital signal D1, ..., Dm.

[0034] and Figure 1A Unlike other examples, when multiple analog signals are generated separately by multiple front-end circuits that receive multiple received signals RXs and are provided to a single analog-to-digital converter, the analog signals may be altered due to parasitic components and noise in the paths through which they are transmitted. Furthermore, as the size of the sensor array 11a (e.g., its length on the Y-axis) increases, the parasitic noise may increase further. Additionally, the time required to detect a touch may increase due to the time-division analog-to-digital conversion of the multiple analog signals, and problems such as electromagnetic interference (EMI) may arise when the clock speed of the analog-to-digital converter is increased to reduce the time required to detect a touch.

[0035] On the other hand, such as Figure 1A As shown, the digital signal is generated from the first front-end circuit at the position corresponding to the multiple second channels CH2s to the m-th front-end circuit FE1, ..., FEm. Therefore, the analog signal does not need to transmit a distance corresponding to the size of the sensor array 11a, i.e., the length on the Y-axis. Furthermore, since the path for transmitting the analog signal can be omitted, the touch processing circuit 12a can have a simple structure, and the redesign of the touch processing circuit 12a due to changes in the size of the sensor array 11a can be easily implemented.

[0036] The controller 12_1a can provide control signals CTR to the first front-end circuit to the m-th front-end circuit FE1, ..., FEm. The controller 12_1a can be called a timing controller, which can control the timing of multiple transmitted signals TXs, and can control the timing of the control signal CTR based on the timing of the multiple transmitted signals TXs.

[0037] In some example embodiments, the controller 12_1a may include combinational logic circuits containing multiple logic gates, and may control the timing of multiple transmit signals TXs and control signals CTR according to the state in the state machine.

[0038] In some other example embodiments, the controller 12_1a may be implemented using processing circuitry, such as hardware including logic circuitry, a hardware / software combination (such as a processor running software), or a combination thereof. For example, the processing circuitry may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, or an application-specific integrated circuit (ASIC). The processing circuitry may be configured as a dedicated computer to control the timing of a plurality of transmitted signals TXs and generate a control signal CTR to reconfigure at least a portion of the first front-end circuitry to the m-th front-end circuitry FE1, ..., FEm.

[0039] Controller 12_1a can reconfigure at least a portion of the first to m-th front-end circuits FE1, ..., FEm via the control signal CTR. For example, each of the first to m-th front-end circuits FE1, ..., FEm may include multiple switches, and controller 12_1a can turn each of the multiple switches on or off via the control signal CTR. A switch in the on state may have two electrically connected ends, while a switch in the off state may have two electrically disconnected ends. Therefore, controller 12_1a can reconfigure at least some of the first to m-th front-end circuits FE1, ..., FEm with different circuits according to the operating portion.

[0040] refer to Figure 1B The touch system 10b may include a sensor array 11b and a touch processing circuit 12b. The sensor array 11b may include multiple touch sensing electrodes TSE and multiple wires C1 respectively connected to the multiple touch sensing electrodes TSE. Figure 1A Unlike the touch system 10a, in Figure 1A In the touch system 10a, the first channel CH1 for transmitting multiple signals TXs and the second channel CH2 for receiving multiple signals RXs are separate from each other, while Figure 1B In the touch system 10b, the transmit signal TX and the first receive signal to the m-th receive signal RX1, ..., RXm can share multiple channels CHs.

[0041] The touch processing circuit 12b may include a first multiplexer to m-th multiplexers MUX1, ..., MUXm, a first front-end circuit to m-th front-end circuits FE1, ..., FEm, a digital error compensation circuit DEC, and a controller 12_1b. The first multiplexer to m-th multiplexers MUX1, ..., MUXm can provide transmit signals TX to multiple channels CHs, or can provide first receive signals to m-th receive signals RX1, ..., RXm transmitted through multiple channels CHs to the first front-end circuits to m-th front-end circuits FE1, ..., FEm respectively. The first front-end circuits to m-th front-end circuits FE1, ..., FEm can generate first digital signals to m-th digital signals D1, ..., Dm respectively, and can provide the first digital signals to m-th digital signals D1, ..., Dm to the digital error compensation circuit DEC. The digital error compensation circuit DEC can generate first to m-th digital output signals DO1, ..., DOm from the first digital signals to m-th digital signals D1, ..., Dm. In some example embodiments, the digital error compensation circuit DEC can sequentially output the first to the mth digital output signals DO1, ..., DOm, as referenced above. Figure 1A The touch processing circuit 12b may include multiple digital error compensation circuits adjacent to the first front-end circuit to the m-th front-end circuits FE1, ..., FEm, respectively. Referring below... Figure 1A The touch system 10a describes one or more exemplary embodiments of the inventive concept, but is not limited thereto.

[0042] Figure 2 This is a block diagram of the front-end circuit 20 according to an example embodiment.

[0043] refer to Figure 1A , 1B and 2, Figure 2 The front-end circuit 20 is Figure 1A and 1B The example shown is the first front-end circuit FE1, and Figure 1A and 1B The other front-end circuits shown can be used with Figure 2 The front-end circuit 20 is the same as or similar to that of the other circuit.

[0044] As per the above reference Figure 1A and 1B The above, Figure 2 The front-end circuit 20 can receive the first receive signal RX1 and the control signal CTR, and can output the first digital signal D1. For example... Figure 2 As shown, the front-end circuit 20 may include a preamplifier 21 and a reconfigurable circuit 22, and will be referred to below. Figure 1A describe Figure 2 .

[0045] Preamplifier 21 can receive the first received signal RX1 and can generate the input signal IN. (See above reference.) Figure 1A The first received signal RX1 can be changed when a touch occurs on the sensor in sensor array 11a that provides the first received signal RX1. For example, when sensor array 11a includes a capacitive sensor, the transmitted signal provided to sensor array 11a through the activated first channel can be a periodic signal that varies with a specific period, and the first received signal RX1 can be a periodic signal sensed by the transmitted signal in the capacitive sensor, and the preamplifier 21 can be referred to as a capacitor-to-voltage converter.

[0046] The reconfigurable circuit 22 can receive the input signal IN from the preamplifier 21 and can generate a first digital signal D1 by processing the input signal IN. For example... Figure 2 As shown, the reconfigurable circuit 22 may include an amplifier 22_1, multiple capacitors 22_2, and multiple switches 22_3. (Refer to the above reference.) Figure 1A The multiple switches 22_3 can be turned on or off according to the control signal CTR, and the amplifier 22_1 and the multiple capacitors 22_2 can be electrically interconnected with each other according to the control signal CTR to form different circuits. For example, see reference later. Figure 3 The multiple switches 22_3 can be configured with a first circuit CKT1 and a second circuit CKT2. The first circuit CKT1 accumulates the deviation of the input signal IN between different stages, and the second circuit CKT2 converts the accumulated deviation into a first digital signal D1 according to the control signal CTR. Furthermore, the multiple switches 22_3 can be configured with a third circuit CKT3, which samples the accumulated deviation according to the control signal CTR. (Refer to the following...) Figure 3 An example describing reconfigurable circuit 22.

[0047] Figure 3 This is a block diagram illustrating an example of a circuit configured by the reconfigurable circuit 22 according to an operational portion, based on an exemplary embodiment. In detail, Figure 3 The block diagram schematically illustrates the function of the circuit formed by the reconfigurable circuit 22 according to the operating portion. In the following text, reference will be made to... Figure 2 describe Figure 3 .

[0048] refer to Figure 2 and 3The reconfigurable circuit 22 can operate sequentially in the integration period, sampling period, and conversion period. The controller 12_1a can control multiple switches 22_3 to form a first circuit CKT1 in the integration period, can control multiple switches 22_3 to form a third circuit CKT3 in the sampling period, and can control multiple switches 22_3 to form a second circuit CKT2 in the conversion period.

[0049] The first circuit CKT1 can perform correlated double sampling (CDS) and accumulation. CDS can mean performing two or more samples under different conditions to eliminate the effects of unwanted noise or offset and remove common parts from the sampled values. The first circuit CKT1 can repeatedly perform CDS on the input signal IN and can generate an accumulated value ACC from the sampled values ​​accumulated by the repeatedly performed CDS.

[0050] The third circuit CKT3 can sample the accumulated value ACC in the first circuit CKT1. For example, a voltage corresponding to the value ACC accumulated by the first circuit CKT1 can be provided, and the third circuit CKT3 can sample the accumulated value ACC by storing the potential corresponding to the accumulated voltage in the capacitor CAP.

[0051] The second circuit CKT2 can convert the accumulated value ACC sampled by the third circuit CKT3 into a first digital signal D1. For example, the second circuit CKT2 can be used as... Figure 3 The illustrated cyclic analog-to-digital converter (ADC) operation may include a sample-and-hold block (S / H), an amplification block (G), an operation block (OP), a digital-to-analog converter (DAC), and a comparator (CMP). The cyclic ADC can be referred to as an algorithmic ADC, and it generates a first digital signal D1 by sampling the accumulated value ACC and repeatedly converting the remaining value RES relative to a reference value. For the cyclic ADC, the remaining value RES1 of the current cycle, the remaining value RES0 of the previous cycle, and the reference value REF0 output from the DAC can have a relationship represented by Equation 1 below.

[0052] RES1 = 2·RES0 - REF0 [Equation 1]

[0053] Figure 4 This illustrates an example embodiment. Figure 2 The timing diagram of an example input signal IN, and Figure 5 This is a flowchart illustrating an example of the operation of a touch processing circuit according to an example embodiment. In the following, reference will be made to... Figure 1A , Figure 2 and Figure 3 describe Figure 4 and Figure 5 .

[0054] refer to Figure 4 The input signal IN can have an input voltage V. IN The input voltage V IN PER by period IN And change, cycle PER IN Includes the first stage P1 and the second stage P2. Input voltage V IN It can have a deviation between the first stage P1 and the second stage P2, and this deviation can change based on touch. For example, as... Figure 4 As shown, when no touch or object approaches the sensor array, the input voltage V IN It can have a first deviation DEV1, but when a touch is present, the input voltage V IN A second deviation, DEV2, can be greater than the first deviation, DEV1. This can be achieved for each cycle of the input signal IN, PER. IN It measures deviations and can accumulate measured deviations to detect whether a touch has occurred and / or the intensity of the touch.

[0055] refer to Figure 5 The touch processing circuit 12a can operate sequentially during the integration period, sampling period, and conversion period. Operations S10, S30, and S50 can be executed during the integration period, operation S70 can be executed during the sampling period, and operation S90 can be executed during the conversion period. Furthermore, as referenced above... Figure 3 The reconfigurable circuit 22 can be configured as a first circuit CKT1 during the integration period, as a third circuit CKT3 during the sampling period, and as a second circuit CKT2 during the conversion period.

[0056] In operation S10, CDS can be executed. For example, see the following reference: Figure 7 , 8A As described in 8B, the reconfigurable circuit 22 can be switched from the current stage (1-Z) -1 The input voltage V IN Subtract the input voltage V from the previous stage IN And therefore, common noise or offset in successive stages can be removed. The reconfigurable circuit 22 can adjust the input voltage V in each of the first stage P1 and the second stage P2 via CDS. IN Perform sampling.

[0057] In operation S30, the operation of accumulating sampled values ​​can be performed. For example, the reconfigurable circuit 22 can accumulate the input voltage V sampled in the first stage P1. IN and the input voltage V sampled in the second stage P2 INThe deviation between them. Therefore, the reconfigurable circuit 22 can act as an integrator and can accumulate the input signal IN for each cycle of PER. IN The deviation.

[0058] In operation S50, an operation can be performed to determine whether the accumulation is complete. For example, controller 12_1a can determine whether the deviation has accumulated a predetermined number of times. That is, when the period PER of the predetermined number of input signals IN has elapsed... IN Once it has ended, the accumulation can also end. For example... Figure 4 As shown, when accumulation is not yet complete, operation S10 can be executed next, and the reconfigurable circuit 22 can remain in the integration period. On the other hand, when accumulation is complete, operation S70 can be executed next, and the reconfigurable circuit 22 can enter the sampling period.

[0059] In operation S70, the operation of sampling the accumulated value can be performed. For example, the reconfigurable circuit 22 can sample the accumulated deviation in operations S10 and S30. The accumulated deviation can be sampled as a voltage into two or more capacitors, and the voltage sampled into the two or more capacitors can be provided as an input for analog-to-digital conversion.

[0060] In operation S90, analog-to-digital conversion can be performed. For example, reconfigurable circuit 22 can convert the accumulated value sampled in operation S70 into a first digital signal D1. (Refer to the above) Figure 3 The reconfigurable circuit 22 can be used as a cyclic analog-to-digital converter.

[0061] Figure 6 This is a circuit diagram of an example of a reconfigurable circuit 60 according to an example embodiment. (Refer to the above.) Figure 2 The above, Figure 6 The reconfigurable circuit 60 may include an amplifier A, multiple capacitors C1p, C2p, C3p, C1n, C2n and C3n, multiple switches S01, S02, S10p to S22p and S10n to S22n, a first digital-to-analog converter to a fourth digital-to-analog converter DAC1 to DAC4, and a comparator 61.

[0062] In some example embodiments, amplifier A may include a differential amplifier and may receive a common-mode voltage V. CM Amplifier A can operate during the integration and conversion periods and can be shared by the first circuit CKT1 and the second circuit CKT2. The output voltage V of amplifier A... OUT Feedback can be provided by a feedback capacitor and can be supplied to comparator 61.

[0063] The plurality of capacitors C1p, C2p, C3p, C1n, C2n, and C3n may include a first pair of capacitors C1p and C1n, a second pair of capacitors C2p and C2n, and a third pair of capacitors C3p and C3n. In some example embodiments, the plurality of capacitors C1p, C2p, C3p, C1n, C2n, and C3n may have the same capacitance. According to the control signal CTR provided by the controller 12_1a, the plurality of switches S01, S02, S10p to S22p, and S10n to S22n may be in an on or off state, and therefore can be configured with different circuits. Furthermore, at least some of the plurality of switches S01, S02, S10p to S22p, and S10n to S22n may switch between an on and off state according to their stage in an operating section. In some exemplary embodiments, each of the plurality of switches S01, S02, S10p to S22p, and S10n to S22n may be an n-channel field-effect transistor (NFET) and / or a p-channel field-effect transistor (PFET) having a gate to which a control signal CTR is applied.

[0064] The first to fourth digital-to-analog converters (DAC1 to DAC4) and comparator 61 can be used in the conversion cycle and can be included in the second circuit CKT2. Comparator 61 can receive the output voltage V of amplifier A. OUT And it can be achieved by adjusting the output voltage V OUT The output signal C is generated by comparing it with two reference levels (i.e., a first reference level and a second reference level higher than the first reference level). OUT Therefore, the output signal C OUT This can be described as having a 1.5-bit value. The first to fourth digital-to-analog converters, DAC1 to DAC4, can receive the output signal C from comparator 61. OUT And it can output a signal with the same characteristics as the output signal C. OUT The value corresponds to the level of the reference voltage. Therefore, the first digital-to-analog converter (DAC) to the fourth digital-to-analog converter (DAC1 to DAC4) can output three different levels of reference voltage.

[0065] Figure 7 This illustrates an example embodiment. Figure 6 The timing diagram of the operation of the reconfigurable circuit 60 during the integration period, and Figure 8A and 8B This illustrates an example embodiment. Figure 6 The equivalent circuit diagram of the reconfigurable circuit 60 in the integration period.

[0066] Reference Figure 7 , 8A And 8B, Figure 7 The timing diagram shows the time PER during the integration period based on the period of the input signal IN. IN Input voltage V during the period IN Output voltage V OUT And the states of some of the multiple switches S01, S02, S10p to S22p, and S10n to S22n. Furthermore, Figure 8A The circuit diagram shows the circuit including Figure 7 The equivalent circuit 80a of the reconfigurable circuit 60 at time t11 in the first stage P1, and Figure 8B It shows that it includes Figure 7 The equivalent circuit 80b of the reconfigurable circuit 60 at time t12 in the second stage P2.

[0067] As per the above reference Figure 3 The reconfigurable circuit 60 can be configured as the first circuit CKT1 during the integration period. For this purpose, some switches S11p, S17p, S19p, S20p, S11n, S17n, S19n, and S20n can be in the on state, some switches S01, S02, S10p, S14p, S15p, S21p, S22p, S10n, S14n, S15n, S21n, and S22n can be in the off state, and other switches S12p, S13p, S16p, S18p, S12n, S13n, S16n, and S18n can switch between the on and off states according to the first stage P1 and the second stage P2. Therefore, as described below, the first pair of capacitors C1p and C1n can respond to the input voltage V. IN During sampling, the second pair of capacitors C2p and C2n can provide a common-mode voltage V to amplifier A. CM As a virtual ground, the third pair of capacitors C3p and C3n can be used as feedback capacitors for amplifier A.

[0068] Reference Figure 7 Switches S12p, S18p, S13n, and S16n can be turned on at the start of the first stage P1 and can be switched to the off state before the end of the first stage P1. Furthermore, switches S13p, S16p, S12n, and S18n can remain in the off state throughout the first stage P1. Therefore, Figure 8A The equivalent circuit 80a can be formed at time t11. When switch S16n is open, the capacitor C2n of the second pair of capacitors C2p and C2n can respond to the input voltage V. IN Sampling is performed. Additionally, the input voltage V...IN Capacitor C1p can be applied to the first pair of capacitors C1p and C1n, and as described below, due to the input voltage V in the previous stage of the first stage P1. IN Sampled by capacitor C1p, so it can be executed from the current input voltage V. IN Subtract the previous input voltage V IN The operation. As described later, one of the terminals of capacitor C2n in the second pair of capacitors C2p and C2n (common-mode voltage V) CM The terminal (which was previously applied to this point) can be connected to the inverting input of amplifier A. Therefore, a virtual ground can be provided to amplifier A as the common-mode voltage V. CM Furthermore, the integral gain can be C1p / C3p.

[0069] Switches S12p, S18p, S13n, and S16n can remain in the open state during the second stage P2. Furthermore, when the second stage P2 begins, switches S13p, S16p, S12n, and S18n can be turned on and can be switched back to the open state before the second stage P2 ends. Therefore, Figure 8B The equivalent circuit 80b can be formed at time t12. When switch S16p is open, capacitor C2p in the second pair of capacitors C2p and C2n can respond to the input voltage V. IN Sampling is performed. Additionally, the input voltage V... IN Capacitor C1n can be applied to the first pair of capacitors C1p and C1n, and as described below, due to the input voltage V in the first stage P1. IN Sampling is performed using capacitor C1n, so the current input voltage V can be used for sampling. IN Subtract the previous input voltage V IN The operation. One of the terminals of capacitor C2p in the second pair of capacitors C2p and C2n (common-mode voltage V) CM In the previous stage, P1 was commonly applied to this terminal, which can be connected to the non-inverting input terminal of amplifier A. Therefore, a virtual ground can be provided to amplifier A as the common-mode voltage V. CM Furthermore, the integral gain can be C1n / C3n.

[0070] Figure 9A and 9B According to one or more embodiments Figure 6 The equivalent circuit diagram of the reconfigurable circuit 60 during the sampling period is shown above. Figure 3 The reconfigurable circuit 60 can be configured as the third circuit CKT3 during the sampling period. As described below, in... Figure 9A and 9BIn the equivalent circuits 90a and 90b, the first pair of capacitors C1p and C1n and the third pair of capacitors C3p and C3n can sample the accumulated voltage, and the second pair of capacitors C2p and C2n can be used as feedback capacitors for amplifier A.

[0071] Reference Figure 9A During the sampling period, some switches S02, S13p, S14p, S15p, S16p, S19p, S20p, S13n, S14n, S15n, S16n, S19n, and S20n can be in the on state, while other switches S01, S11p, S12p, S17p, S18p, S21p, S22p, S11n, S12n, S17n, S18n, S21n, and S22n can be in the off state. Therefore, it is possible to form Figure 9A The equivalent circuit is 90a. (See above reference.) Figure 7 , 8A As described in 8B, since the charge corresponding to the accumulated voltage can be charged in the third pair of capacitors C3p and C3n, and the common-mode voltage V CM During the integration period, the current is applied to the two ends of the second pair of capacitors C2p and C2n, so that the first pair of capacitors C1p and C1n can be charged with the current. Figure 9A The equivalent circuit 90a has the corresponding charges of the third pair of capacitors C3p and C3n. For example, the charge discharged from the third pair of capacitors C3p and C3n can be transferred to the second pair of capacitors C2p and C2n, and therefore, the charge corresponding to the accumulated voltage can be sampled by the first pair of capacitors C1p and C1n.

[0072] Reference Figure 9B During the sampling period, some switches S13p, S14p, S15p, S16p, S19p, S20p, S22p, S13n, S14n, S15n, S16n, S19n, S20n, and S22n can be in the on state, while other switches S01, S02, S11p, S12p, S17p, S18p, S21p, S11n, S12n, S17n, S18n, and S21n can be in the off state. Furthermore, the second digital-to-analog converter DAC2 and the fourth digital-to-analog converter DAC4 can output a common-mode voltage V. CM Therefore, it can form Figure 9B The equivalent circuit is 90b. That is, Figure 9A In the equivalent circuit 90a, the terminals of the third pair of capacitors C3p and C3n can be connected to each other, while the common-mode voltage V CM Can be applied to Figure 9B The ends of the third pair of capacitors C3p and C3n in the equivalent circuit 90b.

[0073] Figure 10This illustrates an exemplary embodiment. Figure 6 The timing diagram of the operation of the reconfigurable circuit 60 during the switching cycle, and Figure 11A and 11B This illustrates an exemplary embodiment. Figure 6 The equivalent circuit diagram of the reconfigurable circuit 60 during the switching cycle. In detail, Figure 10 The timing diagram shows some of the switches S01, S02, S10p to S22p, and S10n to S22n during the transition cycle, the clock signal CLK, and the output signal C from comparator 61. OUT The state of things over time. Furthermore... Figure 11A The circuit diagram shows the circuit including Figure 10 The equivalent circuit 110a of the reconfigurable circuit 60 at time t21 in the third stage P3, and Figure 11B It shows that it includes Figure 10 The equivalent circuit 110b of the reconfigurable circuit 60 at time t22 in the fourth stage P4. In the following text, details regarding... Figure 11A and 11B Redundant description.

[0074] As per the above reference Figure 3 The reconfigurable circuit 60 can be configured as the second circuit CKT2 during the switching cycle. For this purpose, some switches S15p, S16p, S15n, and S16n can be in the ON state, some switches S01, S02, S11p, S17p, S18p, S11n, S17n, and S18n can be in the OFF state, while other switches S10p, S12p, S13p, S14p, S19p, S20p, S21p, S22p, S10n, S12n, S13n, S14n, S19n, S20n, S21n, and S22n can switch between ON and OFF states according to the third stage P3 and the fourth stage P4. Therefore, as described below, the first pair of capacitors C1p and C1n and the third pair of capacitors C3p and C3n can affect the output voltage V of amplifier A. OUT Sampling is performed, and the second pair of capacitors C2p and C2n can be used as feedback capacitors for amplifier A.

[0075] refer to Figure 11A and 11B The first to fourth digital-to-analog converters (DACs 1 to DAC4) may include two switches. For example, the first DAC DAC 1 may include one terminal to which a high-level voltage V is applied. H The first switch S1p and one end are subjected to a low-level voltage V LThe second switch S2p. The first digital-to-analog converter DAC1 can turn on one of the first switch S1p and the second switch S2p and turn off the other, or it can turn on both the first switch S1p and the second switch S2p, or it can respond to the 1.5-bit output signal C. OUT Disconnect both the first switch S1p and the second switch S2p. High-level voltage V H and low-level voltage V L The intermediate voltage between them can be the common-mode voltage V. CM Therefore, the first digital-to-analog converter DAC1 can respond to the output signal C OUT Output high-level voltage V H Common-mode voltage V CM and low-level voltage V L One of them. High-level voltage V H and low-level voltage V L The intermediate voltage between (e.g., V) CM This can be generated by turning on both the first switch S1p and the second switch S2p, or by turning off both the first switch S1p and the second switch S2p and electrically connecting the outputs of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 (e.g., by turning on...). Figure 6 Switch S01) is used to supply power to the first pair of capacitors C1p and C1n. In some example embodiments, two switches included in the first to fourth digital-to-analog converters DAC1 to DAC4 can be turned off according to the control signal CTR, and therefore, switches S10p, S22p, S10n, and S22n connected to the outputs of the first to fourth digital-to-analog converters DAC1 to DAC4 can be turned off. Figure 6 The reconfigurable circuit 60 is omitted.

[0076] Back Figure 10 Switches S14p, S22p, S14n, and S22n, as well as switches S13p, S19p, S13n, and S19n, can be in the open state during the third stage P3. Furthermore, after the start of the third stage P3, switches S12p, S21p, S12n, and S21n, as well as switches S10p, S20p, S10n, and S20n, can be turned on, and switches S12p, S21p, S12n, and S21n can be switched to the open state before the end of the third stage P3. Therefore, Figure 11A The equivalent circuit 110a can be formed at time t21. When switches S21p and S21n are open, the third pair of capacitors C3p and C3n can sample the output voltage V. OUTThe outputs from the first digital-to-analog converter DAC1 and the third digital-to-analog converter DAC3, i.e., the reference voltage, can be applied to the first pair of capacitors C1p and C1n, and as described below, because the output voltage V of the previous stage of the third stage P3... OUT Since the sampling is performed by the first pair of capacitors C1p and C1n, the operation represented by Equation 1 above can be performed by the first pair of capacitors C1p and C1n and the second pair of capacitors C2p and C2n.

[0077] After the start of the fourth stage P4, switches S14p, S22p, S14n, and S22n, as well as switches S13p, S19p, S13n, and S19n, can be turned on, and switches S13p, S19p, S13n, and S19n can be switched to the off state before the end of the fourth stage P4. Furthermore, during the fourth stage P4, switches S12p, S21p, S12n, and S21n, as well as switches S10p, S20p, S10n, and S20n, can be in the off state. Therefore, Figure 11B The equivalent circuit 110b can be formed at time t22. When switches S13p and S13n are open, the first pair of capacitors C1p and C1n can affect the output voltage V. OUT Sampling is performed. The outputs from the second digital-to-analog converter DAC2 and the fourth digital-to-analog converter DAC4, i.e., the reference voltage, can be applied to the third pair of capacitors C3p and C3n, and due to the output voltage V of the third stage P3... OUT Since the sampling is performed by the third pair of capacitors C3p and C3n, the operation represented by Equation 1 above can be performed by the third pair of capacitors C3p and C3n and the second pair of capacitors C2p and C2n.

[0078] The clock signal CLK can be provided to comparator 61, and comparator 61 can update the output signal C in response to the rising edge of the clock signal CLK. OUT The value of PER. Cycle period PER CYC This can correspond to the period of the clock signal CLK, and in some example embodiments, the cycle period PER CYC It can be less than the period PER of the input signal IN. IN .

[0079] Figure 12 This is a circuit diagram of an example of a reconfigurable circuit 120 according to an example embodiment.

[0080] Reference Figure 12 Similar to Figure 6 Reconfigurable circuit 60, Figure 12The reconfigurable circuit 120 may include an amplifier A, a first pair of capacitors C1p and C1n, a second pair of capacitors C2p and C2n, a third pair of capacitors C3p and C3n, switches S01, S02, S10p to S22p, and S10n to S22n, a first digital-to-analog converter to a fourth digital-to-analog converter DAC1 to DAC4, and a comparator 121, and may also include a fourth pair of capacitors C4p and C4n and switches S23p to S26p, and S23n to S26n. In the following text, references to the above will be omitted. Figure 6 Provided about Figure 12 The description.

[0081] The fourth pair of capacitors, C4p and C4n, can be used additionally as feedback capacitors for amplifier A during the integration period. For example, during the integration period, switches S23p, S24p, S23n, and S24n can be in the on state, and switches S25p, S26p, S25n, and S26n can be in the off state. Therefore, the feedback capacitors of amplifier A can be "C3p + C4p" in the first stage P1 and "C3n + C4n" in the second stage P2. Therefore, the integration gain can be "C1p / (C3p + C4p)" in the first stage P1 and "C1n / (C3n + C4n)" in the second stage P2. Depending on the desired integration gain, the fourth pair of capacitors, C4p and C4n, can have the same capacitance as the other capacitors, or they can have different capacitances, such as larger capacitances than the other capacitors.

[0082] The fourth pair of capacitors C4p and C4n may be included in the first circuit CKT1 during the integration period as described above, but may not be included in the third circuit CKT3 during the sampling period and the second circuit CKT2 during the conversion period. For example, during the sampling period and the conversion period, switches S23p, S24p, S23n, and S24n may be in the open state, and switches S25p, S26p, S25n, and S26n may be in the closed state. Therefore, at the end of the integration period, similar to the third pair of capacitors C3p and C3n, a charge corresponding to the accumulated voltage can be charged into the fourth pair of capacitors C4p and C4n, and when the sampling period begins, the charge charged into the fourth pair of capacitors C4p and C4n can be discharged.

[0083] Figure 13 This is a circuit diagram of an example of a reconfigurable circuit 130 according to an example embodiment.

[0084] Reference Figure 13 Similar to Figure 6 Reconfigurable circuit 60, Figure 13The reconfigurable circuit 130 may include an amplifier A, a first pair of capacitors C1p and C1n, a second pair of capacitors C2p and C2n, a third pair of capacitors C3p and C3n, switches S01, S02, S10p to S22p, and S10n to S22n, a first digital-to-analog converter to a fourth digital-to-analog converter DAC1 to DAC4, and a comparator 131. It may also include a fifth pair of capacitors C5p and C5n, and switches S31p to S33p, and S31n to S33n. In the following text, references to the above will be omitted. Figure 6 Provided about Figure 13 The description.

[0085] The fifth pair of capacitors, C5p and C5n, can be used to compensate for the input offset voltage of amplifier A during the integration period. To prevent the input offset voltage of amplifier A from accumulating during the integration period, the input offset voltage of amplifier A can be sampled in the fifth pair of capacitors, C5p and C5n. For example, see reference later. Figure 14 , 15A As described in 15B, when switches S32p, S33p, S32n, and S33n are in the ON state and switches S31p and S31n are in the OFF state, the input offset voltage of amplifier A can be sampled in the fifth pair of capacitors C5p and C5n. Furthermore, when switches S32p, S33p, S32n, and S33n are in the OFF state and switches S31p and S31n are in the ON state, the input offset voltage sampled in the fifth pair of capacitors C5p and C5n can be compensated during integration.

[0086] The following will refer to Figure 14 , 15A Example of operation of the input offset voltage of the compensation amplifier A is described in section 15B.

[0087] Figure 14 This illustrates an exemplary embodiment. Figure 13 The timing diagram of the operation of the reconfigurable circuit 130 during the integration period, and Figure 15A and 15B This illustrates an exemplary embodiment. Figure 13 The equivalent circuit diagram of the reconfigurable circuit 130 during the integration period. In detail, Figure 14 The timing diagram shows the input voltage V during the integration period. IN Output voltage V OUT And some of the multiple switches S01, S02, S10p to S22p, S10n to S22n, S31p to S33p, and S31n to S33n, according to the period PER of the input signal IN. IN The state of time during that period. Furthermore... Figure 15A The circuit diagram shows the circuit including Figure 14 The equivalent circuit 140a of the reconfigurable circuit 130 at time T31 in the first stage P1, and Figure 15B It shows that it includes Figure 14 The equivalent circuit 140b of the reconfigurable circuit 130 at time T32 in the second stage P2. The operation for compensating the input offset of amplifier A, performed in the first stage P1, will be described below; however, the operation for compensating the input offset of amplifier A can be similarly performed in the second stage P2. In the following text, the above-mentioned references will be omitted. Figure 7 , 8A And 8B provided information about Figure 14 , 15A And the description of 15B.

[0088] Reference Figure 14 Switches S31p and S31n can be opened before the start of the first stage P1, and switches S32p, S33p, S32n, and S33n can be turned on at the start of the first stage P1. Therefore, Figure 15A The equivalent circuit 150a can be formed at time t31. When switches S32p, S33p, S32n and S33n are open, the fifth pair of capacitors C5p and C5n can sample the input offset voltage of amplifier A.

[0089] After switching switches S32p, S33p, S32n, and S33n to the open state, switches S31p and S31n can be turned on. Therefore, Figure 15B The equivalent circuit 150b can be formed at time t32. Since the input offset voltage of amplifier A is sampled by the fifth pair of capacitors C5p and C5n, the sampling input offset voltage of amplifier A can be compensated during integration.

[0090] Figure 16 This is a block diagram of the front-end circuit 160 according to an exemplary embodiment of the present invention, and Figure 17 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 16 A timing diagram illustrating an example of the operation of the front-end circuit 160.

[0091] refer to Figure 16 and 17 , Figure 16 The block diagram shows a front-end circuit 160 including a preamplifier 161 that receives a reset signal RST and a reconfigurable circuit 162, and Figure 17 The timing diagram shows when Figure 16 The reconfigurable circuit 162 corresponds to Figure 13 When the reconfigurable circuit 130 is in the integration period, during the period PER of the input signal IN... IN During the period, the reset signal RST and the input voltage VIN The states of multiple switches S31p to S33p and S31n to S33n over time. In the following text, the states already referenced above will be omitted. Figure 13 , 14 The information provided by 15A and 15B regarding Figure 16 and 17 The description.

[0092] In some example embodiments, the preamplifier 161 can be reset at each stage. For example, as... Figure 17 As shown, Figure 1A The controller 12_1a can generate a reset signal RST and a control signal CTR, and the reset signal RST can be activated in a first reset cycle R1 included in the first stage P1 and a second reset cycle R2 included in the second stage P2. The preamplifier 161 can generate a variable input voltage V in response to, for example, a reset signal RST that is deactivated at a low level. IN The input signal IN is as described above with reference to the accompanying drawings. On the other hand, the preamplifier 161 can initialize the input signal IN in response to, for example, a reset signal RST that is activated at a high level. For example, as... Figure 17 As shown, the input voltage V IN It can be initialized to a first voltage V1 that is relatively high in the first reset cycle R1 and a second voltage V2 that is relatively low in the second reset cycle R2.

[0093] In some example embodiments, the operation of sampling the input offset voltage of amplifier A can be performed at the input voltage V. IN Executed during the initialized reset cycle. For example, as... Figure 17 As shown, during the portion including the first reset cycle R1, switches S31p and S31n can be in the off state, and during the first reset cycle R1, switches S32p, S33p, S32n, and S33n can be in the on state. Similarly, during the portion including the second reset cycle R2, switches S31p and S31n can be in the off state, and during the second reset cycle R2, switches S32p, S33p, S32n, and S33n can be in the on state. Due to the input voltage V IN It can have a constant level, independent of touch during the reset cycle, so the input offset voltage of amplifier A can be accurately sampled.

[0094] Figure 18 This is a flowchart illustrating an example of the operation of a touch processing circuit according to an example embodiment.

[0095] Reference Figure 18 Similar to Figure 5Operations S10', S30', and S50' can be executed during the integration period, operation S70' can be executed during the sampling period, and operation S90' can be executed during the conversion period. Additionally, such as Figure 18 As shown, operation S60 can be performed between the integration period and the sampling period. In the following text, the references already made will be omitted. Figure 5 Provided about Figure 18 The description, and will refer to Figure 1A and Figure 2 describe Figure 18 .

[0096] refer to Figure 1A , 2 In step S60, after the integration period, the preamplifier 21 can be disabled. As described above with reference to the accompanying drawings, the input signal IN may not be used in the conversion period after the sampling and integration periods; therefore, the preamplifier 21 can be disabled during the sampling and conversion periods. For example, the controller 12_1a can disable the preamplifier 21 by preventing the input signal IN from being passed to the reconfigurable circuit 22 or by preventing the power supplied to the preamplifier 21. Therefore, in the portion after the integration period, especially during the conversion period, the noise caused by the input signal IN and the preamplifier 21, as well as the accuracy of the cyclic analog-to-digital conversion, can be improved. In some example embodiments, in addition to the preamplifier 21, the generator that generates [something else] can also be disabled in step S60. Figure 1A The circuit can transmit multiple signals TXs, or it can disable multiple first channels CH1s.

[0097] Figure 19 This is a block diagram of system 190 according to an example embodiment.

[0098] refer to Figure 19 ,like Figure 19 As shown, system 190 may include a central processing unit (CPU) 191, a memory 192, a network interface 193, a touch panel 194, a display panel 195, and a touch display driver IC (DDI) 196. In some exemplary embodiments, different... Figure 19 For example, CPU 191 and other components of system 190 can be connected to each other to communicate with each other via a bus.

[0099] CPU 191 can execute instructions stored in memory 192 or in the memory within CPU 191 to control the overall operation of system 190. For example, CPU 191 can provide image data to touch DDI 196, can recognize external input based on the image output to display panel 195 and detected touch, and can perform at least one pre-set function in response to external input. In some example embodiments, CPU 191 can be a system-on-chip (SoC) including a processor, bus, and function blocks, or it can be referred to as an application processor (AP).

[0100] Memory 192 can be accessed by CPU 191 and may include non-volatile memory (such as electrically erasable programmable read-only memory (EEPROM), flash memory, phase change RAM (PRAM), resistance RAM (RRAM), nano floating gate memory (NFGM), polymer RAM (PoRAM), magnetic RAM (MRAM), ferroelectric RAM (FRAM), etc.) or volatile memory (such as dynamic RAM (DRAM), static RAM (SRAM), mobile DRAM, double data rate synchronous DRAM (DDR SDRAM), low power DDR (LPDDR) SDRAM, graphic DDR (GDDR) SDRAM, Rambus DRAM (RDRAM), etc.).

[0101] Network interface 193 can provide CPU 191 with an interface to networks outside system 190. For example, network interface 193 can access wired or wireless networks and can transmit signals sent from the network to CPU 191 or from CPU 191 to the network.

[0102] The touch DDI 196 can be implemented as at least one chip, such as a single chip formed on a substrate. Figure 19As shown, the touch DDI 196 may include an analog front-end (AFE) 196_1 and a touch controller 196_2 as a component for controlling the touch panel 194, and may also include an output driver 196_3 and a display controller 196_4 as a component for controlling the display panel 195. The analog front-end 196_1 and the touch controller 196_2 can be collectively referred to as touch processing circuitry. The touch panel 194 may be arranged on the display panel 195 to transmit light emitted from the display panel 195, and the touch panel 194 and the display panel 195 can be collectively referred to as a touch screen.

[0103] Analog front-end 196_1 can provide a transmit signal TX to touch panel 194 and can receive a receive signal RX from touch panel 194. According to an exemplary embodiment of the present invention, analog front-end 196_1 can include multiple front-end circuits, and therefore, touch can be detected with improved accuracy and reduced cost. Touch controller 196_2 can detect touch based on the digital signal provided by analog front-end 196_1 and can provide signals including information about the touch to CPU 191.

[0104] Display controller 196_4 can convert image data provided by CPU 191 into signals to be displayed on display panel 195, and output driver 196_3 can output display output signal DIS_OUT under the control of display controller 196_4. Figure 19 As shown, the display controller 196_4 can communicate with the touch controller 196_2. For example, the display controller 196_4 can provide the touch controller 196_2 with signals including information about display timing, and the touch controller 196_2 can provide the display controller 196_4 with signals including information about the operating mode, such as whether to enter standby mode.

[0105] In some example embodiments, the touch DDI 196 may include memory accessed by the touch controller 196_2 and / or the display controller 196_4, and may also include power supply circuitry that provides power to the analog front-end 196_1 and the output driver 196_3. Furthermore, in some example embodiments, unlike... Figure 19 In the example shown, the touch controller 196_2 and the display controller 196_4 can communicate with the CPU 191 via separate interfaces (e.g., LosSI, I2C, etc.).

[0106] While the concept of the invention has been specifically shown and described with reference to exemplary embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A front-end circuit configured to process an input signal that varies according to a touch, the front-end circuit comprising: a plurality of switches, each of the plurality of switches configured to selectively form a closed circuit; an amplifier configured to operate during an integration period and a conversion period, in the integration period, a deviation of the input signal between a first phase and a second phase is accumulated as an accumulated deviation, and in the conversion period, the accumulated deviation is converted to a digital signal; a first capacitor configured to sample, through at least some of the plurality of switches, the input signal during the integration period, and to sample an output voltage of the amplifier during the conversion period; a second capacitor configured to provide, through at least some of the plurality of switches, a common mode voltage as a virtual ground to the amplifier during the integration period, and to act as a feedback capacitor of the amplifier during the conversion period; and a third capacitor configured to act as a feedback capacitor through at least some of the plurality of switches during the integration period, and to sample the output voltage during the conversion period.

2. The front-end circuit of claim 1, further comprising: a fourth capacitor configured to act as a feedback capacitor through at least some of the plurality of switches during the integration period.

3. The front-end circuit of claim 1, further comprising: a fifth capacitor configured to sample, through at least some of the plurality of switches, an input offset voltage of the amplifier before the first capacitor samples the input signal during the integration period.

4. The front-end circuit of claim 1, further comprising: a comparator configured to compare the output voltage to at least one reference level; and a digital-to-analog converter configured to output a reference voltage having a level that varies according to an output signal of the comparator, wherein the amplifier, the first capacitor, the second capacitor, the third capacitor, the comparator, and the digital-to-analog converter are configured to operate as a cyclic analog-to-digital converter during the conversion period through at least some of the plurality of switches.

5. The front-end circuit of claim 1, wherein the first capacitor, the second capacitor, and the third capacitor have the same capacitance.

6. A touch processing circuit comprising: a front-end circuit comprising an amplifier, a first capacitor, a second capacitor, a third capacitor, and a plurality of switches, each of the plurality of switches configured to selectively form a closed circuit, the front-end circuit configured to process an input signal that varies according to a touch; and a controller configured to control the plurality of switches such that the front-end circuit is configured to a first circuit for accumulating, during an integration period, a deviation of the input signal between a first phase and a second phase as an accumulated deviation, and a second circuit for converting, during a conversion period, the accumulated deviation to a digital signal. ​ wherein the controller is configured to control the plurality of switches during the conversion period such that an output voltage of the amplifier and a reference voltage are alternately applied to the first capacitor and the third capacitor, and the second capacitor functions as a feedback capacitor of the amplifier.

7. The touch processing circuit of claim 6, wherein the controller is configured to control the plurality of switches during the integration period such that, the first capacitor samples the input signal in either the first phase or the second phase, the second capacitor provides a common mode voltage of the amplifier as a virtual ground in the first phase and the second phase, and the third capacitor functions as a feedback capacitor of the amplifier.

8. The touch processing circuit of claim 7, further comprising: a fourth capacitor, wherein the controller is configured to control the plurality of switches during the integration period such that the fourth capacitor functions as a feedback capacitor of the amplifier during the integration period.

9. The touch processing circuit of claim 7, further comprising: a fifth capacitor, wherein the controller is configured to control the plurality of switches during the integration period such that the fifth capacitor samples an input offset voltage of the amplifier before the first capacitor samples the input signal during the integration period.

10. The touch processing circuit of claim 9, wherein, the first phase and the second phase each include a reset period in which the input signal is initialized, and the controller is configured to control the plurality of switches during the reset period such that the fifth capacitor samples the input offset voltage during the reset period.

11. The touch processing circuit of claim 6, wherein, the front-end circuit comprises: a comparator configured to compare the output voltage with a voltage level of the reference voltage; and a digital-to-analog converter configured to output the reference voltage such that the voltage level of the reference voltage varies according to an output signal of the comparator, wherein the second circuit is configured to operate as a cyclic analog-to-digital converter comprising the comparator and the digital-to-analog converter.

12. The touch processing circuit of claim 11, wherein the controller is configured to control the plurality of switches during the conversion period such that the cyclic analog-to-digital converter operates at a period different from a period of the first phase and the second phase that includes the input signal.

13. The touch processing circuit of claim 6, wherein the controller is configured to control the plurality of switches during a sampling period such that the front-end circuit is configured as a third circuit that samples the accumulated offset, the third circuit comprising the amplifier, the first capacitor, the second capacitor, and the third capacitor, the sampling period being between the integration period and the conversion period.

14. The touch processing circuit of claim 13, wherein, The controller is configured to control the plurality of switches during the sampling period to cause the first and third capacitors to sample the accumulated offset during the sampling period, and the second capacitor to act as a feedback capacitor for the amplifier during the sampling period.

15. The touch processing circuit of claim 6, wherein, the front-end circuit further comprises a preamplifier configured to generate the input signal based on a change in capacitance according to the touch, and the controller is configured to disable the preamplifier during the conversion period.

16. The touch processing circuit of claim 6, wherein, the first, second, and third capacitors have the same capacitance.

17. The touch processing circuit of claim 6, further comprising: a plurality of front-end circuits connected to a sensor array through a plurality of receive channels, respectively, the sensor array configured to provide a change in capacitance according to the touch, wherein the controller is configured to control the plurality of front-end circuits.

18. A touch processing circuit configured to detect a touch based on a change in capacitance according to the touch, the touch processing circuit comprising: a front-end circuit comprising an amplifier, a first capacitor, a second capacitor, a third capacitor, and a plurality of switches, the front-end circuit configured to, produce an input signal based on the change in capacitance, accumulate a deviation of the input signal between a first phase and a second phase during an integration period as an accumulated offset, and convert the accumulated offset into a digital signal during a conversion period; and a controller configured to control the plurality of switches to cause the amplifier, the first capacitor, the second capacitor, and the third capacitor to operate in the integration period and the conversion period, wherein, the controller is configured to control the plurality of switches during the conversion period such that an output voltage of the amplifier and a reference voltage are alternately applied to the first and third capacitors, and the second capacitor acts as a feedback capacitor for the amplifier.

19. The touch processing circuit of claim 18, wherein the controller is configured to control the plurality of switches during the integration period to cause: the first capacitor to sample the input signal in the first phase or the second phase, the second capacitor to provide a common mode voltage of the amplifier as a virtual ground in the first phase and the second phase, and the third capacitor to act as a feedback capacitor for the amplifier.

20. The touch processing circuit of claim 18, wherein, the front-end circuit comprises: a comparator configured to compare the output voltage with a voltage level of the reference voltage; and a digital-to-analog converter configured to output the reference voltage such that the voltage level of the reference voltage varies according to an output signal of the comparator, wherein the front-end circuit is configured to operate as a cyclic analog-to-digital converter comprising the comparator and the digital-to-analog converter.

21. The touch processing circuit of claim 18, wherein, the controller is configured to control the plurality of switches during a sampling period between the integration period and the conversion period such that the front-end circuit is configured as a third circuit to sample the accumulated offset, the third circuit comprising the amplifier, the first capacitor, the second capacitor, and the third capacitor.

22. The touch processing circuit of claim 21, wherein, the controller is configured to control the plurality of switches during the sampling period such that the first capacitor and the third capacitor sample the accumulated offset, and the second capacitor is used as a feedback capacitor for the amplifier.

23. The touch processing circuit of claim 18, wherein, the front-end circuit further comprises a capacitance-to-voltage converter configured to generate the input signal during the integration period, and the controller is configured to disable the capacitance-to-voltage converter during the conversion period.

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