Class D amplifier

Abstract

The present disclosure relates to a class-D amplifier circuit, which includes: an input terminal for receiving an input signal; and first and second output nodes for driving a load connected between the first and second output nodes. A first driver stage is provided for switching the first node between a first power rail and a second power rail, and a second driver stage is provided for switching the second node between the first power rail and the second power rail. The class-D amplifier circuit further includes: a first driver control circuit configured to receive a first carrier and control the switching of the first driver stage partially based on the first carrier; a second driver control circuit configured to receive a second carrier and control the switching of the second driver stage partially based on the second carrier; and a carrier generator configured to provide the first carrier and the second carrier. The phase shift between the first carrier and the second carrier can be adjusted in response to a mode control signal.

Description

Technical Field

[0001] The present disclosure relates to the field of class-D amplifiers. Specifically, the present disclosure relates to systems and methods for dynamically adjusting the operating mode of a class-D amplifier. Background Art

[0002] Class-D amplifiers are increasingly used in the output stages of electronic devices where power efficiency is important, such as mobile phones, portable media players, laptop computers, tablet computers, and wireless headsets, headphones, and earbuds.

[0003] A class-D amplifier receives an analog input signal and outputs a pulse train, where the width and spacing of the pulses represent the amplitude of the input analog signal.

[0004] Some class-D amplifiers can be designed to operate in class-AD mode, and some class-D amplifiers can be designed to operate in class-BD mode.

[0005] In a class-AD design, the signal output by the class-D amplifier at a given point in time can take on one of two amplitude values (i.e., a high value and a low value). Thus, in class-AD mode, the output signal is two-level. This is schematically shown in the upper waveform diagram 110 of Figure 1 which shows (in the bottom waveform 112) the differential signal applied to the bridge-connected load by the output stage of a full-bridge class-D amplifier, and the corresponding output signals 114, 116 generated by the first and second drivers of the output stage of the amplifier. In this example, the output signals 114, 116 generated by the first and second drivers swing between the positive supply rail voltage +Vdd and the negative supply rail voltage -Vdd, and these signals always have opposite polarities, so the differential signal applied to the load can only be +2Vdd or -2Vdd (assuming the magnitude of +Vdd is equal to -Vdd).

[0006] In class-BD mode, the signal output by the class-D amplifier at a given point in time can take on one of the following three amplitude values: a high value; a low value; and an intermediate value between the high value and the low value. Thus, in class-BD mode, the output signal is three-level. This is shown in Figure 1is schematically shown in the lower waveform diagram 120, which shows the differential signal applied by the output stage of the full-bridge class-D amplifier to the bridge-connected load (in the lowest waveform 122), and the corresponding output signals 124, 126 generated by the first and second drivers of the output stage of the amplifier. In this example, the output signals 124, 126 generated by the first driver and the second driver swing between the positive power supply rail voltage +Vdd and the negative power supply rail voltage –Vdd. These outputs sometimes have opposite polarities, but sometimes also have the same polarity, so the differential signal applied to the load can be +2Vdd or -2Vdd (assuming the magnitude of +Vdd is equal to –Vdd) or 0V.

[0007] The choice of designing a particular class-D amplifier to operate in class-AD mode or class-BD mode depends on the requirements of the particular application for which the class-D amplifier is to be used. Each mode offers different advantages and disadvantages. SUMMARY OF THE INVENTION

[0008] According to a first aspect, the present invention provides a class-D amplifier circuit, comprising: an input terminal for receiving an input signal; first and second output nodes for driving a load connected between the first and second output nodes; a first driver stage for switching the first node between a first power supply rail and a second power supply rail; a second driver stage for switching the second node between the first power supply rail and the second power supply rail; a first driver control circuit configured to receive a first carrier wave and control the switching of the first driver stage partially based on the first carrier wave; a second driver control circuit configured to receive a second carrier wave and control the switching of the second driver stage partially based on the second carrier wave; and a carrier wave generator configured to provide the first carrier wave and the second carrier wave, wherein the phase shift between the first carrier wave and the second carrier wave is adjustable in response to a mode control signal.

[0009] The first driver control circuit may be configured to receive a first signal derived from the input signal and control the switching of the first driver stage partially based on the first signal derived from the input signal; and the second driver control circuit may be configured to receive a second signal derived from the input signal and control the switching of the second driver stage partially based on the second signal derived from the input signal.

[0010] In some embodiments, the first and second signals derived from the input signal are complementary signals of a differential signal pair.

[0011] In other embodiments, the first and second signals derived from the input signal are the same.

[0012] The first driver control circuit may be operable to compare the first signal derived from the input signal with the first carrier and to control the switching of the first driver stage based on the comparison; and the second driver control circuit may be operable to compare the second signal derived from the input signal with the second carrier and to control the switching of the second driver stage based on the comparison.

[0013] Alternatively or additionally, the first driver control circuit may be operable to compare a first differential signal with the first carrier, the first differential signal indicating the difference between the signal output by the first driver stage and the first signal derived from the input signal, and to control the switching of the first driver stage based on the comparison; and the second driver control circuit may be operable to compare a second differential signal with the second carrier, the second differential signal indicating the difference between the signal output by the second driver stage and the second signal derived from the input signal, and to control the switching of the second driver stage based on the comparison.

[0014] The first differential signal may represent, for example, the integral of the difference between the voltage of the signal output by the first driver stage and the voltage of the first signal derived from the input signal; and the second differential signal may represent the integral of the difference between the voltage of the signal output by the second driver stage and the voltage of the second signal derived from the input signal.

[0015] The first differential signal may be provided at the output of a first loop filter of the first driver control circuit, and the second differential signal may be provided at the output of a second loop filter of the second driver control circuit.

[0016] The first driver control circuit may include a first integrator circuit configured to receive a first digital signal and to generate the first carrier based on the received first digital signal; and the second driver control circuit may include a second integrator circuit configured to receive a second digital signal and to generate the second carrier based on the received second digital signal.

[0017] The first digital signal and the second digital signal may include respective first and second square wave current waveforms.

[0018] In a first operating mode, the phase shift between the first carrier and the second carrier may be substantially 180 degrees.

[0019] In the second operating mode, the phase shift between the first carrier and the second carrier can be substantially zero.

[0020] In the third operating mode, the phase shift between the first carrier and the second carrier can be a non-zero value other than 180 degrees.

[0021] The carrier generator can be operated to adjust the phase difference between the first carrier and the second carrier between a non-zero value and zero within a predetermined period of time so as to transition from the first or third operating mode to the second operating mode, and to adjust the phase difference between the first carrier and the second carrier between zero and a non-zero value within a predetermined period of time so as to transition from the second operating mode to the first or third operating mode.

[0022] The carrier generator can be operated to substantially continuously scan the phase difference between the first carrier and the second carrier.

[0023] The class D amplifier circuit can further include a monitoring circuit configured to generate the mode control signal based on an indication, parameter, characteristic, or feature of the input signal.

[0024] In one embodiment, the monitoring circuit is configured to monitor a parameter of the input signal and, if the monitored parameter of the input signal reaches or drops below a first threshold, generate a mode control signal to cause the class D amplifier circuit to transition from a first operating mode to a second operating mode, and if the monitored parameter of the input signal reaches or exceeds a second threshold, generate a mode control signal to cause the class D amplifier to transition from the second operating mode to the first operating mode.

[0025] The monitored parameter of the input signal can include at least one of the following: the instantaneous signal level of the input signal; and the envelope of the input signal.

[0026] The second threshold can be different from the first threshold.

[0027] The monitoring circuit can be configured to receive information about the input signal and generate the mode control signal based on the received information. The received information can include at least one of the following: a received indication of the signal level of the input signal; a received indication of an upcoming change in the signal level of the input signal; a received indication of a load attached to the class D amplifier circuit; a received indication of the signal type of the input signal; and a received indication that a silent period has been detected in the input audio signal.

[0028] The monitoring circuit may be configured to generate the mode control signal based on at least one of the following: the signal level of the output signal of the class D amplifier circuit; the envelope of the output signal of the class D amplifier circuit; the duty cycle of the signal at the first or second output node; and the duty cycle of the output signal of the first or second driver control circuit.

[0029] In an embodiment, the carrier generator includes: a source carrier input terminal for receiving a source carrier; a first carrier output terminal for outputting a first carrier; a second carrier output terminal for outputting a second carrier; and a multiplexer. In this embodiment, the source carrier input terminal is coupled to the first carrier output terminal and the first input terminal of the multiplexer; the second input terminal of the multiplexer is configured to receive an inverted version of the source carrier; the output terminal of the multiplexer is coupled to the second carrier output terminal; and the multiplexer is configured to selectively couple its first input terminal or its second input terminal to its output terminal according to the mode control signal, such that the carrier generator outputs the source carrier or the inverted version of the source carrier at the second carrier output terminal and outputs the source carrier at the first carrier output terminal.

[0030] The carrier generator may include an inverting stage coupled between the source carrier input terminal and the second input terminal of the multiplexer.

[0031] In an embodiment, the carrier generator includes: a source carrier input terminal for receiving a source carrier; a first carrier output terminal for outputting a first carrier; a second carrier output terminal for outputting a second carrier; and a variable phase shift element. In this embodiment, the source carrier input terminal is coupled to the first carrier output terminal and the input terminal of the variable phase shift element; the output terminal of the variable phase shift element is coupled to the second carrier output terminal; and the variable phase shift element is configured to apply a phase shift to the source carrier according to the mode control signal and output a phase-shifted version of the source carrier as the second carrier.

[0032] The carrier generator may further include another variable phase shift element coupled between the source carrier input terminal and the first carrier output terminal, wherein the another variable phase shift element is configured to apply a phase shift to the carrier according to the mode control signal and output a phase-shifted version of the source carrier as the first carrier.

[0033] The variable phase shift element or the another variable phase shift element may include at least one of the following: a delay line circuit; and an all-pass filter circuit.

[0034] In an embodiment, the carrier generator includes: a source carrier input terminal for receiving a source carrier; a first carrier output terminal for outputting a first carrier; a second carrier output terminal for outputting a second carrier; a delay line including a plurality of delay elements; and a multiplexer. In this embodiment, the source carrier input terminal is coupled to the first carrier output terminal and the input terminal of the delay line; the output terminal of each of the plurality of delay elements is coupled to the input terminal of the multiplexer; the output terminal of the multiplexer is coupled to the second carrier output terminal, and the multiplexer is configured to selectively couple its output terminal to one of its input terminals according to the mode control signal.

[0035] The plurality of delay elements may form part of a phase-locked loop including a loop control circuit, where the loop control circuit is configured to output a control signal to each of the plurality of delay elements to adjust the delay of each of the plurality of delay elements, thereby adjusting the total delay of the delay line so as to phase-lock the output of the delay line to the source carrier.

[0036] In an embodiment, the carrier generator includes: a first carrier output terminal for outputting a first carrier; a second carrier output terminal for outputting a second carrier; a first ramp signal generator configured to output a ramp signal; a first comparator configured to compare the signal output by the first ramp signal generator with a first threshold and output a signal when the output signal of the first ramp signal generator reaches the first threshold; a second comparator configured to compare the signal output by the first ramp signal generator with a second threshold and output a signal when the output signal of the first ramp signal generator reaches the second threshold; a third comparator configured to compare the signal output by the first ramp signal generator with a third threshold and output a signal when the output signal of the first ramp signal generator reaches the third threshold; a fourth comparator configured to compare the signal output by the first ramp signal generator with a fourth threshold and output a signal when the output signal of the first ramp signal generator reaches the fourth threshold; a first bistable element having a first input terminal coupled to the output terminal of the first comparator and a second input terminal coupled to the output terminal of the second comparator; and a second bistable element having a first input terminal coupled to the output terminal of the third comparator and a second input terminal coupled to the output terminal of the fourth comparator, where the output terminal of the first bistable element is coupled to the first carrier output terminal and the output terminal of the second bistable element is coupled to the second carrier output terminal.

[0037] The first ramp signal generator may include a counter configured to receive a clock signal and output a signal indicative of the number of clock pulses of the clock signal counted by the counter.

[0038] The carrier generator may further include: a second ramp signal generator coupled between the output of the first bistable element and the first carrier output; and a third ramp signal generator coupled between the output of the second bistable element and the second carrier output.

[0039] In an embodiment, the carrier generator includes: a counter configured to receive a clock signal and output a signal indicative of the number of clock pulses of the clock signal counted by the counter; and a state machine having an input coupled to the output of the counter and first and second outputs coupled to the first and second carrier outputs. In this embodiment, the state machine is configured to output signals at the first and second outputs of the state machine when the output of the counter reaches a plurality of thresholds.

[0040] According to a second aspect of the present invention, there is provided a class D amplifier circuit including: an input terminal for receiving an input signal; first and second output nodes for driving a load coupled between the first and second output nodes; a first driver stage for switching the first node between a first power rail and a second power rail; a second driver stage for switching the second node between the first power rail and the second power rail; a monitoring circuit for outputting a mode control signal in accordance with an indication of the input signal; and a driver control circuit for controlling the first and second driver stages at least in part in accordance with the mode control signal so as to change a relative phase of switching transitions at the first and second output nodes.

[0041] The monitoring circuit may be configured to monitor a parameter of the input signal and, if the monitored parameter of the input signal reaches or drops below a first threshold, generate a mode control signal to cause the class D amplifier circuit to transition from a first operating mode to a second operating mode, and if the monitored parameter of the input signal reaches or exceeds a second threshold, generate a mode control signal to cause the class D amplifier to transition from the second operating mode to the first operating mode.

[0042] The monitored parameter of the input signal may include at least one of the following: an instantaneous signal level of the input signal; and an envelope of the input signal.

[0043] The second threshold may be different from the first threshold.

[0044] The monitoring circuit may be configured to receive information regarding the input signal and generate the mode control signal based on the received information, and the received information may include at least one of the following: a received indication of the signal level of the input signal; a received indication of an upcoming change in the signal level of the input signal; a received indication of a load attached to the class D amplifier circuit; a received indication of the signal type of the input signal; and a received indication that a silent period has been detected in the input audio signal.

[0045] The monitoring circuit may be configured to generate the mode control signal based on at least one of the following: the signal level of the output signal of the class D amplifier circuit; the envelope of the output signal of the class D amplifier circuit; the duty cycle of the signal at the first or second output node; and the duty cycle of the output signal of the first or second driver control circuit.

[0046] The first driver control circuit may be configured to receive a first signal derived from the input signal and control the switching of the first driver stage based in part on the first signal derived from the input signal; and the second driver control circuit may be configured to receive a second signal derived from the input signal and control the switching of the second driver stage based in part on the second signal derived from the input signal.

[0047] The first and second signals derived from the input signal may be complementary signals of a differential signal pair.

[0048] Alternatively, the first and second signals derived from the input signal may be the same.

[0049] The first driver control circuit may operate to compare the first signal derived from the input signal with the first carrier and control the switching of the first driver stage based on the comparison; and the second driver control circuit may operate to compare the second signal derived from the input signal with the second carrier and control the switching of the second driver stage based on the comparison.

[0050] The first driver control circuit can be operated to compare a first differential signal with the first carrier, where the first differential signal indicates the difference between the signal output by the first driver stage and a first signal derived from the input signal, and control the switching of the first driver stage based on the comparison; and the second driver control circuit can be operated to compare a second differential signal with the second carrier, where the second differential signal indicates the difference between the signal output by the second driver stage and a second signal derived from the input signal, and control the switching of the second driver stage based on the comparison.

[0051] The first differential signal can represent the integral of the difference between the voltage of the signal output by the first driver stage and the voltage of the first signal derived from the input signal; and the second differential signal can represent the integral of the difference between the voltage of the signal output by the second driver stage and the voltage of the second signal derived from the input signal.

[0052] The first differential signal can be provided at the output of a first loop filter of the first driver control circuit, and the second differential signal can be provided at the output of a second loop filter of the second driver control circuit.

[0053] The first driver control circuit can include a first integrator circuit configured to receive a first digital signal and generate the first carrier based on the received first digital signal; and the second driver control circuit can include a second integrator circuit configured to receive a second digital signal and generate the second carrier based on the received second digital signal.

[0054] The first digital signal and the second digital signal can include corresponding first and second square wave current waveforms.

[0055] The class-D amplifier circuit can further include a carrier generator configured to provide the first carrier and the second carrier, where the phase shift between the first carrier and the second carrier can be adjusted in response to a mode control signal.

[0056] In a first operating mode, the phase shift between the first carrier and the second carrier can be substantially 180 degrees.

[0057] In a second operating mode, the phase shift between the first carrier and the second carrier can be substantially zero.

[0058] In a third operating mode, the phase shift between the first carrier and the second carrier can be a non-zero value other than 180 degrees.

[0059] The carrier generator can be operated to adjust the phase difference between the first carrier and the second carrier between a non-zero value and zero within a predetermined period of time, so as to transition from the first or third operating mode to the second operating mode, and adjust the phase difference between the first carrier and the second carrier between zero and a non-zero value within a predetermined period of time, so as to transition from the second operating mode to the first or third operating mode.

[0060] The carrier generator can be operated to substantially continuously scan the phase difference between the first carrier and the second carrier.

[0061] In an embodiment, the carrier generator includes: a source carrier input terminal for receiving a source carrier; a first carrier output terminal for outputting a first carrier; a second carrier output terminal for outputting a second carrier; and a multiplexer. In this embodiment, the source carrier input terminal is coupled to the first carrier output terminal and the first input terminal of the multiplexer; the second input terminal of the multiplexer is configured to receive an inverted version of the source carrier; the output terminal of the multiplexer is coupled to the second carrier output terminal; and the multiplexer is configured to selectively couple its first input terminal or its second input terminal to its output terminal according to the mode control signal, so that the carrier generator outputs the source carrier or the inverted version of the source carrier at the second carrier output terminal and outputs the source carrier at the first carrier output terminal.

[0062] The carrier generator may include an inverting stage coupled between the source carrier input terminal and the second input terminal of the multiplexer.

[0063] In an embodiment, the carrier generator includes: a source carrier input terminal for receiving a source carrier; a first carrier output terminal for outputting a first carrier; a second carrier output terminal for outputting a second carrier; and a variable phase shift element. In this embodiment, the source carrier input terminal is coupled to the first carrier output terminal and the input terminal of the variable phase shift element; the output terminal of the variable phase shift element is coupled to the second carrier output terminal; and the variable phase shift element is configured to apply a phase shift to the source carrier according to the mode control signal and output a phase-shifted version of the source carrier as the second carrier.

[0064] The carrier generator may further include another variable phase shift element coupled between the source carrier input terminal and the first carrier output terminal, wherein the another variable phase shift element is configured to apply a phase shift to the carrier according to the mode control signal and output a phase-shifted version of the source carrier as the first carrier.

[0065] The variable phase shift element or the other variable phase shift element may include at least one of the following: a delay line circuit; and an all-pass filter circuit.

[0066] In an embodiment, the carrier generator includes: a source carrier input terminal for receiving a source carrier; a first carrier output terminal for outputting a first carrier; a second carrier output terminal for outputting a second carrier; a delay line including a plurality of delay elements; and a multiplexer. In this embodiment, the source carrier input terminal is coupled to the first carrier output terminal and the input terminal of the delay line; the output terminal of each of the plurality of delay elements is coupled to the input terminal of the multiplexer; the output terminal of the multiplexer is coupled to the second carrier output terminal, and the multiplexer is configured to selectively couple its output terminal to one of its input terminals according to the mode control signal.

[0067] The plurality of delay elements may form part of a phase-locked loop including a loop control circuit, where the loop control circuit is configured to output a control signal to each of the plurality of delay elements to adjust the delay of each of the plurality of delay elements, thereby adjusting the total delay of the delay line so as to lock the output of the delay line to the source carrier.

[0068] In an embodiment, the carrier generator includes: a first carrier output terminal for outputting a first carrier; a second carrier output terminal for outputting a second carrier; a first ramp signal generator configured to output a ramp signal; a first comparator configured to compare the signal output by the first ramp signal generator with a first threshold and output a signal when the output signal of the first ramp signal generator reaches the first threshold; a second comparator configured to compare the signal output by the first ramp signal generator with a second threshold and output a signal when the output signal of the first ramp signal generator reaches the second threshold; a third comparator configured to compare the signal output by the first ramp signal generator with a third threshold and output a signal when the output signal of the first ramp signal generator reaches the third threshold; a fourth comparator configured to compare the signal output by the first ramp signal generator with a fourth threshold and output a signal when the output signal of the first ramp signal generator reaches the fourth threshold; a first bistable element having a first input terminal coupled to the output terminal of the first comparator and a second input terminal coupled to the output terminal of the second comparator; and a second bistable element having a first input terminal coupled to the output terminal of the third comparator and a second input terminal coupled to the output terminal of the fourth comparator, where the output terminal of the first bistable element is coupled to the first carrier output terminal and the output terminal of the second bistable element is coupled to the second carrier output terminal.

[0069] The first ramp signal generator may include a counter configured to receive a clock signal and output a signal indicative of the number of clock pulses of the clock signal counted by the counter.

[0070] The carrier generator may further include: a second ramp signal generator coupled between the output of the first bistable element and the first carrier output; and a third ramp signal generator coupled between the output of the second bistable element and the second carrier output.

[0071] In an embodiment, the carrier generator includes: a counter configured to receive a clock signal and output a signal indicative of the number of clock pulses of the clock signal counted by the counter; and a state machine having an input coupled to the output of the counter and first and second outputs coupled to the first and second carrier outputs, wherein the state machine is configured to output signals at the first and second outputs of the state machine when the output of the counter reaches a plurality of thresholds.

[0072] According to a third aspect of the present invention, there is provided a class D amplifier circuit including: a mode controller configured to dynamically adjust the operation switching mode of the class D amplifier within a range between an A-D class mode and a B-D class mode according to an indication of the level of an input signal to be amplified.

[0073] The range between the A-D class mode and the B-D class mode may have a first endpoint and a second endpoint, at the first endpoint, the operation switching mode is 100% A-D class, and at the second endpoint, the operation switching mode is 100% B-D class. However, it should be understood that the first endpoint of the range may correspond to an operation switching mode less than 100% A-D class and / or the second endpoint of the range may correspond to an operation switching mode less than 100% B-D class.

[0074] According to a fourth aspect of the present invention, there is provided a class D amplifier circuit including: first and second half-bridge output stages; and a mode controller configured to dynamically adjust the relative phase of the cycle references applied to the respective switching controllers of the first and second half-bridge output stages, thereby dynamically adjusting the operation switching mode of the class D amplifier within a range between an A-D class mode and a B-D class mode.

[0075] According to a fifth aspect of the present invention, there is provided an electronic device including a class D amplifier circuit according to any one of the first to fourth aspects, wherein the electronic device includes at least one of the following: a portable electronic device; a battery-powered device; a computing device; a communication device; a gaming device; a mobile phone; a media player; a laptop computing device, a tablet computing device or a notebook computing device; a wearable device; or a voice-activated or voice-controlled device. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Embodiments of the present invention will now be described with reference to the drawings, which are by way of example only, in which:

[0077] Figure 1 is a schematic representation of an output signal supplied to a load by a class D amplifier operating in class AD mode or class BD mode;

[0078] Figure 2 is a schematic diagram showing the concept of a class D amplifier that can selectively operate in class AD mode or class BD mode according to characteristics, parameters, features, etc., such as the signal level of an input signal;

[0079] Figure 3a and Figure 3b is for Figure 2 a schematic representation of a circuit implementation of the concept shown for bridge-connected loads;

[0080] Figure 3c provides Figure 3a and Figure 3b a schematic representation of different implementations of a carrier generator used in the circuit implementation of;

[0081] Figures 4a - 4c shows a series of waveforms that show Figure 3a and Figure 3b the operation of the circuit implementation of;

[0082] Figure 5 is Figure 3b a schematic representation of an alternative circuit implementation of a half circuit of the implementation of; and

[0083] Figure 6 is Figure 3b another alternative circuit implementation of a half circuit of the implementation of. DETAILED DESCRIPTION

[0084] As described above, the class AD and class BD designs of class D amplifiers offer different advantages and disadvantages.

[0085] Class-AD designs offer high linearity and balance. However, the power supply rejection ratio (PSRR) in Class-AD designs is worse than that in Class-BD designs. As described above, in a full-bridge Class-D amplifier driving a bridged load, even for low signal levels, the output signals generated by the first and second output drivers of the output stage typically swing between the positive and negative power rails, so any noise present in the power rails will be introduced into the signal applied to the load. In addition, the amplifier draws a higher quiescent current in Class-AD mode than in Class-BD mode.

[0086] In contrast, Class-BD designs offer a better power supply rejection ratio (PSRR) than Class-AD designs. Additionally, Class-BD mode offers a lower quiescent current than Class-AD mode. However, the cost of these advantages is lower linearity than Class-AD mode and a higher amplitude of the common-mode signal.

[0087] Since Class-AD only employs two output states, the output linearity is insensitive to any mismatch in the output amplitude between these two states. In contrast, the output of a Class-BD design will assume different proportions of three output states according to the instantaneous input signal level, so any mismatch in the output amplitude will result in non-linearity. Additionally, since the polarities of the outputs of a Class-AD design are inherently complementary, the output common-mode voltage is constant, while in Class-BD, since the output alternates between a state where both outputs are high and a state where both outputs are low, there is a common-mode ripple even for small signals. This can cause electromagnetic interference (EMI) emissions.

[0088] Figure 2 is a schematic diagram showing a Class-D amplifier system configured to dynamically switch between Class-AD and Class-BD operating modes according to characteristics, parameters, features, etc. of an input signal, such as the signal level.

[0089] The system, generally designated 200, includes a Class-D amplifier 202 capable of operating in Class-AD mode or in Class-BD mode. The Class-D amplifier 202 includes a mode control mechanism 204 for switching the Class-D amplifier 202 between Class-AD and Class-BD operating modes. The Class-D amplifier 202 has an input terminal 206 for receiving an input signal and an output terminal 208 (or a pair of output terminals in the case of a full-bridge amplifier) for outputting a pulse train to a load, the pulse train delivering an output signal indicative of the input signal.

[0090] The signal monitor 210 can be coupled to the input terminal 206 of the class-D amplifier and is configured to monitor the analog input signal and output a control signal to the mode control mechanism 204 of the class-D amplifier 202 according to, for example, an indication or characteristic, parameter, feature, etc. of the input signal (such as the input signal level), so as to cause the class-D amplifier 202 to switch between the A-class-D mode and the B-class-D mode.

[0091] The signal monitor 210 can be configured to operate in a variety of different ways. For example, the signal monitor 210 can be configured to monitor the instantaneous signal level of the input signal and output a control signal to cause the class-D amplifier 202 to transition to its A-class-D operating mode or its B-class-D operating mode, or vice versa, depending on which specific conditions are met. For example, the signal monitor 210 can be configured to: if the instantaneous input signal level reaches or drops below a first predefined threshold, output a control signal to cause the class-D amplifier 202 to transition from the A-class-D mode to the B-class-D mode, and if the instantaneous input signal level reaches or exceeds a second predefined threshold, output a control signal to cause the class-D amplifier 202 to transition from the B-class-D mode to the A-class-D mode.

[0092] Alternatively, the signal monitor 210 can be configured to monitor parameters, characteristics, features, etc. (such as the envelope level) of the envelope of the input signal, and if specific conditions are met, output a control signal to cause the class-D amplifier 202 to switch its operating mode. For example, the signal monitor 210 can be configured to: if the envelope parameter (such as the envelope level) of the input signal reaches or drops below a first predefined threshold, output a control signal to cause the class-D amplifier 202 to transition from the A-class-D mode to the B-class-D mode, and if the envelope parameter (such as the envelope level) of the input signal reaches or exceeds a second predefined threshold, output a control signal to cause the class-D amplifier 202 to switch from the B-class-D mode to the A-class-D mode.

[0093] Advantageously, the envelope detector used can have a relatively fast rise time constant, so as to respond quickly to any increase in the input signal amplitude and change to the A-class-D mode in a timely manner. On the contrary, the envelope detector can have a relatively slow decay time constant, so as to delay the response to any decrease in the signal amplitude to avoid excessive frequent changes in the switching mode. The envelope detector can also implement a hold period, in which the current value of the envelope level is maintained within the hold period before the current value of the envelope level decreases, so as to delay any change in the switching mode, thereby effectively providing a time-domain hysteresis to the mode switching and avoiding excessive frequent changes in the switching mode.

[0094] In either case, the first and second predefined envelope parameter (e.g., envelope level) thresholds can be the same or can be different to provide a certain hysteresis. The envelope threshold can be a given fraction of the maximum expected input signal amplitude (e.g., the threshold can be set to a level of, for example, 10% or 20%), or can be any desired fraction of the expected maximum input signal amplitude (e.g., the threshold can be set in the range of 5 - 25% of the maximum signal amplitude (e.g., level), with a different threshold of 5 - 10% to provide a voltage hysteresis). Additionally or alternatively, the envelope threshold can be expressed in decibels relative to the full scale (dBFS) of the maximum expected input signal amplitude. For example, the threshold can be set at a level between -6 dB and -30 dB, while another threshold is set at a different level between, for example, -6 dB and -12 dB to provide a voltage hysteresis.

[0095] As another alternative, the signal monitor can be configured to receive information about the input signal, such as its level, from one or more upstream components of system 200 (such as a volume control or some digital peak or envelope detector), and output a control signal based on the received information to cause the class D amplifier 202 to switch operating modes. The indication or characteristics, parameters, features, etc. of the input signal can additionally or alternatively be derived from the high-level operation information in the host system. For example, the high-level system controller in a host device (such as a mobile phone) may know whether the output is connected to a 10 kΩ line level load or a 600 Ω speaker, or to a more sensitive 8 Ω low impedance headphone load, which has a defined smaller allowable maximum signal level, such that class BD operation is desired even at the reduced maximum allowable signal level. Similarly, the system controller may be able to anticipate an upcoming change in the input signal level, such as a temporary silence period, or an impending change in the class or type of the input signal, resulting in a requirement to output, for example, a high amplitude notification such as a ringtone instead of a regular audio signal. The high-level controller can convey this information to the class D amplifier to provide an indication of the input signal.

[0096] In the above-described embodiments, the characteristics, parameters, or features of the amplitude of the input signal may be derived from monitoring the received input signal or from a volume control signal or some other upstream signal. However, in other embodiments, the parameters of the amplitude of the input signal may be derived at least in part from other parts of the signal chain within the class D amplifier circuit and used to change the switching mode (class AD / class BD) accordingly. For example, the output voltage of amplifier circuit 300 may be used to provide an indication of the input signal level, either before filtering by looking at the duty cycle of the signals at output nodes 324, 332 or after filtering by comparing with a reference voltage. Similarly, the timing or duty cycle of the control signals used to control the switching of output stages 312, 314 may be used to provide a characteristic of the input signal level.

[0097] Embodiments may use digital hardware (such as a counter) to determine the pulse width or duty cycle of the drive or control signal of the output driver stage and thus provide a method of controlling the switching mode using a small amount of pure digital hardware. This is particularly advantageous in the case of systems with analog inputs and thus no upstream digital representation of the input signal, or for amplifiers in smaller geometry manufacturing processes.

[0098] Other embodiments may directly obtain the output signal from the output driver stage, possibly with some filtering, or after a smoothing post-filter between the output and the physical load, and derive its envelope for processing similar to that described for processing the input signal to provide a signal for controlling the switching mode (class AD / class BD) of the class D amplifier. In some embodiments, the analog output signal may be passed through an analog-to-digital converter (ADC) to possibly enable some other digital signal processing, such as linearization or digital echo cancellation. Digital envelope detection or other digital filtering may be employed to provide an output indication and thus an indication of the input signal level.

[0099] Preferably, such an ADC will be a continuous-time ADC, i.e., an ADC that does not sample its input signal, to allow accurate capture of the duty cycle and any transients generated around the switching edges without having to operate at an excessive sampling frequency. This ADC includes a continuous-time delta-sigma converter and a converter including a voltage-to-frequency converter or a voltage-controlled oscillator.

[0100] As another alternative, the signal monitor 210 can be configured to receive information about other aspects of the operation of the host system in addition to or instead of information about the input signal. For example, as described above, class-D operation may generate more EMI emissions due to generally larger common-mode output voltage activity. For example, this can be a problem if the host device includes components that may attempt to receive radio signals with a carrier frequency similar to the switching frequency of a class-D amplifier. Thus, the signal monitor can receive a control signal from, for example, a high-level system controller in the host device (such as a mobile phone), the control signal indicating that an EMI-sensitive function is currently being activated, such that class-AD operation will be preferred even for small audio signal levels.

[0101] Figure 3a is Figure 2 A schematic representation of an exemplary circuit implementation of the concept shown, the exemplary circuit implementation receiving a differential input signal pair S INP 、S INN derived from an input signal such as an analog audio signal, and driving a first node 324 and a second node 332 of a bridge-connected load 316 with a differential output signal of the type shown. Figure 1 The circuit 300 of

[0102] Figure 3a includes a first half-circuit 300a, a second half-circuit 300b, a carrier generator 310, and a signal monitor 210.

[0103] The first half-circuit 300a includes a first driver stage 312 for switching the first node 324 between a first power rail +Vdd or a second power rail -Vdd, and also includes a first driver control circuit 340 configured to receive a first carrier CW a and to control the switching of the first driver stage 312 based on the first carrier CW a and a first input signal component S INP . Similarly, the second half-circuit 300b includes a second driver stage 342 for switching the second node 332 between the first power rail +Vdd or the second power rail -Vdd, and also includes a second driver control circuit 342 configured to receive a second carrier CW b and to control the switching of the second driver stage 314 based on the second carrier CW b and a second input signal component S INN .

[0104] The carrier generator 310 receives a source carrier CW and generates a first carrier CW a and a second carrier CW b ​。The carrier generator 310 adjusts the first carrier CW in response to the mode control signal MC a and the second carrier CW b The phase shift between. The mode control signal can be generated by the signal monitor block 210, which can monitor the input signal or a signal indicating its characteristics (such as the signal level of the input signal).

[0105] Figure 3b is Figure 3a A more detailed schematic representation of an exemplary circuit implementation 300 of the concept shown. The circuit 300 receives a differential input signal pair S INP 、S INN derived from an input signal such as an analog audio signal, and uses the differential output signal to drive the bridge-connected load 316. Figure 3b The circuit 300 of includes two half-circuits 300a and 300b, each of which receives one of the differential input signals and drives the corresponding side of the load 316 from the corresponding driver stage 312 or 314.

[0106] In Figure 3b In the circuit 300 of, the first comparator 302 receives the first input signal S of the differential input signal pair at its non-inverting input terminal INP . The second comparator 304 receives the second input signal S of the differential input signal pair at its non-inverting input terminal INN , which is complementary to the first input signal, for example, inverted with respect to a certain static signal reference. The inverting input terminal of the first comparator 302 is connected to the output terminal of the carrier generator 310, and receives the first carrier CW a from it. In this example, the first carrier is a triangular wave. The carrier CW a is a repetitive periodic signal, that is, a cyclic reference signal. The second output terminal of the carrier generator 310 is connected to the inverting input terminal of the second comparator 304, so that the carrier generator 310 provides the second carrier to the second comparator 304. By changing the phase of the second carrier or cyclic reference signal provided to the second comparator 304, the carrier generator 310 can adjust the operating mode of the circuit 300, as will be described in more detail below.

[0107] The output of the first comparator 302 drives the first driver stage 312 of the circuit 300, while the output of the second comparator 304 drives the second driver stage 314 of the circuit 300. The output terminals of the first driver stage 312 and the second driver stage 314 are connected to the corresponding first node 324 and second node 332, which are connected to the corresponding first and second terminals of the load 316, and the load is in Figure 3bis shown as a speaker in the exemplary circuit 300 (although it could be another audio transducer, such as a headset, earphones, or earbuds, or some other transducer, such as a haptic transducer, such as a linear resonant actuator or other mechanical transducer). Thus, the first comparator serves as a first driver control circuit that is configured to receive a first carrier CW a and, in part, based on the first carrier CW a to control the switching of the first driver stage 312. Similarly, the second comparator 304 serves as a second driver control circuit that is configured to receive a second carrier CW b and, in part, based on the second carrier CW b to control the switching of the second driver stage 314.

[0108] The first driver stage 312 may include first and second switching devices, such as transistors, connected in series between the positive power supply rail +Vdd and the negative power supply rail –Vdd of the circuit 300. The gate terminal of the first switching device 318 is connected to the output terminal of the first comparator 302, while the gate terminal of the second switching device 320 is connected to the output terminal of an inverter 322, the input terminal of which is connected to the output terminal of the first comparator 302. The output of the first output portion 312 is provided by a node 324 that connects the terminals of the first switching device 318 to the terminals of the second switching device 320. For example, the first switching device 318 may be an n-channel MOSFET (NMOS) having a drain terminal connected to the positive power supply rail +Vdd. The second switching device 320 may be an n-channel MOSFET (NMOS) having a drain terminal connected to the source terminal of the first switching device 318 and a source terminal connected to the negative power supply rail -Vdd. In this case, the output of the first output portion 312 is provided by a node 324 that connects the source terminal of the first switching device 318 to the drain terminal of the second switching device 320.

[0109] The second driver stage 314 is similar to the first driver stage 312 and includes a third switching device 326 and a fourth switching device 328 such as transistors connected in series between the positive power supply rail +Vdd and the negative power supply rail –Vdd of the circuit 300. The gate terminal of the third switching device 326 is connected to the output terminal of the second comparator 304, while the gate terminal of the fourth switching device 328 is connected to the output terminal of an inverter 330, the input terminal of which is connected to the output terminal of the second comparator 304. The output of the second output section 314 is provided by a node 332 that connects the terminals of the third switching device 326 to the terminals of the fourth switching device 328. For example, the third switching device 326 can be an NMOS transistor having a drain terminal connected to the positive power supply rail +Vdd. The fourth switching device 328 can be an NMOS transistor having a drain terminal connected to the source terminal of the third switching device 326 and a source terminal connected to the negative power supply rail -Vdd. In this case, the output of the second output section 314 is provided by a node 332 that connects the drain terminal of the third switching device 326 to the source terminal of the fourth switching device 328.

[0110] It should be understood that alternative arrangements of switching devices providing equivalent functionality can be equivalently employed in the first driver stage 312 and the second driver stage 314. For example, all four switching devices 318, 320, 326, 328 can be p-channel MOSFETs (PMOS). The overall effect will merely be to invert the polarity of the output signals on nodes 320 and 332, thus inverting the differential voltage across the load.

[0111] Alternatively, the second switching device 320 and the fourth switching device 328 can be n-channel MOSFETs (NMOS), while the first switching device 318 and the third switching device 326 can be p-channel MOSFETs (PMOS) to provide a CMOS output stage including complementary n- and p-channel switching devices. In the latter case, the inverters 322, 330 can be omitted.

[0112] It should also be understood that the MOS switching devices 318, 320, 326, and 328 may not be driven directly from the comparator outputs. The output devices 318, 320, 326, and 328 may have to carry relatively high drive currents to and from the load 316 and may thus require more than the generally small-signal MOS circuitry found, for example Figure 3b in comparators. Thus, there can be one or more intermediate pre-driver circuit stages. This can also include means for limiting the output voltage slew rate or for overlapping or underlapping the detailed switching transitions. The intermediate pre-driver circuit can also include means for avoiding pulses having a duration less than a certain minimum value (e.g., on the order of about 1% of the switching period). However, the switching devices are still substantially controlled by the respective switching control circuits (e.g.,

[0113] Although Figure 3b Exemplary circuit implementation 300 shows that a first switching device 318 and a second switching device 320 connected in series, and a third switching device 326 and a fourth switching device 328 connected in series are connected between a positive power supply rail and a negative power supply rail. It should be understood that, in general, any suitable arrangement of the positive and negative power supply rails can be used. For example, the positive power supply rail can be at a positive voltage, while the negative power supply rail can be grounded or can be a negative voltage of the same or different magnitude as the positive power supply rail.

[0114] In the operation of circuit 300, a first comparator 302 receives a first input signal S of a differential input signal pair INP and compares it with a first carrier CW a to generate an output signal for driving a first output section 312. A second comparator 304 receives a second input signal S of the differential input signal pair INN and compares it with a second carrier CW b to generate an output signal for driving a second output section 314. The signals output by the first and second output sections 312, 314 appear on a load 316 as differential output signals.

[0115] Thus, when the output of the first comparator 302 is high, the first switching device 318 is in the on state, and the second switching device 320 is in the off state (due to the inversion of the inverter 322). Therefore, there is a low-impedance current path between the positive power supply rail +Vdd and node 324, and the voltage at node 324 is substantially equal to +Vdd.

[0116] When the output of the first comparator 302 is low, the first switching device 318 is in the off state, and the second switching device 320 is in the on state (again due to the inversion of the inverter 322). Therefore, there is a low-impedance current path between the negative power supply rail -Vdd and node 324, and the voltage at node 324 is substantially equal to -Vdd.

[0117] When the output of the second comparator 304 is high, the third switching device 326 is in the on state, and the fourth switching device 328 is in the off state (due to the inversion of the inverter 330). Therefore, there is a low-impedance current path between the positive power supply rail +Vdd and node 332, and the voltage at node 332 is substantially equal to +Vdd.

[0118] When the output of the second comparator 304 is low, the third switching device 326 is in the off state and the fourth switching device 328 is in the on state (again due to the inversion by the inverter 330). Therefore, there is a low-impedance current path between the negative power supply rail -Vdd and the node 332, and the voltage at the node 332 is substantially equal to -Vdd.

[0119] In the class-AD operation mode, a two-level differential output signal is generated on the load, whose value swings between +2Vdd and -2Vdd. This is achieved by invertingly turning on and off the first switching device 318 and the third switching device 326. Therefore, when the first switching device 318 is in the on state, the third switching device 326 is in the off state, and vice versa.

[0120] When the first switching device 318 is in the on state and the third switching device 326 is in the off state, a voltage substantially equal to +Vdd is generated at the node 324, and a voltage substantially equal to -Vdd is generated at the node 332. Therefore, a differential output voltage equal to +Vdd - (-Vdd) = +2Vdd appears across the load 316, and current flows through the load 316 from left to right. When the first switching device 318 is turned off and the third switching device 326 is turned on, a voltage substantially equal to -Vdd is generated at the node 324, and a voltage substantially equal to +Vdd is generated at the node 332. Therefore, a differential output voltage equal to -Vdd - Vdd = -2Vdd appears across the load 316, and current flows through the load 316 from right to left.

[0121] Therefore, for class-AD operation, the output of the second comparator 304 is inverted with respect to the output of the first comparator 302 to ensure that the first switching device 318 and the third switching device 326 are turned on and off in the correct sequence. The manner in which this can be achieved is described in detail below.

[0122] In the class-BD operation mode, a three-level differential output signal is generated on the load 316, whose amplitude can be +2Vdd, –2Vdd, or 0V. This is achieved by selectively turning on and off the first switching device 318 and the third switching device 326 such that at certain times, both the first switching device 318 and the third switching device 326 can be in the conducting state or both in the non-conducting state, and at other times, one of the first switching device 318 and the third switching device 326 is in the conducting state while the other of the third switching device 326 and the first switching device 318 is in the non-conducting state.

[0123] As described above, when the first switching device 318 is turned on and the second switching device 326 is turned off, a differential output voltage of +2Vdd is generated across the load 316. When the first switching device 318 is turned off and the second switching device 326 is turned on, a differential output voltage of -2Vdd is generated across the load 316.

[0124] If the first switching device 318 is in the conducting state while the third switching device 326 is in the conducting state, a voltage of +Vdd is generated at the node 324 due to the connection between the positive power supply rail +Vdd and the node 324. At the same time, a voltage of +Vdd is generated at the node 332 due to the connection between the positive power supply rail +Vdd and the node 332. Therefore, when both the first switching device 318 and the third switching device 328 are turned on, a differential voltage of (+Vdd)-(+Vdd) = 0 volts appears across the load 316.

[0125] Similarly, if the second switching device 320 is turned on while the fourth switching device 328 is turned on, a voltage of -Vdd is generated at the node 324 due to the connection between the negative power supply rail -Vdd and the node 322. At the same time, a voltage of -Vdd is generated at the node 332 due to the connection between the negative power supply rail -Vdd and the node 332. Therefore, when both the second switching device 320 and the fourth switching device 328 are turned on, a differential voltage of (-Vdd)-(-Vdd) = 0 volts appears across the load 316.

[0126] Therefore, by configuring the circuit 300 such that different combinations of the first switching device 318 and the third switching device 326 and the second switching device 322 and the fourth switching device 330 are turned on simultaneously, one of the three different differential output voltages +2Vdd, –2Vdd, or 0V as described above can be generated and applied to the load 316.

[0127] The circuit 300 can be arranged to operate in class-AD or class-BD mode by adjusting the phase difference between the first carrier CW a (which is input to the inverting input of the first comparator 302) and the second carrier CW b (which is input to the inverting input of the second comparator 304).

[0128] If there is no phase difference between the first carrier CW a and the second carrier CW b , the circuit 300 operates in class-BD mode, and any one of the three differential output voltages as described above can be generated across the load 316 due to the outputs of the first comparator 302 and the second comparator 304.

[0129] On the other hand, if relative to the first carrier CW aApply a 180-degree phase shift to the second carrier CW b , or equivalently, if the second carrier is inverted relative to the first carrier, the outputs of the first comparator 302 and the second comparator 304 will always be inverted with respect to each other and cannot produce a differential output voltage of 0 volts across the load 316. Thus, the circuit 300 operates in class AD mode.

[0130] In some embodiments, to avoid having to generate an inverted input signal S INN , the same input signal can be connected to the input terminals of both comparators. To compensate for the non-inversion of its signal input, the polarity of the second comparator input will be reversed such that the signal input will be applied to the inverted input terminal of comparator 304 and the second carrier is applied to the non-inverted input terminal. In this example case, when no phase shift is applied to the second carrier CW b , the circuit 300 operates in class AD mode, while applying a phase shift to the second carrier CW b causes the circuit 300 to operate in class BD mode.

[0131] To allow the circuit 300 to transition between class AD operation and class BD operation, the carrier generator 310 is configured to be controllable to invert or impart a phase shift to one carrier signal relative to another carrier signal in response to a received mode control signal MC. Figure 3c Various possible implementations of the carrier generator 310 are shown.

[0132] In Figure 3c one approach represented by 310a, the carrier generator 310 includes an inversion stage 356 and a multiplexer 358 and provides a first carrier CW at a first carrier generator output 352 a , and provides a second carrier CW at a second carrier generator output 354 b . The input terminal of the inversion stage 356 is connected to the input terminal of the carrier generator 310a to receive the source carrier CW, and the output terminal of the inversion stage 356 is connected to the first input terminal of the multiplexer 358. The second input terminal of the multiplexer 358 is directly connected to the input terminal of the carrier generator 310a to receive the source carrier CW. Thus, the first input terminal of the multiplexer receives the inverted version CW of the source carrier CW b , while the second input terminal receives the non-inverted version CW of the source carrier CW a . The output terminal of the multiplexer 358 is connected to the second output 354 of the carrier generator 310a to provide the second carrier CW b . When the circuit 300 is required to operate in class AD mode (as for example by the above reference Figure 2As determined by the signal monitor 210 of the type described, the carrier generator 310 receives a corresponding mode control signal MC that controls the multiplexer 358 to connect the output of the multiplexer 358 to the first input of the multiplexer, such that the carrier generator 310a outputs an inverted version CW of the source carrier CW. b As the second carrier CW b Meanwhile, the first carrier generator output 352 (possibly via a non-inverting buffer) is connected to the carrier generator input that receives the source carrier CW input, and thus provides a non-inverted version of the source carrier as the first carrier CW. a Thus, in this mode, the carrier generator 310a provides the second carrier as an inverted version of the first carrier. It will be understood that providing the inverted version in this way is equivalent to establishing a 180-degree phase shift between the two carriers CW a and CW b or providing a time delay equal to half of the cycle period of the source carrier CW.

[0133] When the circuit 300 is required to operate in class BD mode, the carrier generator 310a is operable to connect the output of the multiplexer 358 to the second input of the multiplexer 358, such that the carrier generator 310a outputs a non-inverted version of the source carrier as the second carrier output, i.e., equivalent to providing a non-inverted version of the first carrier, i.e., establishing a zero-degree phase difference or zero time delay between the two carrier outputs.

[0134] In some embodiments, the inverted and non-inverted versions of the source carrier CW may have been generated within an upstream circuit that generates the source carrier, and thus these non-inverted and inverted source carrier signals can be directly coupled to the corresponding inputs of the multiplexer 358 via the corresponding carrier generator inputs.

[0135] In Figure 3c the alternative method denoted by 310b in a the carrier generator 310 provides the first carrier CW at the first carrier generator output 352 b and provides the second carrier CW at the second carrier output 354. The carrier generator 310b includes a variable phase shift element 360. The input of the variable phase shift element 360 is connected to the input of the carrier generator 310b to receive the source carrier CW, and the output of the variable phase shift element 360 is connected to the second output 354 of the carrier generator 310b. When the circuit 300 is required to operate in class AD mode (as, for example, by referring to the above Figure 2As determined by the signal monitor 210 of the type described, the carrier generator 310 receives a corresponding mode control signal MC, which controls the variable phase shift element 360 such that it applies a 180-degree phase shift to the source carrier input signal, and thus the carrier generator 310b outputs this phase-shifted version of the source carrier CW as the second carrier CW b Meanwhile, the first carrier generator output 352 is connected (possibly via some non-inverting buffer) to the carrier generator input, which receives the source carrier CW input, and thus provides a non-inverted version of the source carrier without any phase shift as the first carrier CW a Thus, in this mode, the carrier generator 310b provides a second carrier that has a 180-degree phase shift relative to the first carrier. It will be understood that providing a 180-degree phase shift between the two carriers in this manner is equivalent to providing mutually inverted versions of the two carriers, or providing a time delay equal to half of the cycle period of the source carrier. In contrast, when the circuit 300 is required to operate in class BD mode, the variable phase shift element 360 does not apply any phase shift to the first carrier, and thus the second carrier has a zero-degree phase shift relative to the first carrier, i.e., there is zero time delay between the two carrier outputs.

[0136] In some variants, it may be convenient to apply variable phase delays to both paths. For example, a 90-degree phase lead may be controllably applied in the path providing the first carrier, and a 90-degree phase lag may be controllably applied in the path providing the first carrier to provide an equivalent 180-degree phase shift between the two paths. Thus, the carrier generator 310b may include another variable phase shift element 362, which is coupled between the input of the carrier generator 310b and the first output 352 of the carrier generator 310b, and is operable to apply a variable phase delay to the source carrier, the variable phase delay being complementary to the phase delay applied by the variable phase shift element according to the received mode control signal MC to achieve a 180-degree relative phase delay between the first and second carriers output by the carrier generator 310b.

[0137] The variable phase shift element may include known analog techniques for applying a phase delay or a time delay to a signal, such as a delay line or an all-pass filter circuit, which can be bypassed when zero phase delay is required. Additionally, in some embodiments of the driver control circuit 340 (e.g., as discussed below with reference to Figure 6 ) the carrier may be provided to the driver control circuit as a digital signal, which may be a simple two-level signal, in which case a digital delay line may be employed.

[0138] In the embodiments discussed so far, the mode control signal MC can be a two-level signal, and the amplifier 300 can be configured to operate only in class AD or class BD mode. In some embodiments, the variable phase element 360 can be controlled by the carrier generator 310b to impart different phase shifts to the first carrier, e.g., to "tune" the operating mode of the circuit 300 according to the nature of the input signal (such as its signal level) to adjust the duration of each instance of the 0-volt output state in the differential output signal (designated as zero in class AD mode).

[0139] In such embodiments, the signal monitor can provide a multi-level mode control signal MC, e.g., the multi-level mode control signal is associated with comparing a multi-level indication of the input signal level with a plurality of thresholds, the plurality of thresholds being associated with or corresponding to a plurality of different modes ranging from class AD to class BD, i.e., operating in one or more intermediate "ADBD" modes.

[0140] In some embodiments, even when only comparing an indication of the signal with a single threshold such that the mode control signal is binary between full AD and full BD, the operating mode can ramp over time. For example, to transition from a class AD operating mode or an intermediate "ADBD" operating mode to a class BD operating mode, the carrier generator 310 can adjust the phase shift between the first and second carriers from a non-zero value (such as 180 degrees) to zero over a predetermined period of time. Similarly, to transition from a class BD mode to a class AD mode or an intermediate "ADBD" mode, the carrier generator can adjust the phase shift between the first and second carriers from zero to a non-zero value (such as 180 degrees for full class AD mode) over a predetermined period of time. In some embodiments, the operating range can be limited to only a subset of the entire range from class AD to class BD. Thus, more generally, to change the operating mode of a class D amplifier from one mode to another, the carrier generator can adjust the phase shift between the first and second carriers from a first value to a second value over a predetermined period of time, where one of the first value or the second value can be zero or neither can be zero and where one of the first value or the second value can be 180 degrees or neither can be 180 degrees.

[0141] In some embodiments, the switching frequency can be changed in a substantially continuous manner when the signal amplitude is above at least a first range of the signal amplitude by substantially continuously scanning the phase delay introduced by the carrier generator.

[0142] In Figure 3c In another example of the carrier generator denoted by 310c in, the carrier generator 310 again provides a first carrier CW at the first carrier generator output 352 a and a second carrier CW at the second carrier output 354 b。The carrier generator 310c includes a delay line that includes a plurality of delay elements 370, 372, and 374. The carrier generator 310c provides a first carrier from a node that also serves as the input of the first delay element 370. The carrier generator 310c provides a second carrier from the output of the multiplexer 376, which selects the input or output of a selected one of the plurality of delay elements 370, 372, or 374 under the control of the mode control signal MC. Thus, depending on whether an AD class, BD class, or some intermediate operating mode is required, the second carrier output CW is under the control of the mode control signal MC b can undergo a controllable number of delay increments. In some variations, the source carrier can be applied directly to the input of the first delay element 370, and the delay introduced by each element is controlled by design. However, in the example shown, the delay elements include part of a phase-locked loop that includes a loop control circuit 378, which itself can include a phase detector and a loop filter or the like, and outputs control signals VC that adjust the delay of each element via corresponding control ports. In operation, this control signal adjusts the total delay of the delay line until the output of the delay line is phase-locked with the source signal, thus providing a per-element delay that is 1 / N source carrier periods. The delay elements can be digital gates, such as CMOS inverters with a control power rail or reverse bias VC, or can be voltage-controlled analog delay stages that use, for example, voltage-controlled transconductance or capacitance. The delay line and the multiplexer can be considered variable phase elements.

[0143] In Figure 3c another example of a carrier generator denoted 310d in a the carrier generator 310 again provides a first carrier CW at the first carrier generator output 352 b and a second carrier CW at the second carrier output 354. In this example, the carrier does not receive an explicit source carrier but provides a carrier output based on the received digital clock signal CLK. This clock is used to time a counter 380, and the output of the counter 380 is compared with a set of thresholds or comparison levels N1, N2, N3, N4, which can be considered together as the mode control signal MC or can be generated using, for example, a look-up table based on different formats of the received mode control signal MC.

[0144] In operation, the output of the counter ramps up as the number of pulses of the clock signal by which the counter is incremented increases, thereby exceeding thresholds N1, N2, N3, N4. The digital comparator 382 detects when each threshold is crossed and delivers a corresponding pulse to set or reset the subsequent flip-flops 384a or 384b. Thus, the flip-flop output signals Da and Db are controlled to switch from low to high or from high to low at times defined by N1, N2, N3, N4, etc. These outputs Da and Db can be used directly as the first carrier CWa and the second carrier CWb, respectively, if the binary digital levels are sufficient for the operation of the driver control circuit. If, for example, a triangular wave is required, the digital signals can control ramp generators 386a and 386b to provide a triangular wave. If an analog output is required, the ramp generator can include a digital-to-analog converter. A similar analog variant can be implemented using an analog ramp signal and an analog input comparator in place of the counter and the digital comparator.

[0145] In an alternative embodiment, a similar operation can be obtained by employing a digital state machine in place of the digital comparator 382 and the flip-flops 384a or 384b. The digital state machine has an input terminal coupled to the output terminal of the counter, and first and second output terminals coupled to the first carrier output terminal 352 and the second carrier output terminal 354 of the carrier generator 310d, respectively, and is operable in use to switch its output from a low state to a high state, or from a high state to a low state, at times defined by the thresholds N1 - N4 when the output of the counter crosses each threshold.

[0146] In Figure 3b the exemplary circuit 300 of, the first and second carriers are input to the inverting input terminals of the first comparator 302 and the second comparator 304 (appropriately applying a phase shift to the second carrier) and the first and second signals of the differential input signal pair received at the inverting input terminals of the first comparator 302 and the second comparator 304 so as to generate control signals to control the first output portion 312 and the second output portion 314 of the circuit 300. Those skilled in the art will recognize that alternative arrangements of the comparators 302, 304 can be equivalently used to achieve the same effect. For example, the polarities of the connections of the comparators 302, 304 can be reversed such that the first and second carriers (with a phase shift where appropriate) can be input to the non-inverting input terminals of the first comparator 302 and the second comparator 304, and the first and second signals of the differential input signal pair are input to the inverting input terminals of the comparators 302, 304. Unless the NMOS switches 3018, 320, 326, 330 are also replaced by PMOS switches, the operation will be similar to that described with respect to Figure 3b described operation.

[0147] Figures 4a - 4cshows a series of waveforms that show Figure 3b the operation of the circuit implementation thereof.

[0148] Figure 4a shows the effect of not applying a phase shift to the second carrier applied to the second comparator 304 of the circuit with respect to the first carrier applied to the first comparator 302. Figure 3b of the circuit.

[0149] Figure 4a The top waveform 402 of shows the first input signal 402a of the differential input signal pair, which is input to the non-inverting input terminal of the first comparator 302, and the triangular wave carrier 402b, which is input to Figure 3b the inverting input terminal of the first comparator 302 in the circuit 300 of. The second waveform 404 from the top shows the composite voltage at the node 324 of the first output section 312. In this embodiment, the positive power supply rail is 1V and the negative power supply rail is 0V, so this waveform switches between 1V and 0V.

[0150] The third waveform 406 from the top shows the second input signal 406a of the differential input signal pair, which is input to the non-inverting input terminal of the second comparator 304, and the triangular wave carrier 406b, which is input to the inverting input terminal of the second comparator 304. It should be noted that in this waveform, the triangular wave carrier is the same as the triangular wave carrier of the top waveform, that is, the triangular wave carrier input to the second comparator 304 is not phase-shifted with respect to the triangular wave carrier input to the first comparator 302. The fourth waveform 408 from the top shows the composite voltage at the node 332 of the second output section 314.

[0151] Figure 4a The bottom waveform 410 in shows the differential output on the load 316. It can be seen that the differential output has three levels (+1V, -1V, 0V). Therefore, when no phase shift is applied to the triangular wave carrier input to the second comparator 304 with respect to the triangular wave carrier input to the first comparator 302, the circuit 300 operates in class BD mode.

[0152] Figure 4b shows the effect of applying a 180-degree phase shift to the carrier of the second comparator 304 of the circuit input to Figure 3b This is equivalent to inverting the carrier applied to the first comparator 302 and applying the inverted version of the carrier to the second comparator 304.

[0153] Figure 4b The top waveform 412 of shows the first input signal 412a of the differential input signal pair, which is input to the non-inverting input terminal of the first comparator 302, and the triangular wave carrier 412b, which is input to Figure 3bThe inverting input terminal of the first comparator 302 in the circuit 300. The second waveform 414 from the top shows the combined voltage at the node 324 of the first output section 312.

[0154] The third waveform 416 from the top shows the second input signal 416a of the differential input signal pair, which is input to the non-inverting input terminal of the second comparator 304, and the triangular wave carrier 416b, which is input to the inverting input terminal of the second comparator 304. It should be noted that in this waveform, the triangular wave carrier is the inversion of the triangular wave carrier of the top waveform, that is, the triangular wave carrier input to the second comparator 304 is phase-shifted by 180 degrees relative to the triangular wave carrier input to the first comparator 302. The fourth waveform 418 from the top shows the combined voltage at the node 332 of the second output section 314.

[0155] Figure 4b The bottom waveform 420 in shows the differential output on the load 316. It can be seen that the differential output has only two levels (+1V, -1V). Therefore, when a 180-degree phase shift is applied to the triangular wave carrier input to the second comparator 304 relative to the triangular wave carrier input to the first comparator 302 (equivalent to inverting the carrier signal), the circuit 300 operates in class D mode.

[0156] Figure 4c shows the effect of applying a 90-degree phase shift to the carrier signal of the second comparator 304 of the circuit input to Figure 3b the circuit.

[0157] Figure 4c The top waveform 422 in shows the first input signal 422a of the differential input signal pair, which is input to the non-inverting input terminal of the first comparator 302, and the triangular wave carrier 422b, which is input to Figure 3b the inverting input terminal of the first comparator 302 in the circuit 300. The second waveform 424 from the top shows the combined voltage at the node 324 of the first output section 312.

[0158] The third waveform 426 from the top shows the second input signal 426a of the differential input signal pair, which is input to the non-inverting input terminal of the second comparator 302, and the triangular wave carrier 426b, which is input to the inverting input terminal of the second comparator 304. It should be noted that in this waveform, the triangular wave carrier is phase-shifted by 90 degrees relative to the triangular wave carrier input to the first comparator 302. The fourth waveform 428 from the top shows the combined voltage at the node 332 of the second output section 314.

[0159] Figure 4cThe bottom waveform 430 in shows the differential output across the load 316. It can be seen that the differential output has three levels (+1V, -1V, 0). Thus, when a 90-degree phase shift is applied to the triangular wave carrier input to the second comparator 304 relative to the triangular wave carrier input to the first comparator 302, the circuit 300 operates in class BD mode. However, Figure 4c A comparison of the bottom waveform 430 with Figure 4a the bottom waveform 410 of shows that there are fewer instances of the 0V state in the output waveform in Figure 4c than in, and the duration of the output pulses in the +1V and -1V states is generally longer than Figure 4a the duration of the output pulses in the +1V and -1V states in the waveform of. This demonstrates how changing the phase shift applied to the second carrier input to the second comparator 304 can be used to tune the operating mode of the circuit 300 to accommodate different characteristics of the input signal. For example, Figure 4a the phase shift applied in may be suitable for use when the input signal level is large most of the time but has periods of low signal level. Additionally, Figure 4c the phase shift applied in may be suitable for allowing a class D amplifier to be designed to operate in one or more modes to deliver a desired trade-off between, for example, linearity and EMI, such that, for example, the linearity can be obtained with the best possible EMI performance under specified linearity constraints, or vice versa. Figure 4c

[0160] It should be noted that for signals close to zero, for class BD operation, the differential output is mainly zero, i.e., the two driver stages operate in phase with each other. For class AD operation, the differential output alternates between +1V and -1Vd, i.e., the two driver stages operate in antiphase with each other. For an intermediate operating mode intermediate between the extremes, the two driver stages can operate in phase for half the time and in antiphase for the other half. The percentage of time of in-phase and antiphase operation can be used to measure the distance of a given mode from class AD or class BD. (If the signal monitor 210 is controlling the mode, typically in many implementations, a constant or long-duration zero input signal will result in class BD operation. However, the mode control can be based on the signal envelope, so a signal with a high peak-to-peak amplitude may have a signal close to zero in some time regions, allowing some measurement of the distance of the current mode from class AD or class BD.)

[0161] Figure 3b The circuit of illustrates the present invention and can provide sufficient performance for certain applications, such as driving tactile or other mechanical transducers. However, high-performance class D amplifiers typically incorporate some feedback from the output rather than open-loop operation.

[0162] Figure 5 ​is a schematic representation of how feedback can be applied around the comparator and driver sections of a half - circuit of a class - D amplifier. In Figure 5 the half - circuit generally shown as 500 includes a comparator 502 similar to Figure 3b comparator 302, whose inverting input terminal (-) is connected to the output of a carrier generator 508 similar to Figure 3b carrier generator 308. The carrier generator 508 is configured in this example to generate a triangular - wave carrier. The output of comparator 502 drives a driver stage 512, similar to Figure 3b driver stage 312. The output terminal of driver stage 512 can be connected to drive one terminal of a load (not shown), but is also connected to provide feedback V FBP of the output voltage via a feedback resistor 552.

[0163] The other terminal of resistor 552 is connected to the inverting input terminal of an amplifier 550, which is used to establish a virtual ground at that inverting input terminal. The virtual ground also receives an input analog signal S INP via an input resistor 554. The resulting signal currents through the input resistor 554 and the feedback resistor 552 are respectively proportional to the input signal S INP and the feedback output signal V FBP , scaled by the respective resistor values. The net signal current is integrated across a feedback capacitor 556 to provide a signal representing the integral of the error between the input signal S INP and the feedback output signal V FBP . This integral error signal, indicating the difference between the signal output by the first driver stage and the first signal derived from the input signal, is input to the other non - inverting (+) input terminal of comparator 502.

[0164] Thus, a negative - feedback loop is established, which includes an operational amplifier 550 and a capacitor 556 in combination with resistors 552 and 554 acting as a loop filter. The output of the loop filter is connected to the input of comparator 502, which then controls the output driver stage 512 to complete the loop. The loop filter provides high loop gain at low frequencies but low gain at higher frequencies to avoid loop oscillations or other instabilities.

[0165] To provide a complete class - D amplifier, a similar half - circuit is provided to drive the other terminal of the load and can receive an inverted input signal to replace Figure 3b comparator 304 and driver stage 314. The second half - circuit can receive a carrier from a carrier generator that is similar to Figure 3b carrier generator 310 instead of receiving the same carrier from carrier generator 508, and thus the entire circuit can be controlled to operate in class - AD or class - BD modes, as generally regardingFigure 3b as described above

[0166] As will be appreciated by those skilled in the art, due to negative feedback, an amplifier including a half - circuit Figure 5 can provide improved performance, for example, with respect to output signal distortion on an open - loop circuit 300 Figure 3b such as that shown in FIG. 3.

[0167] Figure 6 is a schematic representation of an alternative implementation of a half - circuit for use in a circuit 300 Figure 3b where a square wave is injected into an integrator to indirectly provide a triangular wave carrier, rather than generating a triangular wave which may be difficult to provide sufficient linearity for some applications.

[0168] This alternative half - circuit, generally designated 600, includes an operational amplifier 650, a comparator 602, an output driver stage 612, a feedback resistor 652, an input resistor 654, and an integrator feedback capacitor 656, which are similar to Figure 5 their respective similarly numbered elements 502, 512, 550, 552, 554, 556 of FIG. 5.

[0169] However, the output of the operational amplifier 650 does not directly drive the comparator. Instead, its output terminal is coupled to the comparator via another loop filter stage, which includes a second - stage input resistor 664, a second operational amplifier 660, and a second integration capacitor 666. There may also be a capacitor 668, which is connected in parallel with the resistor 664, to allow customization of the loop filter response for stability reasons.

[0170] In addition, in this example, no carrier is received and applied separately to the comparator input. Instead, a square - wave input current waveform is injected into the virtual - ground current - summing node at the inverting input of the second operational amplifier 660. This current can be provided by one or more active current sources connected to this virtual - ground node, or as shown, can be provided by applying a square - wave voltage to a resistor 662 connected to the virtual - ground node.

[0171] The square - wave current signal injected into the virtual - ground node is integrated by the capacitor 666 to provide a triangular - wave component of voltage at the output of the operational amplifier 660: this signal component is combined with a loop - filter signal component originating from the output of the operational amplifier 650, passing through the resistor 664 (and capacitor 668) and integrated by the capacitor 666, and the net signal is applied to the input of the comparator 602, the other input of which is the signal ground. Thus, the loop - filter signal component representing the difference between the signal output by the driver stage and the signal originating from the input signal is effectively compared with the triangular - wave carrier component.

[0172] To provide a complete class-D amplifier, a similar half-circuit is provided to drive the other terminal of the load and receive an inverted input signal to replace Figure 3b comparator 304 and driver stage 314 of Figure 3b . The second half-circuit may receive a square wave from a carrier generator similar to Figure 3b carrier generator 310 of

[0173] instead of receiving the same square wave as the first half-circuit, and depending on the delay between the square waves used in the two half-circuits, the entire circuit may be controlled to operate in two or more of class-AD or class-BD or intermediate "class-ADBD" modes, as generally described with respect to Figure 6

[0174]

[0175]

[0176]

[0177] Thus, Figure 6 half-circuit 600 of

[0174] eliminates the need for a complex circuit for providing a triangular-wave carrier with the necessary linearity. In addition, delaying a square wave by, for example, several cycles of a relatively high-speed clock can be easily performed merely digitally. In addition, the loop filter is second-order, allowing for a higher loop gain at low frequencies and flexibility in designing the loop response. As will be understood by those skilled in the art, the systems described herein provide a mechanism for dynamically switching between two or more class-AD or class-BD or class-ADBD operating modes in a class-D amplifier. This allows for selection of the most appropriate operating mode based on the nature or characteristics of the input signal, thus enabling the advantages of each operating mode to be realized in a single amplifier. Embodiments may be implemented in a range of applications and are particularly applicable to audio applications. For example, the class-D amplifier circuit described above may be used to drive an audio transducer, such as a speaker, a headset, headphones, or earbuds. However, it should be understood that the class-D amplifier circuit described above may equivalently be used in applications other than audio, for example, as a haptic output driver to drive a haptic transducer such as a linear resonant actuator, or more generally as a mechanical transducer driver to drive a mechanical transducer. Embodiments may be implemented as an integrated circuit, which may in some examples be a codec or an audio DSP or the like. Embodiments may be incorporated in an electronic device, which may be, for example, a portable device, and / or a device operable with battery power. The device may be a communication device, such as a mobile phone or a smartphone or the like. The device may be a computing device, such as a notebook, a laptop computing device, or a tablet computing device. The device may be a wearable device, such as a smartwatch. The device may be a device having voice control or activation functionality. In some cases, the device may be an accessory device to be used with some other product, such as headphones, etc.Those skilled in the art will recognize that certain aspects of the above devices and methods, such as the discovery and configuration methods, may be embodied as processor control code, which, for example, is on non-volatile carrier media such as disks, CD- or DVD-ROMs, programmed memories (such as read-only memories (firmware)), or on data carriers such as optical or electrical signal carriers. For many applications, the implementation will be on a DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), or FPGA (Field Programmable Gate Array). Thus, the code may include conventional program code or microcode, or, for example, code for setting or controlling an ASIC or FPGA. The code may also include code for dynamically configuring reconfigurable devices such as reprogrammable logic gate arrays. Similarly, the code may include code for hardware description languages such as Verilog TM or VHDL (Very High Speed Integrated Circuit Hardware Description Language). As those skilled in the art will understand, the code may be distributed among multiple coupled components that communicate with each other. Where appropriate, code running on a field programmable (re)programmable analog array or similar device may also be used to configure analog hardware to implement the implementation.

[0178] It should be noted that the above embodiments illustrate rather than limit the invention, and those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in the claims, "a" or "an" does not exclude a plurality, and a single feature or other unit may implement the functions of several units recited in the claims. Any reference signs or labels in the claims should not be construed as limiting their scope.

Claims

1. A class D amplifier circuit, comprising: An input terminal for receiving an input signal; First and second output nodes for driving a load connected between the first and second output nodes; A first driver stage for switching the first output node between a first power rail and a second power rail; A second driver stage for switching the second output node between the first power rail and the second power rail; A first driver control circuit configured to receive a first carrier and control the switching of the first driver stage based in part on the first carrier; A second driver control circuit configured to receive a second carrier and control the switching of the second driver stage based in part on the second carrier; A carrier generator configured to provide the first carrier and the second carrier, wherein a phase shift between the first carrier and the second carrier is adjustable in response to a mode control signal; And A monitoring circuit configured to generate the mode control signal based on an indication, parameter, characteristic, or feature of the input signal to be amplified; Wherein the monitoring circuit is configured to monitor a parameter of the input signal to be amplified and, if the monitored parameter of the input signal reaches or drops below a first threshold, generate a mode control signal to cause the class D amplifier circuit to transition from a first operating mode to a second operating mode, and if the monitored parameter of the input signal reaches or exceeds a second threshold, generate a mode control signal to cause the class D amplifier to transition from the second operating mode to the first operating mode; Wherein the monitored parameter of the input signal includes at least one of the following: an instantaneous signal level of the input signal; and an envelope of the input signal.

2. The class D amplifier circuit according to claim 1, wherein: The first driver control circuit is configured to receive a first signal derived from the input signal and control the switching of the first driver stage based in part on the first signal derived from the input signal; And The second driver control circuit is configured to receive a second signal derived from the input signal and control the switching of the second driver stage based in part on the second signal derived from the input signal.

3. The class D amplifier circuit according to claim 2, wherein the first and second signals derived from the input signal are complementary signals of a differential signal pair.

4. The class D amplifier circuit according to claim 2, wherein the first and second signals derived from the input signal are the same.

5. The class D amplifier circuit according to any one of claims 2 - 4, wherein: The first driver control circuit operates to compare the first signal derived from the input signal with the first carrier and control the switching of the first driver stage based on the comparison; And The second driver control circuit operates to compare the second signal derived from the input signal with the second carrier and control the switching of the second driver stage based on the comparison.

6. The class D amplifier circuit according to claim 1, wherein: The first driver control circuit operates to: compare a first difference signal with the first carrier, the first difference signal indicating a difference between a signal output by the first driver stage and a first signal derived from the input signal; And control the switching of the first driver stage based on the comparison; And The second driver control circuit operates to: compare a second difference signal with the second carrier, the second difference signal indicating a difference between a signal output by the second driver stage and a second signal derived from the input signal; and control the switching of the second driver stage based on the comparison.

7. The class D amplifier circuit according to claim 6, wherein: The first difference signal represents an integral of a difference between a voltage of the signal output by the first driver stage and a voltage of the first signal derived from the input signal; and The second difference signal represents an integral of a difference between a voltage of the signal output by the second driver stage and a voltage of the second signal derived from the input signal.

8. The class D amplifier circuit according to claim 7, wherein the first differential signal is provided at the output of the first loop filter of the first driver control circuit, and wherein the second differential signal is provided at the output of the second loop filter of the second driver control circuit.

9. The class D amplifier circuit according to claim 1, wherein: The first driver control circuit includes a first integrator circuit configured to receive a first digital signal and generate the first carrier based on the received first digital signal; and The second driver control circuit includes a second integrator circuit configured to receive a second digital signal and generate the second carrier based on the received second digital signal.

10. The class D amplifier circuit according to claim 9, wherein the first digital signal and the second digital signal include corresponding first and second square wave current waveforms.

11. The class D amplifier circuit according to claim 1, wherein in a first operating mode, the phase shift between the first carrier and the second carrier is 180 degrees.

12. The class D amplifier circuit according to claim 11, wherein in a second operating mode, the phase shift between the first carrier and the second carrier is zero.

13. The class D amplifier circuit according to claim 12, wherein in a third operating mode, the phase shift between the first carrier and the second carrier is a non-zero value other than 180 degrees.

14. The class D amplifier circuit according to claim 12, wherein the carrier generator operates to adjust the phase difference between the first carrier and the second carrier between a non-zero value and zero within a predetermined time period so as to transition from the first or third operating mode to the second operating mode, and to adjust the phase difference between the first carrier and the second carrier between zero and a non-zero value within a predetermined time period so as to transition from the second operating mode to the first or third operating mode.

15. The class D amplifier circuit according to claim 14, wherein the carrier generator operates to continuously scan the phase difference between the first carrier and the second carrier.

16. The class D amplifier circuit according to claim 1, wherein the second threshold is different from the first threshold.

17. The class D amplifier circuit according to claim 1, wherein the monitoring circuit is configured to receive information about the input signal and generate the mode control signal based on the received information, wherein the received information includes at least one of the following: a received indication of the signal level of the input signal; a received indication of an upcoming change in the signal level of the input signal; a received indication of a load attached to the class D amplifier circuit; a received indication of the signal type of the input signal; and a received indication that a silent period has been detected in the input audio signal.

18. The class D amplifier circuit according to claim 1, wherein the monitoring circuit is configured to generate the mode control signal based on at least one of the following: the signal level of the output signal of the class D amplifier circuit; The envelope of the output signal of the class D amplifier circuit; The duty cycle of the signal at the first or second output node; And The duty cycle of the output signal of the first or second driver control circuit.

19. The class D amplifier circuit according to claim 1, wherein the carrier generator comprises: A source carrier input terminal for receiving a source carrier; A first carrier output terminal for outputting a first carrier; A second carrier output terminal for outputting a second carrier; And A multiplexer, Wherein: The source carrier input terminal is coupled to the first carrier output terminal and a first input terminal of the multiplexer; A second input terminal of the multiplexer is configured to receive an inverted version of the source carrier; An output terminal of the multiplexer is coupled to the second carrier output terminal; And The multiplexer is configured to selectively couple its first input terminal or its second input terminal to its output terminal according to the mode control signal, such that the carrier generator outputs the source carrier or the inverted version of the source carrier at the second carrier output terminal and outputs the source carrier at the first carrier output terminal.

20. The class D amplifier circuit according to claim 19, wherein the carrier generator comprises an inverting stage coupled between the source carrier input and the second input of the multiplexer.

21. The class D amplifier circuit according to claim 1, wherein the carrier generator comprises: A source carrier input terminal for receiving a source carrier; A first carrier output terminal for outputting a first carrier; A second carrier output terminal for outputting a second carrier; And A variable phase shift element, Wherein: The source carrier input terminal is coupled to the first carrier output terminal and an input terminal of the variable phase shift element; An output terminal of the variable phase shift element is coupled to the second carrier output terminal; and The variable phase shift element is configured to apply a phase shift to the source carrier according to the mode control signal and output a phase shifted version of the source carrier as the second carrier.

22. The class D amplifier circuit according to claim 21, wherein the carrier generator further comprises another variable phase shift element coupled between the source carrier input and the first carrier output, wherein the another variable phase shift element is configured to apply a phase shift to the carrier according to the mode control signal and output a phase shifted version of the source carrier as the first carrier.

23. The class D amplifier circuit according to claim 22, wherein the variable phase shift element or the another variable phase shift element comprises at least one of the following: A delay line circuit; and An all-pass filter circuit.

24. The class D amplifier circuit according to claim 1, wherein the carrier generator comprises: A source carrier input terminal for receiving a source carrier; A first carrier output terminal for outputting a first carrier; A second carrier output terminal for outputting a second carrier; A delay line including a plurality of delay elements; And A multiplexer, Wherein: The input terminal of the source carrier is coupled to the output terminal of the first carrier and the input terminal of the delay line; The output terminal of each of the plurality of delay elements is coupled to the input terminal of the multiplexer; The output terminal of the multiplexer is coupled to the output terminal of the second carrier, and the multiplexer is configured to selectively couple its output terminal to one of its input terminals according to the mode control signal.

25. The class D amplifier circuit according to claim 24, wherein the plurality of delay elements form part of a phase-locked loop including a loop control circuit, wherein the loop control circuit is configured to output a control signal to each of the plurality of delay elements to adjust the delay of each of the plurality of delay elements, thereby adjusting the total delay of the delay line so as to lock the output of the delay line to the source carrier.

26. The class D amplifier circuit according to claim 1, wherein the carrier generator comprises: A first carrier output terminal for outputting a first carrier; A second carrier output terminal for outputting a second carrier; A first ramp signal generator configured to output a ramp signal; A first comparator configured to compare the signal output by the first ramp signal generator with a first threshold and output a signal when the signal output by the first ramp signal generator reaches the first threshold; A second comparator configured to compare the signal output by the first ramp signal generator with a second threshold and output a signal when the signal output by the first ramp signal generator reaches the second threshold; A third comparator configured to compare the signal output by the first ramp signal generator with a third threshold and output a signal when the signal output by the first ramp signal generator reaches the third threshold; A fourth comparator configured to compare the signal output by the first ramp signal generator with a fourth threshold and output a signal when the signal output by the first ramp signal generator reaches the fourth threshold; A first bistable element having a first input terminal coupled to the output terminal of the first comparator and a second input terminal coupled to the output terminal of the second comparator; And A second bistable element having a first input terminal coupled to the output terminal of the third comparator and a second input terminal coupled to the output terminal of the fourth comparator, wherein the output terminal of the first bistable element is coupled to the output terminal of the first carrier and the output terminal of the second bistable element is coupled to the output terminal of the second carrier.

27. The class D amplifier circuit according to claim 26, wherein the first ramp signal generator comprises a counter configured to receive a clock signal and output a signal indicative of the number of clock pulses of the clock signal counted by the counter.

28. The class D amplifier circuit according to claim 26, wherein the carrier generator further comprises: A second ramp signal generator coupled between the output terminal of the first bistable element and the output terminal of the first carrier; And a third ramp signal generator coupled between the output terminal of the second bistable element and the output terminal of the second carrier.

29. The class D amplifier circuit according to claim 1, wherein the carrier generator comprises: A counter configured to receive a clock signal and output a signal indicating the number of clock pulses of the clock signal counted by the counter; And A state machine having an input terminal coupled to the output terminal of the counter and first and second output terminals coupled to the first and second carrier output terminals, wherein the state machine is configured to output signals at the first and second output terminals of the state machine when the output of the counter reaches a plurality of thresholds.

30. A class D amplifier circuit, comprising: A mode controller configured to dynamically adjust, within a range between an AD class mode and a BD class mode, an operation switching mode of the class D amplifier according to an indication of a level of an input signal to be amplified; wherein a monitoring circuit is configured to monitor a parameter of the input signal to be amplified, and if the monitored parameter of the input signal reaches or drops below a first threshold, generate a mode control signal to cause the class D amplifier circuit to transition from a first operation mode to a second operation mode, and if the monitored parameter of the input signal reaches or exceeds a second threshold, generate a mode control signal to cause the class D amplifier to transition from the second operation mode to the first operation mode; wherein the monitored parameter of the input signal includes at least one of the following: an instantaneous signal level of the input signal; and an envelope of the input signal.

31. A class D amplifier circuit, comprising: First and second half-bridge output stages; and A mode controller configured to dynamically adjust, within a range between an AD class mode and a BD class mode, an operation switching mode of the class D amplifier by dynamically adjusting a relative phase of a cycle reference of respective switching controllers applied to the first and second half-bridge output stages according to a level indication, parameter, characteristic, or feature of an input signal to be amplified; wherein a monitoring circuit is configured to monitor a parameter of the input signal to be amplified, and if the monitored parameter of the input signal reaches or drops below a first threshold, generate a mode control signal to cause the class D amplifier circuit to transition from a first operation mode to a second operation mode, and if the monitored parameter of the input signal reaches or exceeds a second threshold, generate a mode control signal to cause the class D amplifier to transition from the second operation mode to the first operation mode; wherein the monitored parameter of the input signal includes at least one of the following: an instantaneous signal level of the input signal; and an envelope of the input signal.

32. An electronic device, comprising the class D amplifier circuit according to claim 1, wherein the electronic device comprises at least one of the following: a portable electronic device; a battery-powered device; a computing device; a communication device; a gaming device; a mobile phone; a media player; a laptop computing device, a tablet computing device, or a notebook computing device; a wearable device; or a voice-activated or voice-controlled device.

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