semiconductor devices

Abstract

A semiconductor device includes: an active region extending in a first direction on a substrate, the active region having an upper surface and sidewalls; a plurality of channel layers vertically spaced apart from each other above the active region; a gate electrode extending in a second direction to intersect the active region and partially surround the plurality of channel layers; and a source / drain region on at least one side of the gate electrode on the active region and in contact with the plurality of channel layers, extending from the sidewalls of the active region, and having a large width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layers.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0061678, filed on May 27, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device. Background Art

[0004] As the demand for high-performance, high-speed, and / or multifunctional semiconductor devices increases, the integration density of semiconductor devices is also increasing. When manufacturing semiconductor devices having micropatterns in accordance with the trend toward high integration density in semiconductor devices, it may be advantageous to implement patterns having relatively fine widths and / or spacings. Various efforts have been made to develop semiconductor devices including three-dimensional channels to overcome the limitations on operating characteristics caused by the miniaturization and / or reduction of planar metal oxide semiconductor FETs (MOSFETs). Summary of the Invention

[0005] Example embodiments provide a semiconductor device having improved electrical characteristics.

[0006] According to an exemplary embodiment, a semiconductor device includes: an active region extending in a first direction on a substrate, the active region having an upper surface and sidewalls; a plurality of channel layers disposed on the active region to be vertically spaced apart from each other; a gate electrode extending in a second direction to intersect the active region and partially surround the plurality of channel layers; and source / drain regions on at least one side of the gate electrode on the active region and in contact with the plurality of channel layers. The source / drain regions extend from the sidewalls of the active region and have a widest local width at a maximum width in the second direction in a first region adjacent to a lowermost channel layer of the plurality of channel layers adjacent to the active region.

[0007] According to an exemplary embodiment, a semiconductor device includes an active region extending in a first direction on a substrate; a first channel layer and a second channel layer sequentially spaced vertically apart from each other above the active region; a gate electrode extending in a second direction to intersect the active region on the substrate and surround the first and second channel layers; and a source / drain region disposed on at least one side of the gate electrode on the active region and in contact with the first and second channel layers. The source / drain region has a first maximum width in the second direction in a region adjacent to the first channel layer, and has a second maximum width in the second direction that is smaller than the first maximum width in a region adjacent to the second channel layer.

[0008] According to an exemplary embodiment, a semiconductor device includes: an active region extending in a first direction on a substrate, the active region having an upper surface and sidewalls; a gate electrode extending in a second direction to intersect the active region on the substrate; a plurality of channel layers vertically spaced apart from each other on the active region in a region where the active region and the gate electrode intersect each other; a spacer layer on the sidewall of the active region in the second direction and exposing the upper surface and a portion of the sidewall of the active region; and source / drain regions on at least one side of the gate electrode on the active region and in contact with the plurality of channel layers. The source / drain regions extend from the sidewall of the active region exposed by the spacer layer to be inclined relative to the upper surface of the substrate to have a width extending from both sides of the active region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a top view of a semiconductor device according to example embodiments;

[0011] Figure 2 is a cross-sectional view of a semiconductor device according to example embodiments;

[0012] Figure 3A and Figure 3B are a top view and a cross-sectional view, respectively, of a semiconductor device according to example embodiments;

[0013] Figure 4 is a cross-sectional view of a semiconductor device according to example embodiments;

[0014] Figures 5A to 5C is a cross-sectional view of a semiconductor device according to example embodiments;

[0015] Figure 6 is a cross-sectional view of a semiconductor device according to example embodiments;

[0016] Figures 7A to 7J is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0017] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0018] Figure 1 is a top view of a semiconductor device according to example embodiments.

[0019] Figure 2 is a cross-sectional view of a semiconductor device according to example embodiments. Figure 2 Shown along Figure 1 The cross sections of the semiconductor device are taken along lines II', II-II' and III-III'. Figure 1 and Figure 2 Only the main components of the semiconductor device are shown.

[0020] Reference Figure 1 and Figure 2 , the semiconductor device 100 may include: a substrate 101; an active region 105 on the substrate 101; channel structures 140, each including a plurality of channel layers 141, 142, and 143 disposed on the active region 105 and vertically spaced apart from each other; source / drain regions 150 contacting the plurality of channel layers 141, 142, and 143; a gate structure 160 extending to intersect the active region 105; and / or a contact plug 180 connected to the source / drain region 150. The semiconductor device 100 may further include an isolation layer 110, an inner spacer layer 130, and / or an interlayer insulating layer 190. The gate structure 160 may include a gate dielectric layer 162, a gate electrode 165, a spacer layer 164, and / or a gate capping layer 166.

[0021] In the semiconductor device 100, the active region 105 may have a fin structure, and the gate electrode 165 may be provided between the active region 105 and the channel structure 140 and between the plurality of channel layers 141, 142, and 143 of the channel structure 140. Therefore, the semiconductor device 100 may include an MBCFET formed by the channel structure 140, the source / drain region 150, and the gate structure 160. TM (Multi-bridge channel FET).

[0022] The substrate 101 may have an upper surface extending in the x-direction and the y-direction. The substrate 101 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like.

[0023] The active region 105 may be defined in the substrate 101 by the isolation layer 110 and may be arranged to extend in a first direction (e.g., x-direction). The active region 105 may have an active fin structure protruding from the substrate 101. The active region 105 may be arranged so that its upper end protrudes a predetermined height from the top surface of the isolation layer 110. The active region 105 may include a portion of the substrate 101, or may include an epitaxial layer grown from the substrate 101. A portion of the active region 105 on the substrate 101 may be recessed on the opposite side adjacent to the gate structure 160, and the source / drain region 150 may be provided on the recessed portion of the active region 105. Therefore, as Figure 2As shown, the active region 105 may have a relatively greater height below the channel structure 140 and the gate structure 160. In some embodiments, the active region 105 may include impurities, and at least a portion of the active region 105 may include impurities having opposite conductivity types to each other, but example embodiments of the active region 105 are not limited thereto.

[0024] The isolation layer 110 may define the active region 105 on the substrate 101. The isolation layer 110 may be formed by, for example, a shallow trench isolation (STI) process. The isolation layer 110 may be formed to expose the upper sidewalls of the active region 105. In some embodiments, the isolation layer 110 may include a region extending deeper toward the lower portion of the substrate 101 between the active regions 105. The isolation layer 110 may have a curved top surface whose horizontal height becomes higher in a direction toward the active region 105, but the shape of the top surface of the isolation layer 110 is not limited thereto. The isolation layer 110 may be formed of an insulating material. The isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof. Figure 2 As shown, the isolation layer 110 may have different top surface heights below and outside the gate structure 160. Such shape variation is formed according to a manufacturing process, and the height difference of the top surface may vary according to example embodiments.

[0025] The channel structure 140 includes first to third channel layers 141, 142, and 143, and the plurality of channel layers are disposed on the active region 105 so as to be spaced apart from each other in a direction perpendicular to the top surface of the active region 105 (e.g., the z-direction). The first to third channel layers 141, 142, and 143 may be spaced apart from the top surface of the active region 105 while being connected to the source / drain region 150. Each of the first to third channel layers 141, 142, and 143 may have a width in the y-direction that is equal to or similar to the width of the active region 105, and may have a width in the x-direction that is equal to or similar to the width of the gate structure 160. However, in some embodiments, the first to third channel layers 141, 142, and 143 may have a reduced width so that their side surfaces are disposed below the gate structure 160 in the x-direction. Each of the first to third channel layers 141, 142, and 143 may be formed of a semiconductor material and may include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). For example, the first to third channel layers 141, 142, and 143 may be formed of the same material as the substrate 101. The number and shape of the channel layers 141, 142, and 143 constituting the single channel structure 140 may be variously changed according to example embodiments.

[0026] The source / drain regions 150 may be disposed on opposite sides of the active region 105 adjacent to the gate structure 160. The source / drain regions 150 may be configured as source or drain regions of a transistor. Each source / drain region 150 may be disposed such that its upper surface is higher than the uppermost surface of the channel structure 140 and may be an elevated source / drain disposed higher than the bottom surface of the gate electrode 165 on the channel structure 140.

[0027] The source / drain region 150 may be provided in a region recessed between adjacent channel structures 140 and adjacent gate structures 160 in a portion of the active region 105 in the x-direction. The source / drain region 150 may extend from the sidewalls of the active region 105 to be inclined relative to the upper surface of the substrate 101 on the side opposite to the gate structure 160, as shown in a cross-sectional view taken in the y-direction. The source / drain region 150 may have a large width in a region adjacent to the first channel layer 141 (the lowest layer of the plurality of channel layers 141, 142, and 143 adjacent to the active region 105) in the y-direction (e.g., a region adjacent to the first channel layer 141 in this direction having a height corresponding to the height of the first channel layer 141). The source / drain region 150 may have a relatively reduced width in a region disposed adjacent to the overlying second channel layer 142 and third channel layer 143 (e.g., a region disposed adjacent to the second channel layer 142 and third channel layer 143, each having a height corresponding to the height at which the second channel layer 142 and third channel layer 143 are disposed). In the source / drain region 150, the inclined surface extending from the sidewall of the active region 105 may be a facet provided along a crystal plane (e.g., <111> The shape of the source / drain region 150 will be referred to later. Figure 3A 5 is described in more detail.

[0028] The source / drain region 150 may be formed of a semiconductor material. For example, the source / drain region 150 may include at least one of silicon germanium (SiGe), silicon (Si), silicon arsenic (SiAs), silicon phosphide (SiP), and silicon carbide (SiC). Specifically, the source / drain region 150 may be formed of an epitaxial layer. For example, the source / drain region 150 may include n-type doped silicon (Si) and / or p-type doped silicon germanium (SiGe). In example embodiments, the source / drain region 150 may include multiple regions including elements and / or doping elements with different concentrations. In addition, in example embodiments, the source / drain region 150 may be connected to each other on two or more active regions 105 disposed adjacent to each other, or may be merged to form a single source / drain region 150.

[0029] The gate structure 160 may be disposed above the active region 105 and the channel structure 140 to intersect the active region 105 and the channel structure 140 and extend in one direction (e.g., the y-direction). The channel region of the transistor may be formed in the active region 105 and the channel structure 140 intersecting the gate structure 160. The gate structure 160 includes a gate electrode 165, a gate dielectric layer 162 between the gate electrode 165 and the plurality of channel layers 141, 142, and 143, a spacer layer 164 on the side surface of the gate electrode 165, and a gate capping layer 166 on the top surface of the gate electrode 165.

[0030] The gate dielectric layer 162 may be disposed between the active region 105 and the gate electrode 165 and between the channel structure 140 and the gate electrode 165, and may be disposed to cover at least a portion of the surface of the gate electrode 165. For example, the gate dielectric layer 162 may be disposed to surround all surfaces except the uppermost surface of the gate electrode 165. The gate dielectric layer 162 may extend between the gate electrode 165 and the spacer layer 164, but the extension of the gate dielectric layer 162 is not limited thereto. The gate dielectric layer 162 may include an oxide, a nitride, or a high-k material. A high-k material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2). The high-k material may include, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), or the like. x O y ), Hafnium Oxide (HfO2), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ) and one of praseodymium oxide (Pr2O3).

[0031] The gate electrode 165 may be disposed above the active region 105 to extend to the upper portion of the channel structure 140 while filling the space between the plurality of channel layers 141, 142, and 143. The gate electrode 165 may be spaced apart from the plurality of channel layers 141, 142, and 143 by the gate dielectric layer 162. The gate electrode 165 may include a conductive material and may include a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. The gate electrode 165 may have a multilayer structure including two or more layers. Depending on the configuration of the semiconductor device 100, the gate electrode 165 may be divided by additional dividing portions between at least some adjacent transistors.

[0032] The spacer layer 164 may be disposed on both side surfaces of the gate electrode 165 on the channel structure 140. The spacer layer 164, together with the inner spacer layer 130, may insulate the source / drain region 150 and the gate electrode 165 from each other. In some embodiments, the spacer layer 164 may have a multilayer structure. The spacer layer 164 may include oxide, nitride, and oxynitride. Specifically, the spacer layer 164 may include a low-k dielectric layer. The active spacer layer 164F may be formed simultaneously in the same process as the spacer layer 164 and, therefore, may include the same material as the spacer layer 164. The active spacer layer 164F may be disposed on the upper sidewall of the active region 105 exposed by the isolation layer 110 on the opposite side adjacent to the gate structure 160.

[0033] The gate capping layer 166 may be disposed on the uppermost surface of the gate electrode 165, and its lower surface and side surfaces may be respectively surrounded by the gate electrode 165 and the spacer layer 164. The gate capping layer 166 may include oxide, nitride, and oxynitride.

[0034] The inner spacer layer 130 may be arranged parallel to the gate electrode 165 between the spaces of the channel structure 140. Below the third channel layer 143, the gate electrode 165 may be spaced apart from the source / drain region 150 by the inner spacer layer 130 to be electrically insulated from the source / drain region 150. The inner spacer layer 130 may have a shape in which the side surface facing the gate electrode 165 is convexly rounded inwardly toward the gate electrode 165, but the shape of the inner spacer layer 130 is not limited thereto. The inner spacer layer 130 may include an oxide, a nitride, or an oxynitride. Specifically, the inner spacer layer 130 may include a low-k dielectric layer. In some embodiments, the inner spacer layer 130 may be omitted. In this case, the gate electrode 165 may be arranged to extend between the spaces of the channel structure 140, and the side surface of the gate electrode 165 along the x-direction may be arranged vertically parallel to the side surface of the channel structure 140.

[0035] Interlayer insulating layer 190 may be provided to cover top surfaces of source / drain regions 150, gate structure 160, and isolation layer 110. Interlayer insulating layer 190 may include, for example, at least one of oxide, nitride, and oxynitride, and may include a low-k dielectric material.

[0036] The contact plug 180 may be connected to the source / drain region 150 to apply an electrical signal to the source / drain region 150. The contact plug 180 may penetrate the interlayer insulating layer 190 to extend vertically. Figure 1 As shown, contact plug 180 may be disposed on source / drain region 150. In some embodiments, contact plug 180 may be disposed to have a length in the y-direction greater than the length of source / drain region 150. Depending on the aspect ratio, contact plug 180 may have an inclined side surface with a lower portion narrower than an upper portion, but the shape of contact plug 180 is not limited thereto. Contact plug 180 may be disposed to recess source / drain region 150 by a predetermined depth. Contact plug 180 may extend, for example, to a portion lower than third channel layer 143. Contact plug 180 may be recessed, for example, to the upper surface of second channel layer 142, but the recessing of contact plug 180 is not limited thereto. In example embodiments, contact plug 180 may be disposed to contact source / drain region 150 along the top surface of source / drain region 150 without recessing source / drain region 150.

[0037] Figure 3A and Figure 3B 1 and 2 are a top view and a cross-sectional view, respectively, of a semiconductor device according to example embodiments. Figure 3A and Figure 3B Shown separately Figure 1 A magnified version of area "A" and Figure 2 A magnified version of area "B".

[0038] Reference Figure 3A and Figure 3BThe source / drain region 150 may extend further in the y-direction than the active region 105 to the opposite side adjacent to the gate structure 160, and may include multiple regions each having a width greater than that of the active region 105. From its lower portion, the source / drain region 150 includes: a first region including a first point P1 having a first maximum width W1; a second region including a second point P2 having a second maximum width W2 smaller than the first maximum width W1; and a third region including a third point P3 having a third maximum width W3 smaller than the first maximum width W1. The first maximum width W1 of the first point P1 may be the maximum width of the first region in the y-direction, and may be the maximum width of the entire source / drain region 150 in the y-direction. The source / drain region 150 may have a width greater than that of the active region 105 at least in the first through third points P1, P2, and P3, and thus may have a curvature. The shape of the source / drain region 150 may be derived from the fact that the lower portion of the source / drain region 150 grows from the sidewall of the active region 105 and the upper portion of the source / drain region 150 has a shape due to the reference Figure 1 and Figure 2 The inner spacer layer 130 is described to limit the growth area of ​​the source / drain region 150.

[0039] The first point P1 may be a point where the source / drain region 150 grows from the top surface and sidewalls of the active region 105 and grows from the side surface of the first channel layer 141 in the x-direction to have a large width. Specifically, the source / drain region 150 may grow from the sidewall of the active region 105 to the first point P1 while forming a facet provided along the crystal plane. Therefore, in the source / drain region 150, the side surface extending to the first point P1 may form a specific angle θ according to the crystal plane. For example, when a

[111] facet is formed, the angle θ may be approximately 54.7 degrees. Depending on the crystal plane, the side surface of the upper portion of the first point P1 may also be a facet. Therefore, the side surfaces of the upper and lower portions based on the first point P1 may be facets, and the source / drain region 150 may have a large width at the boundary between the facets. The first point P1 may be set at a height between the first channel layer 141 and the active region 105, but the detailed height may vary in example embodiments. For example, the first point P1 may be set at a height between the upper surface of the first channel layer 141 and the upper surface of the active region 105. For example, the first point P1 may be set at a height between the lower surface of the first channel layer 141 and the upper surface of the active region 105. The position of the first point P1 may be controlled by the first length L1 of the sidewall of the active region 105 exposed through the active spacer layer 164F and the second length L2 (the length between the top surface of the active region 105 and the lower surface of the first channel layer 141). The second length L2 may be controlled by the depth of the active region 105 recessed in the source / drain region 150 during the manufacturing process.

[0040] When the length from the exposed point of the active region 105 to the mid-height of the first channel layer 141 and the second channel layer 142 is defined as the third length L3, the fourth length L4 of the first point P1 protruding from the extension line of the side surface of the first channel layer 141 or the active region 105 in the y direction can be approximately calculated by (L3 / 2) / tanθ. Therefore, the fourth length L4 can increase as the first length L1 of the sidewall of the active region 105 exposed through the active spacer layer 164F and the second length L2 between the top surface of the active region 105 and the lower surface of the first channel layer 141 increase. In example embodiments, the fourth length L4 can be in the range of approximately 7 nm to 20 nm. When the length of the second point P2 protruding from the extension line of the side surface of the second channel layer 142 or the active region 105 in the y direction is defined as the fifth length L5, the length L5 can also be calculated in a manner similar to the calculation method of the fourth length L4. In example embodiments, the ratio (L5 / L4) of the fifth length L5 to the fourth length L4 may be in the range of about 0.4 to about 0.7, which may be controlled by varying the thickness and spacing of the first and second channel layers 141 and 142 and the first and second lengths L1 and L2.

[0041] The second point P2 and the third point P3 may be disposed at heights corresponding to the second channel layer 142 and the third channel layer 143, respectively. Figure 3A As shown, the second point P2 and the third point P3 may be arranged in substantially the same position on a plane. For example, the second maximum width W2 and the third maximum width W3 may be substantially the same, but are not limited thereto. According to embodiments, the third maximum width W3 may be smaller than the second maximum width W2. In this case, the first point P1, the second point P2, and the third point P3 may be arranged sequentially from the outside of the source / drain region 150 in the y-direction on a plane.

[0042] The source / drain region 150 may include regions each having a reduced width between the first point to the third point P1, P2, and P3. For example, the source / drain region 150 may include regions each having a reduced width between the first point P1 and the second point P2 and between the second point P2 and the third point P3, and regions each having a local minimum width. The minimum width may be close to, for example, the width of the active region 105, but is not limited thereto. The regions each having a local minimum width may be set at a height corresponding to, for example, the height at which the internal spacer layer 130 is set. Therefore, the source / drain region 150 may have a curvature corresponding to the setting of the plurality of channel layers 141, 142, and 143 and the internal spacer layer 130, and may have a gently curved top surface above the third point P3. As Figure 3B As shown, the source / drain region 150 may have an outer surface having a cut surface in at least one region between the first to third points P1 , P2 , and P3 .

[0043] Figure 4 is a cross-sectional view of a semiconductor device according to example embodiments. Figure 4 Shown with Figure 2 Region "B" corresponds to an enlarged version of the region.

[0044] Reference Figure 4 , various types of contact plugs 180 , 180 a , and 180 b according to example embodiments are illustrated together with the source / drain regions 150 and the contact plugs 180 to describe a disposition relationship between the source / drain regions 150 and the contact plugs 180 .

[0045] The contact plugs 180, 180a, and 180b may be arranged so that the upper portion of the source / drain region 150 is recessed from its upper surface to a predetermined depth RD. The recessed depth RD may be a height substantially corresponding to the upper surface of the second channel layer 142. However, the recessed depth RD is not limited thereto and may vary in example embodiments. Those skilled in the art will appreciate that when the recessed depth RD is relatively large, the volume of the source / drain region 150 may be reduced and thus insufficient to perform electrical functions. When the recessed depth RD is relatively small, the source / drain region 150 and the contact plugs 180, 180a, and 180b may not be electrically connected to each other due to process variations.

[0046] According to example embodiments, contact plugs 180, 180a, and 180b may have different widths that sequentially increase in the y-direction. Similar to contact plug 180b, when the width of contact plug 180b is greater than the width of source / drain region 150 in contact with contact plug 180b, the upper portion of source / drain region 150 is recessed by a depth RD on the opposite side adjacent to gate structure 160. Therefore, in the final structure of the semiconductor device, the shape of source / drain region 150 may also differ depending on the widths of contact plugs 180, 180a, and 180b.

[0047] Figures 5A to 5C is a cross-sectional view of a semiconductor device according to example embodiments. Figures 5A to 5C Shown respectively with Figure 2 Region "B" corresponds to an enlarged version of the region.

[0048] Reference Figure 5A , the source / drain region 150a may have a shape in which the cross section is generally gentle, and includes first to third points P1, P2, and P3 each having a locally large width, and includes the first point P1 having a large width, as shown in FIG. Figure 3AAs shown. For example, the source / drain region 150a may have a curvature corresponding to the plurality of channel layers 141, 142, and 143. This shape may be controlled according to the material of the source / drain region 150a. For example, when the source / drain region 150a includes impurities occupying interstitial positions, the source / drain region 150a may be grown to have such a curved outer surface. In this case, the source / drain region 150a may be formed of, for example, silicon phosphide (SiP).

[0049] Reference Figure 5B , the source / drain region 150b may have a box-shaped upper portion that does not include the third point P3 but includes the first point P1 and the second point P2 each having a locally larger width, and includes the first point P1 having a large width, as shown Figure 3A As shown. The source / drain region 150b may have a fourth width W4 smaller than the first maximum width W1 at the first point P1 at a height corresponding to the third channel layer 143. The fourth width W4 may be smaller than the second width W2a at the second point P2, or may be similar to the second width W2a. Even in this case, the source / drain region 150b may have an inclined surface up to the first point P1 having the maximum width.

[0050] Reference Figure 5C , the source / drain region 150c may be arranged so that a portion of the source / drain region 150c grows from its lower end onto the active spacer layer 164F to contact the active spacer layer 164F. Therefore, the source / drain region 150c may have a shape in which the surface extending from the sidewall of the active region 105 to the first point P1 includes multiple surfaces or multiple curved surfaces, rather than a single cut surface, while including a first point P1 having a large width. This shape of the source / drain region 150c may occur when the lower end portion of the source / drain region 150c does not grow along a crystal plane under the growth conditions of the source / drain region 150c. A second point P2 and a third point P3, each having a locally larger width, are provided on the upper portion of the source / drain region 150c, but in some embodiments, the source / drain region 150c may have a box shape, such as Figure 5B shown.

[0051] Figure 6 is a cross-sectional view of a semiconductor device according to example embodiments. Figure 6 Shown along with Figure 1 The area corresponding to the cross section taken along line II-II'.

[0052] Reference Figure 6 The semiconductor device 100a may include an active region 105a and a channel structure 140a, the width of which is Figure 2The active region 105a and the channel structure 140a may have relatively small widths, so that the plurality of channel layers 141a, 142a, and 143a of the channel structure 140a may each have a circular shape or an elliptical shape in which the difference between the lengths of the major axis and the minor axis in the cross section in the y direction is relatively small. For example, in Figure 2 In an example embodiment, each of the plurality of channel layers 141, 142, and 143 may have a width of approximately 20 nm to 50 nm in the y direction, and in this embodiment, each of the plurality of channel layers 141 a, 142 a, and 143 a may have a width of approximately 3 nm to 12 nm in the y direction. As described above, in example embodiments, the width and shape of the active region 105 a and the channel structure 140 a may be variously changed.

[0053] Figures 7A to 7J is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment. Figures 7A to 7J In the description Figure 1 and Figure 2 Example embodiments of a method for manufacturing a semiconductor device and illustrating the Figure 2 The corresponding cross section.

[0054] Reference Figure 7A , sacrificial layers 120 and channel layers 141 , 142 , and 143 may be alternately stacked on the substrate 101 .

[0055] The sacrificial layer 120 may be a layer that is replaced by the gate dielectric layer 162 and the gate electrode 165 in subsequent processes, such as Figure 2 As shown. The sacrificial layer 120 may be formed of a material having an etching selectivity relative to the channel layers 141, 142, and 143. The channel layers 141, 142, and 143 may include a material different from that of the sacrificial layer 120. The sacrificial layer 120 and the channel layers 141, 142, and 143 include a semiconductor material including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), and may include different materials. The sacrificial layer 120 and the channel layers 141, 142, and 143 may or may not include impurities. For example, the sacrificial layer 120 may include silicon germanium (SiGe), and the channel layers 141, 142, and 143 may include silicon (Si).

[0056] The sacrificial layer 120 and the channel layers 141, 142, and 143 may be formed by performing an epitaxial growth process using the substrate 101 as a seed. Each of the sacrificial layer 120 and the channel layers 141, 142, and 143 may have a thickness of approximately The number of the channel layers 141 , 142 , and 143 alternately stacked with the sacrificial layer 120 may be variously changed in example embodiments.

[0057] Reference Figure 7B , the stacked structure of the sacrificial layer 120 and the channel layers 141 , 142 , and 143 and a portion of the substrate 101 may be removed to form an active structure.

[0058] The active structure may include a sacrificial layer 120 and channel layers 141, 142, and 143 alternately stacked with each other. The active structure may also include an active region 105 formed by removing a portion of the substrate 101 to protrude toward the upper surface of the substrate 101. The active structure may be formed in one direction (e.g., Figure 1 The linear shapes extend in the x-direction in the y-direction and may be spaced apart from each other in the y-direction.

[0059] In the region where a portion of substrate 101 is removed, isolation layer 110 may be formed by filling the region with an insulating material and recessing the insulating material so that active region 105 protrudes.

[0060] Reference Figure 7C , a sacrificial gate structure 170 and a spacer layer 164 may be formed on the active structure.

[0061] Each sacrificial gate structure 170 may be a sacrificial structure formed in a substrate process in a region where the gate dielectric layer 162 and the gate electrode 165 are disposed above the channel structure 140, such as Figure 2 As shown. The sacrificial gate structure 170 may include a first sacrificial gate layer 172 and a second sacrificial gate layer 175 and a mask pattern layer 176 stacked in sequence. The first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be patterned using the mask pattern layer 176. The first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be an insulating layer and a conductive layer, respectively, but are not limited thereto. The first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be provided as a single layer. For example, the first sacrificial gate layer 172 may include silicon oxide and the second sacrificial gate layer 175 may include polysilicon. The mask pattern layer 176 may include silicon oxide and / or silicon nitride. The sacrificial gate structure 170 may have a linear shape extending in one direction while intersecting the active structure. The sacrificial gate structure 170 may be, for example, Figure 1 The components extend in the y-direction and are spaced apart from each other in the x-direction.

[0062] A spacer layer 164 may be formed on both sidewalls of the sacrificial gate structure 170. Using the spacer layer 164, an active spacer layer 164F may also be formed on both sidewalls of the active structure exposed from the sacrificial gate structure 170. The spacer layer 164 and the active spacer layer 164F may be formed by forming a layer having a uniform thickness along the top and side surfaces of the sacrificial gate structure 170 and the active structure and anisotropically etching the layer having a uniform thickness. The spacer layer 164 and the active spacer layer 164F may be formed of the same material. The spacer layer 164 and the active spacer layer 164F may be formed of a low-k dielectric material and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0063] Reference Figure 7D , the sacrificial layer 120 and the channel layers 141 , 142 , and 143 exposed between the sacrificial gate structures 170 may be removed to form the channel structure 140 .

[0064] The exposed sacrificial layer 120 and the exposed channel layers 141, 142, and 143 may be removed using the sacrificial gate structure 170 and the spacer layer 164 as a mask. Therefore, the channel layers 141, 142, and 143 may each have a finite length in the x-direction and constitute the channel structure 140. In example embodiments, a portion of the sacrificial layer 120 and a portion of the channel structure 140 may be removed from side surfaces thereof below the sacrificial gate structure 170 so that both sides thereof may be disposed below the sacrificial gate structure 170 and the spacer layer 164.

[0065] In this process, a portion of the active region 105 may also be recessed from its top surface and removed. In addition, a portion of the active spacer layer 164F provided on both sidewalls of the active structure is removed at the same time as the sacrificial layer 120 and the channel layers 141, 142, and 143 are removed, and a portion thereof may be further removed during the process of recessing the active region 105.

[0066] By varying process conditions, the active spacer layer 164F is retained, exposing the upper sidewalls of the active region 105 by a predetermined length L1, as shown in the accompanying drawings. Depending on the embodiment, the length L1 may vary within the range that exposes the upper sidewalls of the active region 105. Depending on the embodiment, portions of the spacer layer 164 on both sidewalls of the sacrificial gate structure 170 may also be removed from their upper portions to a predetermined depth during this process. In exemplary embodiments, the active spacer layer 164F may be removed by an additional process to form the active spacer layer 164F in this manner.

[0067] Reference Figure 7E , the exposed portion of the sacrificial layer 120 may be removed from the side surface thereof.

[0068] The sacrificial layer 120 can be selectively etched relative to the channel structure 140 by, for example, a wet etching process to be removed from its side surface to a predetermined depth in the x-direction. Due to this side etching, the sacrificial layer 120 may have an inwardly concave side surface. However, the shape of the side surface of the sacrificial layer 120 is not limited to that shown in the drawings.

[0069] Reference Figure 7F , an inner spacer layer 130 may be formed in the region where the sacrificial layer 120 is removed.

[0070] The inner spacer layer 130 may be formed by filling the region where the sacrificial layer 120 is removed with an insulating material and removing the insulating material deposited outside the channel structure 140. The inner spacer layer 130 may be formed of the same material as the spacer layer 164, but the material of the inner spacer layer 130 is not limited thereto. For example, the inner spacer layer 130 may include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN.

[0071] When the active spacer layer 164F is formed to be higher than the upper sidewall of the active region 105, rather than Figure 7D When the active spacer layer 164F is formed to expose the upper sidewall of the active region 105 in the above-described process, the material of the inner spacer layer 130 may remain between the active spacer layer 164F and the active region 105 during this process. In this case, the growth of the source / drain region 150 may be hindered, and the volume of the source / drain region 150 may be reduced in subsequent processes, thereby degrading the electrical characteristics of the semiconductor device. However, according to example embodiments, since the active spacer layer 164F is formed to expose the upper sidewall of the active region 105, the material of the inner spacer layer 130 does not remain in the region where the source / drain region 150 is to be formed during this process. Therefore, the growth of the source / drain region 150 is not hindered.

[0072] Reference Figure 7G , source / drain regions 150 may be formed on opposite sides of the active region 105 adjacent to the sacrificial gate structure 170 .

[0073] The source / drain regions 150 may be formed by performing a selective epitaxial growth process using the active region 105 and the channel structure 140 as seeds. The source / drain regions 150 may be connected to the channel layers 141, 142, and 143 of the channel structure 140 through their side surfaces and may contact the inner spacer layer 130 between the channel layers 141, 142, and 143.

[0074] Since the source / drain regions 150 grow from the sidewalls of the active region 105 in the cross section in the y direction, each source / drain region 150 can be grown using a cut plane provided along a crystal plane during the epitaxial growth process. For example, the source / drain regions 150 can be grown to form a side surface inclined relative to the upper surface of the active region 105 while growing at a relatively high speed in a direction perpendicular to the top surface on the (100) plane (the top surface of the active region 105). Therefore, the source / drain regions 150 may include a region having a large width provided between the source / drain regions 150 and the first channel layer 141. The source / drain regions 150 may include impurities doped during the growth process or after the growth process.

[0075] Reference Figure 7H , an interlayer insulating layer 190 may be formed, and the sacrificial layer 120 and the sacrificial gate structure 170 may be removed.

[0076] The interlayer insulating layer 190 may be formed by forming an insulating layer to cover the sacrificial gate structure 170 and the source / drain regions 150 and performing a planarization process.

[0077] The sacrificial layer 120 and the sacrificial gate structure 170 may be selectively removed relative to the spacer layer 164, the interlayer insulating layer 190, and the channel structure 140. After the sacrificial gate structure 170 is removed to form the upper gap region UR, the sacrificial layer 120 exposed by the upper gap region UR may be removed to form the lower gap region LR. For example, when the sacrificial layer 120 includes silicon germanium (SiGe) and the channel structure 140 includes silicon (Si), the sacrificial layer 120 may be selectively removed by performing a wet etching process using peracetic acid as an etchant. During the removal process, the source / drain regions 150 may be protected by the interlayer insulating layer 190 and the inner spacer layer 130.

[0078] Reference Figure 7I , a gate dielectric layer 162 may be formed in the upper gap region UR and the lower gap region LR.

[0079] The gate dielectric layer 162 may be formed to conformally cover inner surfaces of the upper gap region UR and the lower gap region LR.

[0080] Reference Figure 7J , a gate electrode 165 may be formed to fill the upper gap region UR and the lower gap region LR, and a gate capping layer 166 may be formed on the gate electrode 165 .

[0081] After forming the gate electrode 165 to completely fill the upper gap region UR and the lower gap region LR, the gate electrode 165 may be removed from its upper portion to a predetermined depth in the upper gap region UR. A gate capping layer 166 may be formed in the region of the upper gap region UR where the gate electrode 165 was removed. Thus, a gate structure 160 including the gate dielectric layer 162, the gate electrode 165, the spacer layer 164, and the gate capping layer 166 may be formed.

[0082] Next, refer to Figure 2 , a contact plug 180 may be formed.

[0083] First, the interlayer insulating layer 190 may be patterned to form a contact hole, and a conductive material may be filled in the contact hole to form a contact plug 180. The contact hole may be formed by removing the interlayer insulating layer 190 on the opposite side adjacent to the gate structure 160 using an additional mask layer (e.g., a photoresist pattern). The bottom surface of the contact hole may be recessed into the source / drain region 150 or may have a curvature along the top surface of the source / drain region 150. In example embodiments, the shape and arrangement of the contact plug 180 may be variously changed.

[0084] As described above, the structure and shape of the source / drain regions can be controlled to provide a semiconductor device with improved electrical characteristics.

[0085] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: an active region extending in a first direction on the substrate, the active region having an upper surface and sidewalls; a plurality of channel layers vertically spaced apart from each other on the active area; a gate electrode extending in a second direction to cross the active region and surround the plurality of channel layers; as well as a source / drain region on the active region, on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from a sidewall of the active region, the source / drain region having a large width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layers, wherein the plurality of channel layers have the same width as each other in the second direction, and The large width is at a height between a lower surface of the lowermost channel layer and an upper surface of the active region.

2. The semiconductor device according to claim 1, wherein The plurality of channel layers include a first channel layer to a third channel layer sequentially stacked from the active region, and The first region is higher than an upper surface of the active region and lower than an upper surface of the first channel layer.

3. The semiconductor device according to claim 2, wherein The source / drain region has a first large width as the large width in the first region, and has a second large width smaller than the first large width in a second region having a height corresponding to a height at which the third channel layer is provided.

4. The semiconductor device according to claim 3, wherein The source / drain region includes a region between the first region and the second region having a third width smaller than the first and second major widths.

5. The semiconductor device according to claim 3, wherein The source / drain region has a fourth maximum width smaller than the first maximum width in a third region having a height corresponding to a height at which the second channel layer is disposed. The semiconductor device according to claim 1 , wherein: The source / drain region has a first surface extending from a sidewall of the active region and inclined relative to an upper surface of the substrate, and the first surface is a cut plane along a crystal plane of the active region.

7. The semiconductor device according to claim 6, wherein The source / drain region has a second surface connected to the first surface, and the second surface is a cut surface along a crystal plane.

8. The semiconductor device according to claim 7, wherein The source / drain region has the large width at a boundary between the first surface and the second surface.

9. The semiconductor device according to claim 1, further comprising: A spacer layer is formed on the sidewall of the active region to expose the upper surface and a portion of the side surface of the active region.

10. The semiconductor device according to claim 9, wherein The source / drain region contacts the spacer layer and covers the entire sidewall of the active region exposed by the spacer layer.

11. The semiconductor device according to claim 1 , further comprising: an inner spacer layer on an opposite side of the gate electrode in the first direction and on lower surfaces of the plurality of channel layers.

12. The semiconductor device according to claim 11, wherein The source / drain regions have a smaller local minimum width in the second direction in a region having a height corresponding to a height of each inner spacer layer than in a region having a height corresponding to a height of each of the plurality of channel layers.

13. The semiconductor device according to claim 1 , further comprising: Contact plugs are connected to the source / drain regions.

14. The semiconductor device according to claim 13, wherein The contact plug is recessed in the source / drain region to below a height of an uppermost channel layer among the plurality of channel layers.

15. The semiconductor device according to claim 1, wherein The active region is an active fin structure having an upper fin surface and side surfaces extending in the first direction.

16. A semiconductor device comprising: an active region extending in a first direction on the substrate; a first channel layer and a second channel layer sequentially disposed on the active region to be vertically spaced apart from each other; a gate electrode extending in a second direction to cross the active region on the substrate and surrounding the first channel layer and the second channel layer; as well as a source / drain region on at least one side of the gate electrode on the active region and arranged to contact the first channel layer and the second channel layer, wherein the source / drain region has a first maximum width in the second direction in a region adjacent to the first channel layer, and has a second maximum width in the second direction in a region adjacent to the second channel layer that is smaller than the first maximum width, wherein the first channel layer and the second channel layer have the same width as each other in the second direction, and The first maximum width is at a height between a lower surface of the first channel layer and an upper surface of the active region.

17. The semiconductor device according to claim 16, wherein The source / drain region has a side surface extending from the active region to the region having the first large width, and the side surface of the source / drain region is a cut plane along a crystal plane.

18. The semiconductor device according to claim 16, wherein The source / drain region has a third width smaller than the first and second large widths between a region having the first large width and a region having the second large width.

19. A semiconductor device comprising: an active region extending in a first direction on the substrate and having an upper surface and sidewalls; a gate electrode extending in a second direction to cross the active region on the substrate; a plurality of channel layers vertically spaced apart from one another on the active region in a region where the active region and the gate electrode cross each other; a spacer layer on the sidewall of the active region in the second direction and exposing the upper surface and a portion of the sidewall of the active region; as well as a source / drain region disposed on the active region at least on one side of the gate electrode and disposed in contact with the plurality of channel layers, wherein the source / drain region extends from a sidewall of the active region exposed through the spacer layer and is inclined relative to the upper surface of the substrate to have a width extending from both sides of the active region, and The source / drain region has a large width in the second direction in an area adjacent to the lowest channel layer among the multiple channel layers adjacent to the active region, and the large width is at a height between the lower surface of the lowermost channel layer and the upper surface of the active region.

20. The semiconductor device according to claim 19, wherein The source / drain regions have a curvature in a region adjacent to an overlying channel layer that corresponds to a height of the channel layer.

Images