Analog switch circuit

Abstract

The present invention discloses an analog switch circuit, comprising: a plurality of switch branches, each including an NMOS transistor, a PMOS transistor, and a negative voltage protection unit. The source and drain of the NMOS transistor are electrically connected to two ports, respectively; the drain and source of the PMOS transistor are electrically connected to two ports, respectively; the gate control signals of the NMOS transistor and the PMOS transistor are VCN and VCP, respectively; the NMOS transistor is a deep n-well MOS transistor, and its substrate voltage is NBULK; and the negative voltage protection unit is configured to configure the substrate voltage NBULK of the NMOS transistor to the smaller of the two port voltages. The analog switch circuit of the present invention can be used in negative voltage applications and can implement a negative voltage protection function. The circuit is simple, saving chip area. The circuit eliminates the body effect of the MOS transistor, reduces the on-resistance and on-impedance variation of the MOS transistor, improves the THD performance of the MOS transistor when it is on, and solves the problem of leakage in the closed switch branch. The entire switch circuit requires no additional static power consumption, achieving zero static power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an analog switch circuit. Background Art

[0002] In integrated circuit design, analog switches are often used to switch paths during signal transmission.

[0003] Ginseng Figure 1 As shown, the analog switch circuit in the prior art includes two channels, B0-A and B1-A, wherein the NMOS transistor NM1 and the PMOS transistor PM1 are connected in parallel on the B0-A channel, and the NMOS transistor NM2 and the PMOS transistor PM2 are connected in parallel on the B1-A channel. The gate control signals of NM1, PM1, NM2, and PM2 are VCN1, VCP1, VCN2, and VCP2 respectively. The timing diagram of the control signals VCN1, VCP1, VCN2, and VCP2 is shown in FIG. Figure 2 As shown, it is controlled by a high level (AVDD) and a low level (0). Meanwhile, the substrate voltages of NM1 and NM2 are AVSS, and the substrate voltages of PM1 and PM2 are AVDD.

[0004] In this analog switch circuit, the B0-A channel is turned on at moments t1-t1 and t4-t5 (NM1 and PM1 are on, NM1's substrate voltage NBULK1 is min(B0, A), and PM1's substrate voltage PBULK1 is at the B0 potential). The B1-A channel is turned on at moment t2-t3 (NM2 and PM2 are on, NM2's substrate voltage NBULK2 is min(B1, A), and PM2's substrate voltage PBULK2 is at the B1 potential). The B0-A channel and the B1-A channel are both turned off at moments t1-t2 and t3-t4 (NM1, PM1, NM2, and PM2 are off). NBULK1 and NBULK2 are connected to min(B0, A) / min(B1, A) regardless of whether they are on or off. PBULK1 / PBULK2 are connected to B0 / B1 when on and to AVDD when off. Among them, B0, B1, and A are all positive voltages. The analog switch circuit does not support applications where B0, B1, and A are negative voltages.

[0005] Ginseng Figure 3 As shown, another analog switch circuit in the prior art includes two channels, B0-A and B1-A, wherein the B0-A channel is connected in parallel with an NMOS transistor NM1 and a PMOS transistor PM1, and the B1-A channel is connected in parallel with an NMOS transistor NM2 and a PMOS transistor PM2. The gate control signals of NM1, PM1, NM2, and PM2 are VCN1, VCP1, VCN2, and VCP2, respectively. The timing diagram of the control signals VCN1, VCP1, VCN2, and VCP2 is shown in FIG. Figure 4As shown, VCP1 and VCP2 are controlled by a high level (AVDD) and a low level (0), and VCN1 and VCN2 are controlled by a high level (AVDD) and a low level (NV, where NV is a separately generated negative voltage). At the same time, the substrate voltage of PM1 and PM2 is AVDD, and NM1 and NM2 use a deep n-well (DNW) process to support negative voltage, and the substrate voltage is NV.

[0006] In this analog switch circuit, the B0-A channel is on at t1-t1 and t4-t5, the B1-A channel is on at t2-t3, and the dead zone is at t1-t2 and t3-t4. The principles and device operating states for B0-A and B1-A channel conduction and the dead zone are similar to those in the first solution and will not be further described here. This analog switch circuit supports applications where B0, B1, and A have negative voltages, and NV is the lowest negative voltage within the allowable operating range of B0, B1, and A.

[0007] Although the second solution can support negative voltage applications, it requires additional static power consumption, and the NMOS tube has a body effect, with large on-resistance and on-impedance variation, which affects the performance of the entire switching circuit.

[0008] Therefore, in order to solve the above technical problems, it is necessary to provide an analog switch circuit. Summary of the Invention

[0009] An object of the present invention is to provide an analog switch circuit to improve the performance of the switch circuit.

[0010] In order to achieve the above-mentioned purpose, the technical solution provided by one embodiment of the present invention is as follows:

[0011] An analog switch circuit, comprising:

[0012] A plurality of switch branches, each switch branch including an NMOS transistor, a PMOS transistor, and a negative voltage protection unit, wherein the source and drain of the NMOS transistor are electrically connected to two ports, respectively, the drain and source of the PMOS transistor are electrically connected to two ports, respectively, the gate control signals of the NMOS transistor and the PMOS transistor are VCN and VCP, respectively, the NMOS transistor is a deep n-well-based MOS transistor, the substrate voltage is NBULK, and the negative voltage protection unit is used to configure the substrate voltage NBULK of the NMOS transistor to the smaller of the two port voltages.

[0013] In one embodiment, the circuit includes:

[0014] a first switch branch, electrically connected between the first port and the third port, comprising a first NMOS transistor, a first PMOS transistor, and a first negative voltage protection unit, wherein the source and drain of the first NMOS transistor are electrically connected to the first port and the third port, respectively, the source and drain of the first PMOS transistor are electrically connected to the third port and the first port, respectively, gate control signals of the first NMOS transistor and the first PMOS transistor are VCN1 and VCP1, respectively, the first NMOS transistor is a deep n-well-based MOS transistor, and the substrate voltage is NBULK1, and the first negative voltage protection unit is configured to configure the substrate voltage NBULK1 of the first NMOS transistor to be the smaller of the first port voltage and the third port voltage;

[0015] The second switch branch is electrically connected between the second port and the third port, and includes a second NMOS transistor, a second PMOS transistor, and a second negative voltage protection unit. The source and drain of the second NMOS transistor are electrically connected to the second port and the third port, respectively, and the source and drain of the second PMOS transistor are electrically connected to the third port and the second port, respectively. The gate control signals of the second NMOS transistor and the second PMOS transistor are VCN2 and VCP2, respectively. The second NMOS transistor is a deep n-well-based MOS transistor with a substrate voltage of NBULK2. The second negative voltage protection unit is used to configure the substrate voltage NBULK2 of the second NMOS transistor to be the smaller of the second port voltage and the third port voltage.

[0016] In one embodiment, the first protection unit includes a third NMOS transistor and a fourth NMOS transistor, wherein the gate of the third NMOS transistor is connected to the source of the first NMOS transistor, the drain of the third NMOS transistor is connected to the first port, the source of the third NMOS transistor and the source of the fourth NMOS transistor are both connected to a substrate voltage NBULK1, the gate of the fourth NMOS transistor is connected to the drain of the first NMOS transistor, the drain of the fourth NMOS transistor is connected to the third port, and the substrates of the third NMOS transistor and the fourth NMOS transistor are connected to the substrate of the first NMOS transistor;

[0017] The second protection unit includes a sixth NMOS transistor and a seventh NMOS transistor, wherein the gate of the sixth NMOS transistor is connected to the source of the second NMOS transistor, the drain of the sixth NMOS transistor is connected to the second port, the source of the sixth NMOS transistor and the source of the seventh NMOS transistor are both connected to the substrate voltage NBULK2, the gate of the seventh NMOS transistor is connected to the drain of the second NMOS transistor, the drain of the seventh NMOS transistor is connected to the third port, and the substrate of the sixth NMOS transistor and the substrate of the seventh NMOS transistor are connected to the substrate of the second NMOS transistor.

[0018] In one embodiment, the first protection unit further includes a fifth NMOS transistor, wherein the gate, drain, and substrate of the fifth NMOS transistor are connected to the substrate of the first NMOS transistor, and the source of the fifth NMOS transistor is connected to the gate of the third NMOS transistor;

[0019] The second protection unit further includes an eighth NMOS transistor, the gate, drain and substrate of the eighth NMOS transistor are connected to the substrate of the second NMOS transistor, and the source of the eighth NMOS transistor is connected to the gate of the sixth NMOS transistor.

[0020] In one embodiment, the circuit further includes:

[0021] A first substrate follower unit, configured to connect the substrate of the first PMOS transistor to the source of the first NMOS transistor when the first switch branch is turned on;

[0022] The second substrate follower unit is used to connect the substrate of the second PMOS transistor to the source of the second NMOS transistor when the second switch branch is turned on.

[0023] In one embodiment, the first substrate follower unit includes a third PMOS transistor and a fourth PMOS transistor, the drain of the third PMOS transistor is connected to the source of the first NMOS transistor, the drain of the third PMOS transistor is connected to the substrate of the first PMOS transistor, the substrate of the third PMOS transistor is connected to a power supply voltage, the drain of the fourth PMOS transistor is connected to the substrate of the first PMOS transistor, and the substrate and source of the fourth PMOS transistor are both connected to the power supply voltage AVDD;

[0024] The second substrate follower unit includes a fifth PMOS tube and a sixth PMOS tube, the drain of the fifth PMOS tube is connected to the source of the second NMOS tube, the drain of the fifth PMOS tube is connected to the substrate of the second PMOS tube, the substrate of the fifth PMOS tube is connected to the power supply voltage, the drain of the sixth PMOS tube is connected to the substrate of the second PMOS tube, and the substrate and source of the sixth PMOS tube are both connected to the power supply voltage AVDD.

[0025] In one embodiment, the gate control signal VCN1 of the first NMOS transistor is controlled by a high level AVDD and a low level NBULK1;

[0026] The gate control signal VCP1 of the first PMOS tube is controlled by the high level AVDD and the low level 0;

[0027] The gate control signal VCN2 of the second NMOS transistor is controlled by the high level AVDD and the low level NBULK2;

[0028] The gate control signal VCP2 of the second PMOS transistor is controlled by a high level AVDD and a low level 0.

[0029] In one embodiment, in the circuit:

[0030] At time t0-t1, VCN1 is at a high level AVDD, VCP1 is at a low level 0, VCN2 is at a low level NBULK2, VCP2 is at a high level AVDD, the first switch branch is turned on, and the second switch branch is turned off;

[0031] At time t1-t2, VCN1 gradually decreases from high level AVDD to low level NBULK1, VCP1 gradually increases from low level 0 to high level AVDD, VCN2 is low level NBULK2, VCP2 is high level AVDD, and the first switch branch and the second switch branch are both closed;

[0032] At time t2-t3, VCN1 is at low level NBULK1, VCP1 is at high level AVDD, VCN2 gradually increases from low level NBULK2 to high level AVDD and maintains, VCP2 gradually decreases from high level AVDD to low level 0 and maintains, the first switch branch is closed, and the second switch branch is turned on;

[0033] At time t3-t4, VCN1 is at low level NBULK1, VCP1 is at high level AVDD, VCN2 gradually decreases from high level AVDD to low level NBULK2 and maintains, VCP2 gradually increases from low level 0 to high level AVDD and maintains, and the first switch branch and the second switch branch are both closed;

[0034] At time t4-t5, VCN1 gradually increases from low level NBULK1 to high level AVDD and maintains it, VCP1 gradually decreases from high level AVDD to low level 0 and maintains it, VCN2 is low level NBULK2, VCP2 is high level AVDD, the first switch branch is turned on, and the second switch branch is turned off.

[0035] Compared with the prior art, the present invention has the following advantages:

[0036] The analog switch circuit of the present invention can be used in negative pressure and can realize negative pressure protection function, and the circuit is simple, saving chip area;

[0037] Eliminates the body effect of the MOS tube, reduces the on-resistance and on-impedance change of the MOS tube, improves the THD performance of the MOS tube when it is turned on, and solves the leakage problem of the closed switch branch;

[0038] The entire switching circuit does not require additional static power consumption and can achieve zero static power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 A schematic diagram of an analog switch circuit in the prior art;

[0041] Figure 2 This is a timing diagram of control signals of an analog switch circuit in the prior art;

[0042] Figure 3 is a schematic diagram of another analog switch circuit in the prior art;

[0043] Figure 4 is a control signal timing diagram of another analog switch circuit in the prior art;

[0044] Figure 5 is a schematic diagram of an analog switch circuit in a specific embodiment of the present invention;

[0045] Figure 6 FIG. 1 is a timing diagram of control signals of an analog switch circuit in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0046] The present invention will be described in detail below with reference to the various embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0047] The present invention discloses an analog switch circuit, comprising a plurality of switch branches, each of which comprises an NMOS transistor, a PMOS transistor, and a negative voltage protection unit. The source and drain of the NMOS transistor are electrically connected to two ports, respectively, the drain and source of the PMOS transistor are electrically connected to two ports, respectively, the gate control signals of the NMOS transistor and the PMOS transistor are VCN and VCP, respectively, the NMOS transistor is a deep n-well-based MOS transistor, the substrate voltage is NBULK, and the negative voltage protection unit is used to configure the substrate voltage NBULK of the NMOS transistor to be the smaller of the two port voltages.

[0048] Ginseng Figure 5 As shown, an analog switch circuit in a specific embodiment of the present invention includes:

[0049] a first switch branch (B0-A) electrically connected between the first port B0 and the third port A, comprising a first NMOS transistor NM1, a first PMOS transistor PM1, and a first negative voltage protection unit 11. The source and drain of the first NMOS transistor NM1 are electrically connected to the first port B0 and the third port A, respectively, and the source and drain of the first PMOS transistor PM1 are electrically connected to the third port A and the first port B0, respectively. Gate control signals of the first NMOS transistor NM1 and the first PMOS transistor PM1 are VCN1 and VCP1, respectively. The first NMOS transistor NM1 is a deep n-well-based MOS transistor with a substrate voltage NBULK1. The first negative voltage protection unit 11 is configured to configure the substrate voltage NBULK1 of the first NMOS transistor NM1 to the smaller of the first port voltage B0 and the third port A voltage, i.e., min(B0, A);

[0050] The second switch branch (B1-A) is electrically connected between the second port B1 and the third port A, and includes a second NMOS transistor NM2, a second PMOS transistor PM2, and a second negative voltage protection unit 12. The source and drain of the second NMOS transistor NM2 are electrically connected to the second port B1 and the third port A, respectively. The source and drain of the second PMOS transistor PM2 are electrically connected to the third port A and the second port B1, respectively. The gate control signals of the second NMOS transistor NM2 and the second PMOS transistor PM2 are VCN2 and VCP2, respectively. The second NMOS transistor NM2 is a deep n-well-based MOS transistor with a substrate voltage NBULK2. The second negative voltage protection unit 12 is used to configure the substrate voltage NBULK2 of the second NMOS transistor NM2 to the smaller of the second port voltage B1 and the third port voltage A, that is, min(B1, A).

[0051] Specifically, the first protection unit 11 includes a third NMOS transistor NM3 and a fourth NMOS transistor NM4, wherein the gate of the third NMOS transistor NM3 is connected to the source of the first NMOS transistor NM1, the drain of the third NMOS transistor NM3 is connected to the first port B0, the source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are both connected to the substrate voltage NBULK1, the gate of the fourth NMOS transistor NM4 is connected to the drain of the first NMOS transistor NM1, the drain of the fourth NMOS transistor NM4 is connected to the third port A, and the substrates of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are connected to the substrate of the first NMOS transistor NM1;

[0052] The second protection unit 12 includes a sixth NMOS transistor NM6 and a seventh NMOS transistor NM7, wherein the gate of the sixth NMOS transistor NM6 is connected to the source of the second NMOS transistor NM2, the drain of the sixth NMOS transistor NM6 is connected to the second port B1, the source of the sixth NMOS transistor NM6 and the source of the seventh NMOS transistor NM7 are both connected to the substrate voltage NBULK2, the gate of the seventh NMOS transistor NM7 is connected to the drain of the second NMOS transistor NM2, the drain of the seventh NMOS transistor NM7 is connected to the third port A, and the substrates of the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 are connected to the substrate of the second NMOS transistor NM2.

[0053] Furthermore, the first protection unit 11 further includes a fifth NMOS transistor NM5, the gate, drain and substrate of the fifth NMOS transistor NM5 are connected to the substrate of the first NMOS transistor NM1, and the source of the fifth NMOS transistor NM5 is connected to the gate of the third NMOS transistor NM3;

[0054] The second protection unit 12 further includes an eighth NMOS transistor NM8 , whose gate, drain and substrate are connected to the substrate of the second NMOS transistor NM2 , and whose source is connected to the gate of the sixth NMOS transistor NM6 .

[0055] The configuration of NM3, NM4, NM6, and NM7 in the negative voltage protection unit of this embodiment enables the voltages of NBULK1 and NBULK2 to be min(B0, A) and min(B1, A), respectively. This ensures that the potentials of NBULK1 and NBULK2 are lower than the source / drain voltages of NM1 and NM2, respectively, thus achieving negative voltage protection. Furthermore, the present invention requires no additional static power consumption, achieving zero static power consumption. The substrate-following source configuration of NM1 and NM2 eliminates the body effect of the NMOS transistors.

[0056] The settings of NM5 and NM8 in the negative pressure protection unit solve the problem of leakage of the closed switch branch under low temperature and fast process corners, especially when voltage B0 is close to voltage B1, reducing the leakage from the potential level of tens of μa to the level of na.

[0057] The switch circuit in this embodiment further includes:

[0058] A first substrate follower unit 21 is configured to connect the substrate of the first PMOS transistor PM1 to the source of the first NMOS transistor NM1 when the first switch branch (B0-A) is turned on;

[0059] The second substrate follower unit 22 is used to connect the substrate of the second PMOS transistor PM2 to the source of the second NMOS transistor NM2 when the second switch branch ( B1 -A) is turned on.

[0060] Specifically, the first substrate follower unit includes a third PMOS transistor PM3 and a fourth PMOS transistor PM4, the drain of the third PMOS transistor PM3 is connected to the source of the first NMOS transistor NM1, the drain of the third PMOS transistor PM3 is connected to the substrate of the first PMOS transistor PM1, the substrate of the third PMOS transistor PM3 is connected to the power supply voltage, the drain of the fourth PMOS transistor PM4 is connected to the substrate of the first PMOS tube PM1, and the substrate and source of the fourth PMOS transistor PM4 are both connected to the power supply voltage AVDD.

[0061] Among them, when the B0-A switch branch is closed, the gate of PM3 is connected to AVDD and the gate of PM4 is connected to 0; when the B0-A switch branch is turned on, the gate of PM3 is connected to 0 and the gate of PM4 is connected to AVDD; when the B0-A switch branch is in the dead zone, the gate of PM3 is connected to AVDD and the gate of PM4 is connected to 0.

[0062] The second substrate follower unit includes a fifth PMOS transistor PM5 and a sixth PMOS transistor PM6, the drain of the fifth PMOS transistor PM5 is connected to the source of the second NMOS transistor NM2, the drain of the fifth PMOS transistor PM5 is connected to the substrate of the second PMOS transistor PM2, the substrate of the fifth PMOS transistor PM5 is connected to the power supply voltage, the drain of the sixth PMOS transistor PM6 is connected to the substrate of the second PMOS transistor PM2, and the substrate and source of the sixth PMOS transistor PM6 are both connected to the power supply voltage AVDD.

[0063] Among them, when the B1-A switch branch is closed, the gate of PM5 is connected to AVDD and the gate of PM6 is connected to 0; when the B1-A switch branch is turned on, the gate of PM5 is connected to 0 and the gate of PM6 is connected to AVDD; when the B1-A switch branch is in the dead zone, the gate of PM5 is connected to AVDD and the gate of PM6 is connected to 0.

[0064] In this embodiment, when the B0-A or B1-A switch branch is turned on, PBULK1 or PBULK2 is connected to the source through PM3 or PM5; when the B0-A or B1-A switch branch is turned off, PBULK1 or PBULK2 is connected to the power supply voltage AVDD through PM4 or PM6. The substrate of the PMOS follows the source, eliminating the body effect of the PMOS tube.

[0065] Since the body effect of NMOS and PMOS is eliminated in the analog switch circuit, the on-resistance of the MOS tube per unit area can be greatly improved (smaller on-resistance); at the same time, the change of on-resistance caused by changes in B0, B1, A and AVDD is also improved (smaller on-resistance change), thereby improving the THD performance of the MOS tube when it is turned on.

[0066] Combine Figure 6As shown, this embodiment includes four control signals, namely VCN1, VCP1, VCN2 and VCP2, where:

[0067] The gate control signal VCN1 of the first NMOS transistor NM1 is controlled by the high level AVDD and the low level NBULK1;

[0068] The gate control signal VCP1 of the first PMOS transistor PM1 is controlled by the high level AVDD and the low level 0;

[0069] The gate control signal VCN2 of the second NMOS transistor NM2 is controlled by the high level AVDD and the low level NBULK2;

[0070] The gate control signal VCP2 of the second PMOS transistor PM2 is controlled by the high level AVDD and the low level 0.

[0071] The operating modes of the first switch branch (B0-A) and the second switch branch (B1-A) are as follows:

[0072] At time t0-t1, VCN1 is at a high level AVDD, VCP1 is at a low level 0, VCN2 is at a low level NBULK2, VCP2 is at a high level AVDD, the first switch branch (B0-A) is turned on (i.e., NM1 and PM1 are turned on), and the second switch branch (B1-A) is turned off (i.e., NM2 and PM2 are not turned on);

[0073] At time t1-t2, VCN1 gradually decreases from high level AVDD to low level NBULK1, VCP1 gradually increases from low level 0 to high level AVDD, VCN2 is low level NBULK2, VCP2 is high level AVDD, and the first switch branch (B0-A) and the second switch branch (B1-A) are both closed (i.e., NM1, PM1, NM2, and PM2 are all off);

[0074] At time t2-t3, VCN1 is at low level NBULK1, VCP1 is at high level AVDD, VCN2 gradually increases from low level NBULK2 to high level AVDD and maintains it, VCP2 gradually decreases from high level AVDD to low level 0 and maintains it, the first switch branch (B0-A) is closed (i.e., NM1 and PM1 are not conducting), and the second switch branch (B1-A) is turned on (i.e., NM2 and PM2 are conducting);

[0075] At time t3-t4, VCN1 is at a low level NBULK1, VCP1 is at a high level AVDD, VCN2 gradually decreases from a high level AVDD to a low level NBULK2 and maintains it, VCP2 gradually increases from a low level 0 to a high level AVDD and maintains it, and the first switch branch (B0-A) and the second switch branch (B1-A) are both turned off (i.e., NM1, PM1, NM2, and PM2 are all off);

[0076] At time t4-t5, VCN1 gradually increases from low level NBULK1 to high level AVDD and maintains it, VCP1 gradually decreases from high level AVDD to low level 0 and maintains it, VCN2 is low level NBULK2, VCP2 is high level AVDD, the first switch branch (B0-A) is turned on (i.e., NM1 and PM1 are turned on), and the second switch branch (B1-A) is turned off (i.e., NM2 and PM2 are not turned on).

[0077] In this embodiment, the low level of the control signals VCN1 and VCN2 is provided by NBULK1 or NBULK2 instead of the traditional fixed level, which ensures that the channel can be completely shut down when it is disconnected again.

[0078] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0079] The analog switch circuit of the present invention can be used in negative pressure and can realize negative pressure protection function, and the circuit is simple, saving chip area;

[0080] Eliminates the body effect of the MOS tube, reduces the on-resistance and on-impedance change of the MOS tube, improves the THD performance of the MOS tube when it is turned on, and solves the leakage problem of the closed switch branch;

[0081] The entire switching circuit does not require additional static power consumption and can achieve zero static power consumption.

[0082] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0083] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. An analog switch circuit, characterized in that: The circuit comprises: a plurality of switch branches, each switch branch including an NMOS transistor, a PMOS transistor, and a negative voltage protection unit, wherein the source and drain of the NMOS transistor are electrically connected to two ports, respectively, the drain and source of the PMOS transistor are electrically connected to two ports, respectively, the gate control signals of the NMOS transistor and the PMOS transistor are VCN and VCP, respectively, the NMOS transistor is a deep n-well-based MOS transistor, and the substrate voltage is NBULK. The negative voltage protection unit is configured to configure the substrate voltage NBULK of the NMOS transistor to be the smaller of the two port voltages; a first switch branch, electrically connected between the first port and the third port, comprising a first NMOS transistor, a first PMOS transistor, and a first negative voltage protection unit, wherein the source and drain of the first NMOS transistor are electrically connected to the first port and the third port, respectively, the source and drain of the first PMOS transistor are electrically connected to the third port and the first port, respectively, gate control signals of the first NMOS transistor and the first PMOS transistor are VCN1 and VCP1, respectively, the first NMOS transistor is a deep n-well-based MOS transistor, and the substrate voltage is NBULK1, and the first negative voltage protection unit is configured to configure the substrate voltage NBULK1 of the first NMOS transistor to be the smaller of the first port voltage and the third port voltage; a second switch branch, electrically connected between the second port and the third port, comprising a second NMOS transistor, a second PMOS transistor, and a second negative voltage protection unit, wherein the source and drain of the second NMOS transistor are electrically connected to the second port and the third port, respectively, and the source and drain of the second PMOS transistor are electrically connected to the third port and the second port, respectively; gate control signals of the second NMOS transistor and the second PMOS transistor are VCN2 and VCP2, respectively; the second NMOS transistor is a deep n-well-based MOS transistor, and has a substrate voltage of NBULK2; the second negative voltage protection unit is configured to configure the substrate voltage NBULK2 of the second NMOS transistor to be the smaller of the second port voltage and the third port voltage; The first negative voltage protection unit includes a third NMOS transistor and a fourth NMOS transistor, wherein the gate of the third NMOS transistor is connected to the source of the first NMOS transistor, the drain of the third NMOS transistor is connected to the first port, the source of the third NMOS transistor and the source of the fourth NMOS transistor are both connected to the substrate voltage NBULK1, the gate of the fourth NMOS transistor is connected to the drain of the first NMOS transistor, the drain of the fourth NMOS transistor is connected to the third port, and the substrates of the third NMOS transistor and the fourth NMOS transistor are connected to the substrate of the first NMOS transistor; The second negative voltage protection unit includes a sixth NMOS transistor and a seventh NMOS transistor, wherein the gate of the sixth NMOS transistor is connected to the source of the second NMOS transistor, the drain of the sixth NMOS transistor is connected to the second port, the source of the sixth NMOS transistor and the source of the seventh NMOS transistor are both connected to the substrate voltage NBULK2, the gate of the seventh NMOS transistor is connected to the drain of the second NMOS transistor, the drain of the seventh NMOS transistor is connected to the third port, and the substrates of the sixth NMOS transistor and the seventh NMOS transistor are connected to the substrate of the second NMOS transistor; The gate control signal VCN1 of the first NMOS transistor is controlled by the high level AVDD and the low level NBULK1; The gate control signal VCP1 of the first PMOS tube is controlled by the high level AVDD and the low level 0; The gate control signal VCN2 of the second NMOS transistor is controlled by the high level AVDD and the low level NBULK2; The gate control signal VCP2 of the second PMOS transistor is controlled by a high level AVDD and a low level 0.

2. The analog switch circuit according to claim 1, wherein: The first negative voltage protection unit further includes a fifth NMOS transistor, wherein the gate, drain and substrate of the fifth NMOS transistor are connected to the substrate of the first NMOS transistor, and the source of the fifth NMOS transistor is connected to the gate of the third NMOS transistor; The second negative voltage protection unit further includes an eighth NMOS transistor, the gate, drain and substrate of the eighth NMOS transistor are connected to the substrate of the second NMOS transistor, and the source of the eighth NMOS transistor is connected to the gate of the sixth NMOS transistor.

3. The analog switch circuit according to claim 1, wherein: The circuit further comprises: A first substrate follower unit, configured to connect the substrate of the first PMOS transistor to the source of the first NMOS transistor when the first switch branch is turned on; The second substrate follower unit is used to connect the substrate of the second PMOS transistor to the source of the second NMOS transistor when the second switch branch is turned on.

4. The analog switch circuit according to claim 3, wherein: The first substrate follower unit includes a third PMOS transistor and a fourth PMOS transistor, the drain of the third PMOS transistor is connected to the source of the first NMOS transistor, the drain of the third PMOS transistor is connected to the substrate of the first PMOS transistor, the substrate of the third PMOS transistor is connected to a power supply voltage, the drain of the fourth PMOS transistor is connected to the substrate of the first PMOS transistor, and the substrate and source of the fourth PMOS transistor are both connected to the power supply voltage AVDD; The second substrate follower unit includes a fifth PMOS tube and a sixth PMOS tube, the drain of the fifth PMOS tube is connected to the source of the second NMOS tube, the drain of the fifth PMOS tube is connected to the substrate of the second PMOS tube, the substrate of the fifth PMOS tube is connected to the power supply voltage, the drain of the sixth PMOS tube is connected to the substrate of the second PMOS tube, and the substrate and source of the sixth PMOS tube are both connected to the power supply voltage AVDD.

5. The analog switch circuit according to claim 1, wherein: In the circuit: At time t0-t1, VCN1 is at a high level AVDD, VCP1 is at a low level 0, VCN2 is at a low level NBULK2, VCP2 is at a high level AVDD, the first switch branch is turned on, and the second switch branch is turned off; At time t1-t2, VCN1 gradually decreases from high level AVDD to low level NBULK1, VCP1 gradually increases from low level 0 to high level AVDD, VCN2 is low level NBULK2, VCP2 is high level AVDD, and the first switch branch and the second switch branch are both closed; At time t2-t3, VCN1 is at low level NBULK1, VCP1 is at high level AVDD, VCN2 gradually increases from low level NBULK2 to high level AVDD and maintains, VCP2 gradually decreases from high level AVDD to low level 0 and maintains, the first switch branch is closed, and the second switch branch is turned on; At time t3-t4, VCN1 is at low level NBULK1, VCP1 is at high level AVDD, VCN2 gradually decreases from high level AVDD to low level NBULK2 and maintains, VCP2 gradually increases from low level 0 to high level AVDD and maintains, and the first switch branch and the second switch branch are both closed; At time t4-t5, VCN1 gradually increases from low level NBULK1 to high level AVDD and maintains it, VCP1 gradually decreases from high level AVDD to low level 0 and maintains it, VCN2 is low level NBULK2, VCP2 is high level AVDD, the first switch branch is turned on, and the second switch branch is turned off.

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