Non-volatile memory bank with embedded inline arithmetic logic

Abstract

A non-volatile memory device is disclosed herein, which has processing logic embedded in a memory bank of the non-volatile memory device. For example, commands for controlling the processing logic can be disclosed to a host device, so that the host device can start the processing capabilities of the memory bank in conjunction with the memory operation. When reading or writing data identified by the memory operation, the processing capabilities can be indicated by a data command transmitted by the host device. The read data can be processed by the memory bank before being output to a data interface connected to the memory bank. Similarly, the write data received at the memory bank can be processed in conjunction with storing the write data in the non-volatile memory device. Therefore, the disclosed memory device can be combined with reading or writing data to a memory device of each memory bank including a two-terminal non-volatile memory to implement internal processing.

Description

Technical Field

[0001] The present invention generally relates to an electronic memory; as an example, the present invention describes an electronic memory including an arithmetic logic unit integrated with a memory bank of the electronic memory. Background Art

[0002] A recent innovation in the field of integrated circuit technology is two-terminal memory technology. For example, two-terminal memory technology is in contrast to gate-controlled transistors, in which the conductivity between the two terminals is regulated by a third terminal called a gate terminal. Two-terminal memory devices can be different from three-terminal devices in function and structure. For example, instead of having a third terminal adjacent to a set of conductive terminals, some two-terminal devices can be built between a pair of conductive contacts. Instead of operating by applying an excitation to the third terminal, the two-terminal memory device can be controlled by applying an excitation to one or both contacts in a pair of conductive contacts. The inventors of the present invention are also aware of various two-terminal memory technologies, such as phase change memory, magnetoresistive memory, conductive bridge memory, and other memories.

[0003] One type of two-terminal memory that is worth noting is resistive memory. Although many resistive memory technologies are in the development stage, the assignee of the present invention has demonstrated various technical concepts of resistive memory, and various technical concepts of resistive memory are in one or more verification stages to support or oppose related theories (multiple). Even so, resistive memory technology is still expected to gain a greater advantage over competing technologies in the semiconductor electronics industry.

[0004] As resistive memory technology models are tested and results are obtained, the results are speculatively extrapolated to memory devices where resistive memory replaces conventional memory. For example, the assignee of the present invention has conducted research related to software models of memory arrays that include resistive memory instead of complementary metal oxide semiconductor (CMOS) NAND or NOR memory. Software engineering suggests that two-terminal memory arrays can provide significant benefits to electronic devices, including reduced power consumption, higher memory density, advanced technology nodes, or improved performance, etc.

[0005] In view of this, the inventor has endeavored to discover an application in which a two-terminal memory can provide practical benefits to electronic devices. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the specification, a brief summary of the specification is provided below. This summary is not a comprehensive overview of the specification. It is neither intended to identify the main or key elements of the specification, nor to describe the scope of any specific embodiment of the specification or any scope of the claims. Its purpose is to provide some concepts of the specification in a simplified form as a prelude to a more detailed description provided by the present invention.

[0007] The present invention provides a non-volatile memory device having processing logic embedded in a memory bank of the non-volatile memory device. Commands for controlling the processing logic can be disclosed to a host device, enabling the host device to initiate processing capabilities of the memory bank in conjunction with a memory operation. When reading or writing data identified by a memory operation, the processing capabilities can be directed by a data command and transmitted by the host device. The read data can be processed by the memory bank before being output to a data interface (e.g., a data latch, a shift register, etc.) connected to the memory bank. Similarly, write data received by the memory bank can be processed in conjunction with storing the write data in the non-volatile memory device.

[0008] In one embodiment, the present invention provides a nonvolatile memory device. The nonvolatile memory device may include: a memory group of a nonvolatile storage memory; a sense amplifier configured to read data stored in a selected subset of the memory group; and a data buffer configured to receive input data through a data interface or output data through a data interface. In addition, the nonvolatile memory device may include a processing logic unit configured to execute a data command in conjunction with a memory group that performs a memory operation related to obtaining read data from a nonvolatile storage memory or storing write data in a nonvolatile storage memory. In addition, the processing logic unit performs at least one of the following: before the data buffer supplies the processed data as output data to the data interface, operating the read data in conjunction with executing the data command to generate processed data; or after the write data is received from the data interface into the data buffer, operating the write data in conjunction with executing the data command to generate processed data.

[0009] In other embodiments, the present invention provides a method for operating a memory device. The method may include: receiving write data and a write address at a data buffer of a memory bank of a non-volatile memory; and receiving a data command related to the write data. In addition, the method may include processing the write data according to the data command and generating processed data in response to successful execution of the data command. In addition, the method may include writing the processed data to the write address of the memory bank in response to successful execution of the data command.

[0010] In one or more additional embodiments, the present invention provides a method of operating a memory device. The method may include: receiving a read command and a read address at a memory bank of a non-volatile memory; and receiving a data command related to data stored at the read address. In addition, the method may include transmitting the read data from the read address to a data buffer. In addition, the method may include generating processed data in response to successful execution of the data command and outputting the processed data to a host device in response to successful execution of the data command.

[0011] The following description and the accompanying drawings set forth certain illustrative aspects of the specification. However, these aspects represent only some of the various ways in which the principles of the specification can be employed. Other advantages and novel features of the present specification will become apparent from the following detailed description of the present specification when considered in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Various aspects or features of the present invention are described with reference to the accompanying drawings, wherein similar reference numerals are used to indicate similar elements in all drawings. In this specification, many specific details are set forth to provide a thorough understanding of the present invention. However, it should be understood that certain aspects of the present invention may be implemented without these specific details, or using other methods, components, materials, etc. In other cases, well-known structures and devices are shown in block diagram form to facilitate description of the present invention.

[0013] Figure 1 depicts a block diagram of an exemplary non-volatile memory group with inline processing logic in accordance with an embodiment of the present invention;

[0014] Figure 2 shows a block diagram of an exemplary non-volatile memory chip according to further embodiments;

[0015] Figure 3 depicts a block diagram of an exemplary memory bank including inline processing logic according to alternative or additional embodiments;

[0016] Figure 4 depicts a block diagram of an exemplary inline processing logic unit according to other embodiments;

[0017] Figure 5 A flowchart illustrating an exemplary method of manufacturing a memory bank including inline processing logic in embodiment(s);

[0018] Figure 6 A flowchart depicting an exemplary method of writing data to a memory bank using inline processing in a further embodiment;

[0019] Figure 7A flow chart illustrating an exemplary method for processing data and writing the processed data to a memory bank in a further embodiment;

[0020] Figure 8 A flowchart depicting an exemplary method of reading data from a memory bank using inline processing in other embodiments;

[0021] Fig. 9 A flow chart depicting an exemplary method for reading data from a memory bank and rewriting processed data in an alternative embodiment;

[0022] Fig.10 A flowchart depicting an exemplary method of processing data and outputting the processed data in response to a read command in embodiment(s);

[0023] Fig.11 A flowchart depicting an exemplary method of processing stored data and rewriting processed data in alternative embodiment(s);

[0024] Fig.12 A flowchart showing an exemplary method for reading data satisfying a query criterion in an embodiment is shown;

[0025] Fig.13 A flow chart depicting an exemplary method for writing data that successfully satisfies query criteria in a further embodiment;

[0026] Fig.14 A block diagram showing an exemplary memory architecture with inline processing logic according to a further embodiment of the present invention;

[0027] Fig.15 A block diagram of an exemplary computing environment is depicted in which the various disclosed embodiments may be implemented. DETAILED DESCRIPTION

[0028] The present invention relates to a non-volatile memory bank including inline arithmetic logic. The inline arithmetic logic can facilitate on-chip processing of data read from a memory bank of a memory chip before the data is moved off the chip. Similarly, the inline arithmetic logic can facilitate on-chip processing of write data after the write data is moved on-chip and then the processed data is written to the memory bank. In addition, control of the on-chip processing can be exposed to devices external to the memory chip, such as a controller, a host, etc.

[0029] In the context, a memory group refers to one or more arrays of non-volatile memory cells that are accessible via column and row addressing dedicated to the non-volatile memory cell array(s). Using different language, non-volatile memory cells of a first memory group may be addressed and accessed separately from non-volatile memory cells of a second memory group having separate dedicated column and row addressing. A memory device including a plurality of memory groups may have a common data path, and the memory groups may have respective data branches on the common data path to transfer data between the respective memory groups and the common data path. The common data path may be linked to an input / output interface for the memory device to transfer data between the memory device and an external device such as a host, a controller, etc.

[0030] Now referring to the accompanying drawings, Figure 1 A block diagram of an exemplary non-volatile memory device 100 including a memory group 102 with inline processing logic is shown. The memory group 102 may include one or more non-volatile memory cell arrays for data storage. In one embodiment, the non-volatile memory cell may be a two-terminal memory. Examples of suitable two-terminal memories may include resistive switching memory, phase change memory, magnetoresistive memory, conductive bridge memory, etc., or a suitable combination of the foregoing memories. In at least one embodiment, the memory group 102 includes one or more non-volatile two-terminal resistive switching memory cell arrays.

[0031] The non-volatile memory device 100 may further include a set of sense amplifiers 110 for measuring signals representing data stored in a selected subset of the non-volatile memory cells of the memory bank 102. The sense amplifiers 110 may be configured to sense the data stored in the ... Fig. 9) to identify a selected subset of memory cells to select a block of memory cells, a page or multiple pages of memory cells, a portion of a page (or a portion of multiple pages). Once selected, the subset of memory cells can be connected to a sense amplifier 110, which is configured to read data from the subset of connected memory cells. The data read from the connected memory cells is written to the data latch 106. The data latch 106 is typically a volatile memory structure for data storage (e.g., an SRAM circuit, an analog or digital switch, a two-terminal volatile switch, a flip-flop, a transistor, a latch, etc.), but the data latch 106 is not so limited and can be a non-volatile memory in some embodiments (e.g., a two-terminal non-volatile memory such as a two-terminal resistive switch memory cell, etc.). According to a conventional read / write mechanism in some embodiments, the data stored in the data latch 106 can be output from the non-volatile memory device 100 via the array interface 104, or can be written to the memory group 102. In further embodiments, data retrieved from memory bank 102 and stored in data latches 106 may be processed by processing logic 108 before being output from non-volatile memory device 100. Similarly, data received through array interface 104 may be processed by processing logic 108 before being written to memory bank 102, unlike conventional read / write mechanisms.

[0032] In some embodiments, the array interface 104 may be a shift register. When the array interface 104 is implemented as a shift register, the array interface 104 moves data from an external device (e.g., a host, a controller, a remote computing or processing device, etc.) to the data latches 106 through the array interface 104. After the data stored at the data latches 106 are moved to the non-volatile memory device 100 through the array interface 104, and before the data is written to the memory bank 102, the data may be processed by the processing logic 108. The processing of the data after the data is moved to the data latches 106 is opposite to a memory device that only writes the data moved to the data latches 106 as is to the memory bank 102 (e.g., without processing). When the array interface 104 is implemented as a shift register, the array interface 104 may further move the data read from the memory bank 102 to the external device. Data read from memory bank 102 may be processed by processing logic 108 before being moved to array interface 104, in contrast to memory devices that simply move the data stored at data latches 106 out as is (e.g., without processing). In at least one embodiment, data read from memory bank 102 and stored in data latches 106 may be processed by processing logic 108 and may be written back to memory bank 102 (e.g., back to the address(es) from which the data was read, or back to a second (different) address(es) from which the data was read), or written back to memory bank 102 and moved out through array interface 104.

[0033] In some embodiments, processing logic 108 may include hardware logic (e.g., shift registers, logic gates, transistors, switches, latches, other circuits or electronic hardware suitable for performing logical or mathematical operations on data, etc.), in other embodiments processing logic 108 may include software logic (e.g., instructions, data routines or processes for operating data stored in volatile or non-volatile memory, etc.), or in yet other embodiments processing logic 108 may include a combination of hardware logic and software logic. In additional embodiments, control of processing logic 108 may be output to an external device (e.g., a host device or computer). Commands and related command data (e.g., command arguments, command filters, command algorithms, command parameters, values ​​of commands or command arguments (multiple) / filters (multiple) / algorithms (multiple) / parameters (multiple)), etc.) may be transmitted to a non-volatile memory device via an external device to cause processing logic 108 to perform logical or mathematical operations on data consistent with the commands and command data. The array interface 104 may additionally include a command interface for transmitting commands and associated command data from an external device to the processing logic 108, and for transmitting command confirmation, command status (e.g., success, failure, busy, not busy, etc.) from the processing logic 108 to the external device. Thus, the non-volatile memory device 100 may be used to offload some of the processing power of an external device for data that has been moved into the non-volatile memory device 100, or for data that is read from the memory bank 102 before the read data is moved out of the non-volatile memory device 100.

[0034] Figure 2A block diagram of a nonvolatile memory chip 200 according to one or more additional embodiments of the present invention is shown. In one embodiment, the nonvolatile memory chip 200 can be implemented on a single integrated circuit chip. The nonvolatile memory chip 200 may include a nonvolatile memory group 230 for data storage. The multiplexer 216 is provided and configured to selectively connect / disconnect a subset of memory cells of the nonvolatile memory group 230 to perform memory operations (e.g., read, write, overwrite, erase, etc.) on the subset of memory cells. The sense amplifier 214 is provided to interpret the signal obtained from the nonvolatile memory group 230 in conjunction with the read operation and interpret the signal as storage data. In at least one embodiment, the nonvolatile memory chip 200 does not have the multiplexer 216, and in such an embodiment, the sense amplifier 214 (and the processing logic 220, see below) can be directly connected to the nonvolatile memory group 230. In other embodiments, the multiplexer 216 may be any conventional multiplexer for selecting a subset of bit lines on a word line of the non-volatile memory group 230 (e.g., a portion of the bit lines on a word line, all the bit lines on a word line, bit lines less than all the bit lines on a word line, etc.). A data buffer 212 is provided, which may optionally include a plurality of buffer subsets (illustrated by individual squares within the rectangular block of the data buffer 212) to store independent data groups (e.g., independent data pages, independent data page groups, data blocks (multiple), or other suitable buffer sizes) for writing to the non-volatile memory group 230, output from the non-volatile memory chip 200, or processing by the processing logic 220. The array interface 202 is provided to facilitate receiving data from an external device (not shown), outputting data to an external device, and transmitting commands (e.g., memory operation commands, logic operation commands), command data (e.g., variables, filters, algorithms, parameters, etc.), and command confirmations between the external device and the processing logic 220.

[0035] The inline data path is shown with a two-dimensional (thick) arrow, and the inline command path is shown with a thin arrow. The inline data path includes a write path for writing data to the non-volatile memory group 230 and a read path for reading data from the non-volatile memory group 230. The inline command path includes a command path for transmitting commands or command variables to the processing logic 220, and a confirmation path for transmitting command status or confirmation from the non-volatile memory chip 200. It should be noted that different data paths and command paths are not necessarily implemented by separate data communication hardware. In some cases, all or part of all data paths and read paths can be transmitted through a common electrical hardware group (e.g., metal wires or other conductive wires), or in other cases can be transmitted through dedicated electrical hardware.

[0036] The input data 240 provided by the external device in conjunction with the write operation can be transmitted through the array interface 202 (e.g., moved to the non-volatile memory chip 200, where the array interface 202 is a shift register). The input data 240 uses the inline data path to be stored in the data buffer 212 (or a subset of the data buffer 212, for example, one or more of the buffer subsets). In some embodiments, the data buffer 212 can be a data latch, or in other embodiments, the data buffer 212 is a volatile memory (e.g., SRAM, etc.), or in other embodiments, the data buffer 212 is a non-volatile memory (e.g., flash memory, two-terminal resistive switch memory, magnetic memory, etc.). The logic command (s) or command variable (s) for performing a logic or mathematical operation on the input data 240 is transmitted from the external device to the processing logic 220 through the array interface 202 via the inline command path. The processing logic 220 accesses the input data 240 from the data buffer 212, and processes the input data 240 according to the command (s) or command variable (s), generating processed input data 242. The processed input data 242 may be provided to the multiplexer 216 for writing to the non-volatile memory bank 230. In one embodiment, the processed input data 242 may alternatively or additionally be written to the data buffer 212 for output via the array interface 202 in response to the logic command(s). It should be noted that the write command used to write the processed input data 242 to the non-volatile memory bank 230 is independent of (and optionally in addition to) the logic command(s) employed by the processing logic 220 to perform logical or mathematical operations on the input data 240, however the write command may also be transmitted in conjunction with the logic command via the array interface 202 (and optionally, the inline command path).

[0037] In the context of a read memory operation, the read command specifies or indicates (in the case of virtual addressing) a read address(es) in the non-volatile memory bank 230. The multiplexer 216 takes a read signal 250 from the read address(es) and supplies the read signal 250 to the sense amplifier(s) 214. The sense amplifier(s) 214 generates output data 252 from the read signal 250 representing data stored at the address(es) of the non-volatile memory bank 230, which can be manipulated by the processing logic 220 according to the logic command(s). The processing logic 220 generates processed output data 254 in response to executing the logic command(s) on the output data 252, and transmits the processed output data 254 to the data buffer 212 (or one or more buffer subsets thereof). The processed output data 254 can be provided to an external device that issued the read memory operation and the logic command through the array interface 202 in response to the read memory operation and the logic command. In an alternative or additional embodiment, if the logic command includes a rewrite command and a rewrite address(es), the processed output data 254 may be rewritten to the rewrite address(es) of the non-volatile memory bank 230. The rewrite address(es) may be the read address(es) or a second (different) address(es), or a combination thereof. It should be noted that the read command for reading the output data 252 from the non-volatile memory bank 230 is independent of (and optionally in addition to) the logic command(s) employed by the processing logic 220 to perform the logic or mathematical operations on the output data 252, however the read command may also be transmitted in conjunction with the logic command(s) through the array interface 202 (and optionally, the inline command path).

[0038] In further embodiments, the read or write command may employ complex variables that both provide data (e.g., write data) and commands, and retrieve data (e.g., read data) from the non-volatile memory group 230 to implement a logic command. For a complex write command, the command may include write data, a logic command (and optional variable(s)), a read address of the non-volatile memory group 230, and a write address. The processing logic 220 may retrieve the data stored at the read address (using a multiplexer 216 and a sense amplifier(s) 214), and operate on the read data and the write data as required by the logic command (optionally including the command variable(s)), and then generate processed input data 242. The processed input data 242 may then be written to the write address of the non-volatile memory group 230. For a complex read command, the command may include command data, a logic command (and optional variable(s)), a read address of the non-volatile memory group 230, and a logic command. The data stored at the read address may be retrieved through the multiplexer 216 and the sense amplifier (s) 214, and the retrieved data may be processed in conjunction with the command data to produce processed output data 254. The processed output data 254 may then be output through the array interface 202. In another embodiment, the read command may include a query command and a query criterion. The processing logic 220 may execute the query criterion, and in response to satisfying the query criterion, the data located at the read address may be retrieved from the non-volatile memory group 230. In one embodiment, the data located at the read address may be processed according to the logic command in conjunction with executing the query criterion. In a further embodiment, the command data may be provided together with the read command and the query command, and processing the read data according to the logic command may incorporate the command data into producing the processed output data 254.

[0039] The logic command may generally include a type of operation performed on the output data 252 or the input data 240 by the processing logic 220. The logic command may optionally include an address (e.g., source address(es)) to read data from the non-volatile memory group 230, an address (e.g., destination address(es)) to write data to the non-volatile memory group 230, or a combination thereof (as an example, a source address(es) for retrieving data and a destination address(es) for storing processed data). In one embodiment, specific examples of such operations may include an AND logic operation, an OR logic operation, an XOR logic operation, a NOR logic operation, or any other suitable logic operation, or a combination of such logic operations, without limitation. As another example, such operations may be suitable mathematical operations. As yet another example, the logic command may include a data filter, and may include a filter variable, and may specify a set of conditional responses. The data filter command may compare the source data (or processed data) with the filter variable, and perform one or more sets of conditional responses based on the result of the comparison. As a further illustrative example, a data filter command may compare source data (or processed data) to a filter variable, and in response to data matching the filter variable, output the data (or rewrite the data to the non-volatile memory group 230), and in response to data not matching the filter variable, output a filter command error. Other suitable types of data operations known in the art or made known to those skilled in the art by the context disclosed herein may be used for such operations.

[0040] Figure 2 The non-volatile memory chip 200 and other embodiments disclosed herein can achieve various advantages. For example, processing power can be offloaded from the host CPU, facilitating distributed computing between the non-volatile memory chip 200 and the host device. In some embodiments (e.g., where the data being processed is larger than the command, command data, or variable(s) sent through the array interface 202 to implement the command), the distributed computing can reduce the amount of communication to / from the non-volatile memory chip 200 via the array interface 202. In addition, in such embodiments, power consumption for transmitting data through the array interface 202, as well as the need for a high-speed or high-throughput interface between the host and the memory device, can be reduced.

[0041] Figure 3A block diagram of an exemplary memory bank 300 with inline processing logic according to an alternative or additional embodiment of the present invention is depicted. The memory bank 300 may include a cell array 302 having a plurality of columns 304 and a plurality of rows 306 of non-volatile resistive switch memory cells. A sense amplifier 310 is provided for reading data from a target page / cell 308 of the cell array 302, and a data latch 312 for latching data received from an external device via a data path 314 or for latching data read from the cell array 302 via the sense amplifier 310. In some embodiments, the target page / cell 308 may include all cells on a word line (e.g., selecting an entire page of cells), or in other embodiments may include cells less than all cells on a word line (e.g., selecting cells less than an entire page of cells). The data path 314 may be used to output data from or to an external device such as a host device or host computer (not shown). A command path (not shown) may be used to receive a memory command, a logic command (and command data, if applicable), or source / destination address(es) of the cell array 302 for implementation by the processing logic 320 .

[0042] Data received on the data path 314 may be written to the data latches 312. Host command information 322 received along with the data through the command path may include a write command, a logic command, and optionally command data (e.g., command variables / filters / algorithms / parameters, etc.) and a destination address for the write command. Processing logic 320 may process the latched data according to the logic command and command data (optionally), and implement the write command to store the processed data to the target page / cell 308 specified by the destination address. The results of the memory operation and the logic operation may be output through the command path as status output 324.

[0043] The read command may be accompanied by a logic command and optionally command data, as well as a source address of the read data. The sense amplifier 310 reads the data stored at the source address and transfers the read data to the data latch 312. The latched data is (optionally) processed according to the logic command and the command data to generate processed read data. The processed read data may be output via the data path 314 in response to the read command. In some embodiments, the processed read data may alternatively (or additionally) be rewritten to the cell array 302, or to the source address or to a different rewrite address. In response to a failure to read data from the source address, a read operation failure may be output as a status output 324 in response to the read command. In response to a failure of the logic command, a logic command failure may be output as a status output 324 in response to the read command. In one or more embodiments, the processing logic 320 may be substantially similar to the processing logic 108 or the processing logic 220. In further embodiments, the processing logic 320 may be substantially as described below. Figure 4 Description.

[0044] In one or more embodiments, the data path 314, the data latch 312, and the sense amplifier 310 can perform conventional memory operations (e.g., read operations, write operations, erase operations, overwrite operations, etc.). For example, this can be implemented by bypassing the processing logic 320. Therefore, in one embodiment, the data received on the data path 314 can be written to the memory cell (e.g., the target page / cell 308) of the cell array 302 corresponding to the received address without requiring the processing logic 320 to perform any processing on the received data. Similarly, in further embodiments, the data retrieved by the sense amplifier 310 in response to the read command can be output on the data path 314 without being processed at the processing logic 320. Therefore, in such embodiments, optionally bypassing the processing logic 320 can provide conventional memory operations. Although not specifically described, in some embodiments, other memory devices disclosed herein can incorporate a bypass of the processing or processing logic.

[0045] Figure 4 A block diagram of exemplary inline processing logic 400 for a memory bank of a memory device in one or more embodiments is depicted. The inline processing logic 400 may include a command input 402 and a data input / output 404. The command input 402 facilitates receiving a logic operation command, command data associated with the logic operation command, and a source address or a destination address of the logic operation command. The data input / output 404 serves as an interface for the inline processing logic 400 to receive data associated with the logic operation command and process the data according to the logic operation command.

[0046] In various embodiments, data processing may be implemented by non-configurable logic element 406 or configurable logic element 408, depending on the implementation. Non-configurable logic element 406 may include hard-coded logic structures (e.g., logic structures made to perform a logic / mathematical operation or a set of logic / mathematical operations), or may include instructions stored in ROM to implement logic / mathematical operation(s) coupled to processing hardware to implement instructions stored in ROM. Configurable logic element 408 may include programmable logic structures that can be programmed to implement logic / mathematical operation(s), such as programmable logic gates, programmable switches, programmable transistors, programmable flip-flops, or other suitable programmable logic elements, or combinations of the above components. Alternatively / additionally, configurable logic element 408 may include instructions stored in a rewritable memory to implement instructions on processing hardware. In one or more embodiments, a combination of non-configurable logic element 406 and configurable logic element 408 may be provided to implement logic / mathematical operations individually or in concert.

[0047] The inline processing logic 400 may further include a storage memory 410, which includes a status code 412 and an operation protocol 414. The status code 412 may include rules for submitting confirmations to memory operations or logic operations. For example, a first set of confirmations may be implemented for the success or failure of a memory operation; a second set of confirmations may be implemented for the success or failure of a logic operation. The operation protocol 414 may include a mapping between logic commands and related command data (e.g., variables, filters, algorithms, parameters, etc.) and the logic / mathematical operations referenced by the commands, as well as the use of command data for implementing the commands. In various embodiments, the status code 412 and the operation protocol 414 may be stored in a read-only memory or an erasable memory, depending on the implementation.

[0048] The above-mentioned figures have been described with respect to the interaction between multiple components of an electronic device, an interface, a memory device, or a memory architecture. It should be understood that in some appropriate alternative aspects of the present invention, such figures may include those components, devices, interfaces, architectures, etc., specified therein, some specified components / devices / interfaces / architectures, or additional components / devices / interfaces / architectures. Subcomponents may also be implemented as being connected to other subcomponents, rather than being included in a parent component. For example, multiple memory groups may be provided on separate memory chips rather than on a single chip, or, as an illustrative example, a status code 412 and an operating protocol 414 may be stored on separate memory media, rather than being included in the same memory medium. In addition, it should be noted that one or more disclosed processes may be combined into a single process that provides a summary function. The components of the disclosed device / architecture may also interact with one or more other components that are not specifically described herein but are known to those skilled in the art.

[0049] In view of the exemplary drawings described above, reference will be made to Figures 5 to 8 Flow charts are provided to better understand the processing methods that can be implemented according to the disclosed subject matter. Although for ease of explanation, Figures 5 to 8 The methods are shown and described as a series of blocks, but it should be understood and appreciated that the claimed subject matter is not limited by the order of the blocks, as some blocks may appear in a different order or appear simultaneously with other blocks depicted and described herein. In addition, not all of the blocks shown must be used to implement the methods described herein. In addition, it should be further understood that some or all of the methods disclosed in this specification can be stored on an article of manufacture to facilitate the transport and transfer of these methods to an electronic device. The term article of manufacture used is intended to include a computer program that can be accessed from any computer-readable device, a device in combination with a carrier, or a storage medium.

[0050] Figure 5 A flow chart of an example method 500 for manufacturing a memory device in one or more disclosed embodiments is shown. At 502, the method 500 may include forming a two-terminal memory cell array on an integrated circuit chip. At 504, the method 500 may optionally include forming a multiplexer, the multiplexer connected to the two-terminal memory cell array and configured to select a subset of memory cells for memory operations. In an alternative embodiment, the method 500 may manufacture a memory device without a multiplexer. At 506, the method 500 may include forming a sense amplifier, the sense amplifier connected to the multiplexer and connected to the two-terminal memory cell array through the multiplexer, and configured to read data stored in a selected subset of the two-terminal memory cells. In an alternative embodiment, the sense amplifier may be formed to be directly connected to the two-terminal memory cell array without an intervening multiplexer. At 508, the method 500 may include forming a data buffer, the data buffer being used for volatile storage of one or more pages of data. In one embodiment, the data buffer may store data less than one page of data, or may store data greater than one page of data. At 510, method 500 may include connecting a sense amplifier or a data buffer to a CMOS processing logic configured to perform a logic or mathematical operation on data stored in the data buffer or retrieved by the sense amplifier. At 512, method 500 may include forming a chip interface for sending and receiving data at a memory chip; at 514, method 500 may include forming a command interface on the memory chip, the command interface configured to receive an external memory command, and an external logic or mathematical command and output a status. In one embodiment, the status may include a memory operation status in addition to a logic / mathematical operation status.

[0051] Figure 6 A flow chart of an exemplary method 600 for operating a memory device according to one or more additional embodiments is depicted. At 602, the method 600 may include receiving write data and a write address at a data buffer of a memory bank of a non-volatile memory. At 604, the method 600 may include receiving a data command related to the write data, and at 606, the method 600 may include optionally receiving command data for implementing the data command. The command data may include command variables (e.g., values, operators, variables, etc.), command filters, command algorithms, command parameters, query criteria (or standards), data to be operated on (alone or together with read data), etc. or a suitable combination thereof. At 608, the method 600 may include processing the write data according to the command and the optional command data. At 610, a determination is made as to whether the logic command is successful. If successful, the method 600 may proceed to 612; if unsuccessful, the method 600 proceeds to 616 and outputs a processing failure of the logic command. At 612, the method 600 may include writing the processed write data at the write address of the memory bank. At 614, the method 600 may include outputting a successful processing and write status.

[0052] In one embodiment, method 600 may further include outputting a data error in response to unsuccessful execution of the data command and generating processed data. In other embodiments, method 600 may further include outputting a write error in response to a failure of the memory device to write the processed data to the write address of the memory bank. In a further embodiment, method 600 may include outputting a command success in response to successful execution of the data command and in response to writing the processed data to the write address of the memory bank. In alternative or additional embodiments, method 600 may include receiving a command variable in addition to the data command. For example, processing the write data according to the data command may further include incorporating the command variable.

[0053] Figure 7A flow chart of an exemplary method 700 for operating a memory device according to an alternative or additional embodiment of the present invention is depicted. At 702, the method 700 may include receiving write data, a read address, and a write address at an interface of a memory bank of a non-volatile memory. In one embodiment, the write data may be stored in a first section of a data buffer. At 704, the method 700 may include receiving a logic command related to the data, the read address, and the write address. The logic command may refer to a logic or mathematical operation that the memory device is programmed to recognize and that is configured to be implemented using processing hardware or software. At 706, the method 700 may include optionally receiving command data related to the logic command along with the logic command. The command data may include a logic / mathematical variable, a logic / mathematical filter, a logic / mathematical operator, a logic / mathematical algorithm, a logic / mathematical parameter, a query criterion (standard), data to be operated on, etc., or a suitable combination thereof. At 708, the method 700 may include acquiring the storage data from the read address of the memory bank to a second section of the data buffer, and at 710, the method 700 may include determining whether the read is successful. In response to a successful read, method 700 may proceed to 714. In response to an unsuccessful read, method 700 may proceed to 712 and may include outputting a read failure in response to the logic command.

[0054] At 714, method 700 may include processing read data from the second section of the data buffer and write data from the first section of the data buffer. Processing may be in accordance with the logic command and optionally incorporated into or as a function of the command data. At 716, a determination is made as to whether the processing was successful. In response to unsuccessful processing, method 700 may proceed to 718 and may include outputting a processing failure in response to the logic command. In response to successful processing, method 700 may proceed to 720 and write the processed data to the write address of the memory bank. At 722, method 700 may include outputting a processing success and a write status of the processed data.

[0055] Figure 8A flow chart of an exemplary method 800 for operating a memory device according to an additional embodiment of the present invention is shown. At 802, the method 800 may include receiving a read command and a read address at a command interface of a memory bank of a non-volatile memory. At 804, the method 800 may include receiving a logic command related to data stored at the read address. The logic command may refer to a logic or mathematical operation, the memory device is programmed to recognize the logic or mathematical operation, and the logic or mathematical operation is configured to be implemented using processing hardware or software. At 806, the method 800 may include optionally receiving command data related to the logic command together with the logic command. The command data may include a logic / mathematical variable, a logic / mathematical filter, a logic / mathematical operator, a logic / mathematical algorithm, a logic / mathematical parameter, a query criterion (standard), data to be operated, etc., or a suitable combination thereof. At 808, the method 800 may include transmitting the read data from the read address to a data buffer in response to the read command. At 810, it may be determined whether the transmission of the read data from the read address to the data buffer is successful. If unsuccessful, the method 800 may proceed to 812 where a read failure is output in response to the read command. Otherwise, the method 800 may proceed to 814.

[0056] At 814, method 800 may include processing the read data according to the logic command and optionally according to the command data. At 816, a determination is made as to whether the processing of the read data was successful. If not, method 800 may proceed to 818 and output a processing failure in response to the logic command. If the processing of the read data was successful, method 800 may proceed to 820, where processed data is output in response to the read command and the logic command.

[0057] Fig. 9A flow chart of an exemplary method 900 for operating a memory device according to an additional embodiment of the present invention is shown. At 902, the method 900 may include receiving a read command and a read address at a command interface of a memory bank of a non-volatile memory. At 904, the method 900 may include receiving a logic command related to data stored at the read address, and a rewrite address. The logic command may reference a logic or mathematical operation, the memory device is programmed to recognize the logic or mathematical operation, and the logic or mathematical operation is configured to be implemented using processing hardware or software. At 906, the method 900 may include optionally receiving command data related to the logic command together with the logic command. The command data may include a logic / mathematical variable, a logic / mathematical filter, a logic / mathematical operator, a logic / mathematical algorithm, a logic / mathematical parameter, etc. or a suitable combination thereof. At 908, the method 900 may include transmitting the read data from the read address to the data buffer in response to the read command. At 910, a determination may be made as to whether the transmission of the read data from the read address to the data buffer is successful. If unsuccessful, the method 900 may proceed to 912, in which a read failure is output in response to the read command. Otherwise, method 900 may proceed to 914 .

[0058] At 914, method 900 may include processing the read data according to the logical command and optionally according to the command data. At 916, a determination is made as to whether the processing of the read data was successful. If not, method 900 may proceed to 918 and output a processing failure in response to the logical command. If the processing of the read data was successful, method 900 may proceed to 920, where the processed data is written to the rewrite address of the memory bank in response to the read command and the logical command.

[0059] Fig.10A flow chart of an exemplary method 1000 for operating a memory bank of a non-volatile memory device according to yet another embodiment is depicted. At 1002, the method 1000 may include receiving a read command, a read address, and input data at an input interface of the memory bank. At 1004, the method 1000 may include saving the input data in a first section of a data buffer. At 1006, the method 1000 may include receiving a logic command related to the read command, the read address, and the input data. The logic command may reference a logic or mathematical operation, the memory device is programmed to recognize the logic or mathematical operation, and the logic or mathematical operation is configured to be implemented using processing hardware or software. At 1008, the method 1000 may include optionally receiving command data related to the logic command along with the logic command. The command data may include a logic / mathematical variable, a logic / mathematical filter, a logic / mathematical operator, a logic / mathematical algorithm, a logic / mathematical parameter, a query criterion (standard), data to be operated on, etc., or a suitable combination thereof. At 1010, the method 1000 may include transferring the read data from the read address to a second section of the data buffer. At 1012, method 1000 may determine whether the transfer of the read data to the second sector of the data buffer is successful, and if so, method 1000 may proceed to 1016. Otherwise, method 1000 may proceed to 1014 and may include outputting a read failure in response to the read command.

[0060] At 1016, method 1000 may include processing read data from the second section of the data buffer and input data from the first section of the data buffer according to the logic command and optionally according to the command data. At 1018, method 1000 may determine whether the processing is successful. If unsuccessful, method 1000 may proceed to 1020 and output a processing failure in response to the read command and the logic command. If successful, method 1000 may proceed to 1022 and output processed data in response to the read command and the logic command.

[0061] Fig.11A flow chart of an example method 1100 for operating a memory bank of a non-volatile memory device according to another additional embodiment is depicted. At 1102, the method 1100 may include receiving a read command, a read address, and input data at an input interface of the memory bank. At 1104, the method 1100 may include saving the input data in a first section of a data buffer. At 1106, the method 1100 may include receiving a logic command related to the read command, the read address, and the input data, and an overwrite address for writing processed data. The logic command may reference a logic or mathematical operation, the memory device is programmed to recognize the logic or mathematical operation, and the logic or mathematical operation is configured to be implemented using processing hardware or software. At 1108, the method 1100 may include optionally receiving command data related to the logic command along with the logic command. The command data may include a logic / mathematical variable, a logic / mathematical filter, a logic / mathematical operator, a logic / mathematical algorithm, a logic / mathematical parameter, a query criterion (standard), data to be operated on, etc., or a suitable combination thereof. At 1110, the method 1100 may include transferring the read data from the read address to a second section of the data buffer. At 1112, method 1100 may determine whether the transfer of the read data to the second sector of the data buffer is successful, and if so, method 1100 may proceed to 1116. Otherwise, method 1100 may proceed to 1114 and may include outputting a read failure in response to the read command.

[0062] At 1116, method 1100 may include processing read data from the second section of the data buffer and input data from the first section of the data buffer according to the logic command and optionally according to the command data. At 1118, method 1100 may determine whether the processing is successful. If unsuccessful, method 1100 may proceed to 1120 and output a processing failure in response to the read command and the logic command. If successful, method 1100 may proceed to 1122 and write the processed data to the rewrite address in response to the read command and the logic command.

[0063] Fig.12A flow chart of an exemplary method 1200 for operating a memory bank of a non-volatile memory in one or more additional embodiments of the present invention is depicted. At 1202, the method 1200 may include receiving a read command, a read address, a query command, and a query criterion. In at least one embodiment, the query command is a non-limiting example of a disclosed logical command, and the query criterion is a non-limiting example of a disclosed command data. At 1204, the method 1200 may include reading data from the read address into a data buffer. At 1210, the method 1200 may determine whether the read is successful, and if successful, proceed to 1206. If unsuccessful, the method 1200 may proceed to 1208 and output a read failure in response to the read command and the query command. At 1210, the method 1200 may include checking the read data against the query criterion in conjunction with satisfying the query command. At 1212, the method 1200 may determine whether the read data matches the query. If there is a match, method 1200 may proceed to 1216, where method 1200 may include outputting read data in response to the read command and the query command. Otherwise, if there is a mismatch, method 1200 may proceed to 1214 and include outputting a query mismatch for the read command and the query command.

[0064] Fig.13 A flow chart of an exemplary method 1300 for operating a memory bank of a non-volatile memory in a further embodiment of the present invention is depicted. At 1302, the method 1300 may include receiving a write command, a write address, a query command, and a query criteria. In at least one embodiment, the query command is a non-limiting example of a disclosed logical command, and the query criteria is a non-limiting example of disclosed command data. At 1304, the method 1300 may include receiving write data and saving the write data to a data buffer. At 1306, the method 1300 may include checking the write data against the query criteria in conjunction with executing the query command. At 1308, the method 1300 may determine whether the query matches the result. If the query does not match, the method 1300 may proceed to 1310 and may include outputting a query mismatch in response to the read command and the query command. If the query matches, the method 1300 may instead proceed to 1312 and may include writing the write data to the write address in response to the query match. At 1314, the method 1300 may include outputting a successful query and write status.

[0065] To provide context for various aspects of the disclosed subject matter, Fig.14The following discussion is intended to provide a brief, general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented or processed. Although the subject matter is described above in the general context of electronic memory or architecture and processing methods for operating such memory or architecture, those skilled in the art will recognize that the subject disclosure may also be implemented in conjunction with other architectures or processing methods. In addition, those skilled in the art will understand that the disclosed processes may be implemented alone or in conjunction with a host computer (e.g., the following Fig.15 The computer 1502 of the present invention may be implemented using a processing system or computer processor together, which may include a single-processor or multi-processor computer system, a small computing device, a mainframe computer, a personal computer, a handheld computing device (e.g., a PDA, a smart phone, a watch), a microprocessor-based consumer or industrial electronic product, or a programmable consumer or industrial electronic product, etc. The illustrated aspects may also be implemented in a distributed computing environment, in which tasks are performed by remote processing devices linked through a communication network. However, some (otherwise all) subject innovations may be implemented on independent electronic devices (e.g., memory cards, flash memory modules, removable memory, etc.). In a distributed computing environment, program modules may be located in local and remote memory storage modules or devices.

[0066] Fig.14 A block diagram of an exemplary operation and control environment 1400 of a memory group 1402 of a memory device in one or more disclosed embodiments is shown. In one or more embodiments, the memory group 1402 may be one of a plurality of memory groups of a plurality of memory groups of a memory device. In at least one aspect of the present invention, the memory group 1402 may include a memory selected from a variety of memory cell technologies. In at least one embodiment, the memory group 1402 may include a two-terminal memory technology arranged in a compact two-dimensional or three-dimensional architecture. Suitable two-terminal memory technologies may include resistive switching memory, conductive bridge memory, phase change memory, organic memory, magnetoresistive memory, etc. or a suitable combination of the foregoing memories. In yet another embodiment, the memory group 1402 may be configured to operate according to a first set of configurations (e.g., MLC, SLC, operating voltage, clock speed, delay, etc.), the first set of configurations being at least partially different from a second set of configurations of a second memory group of the plurality of memory groups of the memory device.

[0067] The column controller 1406 and sense amplifier 1408 may be formed adjacent to the memory group 1402. In addition, the column controller 1406 may be configured to activate (or identify for activation) a subset of the bit lines of the memory group 1402. The column controller 1406 may activate and operate on individual ones of the bit line subsets using control signals provided by the reference and control signal generator(s) 1418, applying appropriate programming, erasing, or reading voltages to the bit lines. Unactivated bit lines may be maintained at an inhibit voltage (also applied by the reference and control signal generator(s) 1418) to mitigate or avoid bit-disturb effects on the unactivated bit lines.

[0068] Additionally, the operating and control environment 1400 may include a row controller 1404. The row controller 1404 may be formed adjacent to and electrically connected to the word lines of the memory group 1402. Additionally, the row controller 1404 may select a particular row of memory cells with an appropriate select voltage using control signals from the reference and control signal generator(s) 1418. Additionally, the row controller 1404 may facilitate programming, erasing, or reading operations by applying an appropriate voltage on the selected word line.

[0069] The sense amplifier 1408 can read data from or write data to the enabled memory cells of the memory group 1402 selected by the column controller 1406 and the row controller 1404. The data read from the memory group 1402 can be supplied to the input and input / output buffer 1412 (e.g., in some embodiments, including a data buffer and a command buffer). Similarly, the data to be written to the memory group 1402 can be received from the input and input / output buffer 1412 and written to the enabled memory cells of the memory group 1402.

[0070] The processing logic 1430 may be configured to implement a logical or mathematical operation. The logical command received at the input / output buffer 1412 may be provided to the processing logic 1430 to implement the logical or mathematical operation (e.g., according to pre-stored instructions, according to configured logic circuits, etc.). Command data related to the logical or mathematical operation may also be received at the input / output buffer 1412, such as command variables, filters, operators, algorithms, parameters, queries, input data, etc. The logical or mathematical operation may be performed on data stored at the input / output buffer 1412, whether data that has been read from the memory bank 1402, data provided by the host to be processed and written to the memory bank 1402, or a suitable combination thereof. In some embodiments, the processing logic 1430 may output a success or failure result of the logical or mathematical operation independently of the success or failure of the memory operation (e.g., a read operation, a write operation, an erase operation, etc.).

[0071] Clock source(s) 1410 may supply respective clock pulses to facilitate the timing of read, write, and program operations of row controller 1404 and column controller 1406. Clock source(s) 1410 may be responsive to external or internal commands received by operating and control environment 1400 to further facilitate word line or bit line selection. Input and input / output buffers 1412 may include command and address inputs and bidirectional data inputs and outputs. Connection to an external host device, such as a computer or other processing device (not shown, but see, e.g., hereinafter) may be facilitated by providing instructions via command and address inputs and transmitting data to be written to and read from memory bank 1402 on bidirectional data inputs and outputs. Fig.10 computer 1002).

[0072] The input and input / output buffer 1412 may be configured to receive write data, receive erase instructions, receive status or maintenance instructions, output read data, output status information, and receive address data and command data as well as address data for various instructions. The address data may be transmitted to the row controller 1404 and the column controller 1406 via the address register 1410. In addition, the input data may be transmitted to the memory group 1402 via a signal input line between the sense amplifier 1408 and the input and input / output buffer 1412, and the output data may be received from the memory group 1402 via a signal output line from the sense amplifier 1408 to the input and input / output buffer 1412. The input data may be received from a host device, and the output data may be transmitted to the host device via an I / O bus.

[0073] The command received from the host device may be supplied to the command interface 1416. The command interface 1416 may be configured to receive an external control signal from the host device and determine whether the data input to the input and input / output buffer 1412 is write data, a command, or an address. The input command may be transmitted to the state machine 1420.

[0074] State machine 1420 may be configured to manage programming and reprogramming of memory bank 1402 (and other memory banks of the multi-bank memory array). Instructions provided to state machine 1420 are implemented according to the control logic configuration, enabling state machine 1420 to manage reading, writing, erasing, data input, data output, and other functions associated with memory bank 1402. In some aspects, state machine 1420 may send and receive acknowledgements and negative acknowledgements regarding successful receipt or execution of various commands. In further embodiments, state machine 1420 may decode and implement state-related commands, decode and implement configuration commands, and the like.

[0075] To implement functions such as read, write, erase, input, output, etc., the state machine 1420 can control the clock source(s) 1408 or reference and control the signal generator(s) 1418. Control of the clock source(s) 1408 can cause the output pulses to be configured to facilitate the row controller 1404 and the column controller 1406 to implement specific functions. For example, the output pulses can be transmitted to a selected bit line through the column controller 1406, or, for example, transmitted to a word line through the row controller 1404.

[0076] Combination Fig.15 , the systems and processes described below may be implemented in hardware such as a single integrated circuit (IC) chip, multiple ICs, an application specific integrated circuit (ASIC), etc. In addition, the order in which some or all of the processing blocks appear in each process should not be considered limiting. Instead, it should be understood that some processing blocks may be performed in a variety of orders, and not all orders may be explicitly stated herein.

[0077] refer to Fig.15 , a suitable operating environment 1500 for implementing various aspects of the claimed subject matter includes a computer 1502. The computer 1502 includes a processing unit 1504, a system memory 1506, a codec 1535, and a system bus 1508. The system bus 1508 couples system components including, but not limited to, the system memory 1506 to the processing unit 1504. The processing unit 1504 can be any of a variety of available processors. Dual microprocessors and other multi-processor architectures can also be used as the processing unit 1504.

[0078] The system bus 1508 can be any of a variety of bus structures (multiple), including a memory bus or memory controller, a peripheral bus or external bus and / or a local bus using any of a variety of available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), card bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Personal Computer Memory Card International Association bus (PCMCIA), FireWire (IEEE1394) and Small Computer System Interface (SCSI).

[0079] In various embodiments, the system memory 1506 includes a volatile memory 1510 and a non-volatile memory 1514, which can adopt one or more of the disclosed memory architectures. A basic input / output system (BIOS) is stored in the non-volatile memory 1512, and the basic input / output system contains basic routines to transfer information between elements within the computer 1502 during, for example, startup. In addition, according to the present innovation, the codec 1535 may include at least one of an encoder or a decoder, wherein at least one of the encoder or the decoder may be composed of hardware, software, or a combination of hardware and software. Although the codec 1535 is described as a separate component, the codec 1535 may be included in the non-volatile memory 1512. As an illustration and not limitation, the non-volatile memory 1512 may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. In at least some disclosed embodiments, the non-volatile memory 1512 may adopt one or more of the disclosed memory architectures. In addition, the non-volatile memory 1512 can be a computer memory (e.g., physically integrated with the computer 1502 or its motherboard) or a removable memory. Examples of suitable removable memory with which the disclosed embodiments can be implemented can include a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) memory stick, and the like. The volatile memory 1510 includes a random access memory (RAM) used as an external cache memory, and one or more of the disclosed memory architectures can also be employed in various embodiments. As an illustration and not limitation, RAM can be available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), and enhanced SDRAM (ESDRAM), and the like.

[0080] The computer 1502 may also include removable / non-removable, volatile / nonvolatile computer storage media. Fig.15Disk storage 1514 is shown as an example. Disk storage 1514 includes, but is not limited to, devices such as disk drives, solid state disks (SSD) floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. In addition, disk storage 1514 can include storage media alone, or can be combined with other storage media, other storage media including, but not limited to, optical disk drives such as compact disc ROM devices (CD-ROM), CD recordable drives (CD-R drives), CD rewritable drives (CD-RW drives), or digital versatile disc ROM drives (DVD-ROM). In order to facilitate the connection of disk storage 1514 to system bus 1508, removable or non-removable interfaces are generally used, such as interface 1516. It should be understood that disk storage 1514 can store information related to the user. This information can be stored on a server or provided to a server or provided to an application running on a user device. In one embodiment, the user can be notified (for example, through output device 1536) of the type of information stored in disk storage 1514 and / or transmitted to a server or application. The user may be provided with an opportunity to opt-in or opt-out of collecting and / or sharing such information with the server or application (eg, via input from input device(s) 1528 ).

[0081] It should be understood that Fig.15 Software that acts as an intermediary between a user and basic computer resources is depicted in a suitable operating environment 1500. Such software includes an operating system 1518. The operating system 1518, which may be stored on disk storage 1514, is used to control and allocate resources of the computer 1502. Applications 1520 utilize the management of resources by the operating system 1518 through program modules 1524, and program data 1526, such as startup / shutdown tables, stored in system memory 1506 or on disk storage 1514. It should be understood that the claimed subject matter may be implemented with various operating systems or combinations of operating systems.

[0082] The user inputs commands or information to the computer 1502 through input device(s) 1528. Input device(s) 1528 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, gamepad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, webcam, etc. These and other input devices are connected to the processing unit 1504 through the system bus 1508 via interface port(s) 1530. For example, interface port(s) 1530 include serial ports, parallel ports, game ports, and universal serial bus (USB). Output device(s) 1536 use a portion of the same type of ports as input device(s) 1528. Thus, for example, a USB port can be used to supply input to the computer 1502 and output information from the computer 1502 to the output device 1536. Output adapter 1534 is provided to illustrate that there are some output devices such as monitors, speakers, and printers that require special adapters among other output devices. By way of illustration and not limitation, output adapters 1534 may include video and sound cards that provide a means of connection between output devices 1536 and system bus 1508. It should be noted that other devices and / or systems of devices provide input and output capabilities such as remote computer(s) 1538.

[0083] The computer 1502 can operate in a network environment using logical connections to one or more remote computers, such as remote computer(s) 1538. The remote computer(s) 1538 can be a personal computer, server, router, network PC, workstation, microprocessor-based device, peer device, smart phone, tablet computer or other network node, and typically includes many elements described with respect to the computer 1502. For simplicity, only the remote computer(s) 1538 are illustrated with a memory storage device 1540. The remote computer(s) 1538 are logically connected to the computer 1502 via a network interface 1542, and then connected via a communication connection 1544. The network interface 1542 includes wired and / or wireless communication networks, such as local area networks (LANs) and wide area networks (WANs) and cellular networks. LAN technologies include fiber distributed data interface (FDDI), copper distributed data interface (CDDI), Ethernet, token ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks such as integrated services digital networks (ISDN) and their variants, encapsulated switching networks, and digital subscriber lines (DSL).

[0084] Communication connection(s) 1544 refers to the hardware / software used to connect the network interface 1542 to the system bus 1508. Although the communication connection 1544 is internal to the computer 1502 for clarity of illustration, it can also be external to the computer 1502. The hardware / software required to connect to the network interface 1542 includes (for exemplary purposes only) internal and external technologies such as modems including regular telephone grade modems, cable and DSL modems, ISDN adapters, and wired and wireless Ethernet cards, hubs, and routers.

[0085] The illustrated aspects of the present invention can also be implemented in a distributed computing environment, in which specific tasks are performed by remote processing devices linked through a communication network. In a distributed computing environment, program modules or stored information, instructions, etc. can be located in local or remote memory storage devices.

[0086] In addition, it should be understood that, in order to implement embodiments of the present invention, the various components described herein may include circuits (multiple), and the circuits (multiple) may include components and circuit elements with appropriate values. In addition, it is understood that many of the various components may be implemented on one or more IC chips. For example, in one embodiment, a group of components may be implemented in a single IC chip. In other embodiments, one or more corresponding components are manufactured or implemented on a separate IC chip.

[0087] As used herein, the terms "component," "system," "architecture," and the like are intended to refer to a computer or electronic related entity, which may be hardware, a combination of hardware and software, software (e.g., in execution), or firmware. For example, a component may be one or more transistors, memory cells, an arrangement of transistors or memory cells, a gate array, a programmable gate array, an application specific integrated circuit, a controller, a processor, a process running on a processor, an object, an executable file, a program or application that accesses or interfaces with a semiconductor memory, a computer, or the like, or a suitable combination thereof. A component may include erasable programming (e.g., processing instructions stored at least in part in an erasable memory) or hard programming (e.g., processing instructions burned into a non-erasable memory at the time of manufacture).

[0088] For example, both the process and the processor executed from the memory can be components. As another example, the architecture can include the following configuration: electronic hardware (e.g., parallel or series transistors), processing instructions and processors, which implement processing instructions in a manner suitable for the arrangement of electronic hardware. In addition, the architecture can include a single component (e.g., transistors, gate arrays, ...) or an arrangement of components (e.g., a series or parallel arrangement of transistors, a gate array connected to a program circuit, a power line, an electrical ground, an input signal line, and an output signal line, etc.). The system can include one or more components and one or more architectures. An exemplary system can include a switching block architecture, which includes a cross input / output line and a channel gate transistor, as well as a power supply (multiple), a signal generator (multiple), a communication bus (multiple), a controller, an I / O interface, an address register, etc. It should be understood that some overlap is expected in the definition, and the architecture or system can be an independent component, or a component of another architecture, system, etc.

[0089] In addition to the above, the disclosed subject matter can be implemented as a product using typical manufacturing, programming or engineering technology to produce hardware, firmware, software or any appropriate combination thereof to control an electronic device to implement the disclosed subject matter. The terms "equipment" and "product" used herein are intended to include electronic devices, semiconductor devices, computers or computer programs that can be accessed from any computer-readable device, carrier or medium. Computer-readable media may include hardware media or software media. In addition, the medium may include non-temporary media or transmission media. In one example, non-temporary media may include computer-readable hardware media. Specific examples of computer-readable hardware media may include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips ...), optical disks (e.g., optical disks (CDs), digital versatile disks (DVDs) ...), smart cards and flash memory devices (e.g., cards, sticks, key drives ...). Computer-readable transmission media may include carrier waves, etc. Of course, those skilled in the art will recognize that many modifications may be made to the configuration without departing from the scope or spirit of the disclosed subject matter.

[0090] The foregoing includes examples of the subject innovations. Of course, it is not possible to describe every conceivable combination of components or methods for the purpose of describing the subject innovations, but those skilled in the art will recognize that many further combinations and permutations of the subject innovations are possible. Therefore, the disclosed subject matter is intended to encompass all such changes, modifications, and variations that fall within the spirit and scope of the present invention. In addition, to the extent that the terms "include," "have," or "have" and variations thereof are used in the detailed description or claims, such terms are meant to be inclusive similar to the terms "include" or "comprise," and are interpreted as "include" when used as transition words in the claims.

[0091] In addition, the word "exemplary" is used herein to refer to serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as being better or advantageous than other aspects or designs. On the contrary, the word exemplary is used to present concepts in a concrete way. As used in this application, the term "or" is intended to refer to an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or the context clearly indicates otherwise, "X uses A or B" is intended to refer to any natural inclusive arrangement. That is, if X uses A; X uses B; or X uses A and B, then "X uses A or B" is satisfied in any of the above cases. In addition, the terms "one" and "an" used in this application and the appended claims should generally be interpreted as "one or more" unless otherwise specified or the context clearly indicates that they are expressed in the singular.

[0092] In addition, some portions of the detailed description have been presented in terms of algorithms or processing operations on data bits within an electronic memory. These process descriptions or representations are given by those skilled in the art to convey the content of their efforts in an effective manner to those of ordinary skill in the art to apply mechanisms that are used by those of ordinary skill in the art. In general, a process is considered to be a self-compatible sequence of actions leading to a desired result. These actions require physical manipulations of physical quantities. Typically, although not necessarily, these quantities are in the form of electrical and / or magnetic signals capable of being stored, transferred, combined, compared, and / or otherwise manipulated.

[0093] It has proven convenient, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise or apparent from the foregoing discussion, it should be understood that discussions in the disclosed subject matter using terms such as process, compute, replicate, simulate, determine, or transmit refer to the action and processing of a processing system and / or similar consumer or industrial electronic device or machine that operates on or transforms data or signals represented as physical (electrical or electronic) quantities in the circuits, registers, or memories of the electronic device(s) to other data or signals similarly represented as physical quantities in the machine or computer system memories or registers or other such information storage, transmission, and / or display devices.

[0094] With respect to the various functions performed by the above-described components, architectures, circuits, processes, etc., unless otherwise noted, the terms used to describe such components (including references to "means") are intended to correspond to any component that performs the specified function of the described component (e.g., a functional equivalent), even if not structurally equivalent to the disclosed structures that perform the functions shown in the exemplary aspects of the embodiments herein. In addition, while a particular feature may be disclosed for only one of a plurality of embodiments, such feature may be combined with one or more other features in other embodiments, which may be desirable and advantageous for any given or particular application. It will also be recognized that embodiments include systems having computer-executable instructions for performing the various processing actions and / or events, as well as computer-readable media.

Claims

1. A non-volatile memory device, comprising: a memory bank of non-volatile storage memory; a sense amplifier configured to read data stored in a selected subset of the memory bank; a data buffer configured to receive input data through the data interface or to supply output data through the data interface; a command interface for receiving, from a host device, a memory command specifying a memory operation and a data command independent of the memory command; as well as a processing logic unit configured to execute the data command in conjunction with the memory group that performs the memory operation associated with obtaining read data from the non-volatile storage memory or storing write data to the non-volatile storage memory, wherein the processing logic unit performs at least one of the following: The processing logic unit operates on the read data in response to the data command to generate first processed data after the read data is read by the sense amplifier and before it is received into the data buffer, or The processing logic unit operates on the write data in response to the data command to generate second processed data after the write data is received from the data interface into the data buffer.

2. The nonvolatile memory device according to claim 1, wherein: The memory command is a read command, a write command, or an erase command, and wherein the data command is not the read command, the write command, or the erase command.

3. The nonvolatile memory device according to claim 1, wherein: The command interface is further configured to receive variables associated with the data command.

4. The nonvolatile memory device according to claim 3, wherein: The data command is a conditional read command, the variable is a read filter, and further wherein the data buffer outputs the processed data only in response to determining that the read data matches the read filter in conjunction with performing the conditional read.

5. The nonvolatile memory device according to claim 1, wherein: The processing logic unit includes logic circuits for executing logic algorithms.

6. The nonvolatile memory device according to claim 5, wherein: The data command is an instruction to execute the logic algorithm, and the processing logic unit executes the logic algorithm on the read data or the write data to generate the processed data.

7. The nonvolatile memory device according to claim 6, wherein: The logic algorithm is selected from the group consisting of an AND operation, an OR operation, and an XOR operation.

8. The non-volatile memory device according to claim 1, wherein: The data command is an operation rewrite command that specifies a logical operation; The variables received with the data command through the command interface include a source address, a destination address, and optional command variables; and The processing logic unit performs the following operations in conjunction with the execution of the operation rewrite, the operations comprising: activating the source address within the memory group; transferring the data stored at the source address to the data buffer as the read data; performing the logic operation on the read data to generate the first processed data, wherein the logic operation on the read data is optionally performed according to the optional command variable to generate the first processed data; and The first processed data is written into the destination address.

9. The nonvolatile memory device according to claim 1, wherein: The processing logic unit further includes a stored status protocol, the status protocol causing the processing logic unit to output a status of execution of the memory command or the data command; and The status protocol indicates that the processing logic unit outputs a read or write failure in response to a first failure of the memory group to perform the memory operation, wherein the status protocol indicates that the processing logic unit outputs a data command failure in response to a second failure of the processing logic unit to perform the data command.

10. A method for operating a memory device, comprising: receiving write data and a write address at a data buffer of a memory bank of a nonvolatile memory; receiving a data command related to the write data; Processing the write data according to the data command; In response to successful execution of the data command, generating processed data, wherein the processed data is different from the write data; as well as In response to successful execution of the data command, the processed data is written to the write address of the memory bank.

11. The method of claim 10, further comprising outputting a data error in response to unsuccessfully executing the data command and generating the processed data.

12. The method of claim 10, further comprising outputting a write error in response to the memory device failing to write the processed data to the write address of the memory group.

13. The method of claim 10, further comprising outputting a command success in response to successful execution of the data command and in response to writing the processed data to the write address of the memory bank.

14. The method of claim 10, further comprising receiving a command argument in addition to receiving the data command.

15. The method according to claim 14, wherein: Processing the write data according to the data command also includes incorporating the command variable.

16. A method for operating a memory device, comprising: receiving a read command and a read address at a memory bank of the nonvolatile memory; receiving a data command related to data stored at the read address; transferring read data from the read address to a data buffer; generating processed data in response to successful execution of the data command, wherein the processed data is different from the read data; as well as The processed data is output to a host device in response to successful execution of the data command.

17. The method of claim 16, further comprising outputting a data error in response to unsuccessfully executing the data command and generating the processed data. 18 . The method of claim 16 , further comprising outputting a read error in response to a failure to transfer the read data from the read address to the data buffer.

19. The method of claim 16, further comprising receiving a command argument in addition to receiving the data command.

20. The method according to claim 19, wherein: Processing the read data according to the data command also includes incorporating the command variable.

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