Display device

Abstract

A display device is provided, comprising: a substrate; an active layer comprising a channel region and a conductive region; a first conductive layer comprising a driving gate electrode and a scan line in a first direction; a second conductive layer comprising a storage line; a third conductive layer above the storage line and comprising a first connecting member; an insulating layer located between the storage line and the first connecting member; and a data line and a driving voltage line crossing the scan line in a second direction, wherein the first connecting member electrically connects the driving gate electrode to the conductive region, the driving voltage line overlaps the first connecting member, and the insulating layer comprises a first sub-insulating layer and a second sub-insulating layer, and an edge of the second sub-insulating layer substantially overlaps an edge of the first connecting member in a thickness direction of the display device.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0064345 filed on May 31, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosure relates to a display device and a method of manufacturing the display device, in which the thickness of the display device is minimized. Background Art

[0003] The display device includes pixels which may be units for displaying images. Specifically, the pixels of the display device including the light emitting layer may include a light emitting diode including the light emitting layer, a cathode and an anode, and a transistor and at least one capacitor for driving the light emitting diode.

[0004] The light emitting diode may include two electrodes and a light emitting layer disposed between the two electrodes. Electrons injected from a cathode as one electrode and holes injected from an anode as the other electrode may be recombined in the organic light emitting layer to form excitons, thereby emitting light when the excitons emit energy.

[0005] The transistor may include at least one switching transistor and at least one driving transistor. The switching transistor may receive a data signal according to a scanning signal and may transmit a voltage according to the data signal, and the driving transistor may be directly or indirectly connected to a light emitting diode to control the amount of driving current transmitted to the light emitting diode so that each pixel may emit light of a desired brightness. Summary of the invention

[0006] Embodiments have been made in an effort to provide a display device including an insulating layer having a uniform thickness and having improved display quality, and a method of manufacturing the same.

[0007] An embodiment may include a display device, comprising: a substrate; an active layer, disposed on the substrate and including a channel region and a conductive region; a first conductive layer, which may be configured to include a driving gate electrode and a scan line extending in a first direction; a second conductive layer, which may be configured to include a storage line; a third conductive layer, which may be configured to include a first connecting member, disposed above the storage line; an insulating layer, which may be disposed between the storage line and the first connecting member; and a data line and a driving voltage line, each of which may be configured to cross the scan line and extend in a second direction, wherein the first connecting member may electrically connect the driving gate electrode to a conductive region among the conductive regions, the driving voltage line may overlap with at least a portion of the first connecting member, and the insulating layer may include a first sub-insulating layer and a second sub-insulating layer, and an edge of the second sub-insulating layer may substantially overlap with an edge of the first connecting member in a thickness direction of the display device.

[0008] An edge of the second sub-insulating layer may be aligned with an edge of the third conductive layer in a thickness direction of the display device.

[0009] The edge of the second sub-insulating layer and the edge of the third conductive layer may be offset in the thickness direction of the display device.

[0010] The third conductive layer may include a second connection member, a third connection member, a fourth connection member, and an initialization voltage line disposed on the same layer as that of the first connection member.

[0011] The second sub-insulating layer may include: a first region configured to overlap with the first connecting member; a second region configured to overlap with the second connecting member; a third region configured to overlap with the third connecting member; a fourth region configured to overlap with the fourth connecting member; and a fifth region configured to overlap with the initialization voltage line.

[0012] The first to fourth regions may be spaced apart from each other in a plan view.

[0013] The fifth region may extend along the first direction.

[0014] The first sub-insulating layer and the second sub-insulating layer may include different materials.

[0015] The first sub-insulating layer may include silicon oxide, and the second sub-insulating layer may include silicon nitride.

[0016] The thickness of the first sub-insulating layer may be greater than the thickness of the second sub-insulating layer.

[0017] The second sub-insulating layer may have a thickness in the range of about 900 angstroms to about 1400 angstroms.

[0018] The third conductive layer may include a lower layer and an upper layer, the lower layer may include titanium (Ti), and the upper layer may include molybdenum (Mo).

[0019] An edge of the second sub-insulating layer may have a tapered shape.

[0020] An edge of the second sub-insulating layer may protrude further than an edge of the first connection member.

[0021] An embodiment may include a method for manufacturing a display device, the method comprising: forming a semiconductor layer on a substrate; forming a first conductive layer including a scan line extending in a first direction on the semiconductor layer; forming a second conductive layer including a storage line extending in the first direction on the scan line; forming a first sub-insulating material layer and a second sub-insulating material layer on the storage line; and forming a third conductive layer including a first connecting member on the second sub-insulating material layer, wherein the second sub-insulating layer can be formed by etching the second sub-insulating material layer during the formation of the third conductive layer.

[0022] The third conductive layer may include a lower layer and an upper layer.

[0023] The second sub-insulating material layer may be etched during the process of etching the lower layer.

[0024] An etching rate of the second sub-insulating material layer may be greater than an etching rate of the lower layer.

[0025] An etch rate of the first sub-insulating material layer may be lower than an etch rate of a lower layer.

[0026] The third conductive layer may include second, third, fourth connecting members, and an initialization voltage line, and edges of the second sub-insulating material layer may substantially overlap edges of the second, third, fourth connecting members, and the initialization voltage line.

[0027] An edge of the second sub-insulating material layer may be aligned with each of edges of the second connection member, the third connection member, the fourth connection member, and the initialization voltage line.

[0028] An edge of the second sub-insulating material layer may be offset from each of edges of the second connection member, the third connection member, the fourth connection member, and the initialization voltage line.

[0029] According to the embodiments herein, a display device including an insulating layer having a uniform thickness and a method for manufacturing the same may be provided. Therefore, a display device having improved display quality and a method for manufacturing the same may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram showing an equivalent circuit of a pixel of a display device according to an embodiment.

[0031] Figure 2 A layout diagram of pixels of a display device according to an embodiment is shown.

[0032] Figure 3 Shown along Figure 2 A schematic cross-sectional view of the display device taken along line A1-A2.

[0033] Figure 4 Shown along Figure 2 A schematic cross-sectional view of the display device taken along line A3 - A4 .

[0034] Figure 5 A schematic top plan view of a pixel in a display device according to an embodiment is shown.

[0035] Figure 6 A layout diagram of pixels of a display device according to an embodiment is shown.

[0036] Figure 7 A schematic cross-sectional view showing conductors constituting a capacitor of the display device according to the embodiment is shown.

[0037] Figure 8 A layout diagram of pixels of a display device according to an embodiment is shown.

[0038] Fig. 9 A schematic cross-sectional view showing a region of a display device according to an embodiment is shown.

[0039] Fig.10 , Fig.13 , Fig.16 , Fig.19 , Fig. 22 , Fig.25 and Fig.28 A layout diagram of pixels of a display device in an intermediate process step of a method for manufacturing a display device according to an embodiment is shown.

[0040] Fig.11 , Fig.14 , Fig.17 , Fig. 20 , Fig.23 , Fig.26 and Fig.29 They are shown along Fig.10 , Fig.13 , Fig.16 , Fig.19 , Fig. 22 , Fig.25 and Fig.28 A schematic cross-sectional view of the display device taken along line A1-A2.

[0041] Fig.12 , Fig.15 , Fig.18 , Fig.21 , Fig.24 , Fig. 27 and Fig.30 They are shown along Fig.10 , Fig.13 , Fig.16 , Fig.19 , Fig. 22 , Fig.25 and Fig.28 A schematic cross-sectional view of the display device taken along line A3 - A4 .

[0042] Fig.31 A cross-sectional view image of a region of a display device according to a comparative example is shown.

[0043] Fig.32A shows a plan view image in a manufacturing process of a display device according to a comparative example, Fig.32B and Fig.32CA cross-sectional view image in a manufacturing process of a display device according to a comparative example is shown.

[0044] Fig.33 A cross-sectional view image of a region of a display device according to embodiments herein is shown.

[0045] Fig.34A , Fig.34B and Fig.34C showing a cross-sectional view image of a region of a display device according to a comparative example, Fig.34D A cross-sectional view image of a region of a display device according to embodiments herein is shown. DETAILED DESCRIPTION

[0046] The disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the disclosed embodiments.

[0047] In order to clearly describe the embodiments, parts irrelevant to the description are omitted, and the same reference numerals are used throughout the disclosure to designate the same or similar constituent elements.

[0048] In addition, since the sizes and thicknesses of the constituent members shown in the drawings may be arbitrarily given for better understanding and ease of description, the embodiments may not be limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. may be exaggerated for clarity. In the drawings, the thicknesses of some layers and regions may be exaggerated for better understanding and ease of description.

[0049] It will be understood that when an element such as a layer, film, region, or substrate may be referred to as being "on" another element, the element may be directly on the other element or there may be intervening elements. Conversely, when an element is referred to as being "directly on" another element, there may be no intervening elements. The terms "on" or "on" indicate positioning on or below a target portion, and do not necessarily mean positioning on the upper side of a target portion based on the direction of gravity.

[0050] Unless expressly described to the contrary, the word "comprise" and variations such as "comprises" or "comprising" will be understood to indicate the inclusion of the stated elements but not the exclusion of any other elements. As used herein, the term "and / or" may include any and all combinations of one or more of the associated listed items. Expressions such as "at least one of" when following a list of elements modify the entire list of elements and do not modify the individual elements of the list.

[0051] In the case where a particular embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described order.

[0052] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements being discussed and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0053] It will be understood that the terms "first", "second", etc. may be used herein to describe various components, and these components should not be limited by these terms. These terms may be used only to distinguish one component from another component. As used herein, the singular forms "a (kind / person)" and "the" are also intended to include plural forms unless the context clearly indicates otherwise.

[0054] In the embodiments below, it will be understood that when an element, region or layer is referred to as being connected to another element, region or layer, the element, region or layer may be directly or indirectly connected to the other element, region or layer. For example, it will be understood that when an element, region or layer is referred to as being in contact with or electrically connected to another element, region or layer in this specification, the element, region or layer may be directly or indirectly in contact with or electrically connected to the other element, region or layer.

[0055] In addition, the phrase "in a plan view" means when the target portion is viewed from above, and the phrase "in a cross-sectional view" means when the cross section cut through the vertical cutting element portion is viewed from the side. In addition, the term "superimposed" or its variants means that the first target can be above or below or on the side of the second target, and vice versa. In addition, as will be appreciated and understood by those of ordinary skill in the art, the term "superimposed" may include layers, stacks, faces or facing, extending above, covering or partially covering or any other suitable terms. The term "facing" and its variants mean that the first element can be directly or indirectly opposite to the second element. In the case where the third element is inserted between the first element and the second element, the first element and the second element can be understood to be indirectly opposite to each other, but still facing each other. When an element is described as "not "superimposed" with another element or "not "superimposed" with another element, as will be appreciated and understood by those of ordinary skill in the art, the description may include elements spaced apart from each other, offset from each other or separated from each other or any other suitable terms. When a layer, region, substrate or district is referred to as "on" another layer, region, substrate or district, the layer, region, substrate or district may be directly on the other layer, region, substrate or district, or there may be an intermediate layer, intermediate region, intermediate substrate or intermediate zone between them. On the contrary, when a layer, region, substrate or district is referred to as "directly on" another layer, region, substrate or district, there may not be an intermediate layer, intermediate region, intermediate substrate or intermediate zone between them. In addition, when a layer, region, substrate or district is referred to as "below" another layer, region, substrate or district, the layer, region, substrate or district may be directly below the other layer, region, substrate or district, or there may be an intermediate layer, intermediate region, intermediate substrate or intermediate zone between them. On the contrary, when a layer, region, substrate or district is referred to as "directly on" another layer, region, substrate or district, there may not be an intermediate layer, intermediate region, intermediate substrate or intermediate zone between them. Furthermore, "above" or "over" may include positioning above or below a target and does not necessarily imply a direction based on gravity.

[0056] For ease of description, spatially relative terms such as "below", "under", "below", "above", "on", etc. may be used herein to describe the relationship between one element or assembly and another element or assembly as shown in the drawings. It will be understood that, in addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of the device in use or operation. For example, in the case where the device shown in the drawings is flipped, a device positioned "below" or "below" another device may be placed "above" the other device. Therefore, the illustrative term "below" may include both a lower position and an upper position. Devices may also be positioned in other directions, so spatially relative terms may be interpreted differently depending on orientation.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0058] Figure 1 A schematic diagram showing an equivalent circuit of a pixel of a display device according to an embodiment.

[0059] Reference Figure 1 , the display device according to the embodiment includes pixels PX capable of displaying an image and signal lines 151, 152, 153, 154, 171, and 172. Figure 1 , the pixel PX includes transistors T1, T2, T3, T4, T5, T6 and T7, a capacitor Cst and at least one light emitting diode ED that may be connected to the signal lines 151, 152, 153, 154, 171 and 172. In an embodiment, the pixel PX may include one light emitting diode ED.

[0060] The signal lines 151 , 152 , 153 , 154 , 171 , and 172 may include scan lines 151 , 152 , and 154 , a control line 153 , a data line 171 , and a driving voltage line 172 .

[0061] The scan lines 151, 152 and 154 may transmit scan signals GWn, GIn and GI(n+1), respectively. The scan signals GWn, GIn and GI(n+1) may transmit gate-on voltages and gate-off voltages capable of turning on or off the transistors T2, T3, T4 and T7 included in the pixel PX.

[0062] The scan lines 151, 152, and 154 connected to the pixel PX may include: a first scan line 151, through which a scan signal GWn may be transmitted; a second scan line 152, through which a scan signal GIn having a gate-on voltage may be transmitted at a time different from that of the first scan line 151; and a third scan line 154, through which a scan signal GI(n+1) may be transmitted. The second scan line 152 may transmit a gate-on voltage at a time earlier than that of the first scan line 151. For example, in the case where the scan signal GWn may be an nth scan signal Sn (n is a natural number equal to or greater than 1) among scan signals applied during one frame, the scan signal GIn may be a previous stage (such as n-1th) scan signal, and the scan signal GI(n+1) may be an nth scan signal Sn. However, the embodiment may not be limited thereto, and the scan signal GI(n+1) may be a scan signal that may be different from the nth scan signal Sn.

[0063] The control line 153 may transmit a control signal, specifically, a light emission control signal EM capable of controlling light emission of the light emitting diode ED included in the pixel PX. The control signal transmitted through the control line 153 may transmit a gate-on voltage and a gate-off voltage, and may have a waveform that may be different from the waveform of the scan signal transmitted through the scan lines 151, 152, and 154.

[0064] The data line 171 may transmit a data signal Dm, and the driving voltage line 172 may transmit a driving voltage ELVDD. The data signal Dm may have different voltage levels according to an image signal input into the display device, and the driving voltage ELVDD may have a substantially constant level.

[0065] Although not shown, the display device may further include a driver that may transmit signals to the signal lines 151 , 152 , 153 , 154 , 171 , and 172 .

[0066] The transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 included in one pixel PX may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor T7 .

[0067] The first scan line 151 may transmit the scan signal GWn to the second transistor T2 and the third transistor T3. The second scan line 152 may transmit the scan signal GIn to the fourth transistor T4. The third scan line 154 may transmit the scan signal GI(n+1) to the seventh transistor T7. The control line 153 may transmit the light emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0068] The gate electrode G1 of the first transistor T1 may be connected to the first end of the capacitor Cst through the driving gate node GN, the first electrode S1 of the first transistor T1 may be connected to the driving voltage line 172 via the fifth transistor T5, and the second electrode D1 of the first transistor T1 may be connected to the anode of the light emitting diode ED via the sixth transistor T6. The first transistor T1 may receive the data signal Dm transmitted by the data line 171 according to the switching operation of the second transistor T2 to supply the driving current Id to the light emitting diode ED.

[0069] The gate electrode G2 of the second transistor T2 may be connected to the first scan line 151. The first electrode S2 of the second transistor T2 may be connected to the data line 171. The second electrode D2 of the second transistor T2 may be connected to the first electrode S1 of the first transistor T1, and may be connected to the driving voltage line 172 via the fifth transistor T5. The second transistor T2 may be turned on according to the scan signal GWn received through the first scan line 151 to transmit the data signal Dm transmitted from the data line 171 to the first electrode S1 of the first transistor T1.

[0070] The gate electrode G3 of the third transistor T3 may be connected to the first scan line 151, the first electrode S3 of the third transistor T3 may be connected to the second electrode D1 of the first transistor T1, and may be connected to the anode of the light emitting diode ED via the sixth transistor T6. The second electrode D3 of the third transistor T3 may be connected to the second electrode D4 of the fourth transistor T4, the first end of the capacitor Cst, and the gate electrode G1 of the first transistor T1. The third transistor T3 may be turned on according to the scan signal GWn transmitted through the first scan line 151 to connect the gate electrode G1 of the first transistor T1 and the second electrode D1 of the first transistor T1 to each other, so that the first transistor T1 may be diode-connected.

[0071] The gate electrode G4 of the fourth transistor T4 may be connected to the second scan line 152, the first electrode S4 of the fourth transistor T4 may be connected to the terminal of the initialization voltage Vint, and the second electrode D4 of the fourth transistor T4 may be connected to the first end of the capacitor Cst via the second electrode D3 of the third transistor T3 and may be connected to the gate electrode G1 of the first transistor T1. In order to perform an initialization operation for initializing the voltage of the gate electrode G1 of the first transistor T1, the fourth transistor T4 may be turned on in response to the scan signal GIn received through the second scan line 152 to transmit the initialization voltage Vint to the gate electrode G1 of the first transistor T1.

[0072] A gate electrode G5 of the fifth transistor T5 may be connected to the control line 153 , a first electrode S5 of the fifth transistor T5 may be connected to the driving voltage line 172 , and a second electrode D5 of the fifth transistor T5 may be connected to the first electrode S1 of the first transistor T1 and to the second electrode D2 of the second transistor T2 .

[0073] The gate electrode G6 of the sixth transistor T6 may be connected to the control line 153, and the first electrode S6 of the sixth transistor T6 may be connected to the second electrode D1 of the first transistor T1 and the first electrode S3 of the third transistor T3. The second electrode D6 of the sixth transistor T6 may be electrically connected to the anode of the light emitting diode ED. The fifth transistor T5 and the sixth transistor T6 may be turned on simultaneously according to the light emitting control signal EM transmitted through the control line 153, whereby the driving voltage ELVDD may be compensated through the diode-connected first transistor T1 to be transmitted to the light emitting diode ED.

[0074] A gate electrode G7 of the seventh transistor T7 may be connected to the third scan line 154, a first electrode S7 of the seventh transistor T7 may be connected to the second electrode D6 of the sixth transistor T6 and the anode of the light emitting diode ED, and a second electrode D7 of the seventh transistor T7 may be connected to the terminal of the initialization voltage Vint and the first electrode S4 of the fourth transistor T4.

[0075] The transistors T1, T2, T3, T4, T5, T6 and T7 may be P-channel transistors such as PMOS transistors, but the disclosure may not be limited thereto. For example, at least one of the transistors T1, T2, T3, T4, T5, T6 and T7 may be an N-channel transistor.

[0076] As described above, a first end of the capacitor Cst may be connected to the gate electrode G1 of the first transistor T1, and a second end may be connected to the driving voltage line 172. A cathode of the light emitting diode ED may be connected to a common voltage ELVSS terminal for transmitting the common voltage ELVSS to receive the common voltage ELVSS.

[0077] The structure of the pixel PX according to the embodiment may not be limited to Figure 1 The structure shown in FIG. 1 may be variously modified, including the number of transistors and capacitors in one pixel PX and their connection relationship.

[0078] The following reference Figure 1 The operation of the display device according to the embodiment is described.

[0079] When a scan signal GIn with a gate-on voltage level can be supplied through the second scan line 152 during the initialization period (the scan signal GIn can be the n-1th scan signal S(n-1)), the fourth transistor T4 can be turned on, the initialization voltage Vint can be transmitted to the gate electrode G1 of the first transistor T1 through the fourth transistor T4, and the first transistor T1 can be initialized by the initialization voltage Vint.

[0080] In the case where a scan signal GWn (the scan signal GWn may be an nth scan signal Sn) of a gate-on voltage level may be supplied through the first scan line 151 during the data programming and compensation period, the second transistor T2 and the third transistor T3 may be turned on. The first transistor T1 may be diode-connected due to the turned-on third transistor T3 and may be forward biased. Therefore, a compensation voltage may be applied to the gate electrode G1 of the first transistor T1, and the compensation voltage may reduce the threshold voltage Vth of the first transistor T1 from the data signal Dm supplied by the data line 171. The driving voltage ELVDD and the compensation voltage may be applied to opposite terminals of the capacitor Cst, respectively, and the capacitor Cst may be charged with charges corresponding to the voltage difference of the opposite terminals.

[0081] The light emitting control signal EM supplied from the control line 153 during the light emitting period may be changed from a gate-off voltage level to a gate-on voltage level, and the change point may be after the scan signal GWn may be applied to all the first scan lines 151 in one frame. Therefore, during the light emitting period, the fifth transistor T5 and the sixth transistor T6 may be turned on, a driving current Id may be generated according to a voltage difference between a gate voltage of the gate electrode G1 of the first transistor T1 and the driving voltage ELVDD, and the driving current Id may be supplied to the light emitting diode (LED) ED through the sixth transistor T6, so that the current Ied may flow to the light emitting diode ED.

[0082] During the initialization period, the seventh transistor T7 may receive a scan signal GI(n+1) of a gate-on voltage level through the third scan line 154 to be turned on. The scan signal GI(n+1) may be an nth scan signal Sn. Some of the driving current Id may flow out as a bypass current Ibp through the turned-on seventh transistor T7.

[0083] The following reference Figures 2 to 8 and Figure 1 The configuration of the display device according to the embodiment is described together.

[0084] For easy understanding, a planar configuration of a display device according to an embodiment is described below, and then a schematic cross-sectional configuration of the display device is discussed.

[0085] Reference Figure 2, a pixel of the display device according to the embodiment may include transistors T1, T2, T3, T4, T5, T6 and T7 and a capacitor Cst which may be connected to scan lines 151, 152 and 154, a control line 153, a data line 171 and a driving voltage line 172. Figure 2 The configuration shown in can be arranged to be repeated in the horizontal direction and the vertical direction.

[0086] The scan lines 151, 152, and 154 and the control line 153 may extend in substantially the same direction (e.g., horizontal direction) in a plan view. The first scan line 151 may be disposed between the second scan line 152 and the control line 153 in a plan view. The third scan line 154, which may be a scan line of the same type as the second scan line 152, may transmit a scan signal GI(n+1) of the next stage of the scan signal GIn transmitted by the second scan line 152.

[0087] The data line 171 and the driving voltage line 172 may extend substantially in a vertical direction in a plan view to cross the scan lines 151, 152, and 154 and the control line 153. The data line 171 may transmit a data signal Dm, and the driving voltage line 172 may transmit a driving voltage ELVDD. The driving voltage line 172 may include an extension 178 disposed at each pixel PX. The extension 178 may extend in a direction that may be perpendicular to the extension direction of the driving voltage line 172.

[0088] The display device according to the embodiment may further include a storage line 156 and an initialization voltage line 169 .

[0089] The storage line 156 and the initialization voltage line 169 may extend substantially in a horizontal direction in a plan view. The storage line 156 may be disposed between the first scan line 151 and the control line 153 in a plan view. The storage line 156 may include an extension 157 disposed at each pixel PX. The storage line 156 may transmit the driving voltage ELVDD. The extension 157 may include an opening 51 that may be substantially centrally located.

[0090] The initialization voltage line 169 transmits the initialization voltage Vint, and most of the area of ​​an initialization voltage line 169 can be set between the first scan line 151 and the second scan line 152, but the disclosure is not limited thereto. Figure 2 As shown in an upper portion of FIG. 1 , the initialization voltage line 169 may be adjacent to the second scan line 152 , or may overlap or face the second scan line 152 in a plan view.

[0091] The scan lines 151, 152, and 154 and the control line 153 may be included in the first conductive layer (including 151, 152, 153, 154, and the driving gate electrode 155a) to be arranged on the same layer in the cross section, and may include the same material. The storage line 156 may be included in a second conductive layer (156 and an extension 157 of the storage line 156) that may be different from the first conductive layer (151, 152, 153, 154, and 155a). For example, the second conductive layer (156 and 157) may be arranged in a layer located above the first conductive layer (151, 152, 153, 154, and 155a). The initialization voltage line 169 may be included in a third conductive layer (including 169 and 161, 162, 163, 164 as discussed below) that may be different from the first conductive layer (151, 152, 153, 154, and 155a) and the second conductive layer (156 and 157). For example, the third conductive layer (161, 162, 163, 164, and 169) may be disposed in a layer located above the second conductive layer (156 and 157). The data line 171 and the driving voltage line 172 may be included in a fourth conductive layer (including 171, 172, and a connecting member 179) that may be different from the first conductive layer to the third conductive layer to be disposed on the same layer in a cross section and may include the same material. For example, the fourth conductive layer (171, 172, and 179) may be disposed in a layer located above the third conductive layer (161, 162, 163, 164, and 169).

[0092] In this way, the initialization voltage line 169 can be provided in the third conductive layer (161, 162, 163, 164, and 169) which can be different from the first conductive layer (151, 152, 153, 154, and 155a) in which the scan lines 151, 152, and 154, the control line 153, and the like are provided. Therefore, the distance between the initialization voltage line 169 and the scan lines 151, 152, and 154 can be minimized in a plan view, and further overlap or facing between the initialization voltage line 169 and the second scan line 152 can be demonstrated in a plan view. Therefore, the use of available space within the display device and the degree of freedom of component design can be optimized, thereby facilitating the manufacture of a high-resolution display device.

[0093] Since the voltage difference between the voltage transmitted through the initialization voltage line 169 and the voltage transmitted through the scan lines 151, 152 and 154 or the control line 153 may be large, there is a high risk of damaging the insulating layer when the initialization voltage line 169 can be adjacent to the scan lines 151, 152 and 154 or the control line 153 and only one insulating layer can be set between them. However, according to the embodiments herein, the second insulating layer 142 and the third insulating layer 143 may be disposed between the third conductive layer (161, 162, 163, 164 and 169) (in which an initialization voltage line 169 may be disposed) and the first conductive layer (151, 152, 153, 154 and 155a) (such as scan lines 151, 152 and 154 or control line 153), so that a sufficient distance between the initialization voltage line 169 and the second scan line 152 in the cross section can ensure that the risk of short circuit is reduced, and the distance between the initialization voltage line 169 and the second scan line 152 can be minimized in the plan view.

[0094] A channel of each of the transistors T1, T2, T3, T4, T5, T6, and T7 may be formed inside one active layer 130, and the active layer 130 may be bent in various shapes. The active layer 130 may be made of a semiconductor material such as amorphous silicon / polysilicon or an oxide semiconductor.

[0095] The active layer 130 may include a channel region and a conductive region that may be a semiconductor. The channel region may include channel regions 131a, 131b, 131c1, 131c2, 131d1, 131d2, 131e, 131f, and 131g that form the respective channels of the transistors T1, T2, T3, T4, T5, T6, and T7. The remaining portion of the active layer 130 except the channel regions 131a, 131b, 131c1, 131c2, 131d1, 131d2, 131e, 131f, and 131g may be used as a conductive region. The conductive region may have a carrier concentration that may be higher than the carrier concentration of the channel regions 131a, 131b, 131c1, 131c2, 131d1, 131d2, 131e, 131f, and 131g. A pair of conductive regions disposed at opposite sides of the channel regions 131a, 131b, 131c1, 131c2, 131d1, 131d2, 131e, 131f, and 131g may function as first and second electrodes of corresponding transistors T1, T2, T3, T4, T5, T6, and T7.

[0096] The first transistor T1 may include a channel region 131 a , first and second electrodes 136 a and 137 a disposed at opposite sides of the channel region 131 a , and a driving gate electrode 155 a overlapping or facing the channel region 131 a in a plan view.

[0097] The channel region 131a may be bent at least once. For example, the channel region 131a may have a meandering shape or a zigzag shape. Figure 2 An example is shown in which the channel region 131 a may include a U-shape that may be substantially inverted upside down.

[0098] The driving gate electrode 155a may be included in the first conductive layer (151, 152, 153, 154, and 155a) described above, and may be connected to the first connection member 161 through the contact hole 61. The contact hole 61 may be provided in the opening 51 of the extension portion 157 of the storage line 156. In cross section, the first connection member 161 may be included in the third conductive layer (161, 162, 163, 164, and 169). The first connection member 161 substantially extends in a vertical direction to cross the first scan line 151. The first connection member 161 may correspond to the driving gate node GN ( Figure 1 ).

[0099] The second transistor T2 may include a channel region 131b, a first electrode 136b and a second electrode 137b disposed at opposite sides of the channel region 131b, and a gate electrode 155b overlapping or facing the channel region 131b in a plan view. The gate electrode 155b may be a portion of the first scan line 151. The first electrode 136b may be connected to the second connection member 162 through the contact hole 63, and the second electrode 137b may be connected to the first electrode 136a of the first transistor T1.

[0100] The second connection member 162 may be included in the third conductive layer (161, 162, 163, 164, and 169) in cross section. Since the second connection member 162 may be connected to the data line 171 through the contact hole 71, the first electrode 136b may be electrically connected to the data line 171 to receive the data signal Dm.

[0101] The third transistor T3 may be formed in two parts to prevent leakage current. For example, the third transistor T3 may include a third transistor first part T3_1 and a third transistor second part T3_2 which may be adjacent to and connected to each other.

[0102] The third transistor first portion T3_1 may include a channel region 131c1 overlapping or facing the first scan line 151 in a plan view, a first electrode 136c1 and a second electrode 137c1 disposed at opposite sides of the channel region 131c1, and a gate electrode 155c1 overlapping or facing the channel region 131c1. The gate electrode 155c1 may be a portion of a protrusion of the first scan line 151. The second electrode 137c1 may be connected to the first connection member 161 through a contact hole 62.

[0103] The third transistor second portion T3_2 may include a channel region 131c2 overlapping or facing the first scan line 151 in a plan view, first and second electrodes 136c2 and 137c2 disposed at opposite sides of the channel region 131c2, and a gate electrode 155c2 overlapping or facing the channel region 131c2. The gate electrode 155c2 may be a portion of the first scan line 151. The first electrode 136c2 of the third transistor second portion T3_2 may be connected to the second electrode 137a of the first transistor T1, and the second electrode 137c2 may be connected to the first electrode 136c1 of the third transistor first portion T3_1.

[0104] The fourth transistor T4 may also be formed in two parts to prevent leakage current. For example, the fourth transistor T4 may include a fourth transistor first part T4_1 and a fourth transistor second part T4_2 that may be adjacent to and connected to each other. Although the fourth transistor first part T4_1 and the fourth transistor second part T4_2 may be arranged in Figure 2 , the third scan line 154 may be the next level of the second scan line 152, thereby proving that the scan line configuration can be repeated.

[0105] The fourth transistor first portion T4_1 may include a channel region 131d1 overlapping or facing the second scan line 152 or the third scan line 154 in a plan view, a first electrode 136d1 and a second electrode 137d1 disposed at opposite sides of the channel region 131d1, and a gate electrode 155d1 overlapping or facing the channel region 131d1. The gate electrode 155d1 may be a portion of the second scan line 152 (or the third scan line 154). The second electrode 137d1 may be connected to the second electrode 137c1 of the third transistor first portion T3_1, and may be connected to the first connection member 161 through the contact hole 62.

[0106] The fourth transistor second portion T4_2 may include a channel region 131d2 overlapping or facing the second scan line 152 or the third scan line 154 in a plan view, a first electrode 136d2 and a second electrode 137d2 disposed at opposite sides of the channel region 131d2, and a gate electrode 155d2 overlapping or facing the channel region 131d2. The gate electrode 155d2 may be a portion of the second scan line 152 (or the third scan line 154). The second electrode 137d2 may be connected to the first electrode 136d1 of the fourth transistor first portion T4_1, and the first electrode 136d2 may be connected to the initialization voltage line 169 through the contact hole 67.

[0107] The fifth transistor T5 may include a channel region 131e, a first electrode 136e and a second electrode 137e disposed at opposite sides of the channel region 131e, and a gate electrode 155e overlapping or facing the channel region 131e. The gate electrode 155e may be a portion of the control line 153. The first electrode 136e may be connected to the third connection member 163 through the contact hole 65, and the second electrode 137e may be connected to the first electrode 136a of the first transistor T1.

[0108] As shown in the cross-sectional view, the third connection member 163 may be included in the third conductive layer (161, 162, 163, 164, and 169). Since the third connection member 163 may extend in the horizontal direction to be connected to the driving voltage line 172 through the contact hole 72, the first electrode 136e may be electrically connected to the driving voltage line 172 to receive the driving voltage ELVDD. The third connection member 163 may extend in the vertical direction to be connected to the extension 157 of the storage line 156 through the contact hole 64 to transmit the driving voltage ELVDD to the storage line 156.

[0109] The sixth transistor T6 may include a channel region 131f, a first electrode 136f and a second electrode 137f disposed at opposite sides of the channel region 131f, and a gate electrode 155f overlapping or facing the channel region 131f. The gate electrode 155f may be a portion of the control line 153. The first electrode 136f may be connected to the second electrode 137a of the first transistor T1, and the second electrode 137f may be connected to the fourth connection member 164 through the contact hole 66.

[0110] As shown in the cross-sectional view, the fourth connection member 164 may be included in the third conductive layer (161, 162, 163, 164, and 169). The fourth connection member 164 may be connected to the connection member 179 disposed in the fourth conductive layer (171, 172, and 179) through the contact hole 73.

[0111] The seventh transistor T7 may include a channel region 131g, a first electrode 136g and a second electrode 137g disposed at opposite sides of the channel region 131g, and a gate electrode 155g overlapping or facing the channel region 131g. The gate electrode 155g may be a portion of the third scan line 154. The first electrode 136g may be connected to the second electrode 137f of the sixth transistor T6, and the second electrode 137g may be connected to the second electrode 137f of the sixth transistor T6 through the contact hole 67 (see FIG. Figure 2 The upper part of the PCB is connected to the initialization voltage line 169 to receive the initialization voltage Vint.

[0112] The capacitor Cst may maintain the voltage of the driving gate electrode 155a. The capacitor Cst may include a first sub-capacitor Cst1 and a second sub-capacitor Cst2.

[0113] The first sub-capacitor Cst1 may include a driving gate electrode 155a and an extension 157 of a storage line 156 overlapping or facing each other in a plan view as two terminals. The extension 157 of the storage line 156 may have an area that may be wider than that of the driving gate electrode 155a in a plan view and may cover the entire area of ​​the driving gate electrode 155a.

[0114] The second sub-capacitor Cst2 may include a first connection member 161 and a driving voltage line 172 (including an extension 178) overlapping or facing each other in a plan view as two terminals. The driving voltage line 172 (including the extension 178) may overlap or face most of the first connection member 161 in a plan view and cover most of the first connection member 161. The extension 178 may appropriately extend in a horizontal direction so that the driving voltage line 172 may overlap or face most of the first connection member 161.

[0115] The driving gate electrode 155a, which may be the first end of the first sub-capacitor Cst1, may be electrically connected to the first connecting member 161, which may be the first end of the second sub-capacitor Cst2, to receive the same voltage. The extension 157 of the storage line 156, which may be the second end of the first sub-capacitor Cst1, may transmit the driving voltage ELVDD like the driving voltage line 172, which may be the second end of the second sub-capacitor Cst2, and the first sub-capacitor Cst1 and the second sub-capacitor Cst2 may have a parallel connection relationship in the circuit. Therefore, even in a narrow space in a plan view, the capacity of the capacitor Cst may be significantly increased, thereby preventing image quality defects such as color deviation and crosstalk between pixels. Even in a high-resolution display device, the capacitance of the capacitor Cst may be effectively ensured to stably maintain the voltage of the driving gate electrode 155a, thereby preventing image quality degradation.

[0116] Reference Figure 2In a plan view, the driving voltage line 172 (including the extension 178) may overlap or face the channel region 131a of the first transistor T1 and cover the channel region 131a of the first transistor T1, and overlap or face at least a portion of the channel regions 131c1 and 131c2 of the third transistor T3. For example, Figure 2 As shown in , the extension 178 of the driving voltage line 172 may cover the entire area of ​​the channel region 131c1 of the third transistor first part T3_1, and may cover some areas of the channel region 131c2 of the third transistor second part T3_2. The extension 178 may also cover the channel region 131c1 of the third transistor T3_1 and the boundary between the first electrode 136c1 and the second electrode 137c1. Therefore, external light may be prevented from being introduced into the channel region 131c1 of the third transistor first part T3_1, which may be directly connected to the driving gate electrode 155a, by the driving voltage line 172 to prevent leakage current from being generated in the third transistor first part T3_1. Since the voltage change at the driving gate electrode 155a caused by external light may be prevented, display defects such as color coordinate changes and brightness changes of the image may be prevented.

[0117] The driving voltage line 172 may cover a large portion of the channel region 131d1 of the fourth transistor first portion T4_1. Therefore, external light may be prevented from being introduced into the channel region 131d1 of the fourth transistor first portion T4_1, which may be directly connected to the driving gate electrode 155a, through the driving voltage line 172 to prevent leakage current from being generated in the fourth transistor first portion T4_1. Therefore, since the voltage variation at the driving gate electrode 155a may be prevented, display defects such as color coordinate variation and brightness variation of an image may be prevented.

[0118] Apart from Figure 2 In addition, refer to Figure 3 and Figure 4 A cross-sectional configuration of a display device according to an embodiment is described.

[0119] The display device according to the embodiment may include a substrate 110. The substrate 110 may include an inorganic insulating material such as glass or an organic insulating material such as plastic (eg, polyimide (PI)). The substrate 110 may have various degrees of flexibility.

[0120] The buffer layer 120 may be disposed on the substrate 110. The buffer layer 120 may prevent impurities from being transferred from the substrate 110 to an upper layer of the buffer layer 120 (specifically, the active layer 130), thereby preventing degradation of characteristics of the active layer 130 and relieving stress. The buffer layer 120 may include an inorganic insulating material such as silicon nitride or silicon oxide, or may include an organic insulating material. A portion or the entire portion of the buffer layer 120 may be omitted.

[0121] The active layer 130 as described above may be disposed on the buffer layer 120, and the first insulating layer 141 may be disposed on the active layer 130. The first insulating layer 141 may include an inorganic insulating material such as silicon nitride or silicon oxide, or may include an organic insulating material.

[0122] A first conductive layer ( 151 , 152 , 153 , 154 , and 155 a ) including scan lines 151 , 152 , and 154 , a control line 153 , and a driving gate electrode 155 a may be disposed on the first insulating layer 141 .

[0123] The second insulating layer 142 may be disposed on the first conductive layer (151, 152, 153, 154, and 155a) and the first insulating layer 141. The second insulating layer 142 may include an inorganic insulating material such as silicon nitride or silicon oxide, or may include an organic insulating material.

[0124] The second conductive layer (156 and 157) including the storage line 156 may be disposed on the second insulating layer 142. The extension 157 of the storage line 156 may overlap the driving gate electrode 155a with the second insulating layer 142 interposed therebetween to form a first sub-capacitor Cst1.

[0125] The third insulating layer 143 may be disposed on the second conductive layer (156 and 157) and the second insulating layer 142. The third insulating layer 143 may include an inorganic insulating material such as silicon nitride or silicon oxide, or may include an organic insulating material.

[0126] The third insulating layer 143 according to the embodiment may include a plurality of layers. For example, the third insulating layer 143 may include a first sub-insulating layer 143 - 1 and a second sub-insulating layer 143 - 2 .

[0127] The first sub-insulating layer 143-1 and the second sub-insulating layer 143-2 may include different materials. The first sub-insulating layer 143-1 and the second sub-insulating layer 143-2 including different materials may have different etching rates for the same etchant. For example, the material included in the second sub-insulating layer 143-2 may have an etching rate higher than the etching rate of the material included in the third conductive layer (161, 162, 163, 164, and 169), and the material included in the third conductive layer (161, 162, 163, 164, and 169) may have an etching rate higher than the etching rate of the material included in the first sub-insulating layer 143-1. For example, the first sub-insulating layer 143-1 may include silicon oxide, the second sub-insulating layer 143-2 may include silicon nitride, and the third conductive layer (161, 162, 163, 164, and 169) may include titanium (Ti).

[0128] The thickness d1 of the first sub-insulating layer 143-1 and the thickness d2 of the second sub-insulating layer 143-2 may be different. The thickness d1 of the first sub-insulating layer 143-1 may be in the range of about 2500 angstroms to about 3500 angstroms, and the thickness d2 of the second sub-insulating layer 143-2 may be in the range of about 900 angstroms to about 1400 angstroms. The sum of the thickness of the first sub-insulating layer 143-1 and the thickness of the second sub-insulating layer 143-2 may be less than or equal to about 5000 angstroms (e.g., less than or equal to about 4000 angstroms). In the case where the sum of the thickness of the first sub-insulating layer 143-1 and the thickness of the second sub-insulating layer 143-2 may exceed about 5000 angstroms, it may be difficult to form a contact hole extending through the first insulating layer 141, the second insulating layer 142, and the third insulating layer 143, and the display device may become unnecessarily thick.

[0129] The first sub-insulating layer 143-1 may overlap or face the front surface of the substrate 110 except for the region where the contact hole may be formed. The second sub-insulating layer 143-2 may have a planar shape substantially the same as the third conductive layer (161, 162, 163, 164, and 169). In other words, the edge of the second sub-insulating layer 143-2 and the edge of the third conductive layer (161, 162, 163, 164, and 169) may substantially overlap or face each other. The edge of the second sub-insulating layer 143-2 and the edge of the third conductive layer (161, 162, 163, 164, and 169) may substantially overlap or face each other along the thickness direction of the display device. As another example, the edge of the second sub-insulating layer 143-2 and the edge of the third conductive layer (161, 162, 163, 164, and 169) may be substantially parallel in the thickness direction of the display device.

[0130] The third insulating layer 143 including the first sub-insulating layer 143-1 and the second sub-insulating layer 143-2 may have different thicknesses at different regions thereof. For example, a portion of the third insulating layer 143 overlapping or facing the third conductive layer (161, 162, 163, 164, and 169) may have a thickness thicker than the thickness of the remaining portion not overlapping or facing the third conductive layer (161, 162, 163, 164, and 169). For example, the third insulating layer 143 may have different thicknesses at a first region overlapping or facing the third conductive layer (161, 162, 163, 164, and 169) and at a second region not overlapping or facing the third conductive layer (161, 162, 163, 164, and 169), and thus be divided into a first region and a second region.

[0131] The third insulating layer 143 may have a contact hole 64 positioned on the extension 157 of the storage line 156. The second insulating layer 142 and the third insulating layer 143 may have a contact hole 61 positioned on the driving gate electrode 155a. The first insulating layer 141, the second insulating layer 142, and the third insulating layer 143 may have a contact hole 62, a contact hole 63, a contact hole 65, a contact hole 66, and a contact hole 67, the contact hole 62 being positioned on a portion where the second electrode 137c1 of the third transistor first portion T3_1 and the second electrode 137d1 of the fourth transistor first portion T4_1 meet each other, the contact hole 63 being positioned on the first electrode 136b of the second transistor T2, the contact hole 65 being positioned on the first electrode 136e of the fifth transistor T5, the contact hole 66 being positioned on the second electrode 137f of the sixth transistor T6, and the contact hole 67 being positioned on a portion where the first electrode 136d2 of the fourth transistor second portion T4_2 and the second electrode 137g of the seventh transistor T7 meet each other.

[0132] A third conductive layer ( 161 , 162 , 163 , 164 , and 169 ) including an initialization voltage line 169 and a connection member ( 161 , 162 , 163 , and 164 ) may be disposed on the third insulating layer 143 .

[0133] The third conductive layer (161, 162, 163, 164, and 169) may have at least a double-layer structure. The third conductive layer (161, 162, 163, 164, and 169) having a double-layer structure may include different materials. For example, the third conductive layer (161, 162, 163, 164, and 169) may include a lower layer (161-1, 162-1, 163-1, 164-1, and 169-1) including titanium (Ti) and an upper layer (161-2, 162-2, 163-2, 164-2, and 169-2) including molybdenum.

[0134] The lower layers (161-1, 162-1, 163-1, 164-1, and 169-1) and the upper layers (161-2, 162-2, 163-2, 164-2, and 169-2) included in the third conductive layer (161, 162, 163, 164, and 169) may have different thicknesses. The lower layer (161-1, 162-1, 163-1, 164-1 and 169-1) can be thinner than the upper layer (161-2, 162-2, 163-2, 164-2 and 169-2), for example, the thickness of the lower layer (161-1, 162-1, 163-1, 164-1 and 169-1) can be in the range of about 300 angstroms to about 700 angstroms, and the thickness of the upper layer (161-2, 162-2, 163-2, 164-2 and 169-2) can be in the range of about 2200 angstroms to about 2800 angstroms.

[0135] Reference Figure 5 , the second sub-insulating layer 143-2 may include: a first region R1, overlapping or facing the first connection member 161 included in the third conductive layer (161, 162, 163, 164, and 169); a second region R2, overlapping or facing the second connection member 162 included in the third conductive layer (161, 162, 163, 164, and 169); a third region R3, overlapping or facing the third connection member 163 included in the third conductive layer (161, 162, 163, 164, and 169); a fourth region R4, overlapping or facing the fourth connection member 164; and a fifth region R5, overlapping or facing the initialization voltage line 169. Although the embodiment provides that the second sub-insulating layer 143-2 may include the first region R1 to the fifth region R5, the embodiment may not be limited thereto. For example, embodiments may include a plurality of regions including a planar surface having a shape substantially the same as that of the third conductive layer ( 161 , 162 , 163 , 164 , and 169 ).

[0136] The first region R1, the second region R2, the third region R3, and the fourth region R4 may be spaced apart from each other in a plan view. Each of the first region R1, the second region R2, the third region R3, and the fourth region R4 may have an island shape. Figure 5 As shown in , a portion of the fifth region R5 overlapping or facing the initialization voltage line 169 may be connected to another portion of the fifth region R5 positioned in a pixel adjacent thereto in the horizontal direction. For example, the fifth region R5 may have a shape extending in the horizontal direction in a plan view.

[0137] The second sub-insulating layer 143-2 may be provided only in the region of one pixel, for example, in the region overlapping or facing the third conductive layer (161, 162, 163, 164, and 169). Therefore, the third insulating layer 143 may have different thicknesses according to its region. For example, the portion of the third insulating layer 143 overlapping or facing the third conductive layer (161, 162, 163, 164, and 169) may have a thickness thicker than the remaining portion of the third insulating layer 143 that does not overlap or face the third conductive layer (161, 162, 163, 164, and 169). In other words, the third insulating layer 143 may have different thicknesses at the first region overlapping or facing the third conductive layer (161, 162, 163, 164, and 169) and at the second region not overlapping or facing the third conductive layer (161, 162, 163, 164, and 169), and thus be divided into the first region and the second region.

[0138] According to an embodiment, the third conductive layer (161, 162, 163, 164, and 169) may overlap or face the first sub-insulating layer 143-1 and the second sub-insulating layer 143-2. ​​A region in which the third conductive layer (161, 162, 163, 164, and 169) may not be disposed may overlap or face the first sub-insulating layer 143-1, but may not overlap or face the second sub-insulating layer 143-2.

[0139] Reference Figure 3 and Figure 4 , the edge of the second sub-insulating layer 143-2 may have a tapered shape. As shown, the edge of the second sub-insulating layer 143-2 may protrude beyond the edge of the third conductive layer (161, 162, 163, 164, and 169).

[0140] Although the first region R1, the second region R2, the third region R3, the fourth region R4, and the fifth region R5 have been described as having edges substantially the same as the edges of the third conductive layer (161, 162, 163, 164, and 169) (i.e., aligned edges), it may be difficult to construct them identically to each other. Therefore, the case where all have substantially the same or aligned edges may include a case where the distance between the edge of the second sub-insulating layer 143-2 and the edge of the third conductive layer (161, 162, 163, 164, and 169) may be less than or equal to about a few nanometers to about tens of nanometers. In other words, even if the edge of the second sub-insulating layer 143-2 and the edge of the third conductive layer (161, 162, 163, 164, and 169) may be offset according to the aforementioned amount, the edge of the second sub-insulating layer 143-2 and the edge of the third conductive layer (161, 162, 163, 164, and 169) may also be substantially the same to be substantially aligned with each other.

[0141] The initialization voltage line 169 may be electrically connected to the first electrode 136d2 of the fourth transistor second portion T4_2 and the second electrode 137g of the seventh transistor T7 through the contact hole 67. The first connection member 161 may be electrically connected to the driving gate electrode 155a, the second electrode 137c1 of the third transistor first portion T3_1, and the second electrode 137d1 of the fourth transistor first portion T4_1 through the contact holes 61 and 62. The second connection member 162 may be electrically connected to the first electrode 136b of the second transistor T2 through the contact hole 63. The third connection member 163 may be electrically connected to the extension 157 of the storage line 156 and the first electrode 136e of the fifth transistor T5 through the contact holes 64 and 65. The fourth connection member 164 may be electrically connected to the second electrode 137f of the sixth transistor T6 through the contact hole 66.

[0142] The fourth insulating layer 144 may be disposed on the third conductive layer ( 161 , 162 , 163 , 164 , and 169 ) and the third insulating layer 143 .

[0143] The fourth insulating layer 144 may include a contact hole 71 positioned on the second connection member 162 , a contact hole 72 positioned on the third connection member 163 , and a contact hole 73 positioned on the fourth connection member 164 .

[0144] The fourth insulating layer 144 may include an inorganic insulating material such as silicon nitride or silicon oxide, and / or may include an organic insulating material. The fourth insulating layer 144 according to the embodiment may directly contact the first sub-insulating layer 143-1 in a region where the second sub-insulating layer 143-2 may not be provided (i.e., the third conductive layer (161, 162, 163, 164, and 169) may not be provided).

[0145] A fourth conductive layer (171, 172, and 179) including a data line 171, a driving voltage line 172, a connecting member 179, etc. may be disposed on the fourth insulating layer 144. The data line 171 may be electrically connected to the second connecting member 162 through a contact hole 71. The driving voltage line 172 may be electrically connected to the third connecting member 163 through a contact hole 72. The connecting member 179 may be electrically connected to the fourth connecting member 164 through a contact hole 73.

[0146] The driving voltage line 172 (including the extension 178 ) may overlap or face the first connection member 161 with the fourth insulating layer 144 interposed therebetween to form the second sub capacitor Cst2 .

[0147] At least one of the first conductive layer (151, 152, 153, 154 and 155a), the second conductive layer (156 and 157) and the fourth conductive layer (171, 172 and 179) may include a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta) and an alloy of at least two of the above metals.

[0148] The passivation layer 180 may be disposed on the fourth conductive layer (171, 172, and 179) and the fourth insulating layer 144. The passivation layer 180 may include an organic insulating material such as a polypropylene resin or a polyimide resin. The top surface of the passivation layer 180 may be substantially flat. The passivation layer 180 may include a contact hole 89 disposed on the connection member 179.

[0149] A fifth conductive layer (191) including pixel electrodes 191 may be disposed on the passivation layer 180. Each pixel electrode 191 may be connected to the connection member 179 through a contact hole 89 to receive a voltage. The pixel electrodes 191 may be arranged in a PENTILE matrix structure.

[0150] The partition wall 350 may be disposed on the passivation layer 180 and the pixel electrode 191. The partition wall 350 may have an opening positioned on each pixel electrode 191.

[0151] The emission layer 370 may be disposed on the pixel electrode 191. The emission layer 370 may be positioned in the opening of the partition wall 350. The emission layer 370 may include an organic emission material or an inorganic emission material.

[0152] The common electrode 270 may be disposed on the emission layer 370. The common electrode 270 may also be disposed on the partition wall 350 to extend over a plurality of pixels.

[0153] The pixel electrode 191, the emission layer 370, and the common electrode 270 constitute a light emitting diode ED.

[0154] A sealing layer (not shown) may be further disposed on the common electrode 270 to protect the light emitting diode ED. The sealing layer may include an inorganic film and an organic film that may be alternately stacked, or may include only an inorganic film or only an organic film.

[0155] Reference Figure 6, the first connection member 161 may include a portion overlapping or facing the driving gate electrode 155a in a plan view to be connected to the driving gate electrode 155a through the contact hole 61. The plane area of ​​the first sub-capacitor Cst1 (indicated by a dotted line) and the plane area of ​​the second sub-capacitor Cst2 (indicated by a dotted line) may at least partially overlap or face each other. For example, the lower portion of the plane area of ​​the second sub-capacitor Cst2 may overlap or face the plane area of ​​the first sub-capacitor Cst1, and the plane area of ​​the second sub-capacitor Cst2 may have a shape extending in an upward direction from the overlapping area or the facing area.

[0156] Figure 7 Schematic cross-sectional arrangement of conductors constituting terminals of the first sub-capacitor Cst1 and the second sub-capacitor Cst2 on the substrate 110 is shown. Figure 7 The first connection member 161 that may be electrically connected to the driving gate electrode 155a may receive the same voltage V1 as the driving gate electrode 155a. The extension portion 157 of the storage line 156 that may be electrically connected to the driving voltage line 172 may receive the same voltage V2 as the driving voltage line 172.

[0157] When viewed in cross section, the driving gate electrode 155a, the extension 157 of the storage line 156, the first connection member 161, and the driving voltage line 172 may be sequentially disposed on the substrate 110. The driving gate electrode 155a and the extension 157 of the storage line 156, which may be adjacent to each other with an insulating layer interposed therebetween, may constitute a first sub-capacitor Cst1. The first connection member 161 and the driving voltage line 172, which may be adjacent to each other with an insulating layer interposed therebetween, may constitute a second sub-capacitor Cst2. Therefore, the four conductors forming the terminals of the first sub-capacitor Cst1 and the terminals of the second sub-capacitor Cst2 may be alternately disposed. Therefore, the first sub-capacitor Cst1 and the second sub-capacitor Cst2 may be effectively formed in a limited planar space.

[0158] The first connection member 161 may also constitute an additional sub-capacitor (not shown) by overlapping or facing the extension portion 157 of the adjacent storage line 156 with an insulating layer interposed therebetween. Considering the additional sub-capacitor, the capacitor Cst according to the embodiment may be considered to include at least three sub-capacitors connected in parallel to each other.

[0159] Therefore, even in a limited planar space, at least two sub-capacitors Cst1 and Cst2 connected in parallel can be formed using four conductors arranged in different conductive layers, thereby increasing the capacitance of the capacitor Cst by more than two times. Figure 6As shown in FIG. 1 , at least two sub-capacitors Cst1 and Cst2 may at least partially overlap or face each other in a plan view, thereby maximizing the efficiency of the space that can be utilized within the display device. Therefore, a display device having a high resolution may be provided and a capacitor Cst having a sufficient capacity may be provided, thereby preventing the occurrence of image quality defects such as color deviation and crosstalk.

[0160] In another example, only one of the first sub-capacitor Cst1 and the second sub-capacitor Cst2 may be selected according to design requirements, thereby further increasing the degree of freedom in designing the display device.

[0161] Refer to the following Figure 8 , the active layer 130 of the display device according to the embodiment is discussed.

[0162] Reference Figure 8 , the width W0 of the continuous portion of the active layer 130 may be substantially constant. However, in order to electrically connect constituent elements of another layer, the planar width of the active layer 130 may be increased where the active layer 130 may overlap with the contact holes 62, 63, 65, 66, and 67. For example, a first width W1 (which may be a horizontal width) of an end portion of the first electrode 136b of the second transistor T2 in the active layer 130 overlapping or facing the contact hole 63 may be greater than a width of a portion of the active layer 130 positioned around the end portion. Similarly, a second width W2 (which may be a horizontal width) of an end portion of the first electrode 136e of the fifth transistor T5 in the active layer 130 overlapping or facing the contact hole 65 may also be greater than a width of a portion of the active layer 130 positioned around the end portion. The second width W2 may be greater than the first width W1, and thus a margin of space where the contact hole 65 may overlap or face the active layer 130 may be greater. According to an embodiment, as Figure 8 As shown in the figure, the second width W2 of the portion of the active layer 130 overlapping or facing the contact hole 65 can extend beyond other portions, thereby reducing the risk of short circuit, and the third conductive layer (161, 162, 163, 164 and 169) and the fourth conductive layer (171, 172 and 179) transmitting different voltages at the other portions have a high risk of short circuit.

[0163] The first connection member 161 and the driving voltage line 172 may overlap or face each other on a portion of the active layer 130 overlapping or facing the contact hole 62, and because the first connection member 161 and the driving voltage line 172 transmit different voltages, a short circuit should not occur. Therefore, when the contact hole 62 may be formed, in order to ensure a process margin so that the contact hole 62 does not escape the active layer 130, the risk of a short circuit may be reduced by increasing a third width W3 (which may be shown as a vertical width for convenience, but may also be a horizontal width) of a portion of the active layer 130 where the active layer 130 overlaps or faces the contact hole 62 (i.e., where the second electrode 137c1 of the third transistor first portion T3_1 and the second electrode 137d1 of the fourth transistor first portion T4_1 meet), wherein the third width W3 is greater than the first width W1.

[0164] Refer to the following Fig. 9 A cross section of a region of a display device according to an embodiment is discussed.

[0165] Reference Fig. 9 , the end of the second sub-insulating layer 143-2 may be aligned with the edge of the third conductive layer (161, 162, 163, 164, and 169). According to the process margin, the edge of the second sub-insulating layer 143-2 may be substantially aligned in the same plane as the edge of the third conductive layer (161, 162, 163, 164, and 169). The planar shape of the second sub-insulating layer 143-2 and the planar shape of the third conductive layer (161, 162, 163, 164, and 169) may be substantially the same. In other words, the edge of the second sub-insulating layer 143-2 and the edge of the third conductive layer (161, 162, 163, 164, and 169) may be substantially parallel to each other to overlap or face each other along the thickness direction of the display device.

[0166] Below and Figures 1 to 4 Refer to Figures 10 to 30 A method for manufacturing a display device according to an embodiment will be discussed.

[0167] Reference Figures 10 to 12 , an inorganic insulating material and / or an organic insulating material may be stacked on the substrate 110 to form a buffer layer 120. A semiconductor pattern 130p may be formed on the buffer layer 120 by stacking and patterning a semiconductor material such as amorphous silicon, polycrystalline silicon, an oxide semiconductor, etc. This patterning process may include a photolithography process in which a mask pattern may be formed and then the mask pattern may be etched by an exposure and development process using a photomask, or various processes known to those skilled in the art. The overall planar shape of the semiconductor pattern 130p may be the same as the planar shape of the active layer 130 described above.

[0168] Reference Figures 13 to 15 , you can Figures 10 to 12 Inorganic insulating materials such as silicon nitride or silicon oxide and / or organic insulating materials are stacked on the semiconductor pattern 130p shown in FIG. 1 to form a first insulating layer 141. A conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy of at least two thereof may be stacked on the first insulating layer 141 and patterned to form a first conductive layer (151, 152, 153, 154, and 155a) including scan lines 151, 152, and 154, a control line 153, and a driving gate electrode 155a.

[0169] The first conductive layer (151, 152, 153, 154 and 155a) may include gate electrodes 155a, 155b, 155c1, 155c2, 155d1, 155d2, 155e, 155f and 155g of the aforementioned first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6 and seventh transistor T7.

[0170] The active layer 130 including the channel regions 131a, 131b, 131c1, 131c2, 131d1, 131d2, 131e, 131f, and 131g and the conductive regions 136a, 136b, 136c1, 136c2, 136d1, 136d2, 136e, 136f, 136g, 137a, 137b, 137c1, 137c2, 137d1, 137d2, 137e, 137f, and 137g may be completed by doping the semiconductor pattern with N-type or P-type impurities using the first conductive layer (151, 152, 153, 154, and 155a) as a mask. Thus, the transistors T1, T2, T3, T4, T5, T6, and T7 as described above may be formed.

[0171] Reference Figures 16 to 18 , the second insulating layer 142 may be formed by stacking an inorganic insulating material and / or an organic insulating material such as silicon nitride or silicon oxide on the first insulating layer 141 and the first conductive layer (151, 152, 153, 154, and 155a). A conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy of at least two thereof may be stacked on the second insulating layer 142 and patterned to form a second conductive layer (156 and 157) including a storage line 156 including an extension 157 and an opening 51.

[0172] Reference Figures 19 to 21, an inorganic insulating material such as silicon nitride or silicon oxide and / or an organic insulating material may be stacked on the second insulating layer 142 and the second conductive layer ( 156 and 157 ) to form a first sub-insulating material layer 143 - a and a second sub-insulating material layer 143 - b .

[0173] The first insulating layer 141, the second insulating layer 142, the first sub-insulating material layer 143-a, and the second sub-insulating material layer 143-b may be patterned by a photolithography process, etc. to have contact holes 61, 62, 63, 64, 65, 66, and 67 that pass through some or all of the first insulating layer 141, the second insulating layer 142, the first sub-insulating material layer 143-a, and the second sub-insulating material layer 143-b. As described above, since the active layer 130 disposed in the portion where the contact holes 62 and 65 are located may be sufficiently extended, the contact holes 62 and 65 may have a sufficient process margin to be formed only on the active layer 130.

[0174] Reference Figure 22 to Figure 24 A conductive material such as an alloy of at least two of copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), and tantalum (Ta) can be stacked on the second sub-insulating material layer 143-b and patterned to form a third conductive layer (161, 162, 163, 164, and 169) including an initialization voltage line 169 and connecting members 161, 162, 163, and 164.

[0175] According to an embodiment, the third conductive layer (161, 162, 163, 164, and 169) may have at least a double-layer structure. The third conductive layer (161, 162, 163, 164, and 169) having a double-layer structure may include different materials. For example, the third conductive layer (161, 162, 163, 164, and 169) may include a lower layer (161-1, 162-1, 163-1, 164-1, and 169-1) including titanium (Ti) and an upper layer (161-2, 162-2, 163-2, 164-2, and 169-2) including molybdenum.

[0176] The lower layer (161-1, 162-1, 163-1, 164-1, and 169-1) and the upper layer (161-2, 162-2, 163-2, 164-2, and 169-2) included in the third conductive layer (161, 162, 163, 164, and 169) may have different thicknesses. The lower layer (161-1, 162-1, 163-1, 164-1, and 169-1) may be thinner than the upper layer (161-2, 162-2, 163-2, 164-2, and 169-2). For example, the thickness of the lower layer (161-1, 162-1, 163-1, 164-1 and 169-1) may be in the range of about 300 angstroms to about 700 angstroms, and the thickness of the upper layer (161-2, 162-2, 163-2, 164-2 and 169-2) may be in the range of about 2200 angstroms to about 2800 angstroms.

[0177] The second sub-insulating layer 143 - 2 may be formed in the process of patterning the third conductive layer ( 161 , 162 , 163 , 164 , and 169 ).

[0178] The third conductive layer (161, 162, 163, 164, and 169) may include lower layers (161-1, 162-1, 163-1, 164-1, and 169-1) and upper layers (161-2, 162-2, 163-2, 164-2, and 169-2) that may have different materials. The lower layers (161-1, 162-1, 163-1, 164-1, and 169-1) and upper layers (161-2, 162-2, 163-2, 164-2, and 169-2) included in the third conductive layer (161, 162, 163, 164, and 169) may be patterned by the same etching process. The lower layer (161-1, 162-1, 163-1, 164-1 and 169-1) and the upper layer (161-2, 162-2, 163-2, 164-2 and 169-2) including different materials may have different etching conditions. In order to simultaneously pattern the lower layer (161-1, 162-1, 163-1, 164-1 and 169-1) and the upper layer (161-2, 162-2, 163-2, 164-2 and 169-2), patterning may be performed based on the layer that requires greater etching power. According to an embodiment, the patterning conditions may be set based on the lower layer (161-1, 162-1, 163-1, 164-1 and 169-1) including titanium (Ti).

[0179] In the case where the lower layers (161-1, 162-1, 163-1, 164-1 and 169-1) and the upper layers (161-2, 162-2, 163-2, 164-2 and 169-2) having different etching levels can be patterned in the same process, the area of ​​the second sub-insulating material layer 143-b overlapping or facing the third conductive layer (161, 162, 163, 164 and 169) may not be etched because of the third conductive layer (161, 162, 163, 164 and 169) used as a mask, while the area of ​​the second sub-insulating material layer 143-b not overlapping or facing the third conductive layer (161, 162, 163, 164 and 169) may be removed by the etching process due to being exposed by the third conductive layer (161, 162, 163, 164 and 169). The second sub-insulating layer 143-2 may be formed to have a planar shape substantially the same as that of the third conductive layer (161, 162, 163, 164, and 169). In other words, the edge of the second sub-insulating layer 143-2 and the edge of the third conductive layer (161, 162, 163, 164, and 169) may be formed to substantially overlap or face each other. The edge of the second sub-insulating layer 143-2 and the edge of the third conductive layer (161, 162, 163, 164, and 169) may be formed to substantially overlap or face each other along the thickness direction of the display device. As another example, the edge of the second sub-insulating layer 143-2 and the edge of the third conductive layer (161, 162, 163, 164, and 169) may be substantially parallel in the thickness direction of the display device.

[0180] The thickness of the second sub-insulating layer 143-2 may be greater than or equal to about 900 angstroms or greater, but less than or equal to about 1400 angstroms. In the case where the thickness of the second sub-insulating layer 143-2 may be less than about 900 angstroms, after the portion of the second sub-insulating layer 143-2 exposed by the third conductive layer (161, 162, 163, 164, and 169) is completely removed, the first sub-insulating layer 143-1 may be damaged, or conversely, in the case of etching the first sub-insulating layer 143-1, an insulating layer having an uneven thickness may be provided. In the case where the thickness of the second sub-insulating layer 143-2 may be greater than about 1400 angstroms, the second sub-insulating layer 143-2 may not be completely removed, and some of the second sub-insulating layer 143-2 may remain in some areas during the etching process of forming the third conductive layer (161, 162, 163, 164, and 169). This may also result in providing an insulating layer of uneven thickness.

[0181] According to an embodiment, the etching rate of the second sub-insulating layer 143-2 for the same etching conditions can be greater than the etching rate of the lower layer (161-1, 162-1, 163-1, 164-1, and 169-1) of the third conductive layer (161, 162, 163, 164, and 169). The second sub-insulating material layer 143-b exposed by the third conductive layer (161, 162, 163, 164, and 169) can be easily patterned in the process of etching the third conductive layer (161, 162, 163, 164, and 169).

[0182] For the same etching condition, the etching rate of the first sub-insulating layer 143-1 may be lower than the etching rate of the second sub-insulating layer 143-2, and may be lower than the etching rate of the lower layer (161-1, 162-1, 163-1, 164-1, and 169-1) of the third conductive layer (161, 162, 163, 164, and 169). In the area exposed by the third conductive layer (161, 162, 163, 164, and 169), the first sub-insulating layer 143-1 may be exposed to the etching process after the second sub-insulating layer 143-2 is patterned. However, since the etching rate of the first sub-insulating layer 143-1 is relatively low, a certain thickness may be maintained without being etched during the predetermined etching process.

[0183] The second sub-insulating layer 143-2 may include silicon nitride, the first sub-insulating layer 143-1 may include silicon oxide, and the lower layer (161-1, 162-1, 163-1, 164-1, and 169-1) may include titanium (Ti). A predetermined etchant used in the process of patterning the lower layer (161-1, 162-1, 163-1, 164-1, and 169-1) containing titanium may form the second sub-insulating layer 143-2 while simultaneously etching the lower layer (161-1, 162-1, 163-1, 164-1, and 169-1). Since the etching rate of the first sub-insulating layer 143-1 is relatively low after the second sub-insulating layer 143-2 is formed, the first sub-insulating layer 143-1 may not be etched.

[0184] Unlike the embodiments here, that is, in the comparative example, when the etching rate of the first sub-insulating layer 143-1 is relatively larger than the etching rate of the lower layer (161-1, 162-1, 163-1, 164-1 and 169-1) and the etching rate of the second sub-insulating layer 143-2 is lower than the etching rate of the lower layer (161-1, 162-1, 163-1, 164-1 and 169-1), undercutting occurs in the third conductive layer (161, 162, 163, 164 and 169).

[0185] For example, in the process of patterning the lower layer (161-1, 162-1, 163-1, 164-1 and 169-1) of the third conductive layer (161, 162, 163, 164 and 169), in the case where the etching rate of the lower layer (161-1, 162-1, 163-1, 164-1 and 169-1) may be greater than the etching rate of the second sub-insulating material layer 143-b, the lower layer (161-1, 162-1, 163-1, 164-1 and 169-1) itself may be continuously etched instead of etching the second sub-insulating material layer 143-b having a relatively low etching rate, and thus the third conductive layer (161, 162, 163, 164 and 169) may include an undercut that may cause wiring failure.

[0186] Reference Figure 25 to Figure 27 The fourth insulating layer 144 may be formed by stacking an inorganic insulating material and / or an organic insulating material such as silicon nitride or silicon oxide on the third insulating layer 143 and the third conductive layer (161, 162, 163, 164, and 169). The fourth insulating layer 144 may have contact holes 71, 72, and 73 that may be patterned by a photolithography process or the like.

[0187] Reference Figures 28 to 30 A conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta) or an alloy of at least two thereof may be stacked on the fourth insulating layer 144, and the conductive material may be patterned to form a fourth conductive layer (171, 172 and 179) including a data line 171, a driving voltage line 172 and a connecting member 179.

[0188] Reference Figures 2 to 4 , a passivation layer 180 may be formed by stacking an organic insulating material or an inorganic insulating material on the fourth conductive layer ( 171 , 172 , and 179 ) and the fourth insulating layer 144 , and patterning the passivation layer 180 to form a contact hole 89 on the connection member 179 .

[0189] A conductive material such as ITO may be stacked on the passivation layer 180, and the conductive material may be patterned to form a fifth conductive layer 191 including a pixel electrode 191. A partition wall 350 may be formed on the pixel electrode 191 and the passivation layer 180, and an emission layer 370 and a common electrode 270 may be sequentially formed to form a light emitting diode ED. A sealing layer (not shown) for sealing the light emitting diode ED may be further formed.

[0190] Fig.31 An image is shown when the second sub-insulating layer according to a comparative example different from the embodiments herein may have a thickness of about 2000 angstroms. Fig.31, it can be seen that the second sub-insulating layer including silicon nitride and having a thickness of 2000 angstroms disposed under titanium (Ti) can be etched in the process of patterning the third conductive layer including molybdenum (Mo) and titanium (Ti). However, it is confirmed that the second sub-insulating layer including silicon nitride is not completely etched, and is only etched by about 1000 angstroms to about 1400 angstroms in the region exposed by the third conductive layer.

[0191] Reference Fig.32A , it can be seen that the second sub-insulating layer can be Fig.31 In particular, the etching degree is quite uneven (eg, the area between the inner circle and the outer circle).

[0192] Fig.32B Shows the settings in Fig.32A The cross-sectional image of a portion of the pixel in the aforementioned region (i.e., the region between the inner circle and the outer circle) in FIG. 1 is shown in FIG. 2 . The thickness of the second sub-insulating layer is found to be about Fig.32C Shows the settings in addition to Fig.32A A cross-sectional image of a portion of pixels in an area outside the area in . Fig.32C It is found that the thickness of the second sub-insulating layer is about As a result, it can be seen that the thickness of the second sub-insulating layer is significantly non-uniform in the aforementioned region (ie, the region between the inner circle and the outer circle). Such non-uniform thickness of the insulating layer may undesirably cause embossed spots.

[0193] However, according to the embodiments herein, in order to prevent the occurrence of embossed spots, the display device may include a process of completely etching the second sub-insulating layer 143-2 exposed by the third conductive layer (161, 162, 163, 164 and 169), so that the edge of the second sub-insulating layer 143-2 and the edge of the third conductive layer (161, 162, 163, 164 and 169) can be set to be substantially parallel to each other so as to overlap or face each other along the thickness direction of the display device.

[0194] like Fig.33 As shown in , it can be seen that the second sub-insulating layer 143-2 including silicon nitride can have a thickness of about 1000 angstroms, and the second sub-insulating layer 143-2 exposed by the third conductive layer (161, 162, 163, 164, and 169) can be completely etched in the process of etching the third conductive layer (161, 162, 163, 164, and 169). It can be confirmed that the first sub-insulating layer 143-1 exposed by the second sub-insulating layer 143-2 and including silicon oxide can be not damaged at all by the selection of the etchant. According to the embodiment, it is therefore possible to provide a display device with improved display quality by providing an insulating layer with a uniform thickness.

[0195] Reference FIG. 34A to FIG. 34D , Fig.34A A comparative example is shown in which the upper layer included in the third conductive layer may be formed of Mo to have The lower layer may be formed of Ti to have a thickness of The first sub-insulating layer may be made of SiO 2 Formed with The second sub-insulating layer may be made of SiN x Formed with Thickness. Fig.34B A comparative example is shown in which the upper layer included in the third conductive layer may be formed of Mo to have The lower layer may be formed of Ti to have a thickness of The thickness of the comparative example includes SiO 2 、SiN x and SiO 2 Stack in this order from the bottom to have and The thickness of the insulation layer. Fig.34C A comparative example is shown in which the upper layer included in the third conductive layer may be formed of Mo to have The lower layer may be formed of Ti to have a thickness of The comparative example includes a SiO 2 、SiN x and SiO 2 Stack in this order from the bottom to have and The thickness of the insulation layer. Fig.34D An example is shown in which the upper layers (161-2, 162-2, 163-2, 164-2, and 169-2) included in the third conductive layers (161, 162, 163, 164, and 169) may be formed of Mo to have The lower layer (161-1, 162-1, 163-1, 164-1 and 169-1) may be formed of Ti to have a thickness of The first sub-insulating layer 143-1 may be made of SiO 2 Formed with The second sub-insulating layer 143-2 may be made of SiN x Formed with Thickness.

[0196] Reference Fig.34A , it can be seen that with about Thickness of SiN xAs a result, as shown in reference FIG. 32A to FIG. 32C As described above, there may be a problem that the etching of the insulating layer becomes uneven in some areas and appears as spots. Fig.34B and Fig.34C , the insulating layer adjacent to the conductive layer is made of SiO 2 In the case of the formation, it can be seen that undercutting occurs in the lower layer containing Ti. This is because the etching selectivity is SiN x >Ti>SiO 2 , so when the second sub-insulating layer is made of SiO 2 When formed, the lower layer including Ti may be over-etched. When undercut occurs in the conductive layer including Ti, driving failure may increase to 30% or more. Fig.34D , including SiN x In a case where the second sub-insulating layer 143 - 2 may be disposed adjacent to the conductive layer, all of the second sub-insulating layer 143 - 2 is etched in a region not overlapping the conductive layer.

[0197] Therefore, according to an embodiment, the second sub-insulating layer may include at least or at least The thickness of SiN x , so as to be completely etched in the area not overlapping with the conductive layer.

[0198] Although the embodiments herein have been described above, it will be understood that such embodiments may not be limited to the descriptions given, but on the contrary, such embodiments are intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, the display device include: substrate; An active layer, disposed on the substrate; A first conductive layer including a driving gate electrode and a scanning line extending in a first direction; a second conductive layer including a storage line; a third conductive layer including a first connecting member disposed above the storage line; an insulating layer disposed between the storage line and the first connection member and including a first sub-insulating layer disposed on the second conductive layer and a second sub-insulating layer disposed under the third conductive layer; as well as The data lines and the driving voltage lines both cross the scanning lines and extend in the second direction, in, The first connection member electrically connects the driving gate electrode to the active layer. The driving voltage line overlaps at least a portion of the first connecting member, An edge of the second sub-insulating layer is disposed outside an edge of the third conductive layer in a plan view.

2. The display device according to claim 1, in, The edge of the second sub-insulating layer is parallel to the edge of the third conductive layer in a thickness direction of the display device.

3. The display device according to claim 1, in, The second sub-insulating layer and the third conductive layer have the same shape in a plan view.

4. The display device according to claim 1, in, The edge of the second sub-insulating layer is offset from the edge of the third conductive layer in a plan view.

5. The display device according to claim 1, in, The third conductive layer further includes a second connection member, a third connection member, a fourth connection member, and an initialization voltage line disposed on the same layer as the first connection member.

6. The display device according to claim 5, in, The second sub-insulating layer comprises: a first region overlapping the first connecting member; a second region overlapping the second connecting member; a third region overlapping the third connecting member; a fourth region overlapping the fourth connecting member; and A fifth region overlaps the initialization voltage line.

7. The display device according to claim 6, in, The first to fifth regions are spaced apart from each other in a plan view.

8. The display device according to claim 6, in, The fifth region extends along the first direction.

9. The display device according to claim 1, in, The first sub-insulating layer and the second sub-insulating layer include different materials.

10. The display device according to claim 9, in, The first sub-insulating layer includes silicon oxide, and the second sub-insulating layer includes silicon nitride.

11. The display device according to claim 1, in, The thickness of the first sub-insulating layer is greater than that of the second sub-insulating layer.

12. The display device according to claim 1, in, The third conductive layer includes a lower layer and an upper layer, The lower layer comprises titanium, and The upper layer includes molybdenum.

13. The display device according to claim 1, in, The edge of the second sub-insulating layer has a tapered shape.

14. The display device according to claim 13, in, The tapered shape of the edge of the second sub-insulating layer is disposed outside an edge of the first connecting member.

15. A display device, the display device include: substrate; An active layer, disposed on the substrate; A first conductive layer including a driving gate electrode and a scanning line extending in a first direction; A second conductive layer includes a storage line, wherein the storage line includes an extension portion; a third conductive layer, comprising a third connecting member disposed above the second conductive layer; an insulating layer disposed between the second conductive layer and the third conductive layer and comprising a first sub-insulating layer disposed on the second conductive layer and a second sub-insulating layer disposed under the third conductive layer; as well as The data lines and the driving voltage lines both cross the scanning lines and extend in the second direction, wherein the third connection member electrically connects the extension portion of the storage line to the active layer, and An edge of the second sub-insulating layer is disposed outside an edge of the third conductive layer in a plan view.

16. The display device according to claim 15, in, The edge of the second sub-insulating layer is parallel to the edge of the third conductive layer in a thickness direction of the display device.

17. The display device according to claim 15, in, The second sub-insulating layer and the third conductive layer have the same shape in a plan view.

18. The display device according to claim 15, in, The edge of the second sub-insulating layer is offset from the edge of the third conductive layer in a plan view.

19. The display device according to claim 15, in, The third conductive layer further includes a first connection member, a second connection member, a fourth connection member, and an initialization voltage line disposed on the same layer as the third connection member.

20. The display device according to claim 19, in, The second sub-insulating layer comprises: a first region overlapping the first connecting member; a second region overlapping the second connecting member; a third region overlapping the third connecting member; a fourth region overlapping the fourth connecting member; and A fifth region overlaps the initialization voltage line.

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