Integrated circuit semiconductor device and method of manufacturing the same

Abstract

An integrated circuit semiconductor device includes a first region including a first transistor and a second region in contact with the first region in a second direction. The first transistor includes a first active fin extending in a first direction, a first gate dielectric layer extending from the first active fin onto a first isolation layer in the second direction, and a first gate electrode on the first gate dielectric layer. The second region includes a second transistor including a second active fin extending in the first direction, a second gate dielectric layer extending from the second active fin onto a second isolation layer in the second direction, and a second gate electrode on the second gate dielectric layer. The integrated circuit semiconductor device includes a gate dielectric layer removal region adjacent to a boundary between the first region and the second region.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0063305, filed on May 29, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to an integrated circuit semiconductor device and a method for manufacturing the same, and more specifically, to an integrated circuit semiconductor device including transistors and a method for manufacturing the integrated circuit semiconductor device. Background Technology

[0004] To meet consumer demand for integrated semiconductor devices with superior performance, transistors should be reliably formed on these devices. However, as integrated circuit semiconductor devices have become increasingly highly integrated, it can be difficult to reliably form three-dimensional transistors on a substrate when such devices include three-dimensional transistors instead of planar transistors. Summary of the Invention

[0005] The present invention provides an integrated circuit semiconductor device comprising a reliably formed three-dimensional transistor.

[0006] The present invention provides a method for manufacturing the aforementioned integrated circuit semiconductor device.

[0007] According to one aspect of the present invention, an integrated circuit semiconductor device is provided, comprising: a first region including a first transistor, wherein the first transistor includes a first active fin extending in a first direction, a first gate dielectric layer extending from the first active fin to a first isolation layer in a second direction perpendicular to the first direction, and a first gate electrode formed on the first gate dielectric layer; a second region configured to contact the first region in a second direction, wherein the second region includes a second transistor, the second transistor including a second active fin extending in the first direction, a second gate dielectric layer extending from the second active fin to a second isolation layer in the second direction, and a second gate electrode formed on the second gate dielectric layer; and a gate dielectric layer removal region located near or adjacent to the boundary between the first region and the second region, wherein the gate dielectric layer removal region is configured to be shifted or offset relative to the boundary in the second direction toward the first region or the second region, or the gate dielectric layer removal region is disposed in either the first region or the second region.

[0008] According to one aspect of the present invention, an integrated circuit semiconductor device is provided, comprising: a first region including a first multi-bridge channel transistor, wherein the first multi-bridge channel transistor includes a first active fin protruding from a substrate and extending in a first direction, a first gate dielectric layer extending from the first active fin to a first isolation layer in a second direction perpendicular to the first direction, a plurality of first nanosheets stacked spaced apart from the first gate dielectric layer, a third gate dielectric layer surrounding the plurality of first nanosheets, and a first gate electrode formed on the first gate dielectric layer and the third gate dielectric layer and formed between the plurality of first nanosheets; a second region formed adjacent to the first region in a second direction, wherein the second region includes a second multi-bridge channel transistor, the second multi-bridge channel transistor including a first active fin protruding from a substrate and extending in a first direction, a first gate dielectric layer extending from the first active fin to a first isolation layer, a plurality of first nanosheets stacked spaced apart from the first gate dielectric layer, a third gate dielectric layer surrounding the plurality of first nanosheets, and a first gate electrode formed on the first gate dielectric layer and the third gate dielectric layer and formed between the plurality of first nanosheets; and a second region formed adjacent to the first region in a second direction, wherein the second region includes a second multi-bridge channel transistor, the second multi-bridge channel transistor including a first active fin protruding from a substrate and extending in a first direction, a second active fin extending in a first direction, a third active fin extending in a first direction, a fourth active fin extending in a first direction, a fifth active fin extending in a first direction, a sixth active fin extending in a first direction, a seventh active fin extending in a first direction, a eighth active fin extending in a first direction, a ninth active fin extending in a first direction, a tenth ... The second active fin extends in a first direction; a second gate dielectric layer extends from the second active fin to the second isolation layer in a second direction perpendicular to the first direction; a plurality of second nanosheets stacked spaced apart from the second gate dielectric layer; a fourth gate dielectric layer surrounding the plurality of second nanosheets; and a second gate electrode formed on the second gate dielectric layer and the fourth gate dielectric layer and between the plurality of second nanosheets; and a gate dielectric layer removal region located on the substrate near or adjacent to the boundary between the first region and the second region, wherein the gate dielectric layer removal region is configured to be shifted or offset relative to the boundary in the second direction toward the first region or the second region, or the gate dielectric layer removal region is located in either the first region or the second region.

[0009] According to one aspect of the present invention, an integrated circuit semiconductor device is provided, comprising: a first region including a first fin transistor, wherein the first fin transistor includes a first active fin protruding from a substrate and extending in a first direction, a first gate dielectric layer extending from the first active fin to a first isolation layer in a second direction perpendicular to the first direction, and a first gate electrode formed on the first gate dielectric layer; a second region configured to contact the first region in a second direction, wherein the second region includes a second fin transistor, the second fin transistor including a second active fin protruding from a substrate and extending in the first direction, a second gate dielectric layer extending from the second active fin to a second isolation layer in the second direction, and a second gate electrode formed on the second gate dielectric layer; and a gate dielectric layer removal region located near or adjacent to the boundary between the first region and the second region, wherein the gate dielectric layer removal region is configured to be shifted or offset relative to the boundary toward the first region or the second region in the second direction, or the gate dielectric layer removal region is disposed in either the first region or the second region.

[0010] According to one aspect of the present invention, a method for manufacturing an integrated circuit semiconductor device is provided, the method comprising: forming a first active fin defined by a first isolation layer and extending in a first direction in a first region; forming a second active fin defined by a second isolation layer and extending in the first direction in a second region, the second region being adjacent to the first region in a second direction perpendicular to the first direction; forming a first gate dielectric layer on the first active fin and the first isolation layer in the first region; forming a second gate dielectric layer on the second active fin and the second isolation layer in the second region; and forming a gate dielectric layer removal region near or adjacent to the boundary between the first region and the second region, wherein the gate dielectric layer removal region is configured to be shifted or offset relative to the boundary in the second direction toward the first region or the second region, or the gate dielectric layer removal region is disposed in either the first region or the second region. Attached Figure Description

[0011] Embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 These are layout diagrams of integrated circuit semiconductor devices according to some embodiments of the present invention;

[0013] Figure 2 It is along Figure 1 A cross-sectional view of an integrated circuit semiconductor device taken from line I-I';

[0014] Figure 3 It is along Figure 1 A cross-sectional view of the integrated circuit semiconductor device taken from line II-II';

[0015] Figure 4 These are cross-sectional views of integrated circuit semiconductor devices according to some embodiments of the present invention;

[0016] Figures 5A to 5E It is used to explain manufacturing Figure 2 A cross-sectional view of a method for developing an integrated circuit semiconductor device;

[0017] Figure 6A and Figure 6B It is used to explain manufacturing Figure 3 A cross-sectional view of a method for developing an integrated circuit semiconductor device;

[0018] Figure 7 These are layout diagrams of integrated circuit semiconductor devices according to some embodiments of the present invention;

[0019] Figure 8 It is along Figure 7 A cross-sectional view of the integrated circuit semiconductor device taken from line III-III';

[0020] Figure 9 It is along Figure 7 A cross-sectional view of the integrated circuit semiconductor device taken from line IV-IV';

[0021] Figure 10 and Figure 11 These are cross-sectional views of integrated circuit semiconductor devices according to some embodiments of the present invention;

[0022] Figures 12A to 12E It is used to explain manufacturing Figure 8 A cross-sectional view of a method for developing an integrated circuit semiconductor device;

[0023] Figure 13A and Figure 13B It is used to explain manufacturing Figure 9 A cross-sectional view of a method for developing an integrated circuit semiconductor device;

[0024] Figure 14 This is a block diagram illustrating the configuration of an electronic device including an integrated circuit semiconductor device according to an embodiment of the present invention;

[0025] Figure 15 This is an equivalent circuit diagram of a static random access memory (SRAM) cell according to some embodiments of the present invention; and

[0026] Figure 16 It shows Figure 15 Layout diagrams of some embodiments of SRAM cells. Detailed Implementation

[0027] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The following embodiments of the inventive concept can be implemented by any one of the embodiments, or by combining one or more embodiments. Therefore, the inventive concept should not be construed as being limited to any single embodiment.

[0028] Figure 1 This is a layout diagram of an integrated circuit semiconductor device according to some embodiments of the present invention.

[0029] Specifically, the integrated circuit semiconductor device 10 may include a logic cell region. The logic cell region may include multiple high-performance cell transistors, such as metal-oxide-semiconductor (MOS) transistors. The cell transistors may include multi-bridge channel transistors.

[0030] The integrated circuit semiconductor device 10 may include a first region NR and a second region PR. In some embodiments, the first region NR may be a region in which a plurality of first transistors TR1 (e.g., a plurality of first multi-bridge channel transistors MBC1) are formed. The first multi-bridge channel transistors MBC1 may include N-type transistors, such as N-type MOS transistors. The terms first, second, etc., may be used herein to distinguish one element from another, but these elements should not be limited by these terms.

[0031] In some embodiments, the second region PR may be a region in which a plurality of second transistors TR2 (e.g., a plurality of second multi-bridge channel transistors MBC2) are formed. The second multi-bridge channel transistors MBC2 may include P-type transistors, such as P-type MOS transistors.

[0032] exist Figure 1 In this configuration, the first direction (X direction) can be the direction of the channel length, and the second direction (Y direction) can be the direction of the channel width. The first transistor TR1 in the first region NR may include at least one active fin 102a, and the second transistor TR2 in the second region PR may include at least one active fin 102b. In some embodiments, the first transistor TR1 in the first region NR may include two active fins 102a, and the second transistor TR2 in the second region PR may include two active fins 102b.

[0033] In the following description, the channel width will be illustrated, for example, based on the case where the first transistor TR1 and the second transistor TR2 each include an active fin 102a and an active fin 102b, respectively. The layout of the integrated circuit semiconductor device 10 will be described in more detail below, and the inventive concept is not limited to this. Figure 1 The layout shown is shown in the image.

[0034] The integrated circuit semiconductor device 10 may include a plurality of first active fins 102a and a plurality of second active fins 102b extending in a first direction. The first width of the first active fin 102a (i.e., the first width in the second direction) may be W1. The second width of the second active fin 102b (i.e., the second width in the second direction) may be W2, which is different from the first width W1. In some embodiments, the first width W1 may be greater than the second width W2.

[0035] The first active fin 102a and the second active fin 102b can be formed in the first region NR and the second region PR, respectively. The first active fin 102a located in the first region NR can serve as the active region of the first transistor TR1. The second active fin 102b located in the second region PR can serve as the active region of the second transistor TR2.

[0036] An isolation layer may be disposed between each of the first active fins 102a and between each of the second active fins 102b. The integrated circuit semiconductor device 10 may include a plurality of first gate electrodes 118a and a plurality of second gate electrodes 118b, each of the plurality of first gate electrodes 118a and the plurality of second gate electrodes 118b extending in a second direction perpendicular to a first direction extending the first active fins 102a and the second active fins 102b.

[0037] Multiple first nanosheets 106a can be stacked in the region where the first active fin 102a and the first gate electrode 118a intersect in the first region NR. Multiple second nanosheets 106b can be stacked in the region where the second active fin 102b and the second gate electrode 118b intersect in the second region PR.

[0038] In this embodiment, the first nanosheet 106a and the second nanosheet 106b may each comprise four nanosheets, but the inventive concept is not limited thereto. For example, the first nanosheet 106a and the second nanosheet 106b may each comprise at least one nanosheet.

[0039] Although the cross-sections of the first nanosheet 106a and the second nanosheet 106b are shown as rectangular in this embodiment, the first nanosheet 106a and the second nanosheet 106b may have circular shapes and may be referred to as nanowires.

[0040] The width of the first nanosheet 106a (in the second direction) constituting the first transistor TR1 in the first region NR can be W3a. The width of the second nanosheet 106b (in the second direction) constituting the second transistor TR2 in the second region PR can be W4a, wherein W4a is different from W3a and can be smaller than W3a.

[0041] Therefore, since the width W3a of the first nanosheet 106a is different from the width W4a of the second nanosheet 106b, the first channel width of the first transistor TR1 and the second channel width of the second transistor TR2 can be different. In some embodiments, the first channel width of the first transistor TR1 can be greater than the second channel width of the second transistor TR2.

[0042] The first region NR and the second region PR can be adjacent to or contact each other in the second direction (Y direction) of the layout diagram. That is, the second region PR can be located below and / or above the first region NR. In some embodiments, the first region NR and the second region PR can be arranged alternately and repeatedly in the second direction (Y direction), such that a corresponding first region NR can be adjacent to a corresponding second region PR. As used herein, when an element or region is "directly located on" or "directly contacting" or "adjacent to" another element or region, there is no intermediate element.

[0043] As described above, a plurality of first transistors TR1 can be formed in the first region NR along the second direction. A plurality of second transistors TR2 can be formed in the second region PR along the second direction. Source / drain regions (not shown) can be formed in the first direction in the first active fins 102a and 102b on both sides of the first nanosheet 106a and the second nanosheet 106b, and the first gate electrode 118a and the second gate electrode 118b.

[0044] A boundary extending in a first direction (X direction), such as a boundary line IF, can be defined at the interface between the first region NR and the second region PR. The boundary line IF can be a metal gate boundary line. The threshold voltage of the first transistor TR1 in the first region NR and the threshold voltage of the second transistor TR2 in the second region PR may deviate from the design value depending on the distance from the boundary line IF.

[0045] It is believed that because impurities contained in the metal layer may diffuse into the gate dielectric layer located near the boundary line IF, the threshold voltages of the first transistor TR1 and the second transistor TR2 may deviate from their design values, and this can therefore be referred to as the metal gate boundary effect. To reduce or prevent the metal gate boundary effect, according to the present invention, the first gate dielectric layer removal region R2 may be located near or adjacent to the boundary line IF of the first region NR and the second region PR, in which the gate dielectric layer is removed.

[0046] As used herein, a gate dielectric layer removal region can refer to a region in which a portion of the gate dielectric layer has been removed or is substantially free of a gate dielectric layer, for example, a region separating the first and second gate dielectric layers (of adjacent first and second transistors). For example, a portion of the gate dielectric layer may be removed to define the first and second gate dielectric layers, which are separated by a gate dielectric layer removal region between them.

[0047] The first gate dielectric layer removal region R2 can be configured to be shifted relative to the boundary line IF in a second direction toward either the first region NR or the second region PR. In other words, the first gate dielectric layer removal region R2 can be offset from the boundary line IF toward either the first region NR or the second region PR. The first gate dielectric layer removal region R2 can be at different distances from the boundary line IF toward the first region NR and toward the second region PR in the second direction. Therefore, the threshold voltage of the first transistor TR1 located in the first region NR and the threshold voltage of the second transistor TR2 located in the second region PR can be reduced or prevented from deviating from the design value.

[0048] In some embodiments, the width of the first gate dielectric layer removal region R2 in the second direction may be W5. The relative boundaries of the first gate dielectric layer removal region R2 may have a distance d1 from the boundary line IF toward the first region NR and a distance d2 from the boundary line IF toward the second region PR in the second direction, respectively.

[0049] In the first gate dielectric layer removal region R2, a first gate dicing region CT1 may be provided, in which the first gate electrode 118a and the second gate electrode 118b are separated or disconnected in a second direction. The first gate dicing region CT1 can be more easily formed in the first gate dielectric layer removal region R2. In some embodiments, the width of the first gate dicing region CT1 in the second direction may be W6, which is less than W5.

[0050] In some embodiments, the second gate dielectric layer removal region R2-1 may be located within the first region NR. In some embodiments, the width of the second gate dielectric layer removal region R2-1 in the second direction may be W5-1. In some embodiments, the width W5-1 of the second gate dielectric layer removal region R2-1 may be equal to or less than the width W5 of the first gate dielectric layer removal region R2.

[0051] The second gate dicing region CT2 may be disposed in the second gate dielectric layer removal region R2-1 of the first region NR, in which the first gate electrode 118a is separated or disconnected. In some embodiments, the width of the second gate dicing region CT2 in the second direction may be W6, which is equal to the width of the first gate dicing region CT1. The second gate dicing pattern defining the second gate dicing region CT2 may include an insulating layer, such as a silicon nitride layer.

[0052] In some embodiments, the second gate cutting region CT2 in the first region NR may have a shape that extends wholly or partially in the first direction. In some embodiments, the second gate cutting region CT2 may be a region that cuts or separates two or four first gate electrodes 118a.

[0053] In some embodiments, the third gate dielectric layer removal region R2-2 may be located within the second region PR. In some embodiments, the width of the third gate dielectric layer removal region R2-2 in the second direction may be W5-2. In some embodiments, the width W5-2 of the third gate dielectric layer removal region R2-2 may be equal to or less than the width W5 of the first gate dielectric layer removal region R2.

[0054] The third gate dicing region CT3 can be disposed in the second region PR, in which the second gate electrode 118b is separated or disconnected. In some embodiments, the width of the third gate dicing region CT3 in the second direction can be W6, which is similar to the width of the first gate dicing region CT1 and the second gate dicing region CT2.

[0055] In some embodiments, the third gate dicing region CT3 in the second region PR may have a shape that extends fully or partially in the first direction. In some embodiments, the third gate dicing region CT3 may be a region that cuts or separates two or four second gate electrodes 118b.

[0056] Figure 2 It is along Figure 1 A cross-sectional view of the integrated circuit semiconductor device taken from line I-I'.

[0057] Specifically, the integrated circuit semiconductor device 10 may include a first transistor TR1 and a second transistor TR2 located in a first region NR and a second region PR of the substrate 100, respectively. The first transistor TR1 and the second transistor TR2 may each include a first multi-bridge channel transistor MBC1 and a second multi-bridge channel transistor MBC2. The integrated circuit semiconductor device 10 may include a first active fin 102a and a second active fin 102b protruding from the substrate 100 in the third direction (Z direction).

[0058] The substrate 100 may include semiconductor materials such as silicon, germanium, silicon-germanium, or III-V semiconductor compounds such as GaP, GaAs, and GaSb. In some embodiments, the substrate 100 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0059] The first active fin 102a and the second active fin 102b can extend in the first direction (X direction) as described above. The first active fin 102a and the second active fin 102b can have different widths in the second direction (Y direction), that is, the widths W1 and W2.

[0060] In some embodiments, in the second direction, the first width W1 of the first active fin 102a may be greater than the second width W2 of the second active fin 102b. In some embodiments, the upper width W1a of the first active fin 102a may be smaller than its lower width W1b. The upper width W2a of the second active fin 102b may be smaller than its lower width W2b.

[0061] The first isolation layer 104a and the second isolation layer 104b can be formed on a portion of the substrate 100 other than the portion on which the first active fin 102a and the second active fin 102b are formed. The first isolation layer 104a and the second isolation layer 104b can include a silicon oxide film, a silicon nitride film, or a combination thereof. The first isolation layer 104a and the second isolation layer 104b can be formed around the first active fin 102a and the second active fin 102b, respectively.

[0062] In some embodiments, the first active fin 102a and the second active fin 102b may include a first fin protrusion 102p and a second fin protrusion 102q protruding from the surface of the first isolation layer 104a and the surface of the second isolation layer 104b, respectively. In some embodiments, the first fin protrusion 102p and the second fin protrusion 102q may not be formed.

[0063] In the first region NR, the first gate dielectric layer 108a may extend in the second direction (Y direction) from the first active fin 102a and the first fin protrusion 102p onto the first isolation layer 104a. The first gate dielectric layer 108a may be formed on the upper surface and side surface of the first fin protrusion 102p, and on a portion of the upper surface of the first isolation layer 104a.

[0064] Multiple first nanosheets 106a can be stacked on a first gate dielectric layer 108a and spaced apart from each other, and a third gate dielectric layer 108c can be formed around the first nanosheets 106a. The width and height of the first nanosheets 106a in the first region NR can be W3a and W3b, respectively. A first gate electrode 118a can be formed on the first gate dielectric layer 108a and the third gate dielectric layer 108c, and is formed between the first nanosheets 106a. In other words, the first gate electrode 118a can be formed on the first gate dielectric layer 108a and the third gate dielectric layer 108c surrounding the first nanosheets 106a.

[0065] In the second region PR, the second gate dielectric layer 108b may extend in the second direction (Y direction) from the second active fin 102b and the second fin protrusion 102q onto the second isolation layer 104b. The second gate dielectric layer 108b may be formed on the upper surface and side surface of the second fin protrusion 102q, and on a portion of the upper surface of the second isolation layer 104b.

[0066] Multiple second nanosheets 106b can be stacked on the second gate dielectric layer 108b and spaced apart from each other, and a fourth gate dielectric layer 108d can be formed around the second nanosheets 106b. The width and height of the second nanosheets 106b in the second region PR can be W4a and W4b, respectively.

[0067] The first channel width of the first transistor TR1 (in the second direction) in the first region NR can be determined based on the width W3a and height W3b of the first nanosheet 106a and the number of stacked first nanosheets 106a. That is, the first channel width can be (W3a+2×W3b)×4.

[0068] The second channel width of the second transistor TR2 (in the second direction) in the second region PR can be determined based on the width W4a and height W4b of the second nanosheet 106b and the number of stacked second nanosheets 106b. That is, the second channel width can be (W4a + 2 × W4b) × 4.

[0069] In some embodiments, when the width W3a of the first nanosheet 106a is different from the width W4a of the second nanosheet 106b, the width of the first channel and the width of the second channel can be different. In some embodiments, when the width W3a of the first nanosheet 106a is greater than the width W4a of the second nanosheet 106b, the width of the first channel can be greater than the width of the second channel.

[0070] In some embodiments, depending on the need or expectation of threshold voltage adjustment, a threshold voltage adjustment layer 114a may be formed on the surfaces of the second gate dielectric layer 108b and the fourth gate dielectric layer 108d and between the respective second nanosheets 106b. The threshold voltage adjustment layer 114a may comprise a metallic material having a work function matching the threshold voltage characteristics of the second transistor TR2 (e.g., a P-type transistor). In some embodiments, the threshold voltage adjustment layer 114a may comprise, for example, Ti, TiN, Ta, TaN, etc.

[0071] The second gate electrode 118b can be formed on the threshold voltage adjustment layer 114a. When the threshold voltage adjustment layer 114a is not formed, the second gate electrode 118b can be formed on the surfaces of the second gate dielectric layer 108b and the fourth gate dielectric layer 108d, and between each of the second nanosheets 106b. The first gate electrode 118a and the second gate electrode 118b can be connected to each other. In the integrated circuit semiconductor device 10, an interlayer insulating film can be formed in addition to the regions where the first gate electrode 118a and the second gate electrode 118b are formed.

[0072] In some embodiments, the first to fourth gate dielectric layers 108a to 108d may include a high dielectric constant dielectric layer having a higher dielectric constant than the silicon oxide layer. For example, the first to fourth gate dielectric layers 108a to 108d may include at least one material selected from the following: hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride (HfSiON), hafnium alumina (HfAlO3), lanthanum oxide (LaO), lanthanum alumina (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride (ZrSiON), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (Al2O3), tantalum oxide (Ta2O3), or lead scandium tantalum oxide (PbTaScO).

[0073] In some embodiments, the first gate electrode 118a and the second gate electrode 118b may comprise a metal or a metal nitride. According to an example embodiment, the first gate electrode 118a and the second gate electrode 118b may comprise Ti, TiN, Ta, TaN, TiAlC, TiAlCN, TiAlSiCN, Co, W, etc.

[0074] Near the boundary line IF between the first region NR and the second region PR, a first gate dielectric layer removal region R2 may be provided, in which the gate dielectric layer is removed. The width of the first gate dielectric layer removal region R2 in the second direction may be W5. The first gate dielectric layer 108a and the second gate dielectric layer 108b may be partially removed at portions of the first isolation layer 104a and the second isolation layer 104b, said portions being close to or adjacent to the boundary line IF between the first region NR and the second region PR.

[0075] The aforementioned metal gate boundary effect can be reduced or prevented by forming a first gate dielectric layer removal region R2. The first gate dielectric layer removal region R2 can be configured to be shifted or offset relative to the boundary line IF as described above in the second direction (Y direction) toward the first region NR or the second region PR.

[0076] In some embodiments, in the first gate dielectric layer removal region R2, the distance d1 from the boundary line IF to the edge of the first gate dielectric layer 108a may be different from the distance d2 from the boundary line IF to the edge of the second gate dielectric layer 108b. In some embodiments, in the first gate dielectric layer removal region R2, the distance d1 from the boundary line IF to the edge of the first gate dielectric layer 108a may be less than the distance d2 from the boundary line IF to the edge of the second gate dielectric layer 108b.

[0077] A threshold voltage adjustment layer 114a may be formed on one side of the first gate dielectric layer removal region R2 to extend along or cover the second gate dielectric layer 108b. The threshold voltage adjustment layer 114a may not be connected to the first gate dielectric layer 108a. Due to the threshold voltage adjustment layer 114a, a first step portion ST1 may be formed on one side of the first gate dielectric layer removal region R2 in the second region PR. The distance from the boundary line IF to the threshold voltage adjustment layer 114a in the second region PR may be d3, which is less than d2.

[0078] Figure 3 It is along Figure 1 A cross-sectional view taken from line II-II' of the integrated circuit semiconductor device 10.

[0079] Specifically, Figure 2 and Figure 3 The same reference numerals in the figures indicate the same elements. Figure 3 The integrated circuit semiconductor device 10 may further include a first gate dicing region CT1. The first gate dicing region CT1 may be a region for dicing the first gate electrode 118a and the second gate electrode 118b in the first gate dielectric layer removal region R2.

[0080] Because the first gate dicing region CT1 is formed on the first gate dielectric layer removal region R2, it is easier to form the first gate dicing region CT1. Furthermore, since no gate dielectric layer is formed in the first gate dielectric layer removal region R2, it is easier to etch the gate electrode material. In some embodiments, the width of the first gate dicing region CT1 in the second direction may be W6. The first gate electrode 118a and the second gate electrode 118b may be separated from each other due to the first gate dicing region CT1.

[0081] In some embodiments, the gate dicing pattern 124 defining the first gate dicing region CT1 may include an insulating layer, such as a silicon nitride layer. In some embodiments, a sidewall of the gate dicing pattern 124 defining the first gate dicing region CT1 may be inclined in a third direction (Z direction) perpendicular to the plane defined by the first direction and the second direction. In other words, a sidewall of the gate dicing pattern 124 may be inclined from the upper surface of the first gate electrode 118a and the second gate electrode 118b toward the bottom surface of the first gate electrode 118a and the second gate electrode 118b.

[0082] In some embodiments, the lower width W6b of the gate dicing pattern 124 may be smaller than its upper width W6a. The bottom of the gate dicing pattern 124 may be located below the upper surfaces of the isolation layers 104a and 104b.

[0083] Figure 4This is a cross-sectional view of an integrated circuit semiconductor device according to some embodiments of the present invention.

[0084] Specifically, apart from the different formation location of the first gate dielectric layer removal region R2a, the integrated circuit semiconductor device 20 can be the same as... Figure 2 The integrated circuit semiconductor device 10 is the same as or similar to it. Figure 4 In, with Figure 2 The same reference numerals in the accompanying drawings indicate the same elements, and the same content will be simply explained or omitted.

[0085] In some embodiments, the integrated circuit semiconductor device 20 may have a first gate dielectric layer removal region R2a formed in a first region NR relative to the boundary line IF. In some embodiments, with Figure 4 Conversely, the gate dielectric layer removal region can be formed in the second region PR.

[0086] The second gate dielectric layer 108b may extend relative to the boundary line IF to the first region NR. The second gate dielectric layer 108b may extend a distance d5 from the boundary line IF to the first region NR in a second direction. One end of the first gate dielectric layer 108a may be located at a distance d4 from the boundary line IF to the first region NR in the second direction. Therefore, the first gate dielectric layer removal region R2a may be the region disposed between the distance d4 from the boundary line IF to the first gate dielectric layer 108a in the direction toward the first region NR and the distance d5 from the boundary line IF to the second gate dielectric layer 108b in the direction toward the first region NR.

[0087] The integrated circuit semiconductor device 20 may include a threshold voltage adjustment layer 114a-1 formed on a second gate dielectric layer 108b in a second region PR. In the second region PR, the distance from the boundary line IF to the threshold voltage adjustment layer 114a-1 may be d6. A second step portion ST2 may be formed between the threshold voltage adjustment layer 114a-1 and the second gate dielectric layer 108b.

[0088] Figures 5A to 5E It is used to explain manufacturing Figure 2 A cross-sectional view of a method for developing an integrated circuit semiconductor device.

[0089] Specifically, in Figures 5A to 5E In, with Figure 1 and Figure 2 In the accompanying drawings, the same reference numerals denote the same elements. Figures 5A to 5E In the text, a brief description or omission of the relevant information will be provided. Figure 1 and Figure 2 The content is the same as the content.

[0090] Reference Figure 5A A first active fin 102a, including a first fin protrusion 102p, and a second active fin 102b, including a second fin protrusion 102q, can be formed on a substrate 100 having a first region NR and a second region PR.

[0091] The first active fin 102a and the second active fin 102b can be formed to have a first width W1 and a second width W2, respectively. The upper width W1a of the first active fin 102a can be smaller than the lower width W1b. The upper width W2a of the second active fin 102b can be smaller than the lower width W2b. The first isolation layer 104a and the second isolation layer 104b can be formed on the portion of the substrate 100 other than the portion on which the first active fin 102a and the second active fin 102b are formed.

[0092] Multiple first nanosheets 106a and multiple second nanosheets 106b can be formed on or above the first active fin 102a and the second active fin 102b, respectively. The first nanosheets 106a and the second nanosheets 106b can be formed to have widths W3a and W4a, respectively. A gate dielectric material layer 108 can be formed on the first active fin 102a, the second active fin 102b, the first isolation layer 104a, and the second isolation layer 104b. In addition, a third gate dielectric layer 108c and a fourth gate dielectric layer 108d can be formed to surround the first nanosheets 106a and the second nanosheets 106b, respectively.

[0093] Subsequently, a first mask pattern 110 with a first opening 112 for exposing a portion of the gate dielectric material layer 108 can be formed near the boundary line IF of the first region NR and the second region PR. The first mask pattern 110 can cover the first active fin 102a, the first nanosheet 106a surrounded by the third gate dielectric layer 108c, the second active fin 102b, the second nanosheet 106b surrounded by the fourth gate dielectric layer 108d, and a portion of the gate dielectric material layer 108. The first opening 112 can correspond to the first gate dielectric layer removal region R2. The opposite edges of the first opening 112 can have distances d1 from the boundary line IF toward the first region NR and d2 from the boundary line IF toward the second region PR, respectively, in a second direction.

[0094] refer to Figure 5B and Figure 5C A portion of the gate dielectric material layer 108 is etched using the first mask pattern 110 as an etching mask to form a shape such as Figure 5BThe first gate dielectric layer 108a and the second gate dielectric layer 108B are shown. Therefore, a first gate dielectric layer removal region R2 can be formed near the boundary line IF between the first region NR and the second region PR, at which the first gate dielectric layer removal region R2... Figure 5A The portion of the gate dielectric material layer 108 is removed. The width of the first gate dielectric layer removal region R2 can be W5. The first gate dielectric layer removal region R2 can have distances d1 and d2 in a second direction from the boundary line IF toward the first region NR and the second region PR, respectively.

[0095] It is possible Figure 5C Remove as shown Figure 5B The first mask pattern 110 is shown. A threshold voltage adjustment material layer 114 can be formed on a first gate dielectric layer 108a, a third gate dielectric layer 108c surrounding a first nanosheet 106a, a second gate dielectric layer 108b, a fourth gate dielectric layer 108d surrounding a second nanosheet 106b, a first isolation layer 104a, and a second isolation layer 104b. The threshold voltage adjustment material layer 114 can be formed on the entire surface of the substrate 100.

[0096] Reference Figure 5D and Figure 5E ,like Figure 5D As shown, the second mask pattern 116 can be formed with a second opening 117, which exposes the entire first region NR and a portion of the threshold voltage adjustment material layer 114 of the second region PR. The distance from the boundary line IF to the second mask pattern 116 of the second opening 117 can be d3. Then, etching is performed using the second mask pattern 116 as an etching mask. Figure 5C A portion of the threshold voltage adjustment material layer 114 in the second region PR can be formed as a threshold voltage adjustment layer 114a.

[0097] like Figure 5E As shown, the second mask pattern 116 can be removed. In this case, the distance from the boundary line IF to one end of the threshold voltage adjustment layer 114a in the second region PR can be d3. Furthermore, as... Figure 2 As shown, the first gate electrode 118a and the second gate electrode 118b can be formed on the first region NR and the second region PR, respectively.

[0098] Figure 6A and Figure 6B It is used to explain manufacturing Figure 3 A cross-sectional view of a method for developing an integrated circuit semiconductor device.

[0099] Specifically, in Figure 6A and Figure 6B In, with Figures 1 to 3 and Figures 5A to 5E In the accompanying drawings, the same reference numerals denote the same elements. Figure 6A and Figure 6B In, with Figures 1 to 3 and Figures 5A to 5E Content that is identical to the content in the text can be briefly described or omitted.

[0100] As per the above reference Figure 2 and Figures 5A to 5E The first gate electrode 118a and the second gate electrode 118b can be formed on the first region NR and the second region PR, respectively. Figure 2 As shown, the first gate electrode 118a and the second gate electrode 118b can be connected to each other.

[0101] Next, as Figure 6A As shown, a third opening 120 can be formed near the boundary line IF between the first region NR and the second region PR, passing through the first gate electrode 118a and the second gate electrode 118b. The bottom of the third opening 120 can be below the upper surfaces of the isolation layers 104a and 104b.

[0102] Since the third opening 120 can be formed in the first gate dielectric layer removal region R2, it is easier to form the third opening 120. In addition, since the third opening 120 can be formed in the region where the gate dielectric layer is removed, it is easier to form the third opening 120 without excessively damaging the interlayer insulating layer (not shown) formed around the first gate electrode 118a and the second gate electrode 118b.

[0103] The width of the third opening 120 in the second direction can be W6. One sidewall of the third opening 120 may slope from the upper surface of the first gate electrode 118a and the second gate electrode 118b toward the bottom surface of the first gate electrode 118a and the second gate electrode 118b. In some embodiments, the bottom width W6b of the third opening 120 may be smaller than the top or upper width W6a. The first gate electrode 118a and the second gate electrode 118b may be separated from each other due to the third opening 120.

[0104] like Figure 6B As shown, a gate dicing material layer 122 can be formed on the first gate electrode 118a and the second gate electrode 118b while filling the third opening 120. The gate dicing material layer 122 can be planarized to form a shape as shown. Figure 3 The gate dicing pattern 124 is shown.

[0105] Gate dicing pattern 124 can be defined as follows: Figure 3 The first gate dicing region CT1 shown can be electrically separated from the first gate electrode 118a and the second gate electrode 118b due to the gate dicing pattern 124 constituting the first gate dicing region CT1.

[0106] Figure 7 This is a layout diagram of an integrated circuit semiconductor device according to some embodiments of the present invention.

[0107] Specifically, apart from the first transistor TR1-1 and the second transistor TR2-1 being fin transistors, the integrated circuit semiconductor device 40 can be connected to... Figure 1 The integrated circuit semiconductor device 10 is the same as or similar to it. Regarding Figure 7 It can be briefly described or omitted. Figure 1 The corresponding description. The integrated circuit semiconductor device 40 may include multiple unit transistors, such as MOS transistors. The unit transistors may be fin transistors.

[0108] The integrated circuit semiconductor device 40 may include a first region NR and a second region PR. In some embodiments, the first region NR may be a region in which a plurality of first transistors TR1-1 (e.g., first fin transistors FIN1) are formed. The first fin transistors FIN1 may be N-type transistors, such as N-type MOS transistors.

[0109] In some embodiments, the second region PR may be a region in which a plurality of second transistors TR2-1 (e.g., second fin transistors FIN2) are formed. The second fin transistor FIN2 may be a P-type transistor, such as a P-type MOS transistor.

[0110] exist Figure 7 In this configuration, the first direction (X direction) can be the direction of the channel length, and the second direction (Y direction) can be the direction of the channel width. The first transistor TR1-1 in the first region NR and the second transistor TR2-1 in the second region PR can each include at least one active fin 202a and at least one active fin 202b. For example, in some embodiments, the first transistor TR1-1 in the first region NR and the second transistor TR2-1 in the second region PR can each include at least two active fins 202a and at least two active fins 202b.

[0111] In the following description, the channel width will be based on an example where the first transistor TR1-1 and the second transistor TR2-1 each include an active fin 202a and an active fin 202b, respectively. The layout of the integrated circuit semiconductor device 40 will be described in more detail below, but the inventive concept is not limited thereto. Figure 7 The layout shown is shown in the image.

[0112] The integrated circuit semiconductor device 40 may include a plurality of first active fins 202a and a plurality of second active fins 202b, the first active fins 202a and the second active fins 202b extending in a first direction. A first width (i.e., a first width in a second direction) of the first active fin 202a may be W7. A second width (i.e., a second width in a second direction) of the second active fin 202b may be W8, which is different from the first width W7. In some embodiments, the first width W7 may be greater than the second width W8.

[0113] A first active fin 202a located in the first region NR can serve as the active region of the first transistor TR1-1. A second active fin 202b located in the second region PR can serve as the active region of the second transistor TR2-1. An isolation layer can be provided between each of the first active fins 202a.

[0114] The integrated circuit semiconductor device 40 may include a plurality of first gate electrodes 218a and a plurality of second gate electrodes 218b extending in a second direction perpendicular to a first direction extending the first active fin 202a and the second active fin 202b. The first channel width of the first transistor TR1-1 in the first region NR in the second direction may be determined by the width W9a of the first active fin 202a located below the first gate electrode 218a.

[0115] The second channel width of the second transistor TR2-1 in the second region PR can be different from the first channel width in the second direction, and can be determined by the width W10a of the second active fin 202b located below the second gate electrode 218b. Since the width W9a of the first active fin 202a located below the first gate electrode 218a and the width W10a of the second active fin 202b located below the second gate electrode 218b can be different from each other, the first channel width of the first transistor TR1-1 can be different from the second channel width of the second transistor TR2-1. In some embodiments, the first channel width of the first transistor TR1-1 can be greater than the second channel width of the second transistor TR2-1.

[0116] The first region NR and the second region PR can be arranged in the layout diagram to be in contact with or adjacent to each other in the second direction (Y direction). A plurality of first transistors TR1-1 can be formed in the first region NR along the second direction. A plurality of second transistors TR2-1 can be formed in the second region PR along the second direction. Source / drain regions (not shown) can be formed in the first active fins 202a and 202b on both sides of the gate electrodes 218a and 218b in the first direction.

[0117] A boundary extending in a first direction (X direction), such as a boundary line IF, can be defined at the interface between the first region NR and the second region PR. The boundary line IF can be a metal gate boundary line. As described above, due to the metal gate boundary effect based on the distance between transistors TR1-1 and TR2-1 and the boundary line IF, the threshold voltage of the first transistor TR1-1 in the first region NR and the threshold voltage of the second transistor TR2-1 in the second region PR may deviate from the design value.

[0118] To reduce or prevent metal gate boundary effects, according to the present invention, a first gate dielectric layer removal region R4 may be disposed near the boundary line IF of the first region NR and the second region PR. The first gate dielectric layer removal region R4 may be configured to be shifted or offset relative to the boundary line IF in a second direction towards the first region NR or the second region PR.

[0119] The first gate dielectric layer removal region R4 can have different distances from the boundary line IF toward the first region NR and the second region PR in the second direction. Therefore, the threshold voltages of the first transistor TR1-1 and the second transistor TR2-1 located in the first region NR and the second region PR, respectively, can be reduced or prevented from deviating from the design value.

[0120] In some embodiments, the width of the first gate dielectric layer removal region R4 in the second direction may be W11. The first gate dielectric layer removal region R4 in the second direction from the boundary line IF toward the first region NR and the second region PR may have distances d7 and d8, respectively.

[0121] In the first gate dielectric layer removal region R4, a first gate dicing region CT4 may be provided, in which the first gate electrode 218a and the second gate electrode 218b are separated or disconnected in a second direction. The first gate dicing region CT4 can be more easily formed in the first gate dielectric layer removal region R4. In some embodiments, the width of the first gate dicing region CT4 (in the second direction) may be W12. The gate dicing pattern defining the first gate dicing region CT4 may include an insulating layer, such as a silicon nitride layer.

[0122] In some embodiments, the second gate dielectric layer removal region R4-1 may be located within the first region NR. In some embodiments, the width W11-1 of the second gate dielectric layer removal region R4-1 in the second direction may be equal to or less than the width W11 of the first gate dielectric layer removal region R4. A second gate dicing region CT5 may be disposed within the second gate dielectric layer removal region R4-1 of the first region NR, in which the first gate electrode 218a is separated or disconnected.

[0123] In some embodiments, the width of the second gate dicing region CT5 (in the second direction) may be W12, which is equal to the width of the first gate dicing region CT4. The second gate dicing pattern defining the second gate dicing region CT5 may include an insulating layer, such as a silicon nitride layer.

[0124] In some embodiments, the third gate dielectric layer removal region R4-2 may be located in the second region PR. The width of the third gate dielectric layer removal region R4-2 in the second direction may be W11-2, which is equal to or less than W11.

[0125] A third gate dicing region CT6, in which the second gate electrode 218b is separated or disconnected, may be disposed in the second region PR. In some embodiments, the width of the third gate dicing region CT6 (in the second direction) may be W12, which is equal to the width of the first gate dicing region CT4 and the second gate dicing region CT5. The gate dicing pattern defining the third gate dicing region CT6 may include an insulating layer, such as a silicon nitride layer.

[0126] Figure 8 It is along Figure 7 A cross-sectional view taken from line III-III' of an integrated circuit semiconductor device.

[0127] Specifically, the integrated circuit semiconductor device 40 may include a first transistor TR1-1 and a second transistor TR2-1 located in the first region NR and the second region PR, respectively. The first transistor TR1-1 and the second transistor TR2-1 may be a first fin transistor FIN1 and a second fin transistor FIN2, respectively. The integrated circuit semiconductor device 40 may include a first active fin 202a and a second active fin 202b protruding from the substrate 200 in the third direction (Z direction). The substrate 200 may include components as described above. Figure 2 The substrate 100 is made of the same material.

[0128] The first active fin 202a and the second active fin 202b can extend in the first direction (X direction) as described above. The first active fin 202a and the second active fin 202b can have different widths in the Y direction, namely widths W7 and W8.

[0129] In some embodiments, in the second direction, the first width W7 of the first active fin 202a may be greater than the second width W8 of the second active fin 202b. In some embodiments, the upper width W7a of the first active fin 202a may be smaller than its lower width W7b. The upper width W8a of the second active fin 202b may be smaller than its lower width W8b.

[0130] In addition to the first active fin 202a and the second active fin 202b, a first isolation layer 204a and a second isolation layer 204b may be formed on the substrate 200. The first isolation layer 204a and the second isolation layer 204b may include a silicon oxide film, a silicon nitride film, or a combination thereof. The first isolation layer 204a and the second isolation layer 204b may be formed around the first active fin 202a and the second active fin 202b, respectively.

[0131] In some embodiments, the first active fin 202a and the second active fin 202b may each include a first fin protrusion 202p protruding from the surface of the first isolation layer 204a and a second fin protrusion 202q protruding from the surface of the second isolation layer 204b, respectively. The width and height of the first fin protrusion 202p defining the first active fin 202a in the first region NR may be W9a and W9b, respectively.

[0132] In the first region NR, a first gate dielectric layer 208a may extend in a second direction (Y direction) from the first active fin 202a and the first fin protrusion 202p onto the first isolation layer 204a. The first gate dielectric layer 208a may be formed on the upper and side surfaces of the first fin protrusion 202p and a portion of the upper surface of the first isolation layer 204a. A first gate electrode 218a may be formed on the first gate dielectric layer 208a.

[0133] In the second region PR, the second gate dielectric layer 208b may extend in the second direction (Y direction) from the second active fin 202b and the second fin protrusion 202q onto the second isolation layer 204b. The second gate dielectric layer 208b may be formed on the upper and side surfaces of the second fin protrusion 202q and a portion of the upper surface of the second isolation layer 204b.

[0134] The first gate dielectric layer 208a and the second gate dielectric layer 208b may include the above-mentioned references. Figure 2 The first to fourth gate dielectric layers 108a to 108d are made of the same material. The first gate electrode 218a and the second gate electrode 218b (discussed below) may include materials similar to those mentioned above. Figure 2 The first gate electrode 118a and the second gate electrode 118b are made of the same material.

[0135] The width and height of the second fin protrusion 202q defining the second active fin 202b in the second region PR can be W10a and W10b, respectively. In some embodiments, a threshold voltage adjustment layer 214a can be formed on the second gate dielectric layer 208b of the second region PR. The threshold voltage adjustment layer 214a can include a metallic material having a work function that matches the threshold voltage characteristics of the second transistor TR2-1 (e.g., a P-type transistor). In some embodiments, the threshold voltage adjustment layer 214a can include Ti, TiN, Ta, TaN, etc.

[0136] The second gate electrode 218b can be formed on the threshold voltage adjustment layer 214a. In embodiments where the threshold voltage adjustment layer 214a is not formed, the second gate electrode 218b can be formed on the second gate dielectric layer 208b. The first gate electrode 218a and the second gate electrode 218b can be connected to each other.

[0137] The first channel width of the first transistor TR1-1 in the first region NR in the second direction can be determined by the width W9a and height W9b of the first fin protrusion 202p. That is, the first channel width can be (W9a + 2 × W9b). The second channel width of the second transistor TR2-1 in the second region PR in the second direction can be determined by the width W10a and height W10b of the second fin protrusion 202q. That is, the second channel width can be (W10a + 2 × W10b).

[0138] In some embodiments, since the width W9a of the first fin protrusion 202p may be different from the width W10a of the second fin protrusion 202q, the width of the first channel and the width of the second channel may be different. In some embodiments, when the width W9a of the first fin protrusion 202p is greater than the width W10a of the second fin protrusion 202q, the width of the first channel may be greater than the width of the second channel.

[0139] To reduce or prevent metal gate boundary effects, the first gate dielectric layer removal region R4, where no gate dielectric layer is formed, can be located near the boundary line IF between the first region NR and the second region PR. The width of the first gate dielectric layer removal region R4 (in the second direction) can be W11.

[0140] The first gate dielectric layer removal region R4 can be configured to be shifted or offset relative to the boundary line IF in a second direction (Y direction) toward the first region NR or the second region PR. In some embodiments, the opposite edges of the first gate dielectric layer removal region R4 can each have a distance d7 from the boundary line IF to the first gate dielectric layer 208a and a distance d8 from the boundary line IF to the second gate dielectric layer 208b, respectively. In some embodiments, the first gate dielectric layer removal region R4 can have a distance d7 from the boundary line IF to the first gate dielectric layer 208a, wherein the distance d7 can be smaller than the distance d8 from the boundary line IF to the second gate dielectric layer 208b.

[0141] A threshold voltage adjustment layer 214a may be formed on one side of the first gate dielectric layer removal region R4 to cover the second gate dielectric layer 208b. The threshold voltage adjustment layer 214a may not be connected to the first gate dielectric layer 208a. Due to the threshold voltage adjustment layer 214a, a stepped portion may be formed on one side of the first gate dielectric layer removal region R4 in the second region PR.

[0142] Figure 9 It is along Figure 7 A cross-sectional view of line IV-IV' of an integrated circuit semiconductor device.

[0143] Specifically, Figure 7 and Figure 9 The same reference numerals in the figures indicate the same elements. Figure 9 The integrated circuit semiconductor device 40 may further include a first gate dicing region CT4. The first gate dicing region CT4 may be a region in a first gate dielectric layer removal region R4 that cuts or separates the first gate electrode 218a and the second gate electrode 218b. Since the first gate dicing region CT4 can be formed in the first gate dielectric layer removal region R4, it is easier to form the first gate dicing region CT4. In some embodiments, the width of the first gate dicing region CT4 (in a second direction) may be W12. The first gate electrode 218a and the second gate electrode 218b can be separated by the first gate dicing region CT4.

[0144] In some embodiments, a sidewall of the gate dicing pattern 222 defining the first gate dicing region CT4 may be inclined in a third direction (Z direction) perpendicular to the plane defined by the first and second directions. In other words, the sidewall of the gate dicing pattern 222 may be inclined from the upper surfaces of the first gate electrode 218a and the second gate electrode 218b toward the bottom surfaces of the first gate electrode 218a and the second gate electrode 218b. In some embodiments, the bottom width W12b of the gate dicing pattern 222 may be smaller than the top or upper width W12a.

[0145] Figure 10 and Figure 11 This is a cross-sectional view of an integrated circuit semiconductor device according to some embodiments of the present invention.

[0146] Specifically, in Figure 10 and Figure 11 In, with Figure 7 and Figure 8 In the accompanying drawings, the same reference numerals denote the same elements. Except for those with... Figure 8 Compared to the integrated circuit semiconductor device 60, which includes a second threshold voltage adjustment layer 214b, Figure 10 The integrated circuit semiconductor device 60 can be with Figure 8 The integrated circuit semiconductor device 40 is the same as or similar to it. Except for... Figure 9 Compared to the integrated circuit semiconductor device 60, which includes a second threshold voltage adjustment layer 214b, Figure 11 The integrated circuit semiconductor device 60 can be with Figure 9 The integrated circuit semiconductor device 40 is the same as or similar to it.

[0147] like Figure 10 and Figure 11 As shown, the second threshold voltage adjustment layer 214b can be formed on the first gate dielectric layer 208a of the first region NR. The second threshold voltage adjustment layer 214b may include a metal material having a work function that matches the threshold voltage characteristics of the first transistor TR1-1 (e.g., an N-type transistor). In some embodiments, the second threshold voltage adjustment layer 214b may include TiAlC, TiAlCN, TiAlSiCN, etc.

[0148] The second threshold voltage adjustment layer 214b may not be connected to the second gate dielectric layer 208b of the second region PR. By forming the second threshold voltage adjustment layer 214b in the first region NR, the threshold voltage of the first transistor TR1-1 can be adjusted more easily.

[0149] In addition, such as Figure 11 As shown, the integrated circuit semiconductor device 60 may further include a first gate dicing region CT4. The first gate dicing region CT4 may be a region for dicing the first gate electrode 218a and the second gate electrode 218b within the first gate dielectric layer removal region R4. Since the first gate dicing region CT4 is formed within the first gate dielectric layer removal region R4, it is easier to form the first gate dicing region CT4. The first gate electrode 218a and the second gate electrode 218b can be separated by the first gate dicing region CT4.

[0150] Figures 12A to 12E It is used to explain manufacturing Figure 8 A cross-sectional view of a method for developing an integrated circuit semiconductor device.

[0151] Specifically, in Figures 12A to 12E In, with Figure 7 and Figure 8 In the accompanying drawings, the same reference numerals denote the same elements. Figures 12A to 12E In the text, a brief description or omission of the relevant information will be provided. Figure 7 and Figure 8 The content is the same as the content.

[0152] Reference Figure 12A A first active fin 202a, including a first fin protrusion 202p, and a second active fin 202b, including a second fin protrusion 202q, can be formed on a substrate 200 on which a first region NR and a second region PR are formed.

[0153] The first active fin 202a and the second active fin 202b can be formed to have a first width W7 and a second width W8, respectively. The upper width W7a of the first active fin 202a can be smaller than the lower width W7b. The upper width W8a of the second active fin 202b can be smaller than the lower width W8b. Then, in addition to the regions where the first active fin 202a and the second active fin 202b are formed, a first isolation layer 204a and a second isolation layer 204b can be formed on the substrate 200.

[0154] A gate dielectric material layer 208 may be formed on a first active fin 202a, a second active fin 202b, a first isolation layer 204a, and a second isolation layer 204b. A first mask pattern 210 has a first opening 212 for exposing a portion of the gate dielectric material layer 208 near the boundary line IF of the first region NR and the second region PR.

[0155] The first mask pattern 210 may cover a portion of the first active fin 202a, the second active fin 202b, and the gate dielectric material layer 208. The first opening 212 may correspond to the first gate dielectric layer removal region R4. The opposite edges of the first opening 212 may have distances d7 from the boundary line IF toward the first region NR and d8 from the boundary line IF toward the second region PR, respectively, in a second direction.

[0156] Reference Figure 12B and Figure 12C The gate dielectric material layer 208 can be etched by using the first mask pattern 210 as an etching mask to form a structure such as... Figure 12B The first gate dielectric layer 208a and the second gate dielectric layer 208b are shown.

[0157] Therefore, a first gate dielectric layer removal region R4 can be formed, wherein removal is performed near the boundary line IF between the first region NR and the second region PR. Figure 12A The gate dielectric material layer 208 is in the middle. The width of the first gate dielectric layer removal region R4 can be W11. The relative edges of the first gate dielectric layer removal region R4 can have a distance d7 from the boundary line IF toward the first region NR and a distance d8 from the boundary line IF toward the second region PR in the second direction, respectively.

[0158] like Figure 12C As shown, it can remove Figure 12B The first mask pattern 210 is shown in the image. A threshold voltage adjustment material layer 214 can be formed on the first gate dielectric layer 208a, the second gate dielectric layer 208b, the first isolation layer 204a, and the second isolation layer 204b. The threshold voltage adjustment material layer 214 can be formed on the entire surface of the substrate 200.

[0159] Reference Figure 12D and Figure 12E A second mask pattern 216 can be formed, the second mask pattern 216 having a second opening 217 that exposes the entire first region NR and a portion of the threshold voltage adjustment material layer 214 of the second region PR, as shown. Figure 12D As shown. The distance from the boundary line IF to the second mask pattern 216 of the second opening 217 can be d9. Etching is performed by using the second mask pattern 216 as an etching mask. Figure 12C A portion of the threshold voltage adjustment material layer 214 in the second region PR can be formed as a threshold voltage adjustment layer 214a.

[0160] like Figure 12E As shown, the second mask pattern 216 can be removed. In this case, the distance from the boundary line IF to one end of the threshold voltage adjustment layer 214a in the second region PR can be d9. Figure 8 As shown, the first gate electrode 218a and the second gate electrode 218b can be formed on the first region NR and the second region PR, respectively.

[0161] Figure 13A and Figure 13B It is used to explain manufacturing Figure 9 A cross-sectional view of a method for developing an integrated circuit semiconductor device.

[0162] Specifically, in Figure 13A and Figure 13B In, with Figures 7 to 9 and Figures 12A to 12E In the accompanying drawings, the same reference numerals denote the same elements. Figure 13A and Figure 13B In, with Figures 7 to 9 and Figures 12A to 12E Content that is identical to the content in the text can be briefly described or omitted.

[0163] As per the above reference Figure 8 and Figures 12A to 12E The first gate electrode 218a and the second gate electrode 218b can be formed on the first region NR and the second region PR, respectively. Figure 8 As shown, the first gate electrode 218a and the second gate electrode 218b can be connected to each other.

[0164] Then, as Figure 13A As shown, a third opening 220 can be formed near the boundary line IF between the first region NR and the second region PR, passing through the first gate electrode 218a and the second gate electrode 218b. Since the third opening 220 can be formed in the first gate dielectric layer removal region R4, it is easier to form the third opening 220.

[0165] Furthermore, since the third opening 220 can be formed in the region where the gate dielectric layer is removed, the third opening 220 can be formed more easily without excessively damaging the interlayer insulating layer (not shown) formed around the first gate electrode 218a and the second gate electrode 218b.

[0166] The width of the third opening 220 in the second direction can be W12. One sidewall of the third opening 220 can slope from the upper surface of the first gate electrode 218a and the second gate electrode 218b toward the bottom surface of the first gate electrode 218a and the second gate electrode 218b. In some embodiments, the bottom width W12b of the third opening 220 can be smaller than the top or upper width W12a. The first gate electrode 218a and the second gate electrode 218b can be separated by the third opening 220.

[0167] like Figure 13B As shown, a gate dicing material layer 221 can be formed on the first gate electrode 218a and the second gate electrode 218b while filling the third opening 220. Then, the gate dicing material layer 221 can be planarized to form a shape as shown. Figure 9 The gate dicing pattern 222 is shown.

[0168] The gate dicing pattern 222 can be defined as follows: Figure 9 The first gate dicing region CT4 shown, the first gate electrode 218a and the second gate electrode 218b can be electrically separated by the gate dicing pattern 222 that defines the first gate dicing region CT4.

[0169] Figure 14 This is a block diagram illustrating the configuration of an electronic device including an integrated circuit semiconductor device according to an embodiment of the present invention.

[0170] Specifically, the electronic device 300 may include a semiconductor chip 310. The semiconductor chip 310 may include a processor 311, embedded memory 313, and cache memory 315. The processor 311 may include one or more processor cores C1 to Cn. Processor cores C1 to Cn can process data and signals. Processor cores C1 to Cn may include integrated circuit semiconductor devices according to embodiments of the present invention.

[0171] Electronic device 300 can perform its own functions by using processed data and signals. In one example, processor 311 may include an application processor. Embedded memory 313 can exchange first data DAT1 with processor 311. First data DAT1 may be data processed or to be processed by processor cores C1 to Cn. Embedded memory 313 can manage first data DAT1. For example, embedded memory 313 may buffer first data DAT1. Embedded memory 313 may operate as a buffer memory or working memory of processor 311.

[0172] Embedded memory 313 may include static random access memory (SRAM). SRAM can operate faster than dynamic random access memory (DRAM). When SRAM is embedded in semiconductor chip 310, electronic device 300 with small size and high-speed operation can be realized. In addition, when SRAM is embedded in semiconductor chip 310, the active power consumption of electronic device 300 can be reduced.

[0173] In one example, SRAM may include an integrated circuit semiconductor device according to an embodiment of the present invention. Cache memory 315 may be mounted on semiconductor chip 310 together with processor cores C1 to Cn. Cache memory 315 may store cached data DATc. Cached data DATc may include data used by processor cores C1 to Cn. Cache memory 315 may have a relatively small storage capacity but can operate at a relatively high speed.

[0174] For example, cache memory 315 may include SRAM, which includes an integrated circuit semiconductor device according to an embodiment of the present invention. When cache memory 315 is used, the number of times processor 311 accesses embedded memory 313 and the duration of processor 311 accessing embedded memory 313 can be reduced. Therefore, when cache memory 315 is used, the operating speed of electronic device 300 can be improved.

[0175] exist Figure 14For ease of understanding, cache memory 315 is shown as a component separate from processor 311. However, cache memory 315 can be configured to be included in processor 311.

[0176] Figure 15 This is an equivalent circuit diagram of an SRAM cell according to some embodiments of the present invention.

[0177] Specifically, the SRAM cell 330 can be implemented using integrated circuit semiconductor devices 10, 20, 40 and / or 60 according to some embodiments of the present invention. For example, the SRAM cell 330 can be provided as... Figure 14 The embedded memory 313 and / or cache memory 315 described herein.

[0178] SRAM cell 330 may include a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first access transistor PG1, and a second access transistor PG2.

[0179] The first pull-up transistor PU1 and the second pull-up transistor PU2 can be P-type MOS transistors, while the first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PG1, and the second access transistor PG2 can be N-type MOS transistors.

[0180] The first pull-up transistor PU1 and the first pull-down transistor PD1 can constitute a first inverter. The gate electrodes (gates) of the first pull-up transistor PU1 and the first pull-down transistor PD1 connected to each other can correspond to the input terminals of the first inverter, and the first node N1 can correspond to the output terminals of the first inverter.

[0181] The second pull-up transistor PU2 and the second pull-down transistor PD2 can constitute a second inverter. The gate electrodes (gates) of the second pull-up transistor PU2 and the second pull-down transistor PD2 connected to each other can correspond to the input terminals of the second inverter, and the second node N2 can correspond to the output terminals of the second inverter.

[0182] The first inverter and the second inverter can be combined to form a latch structure. The gates of the first pull-up transistor PU1 and the first pull-down transistor PD1 can be electrically connected to the second node N2, and the gates of the second pull-up transistor PU2 and the second pull-down transistor PD2 can be electrically connected to the first node N1. The second source / drain of the first pull-up transistor PU1 and the second pull-up transistor PU2 can be connected to the power supply voltage Vdd. The second source / drain of the first pull-down transistor PD1 and the second pull-down transistor PD2 can be connected to the ground voltage Vss.

[0183] The first source / drain of the first access transistor PG1 can be connected to the first node N1, and the second source / drain of the first access transistor PG1 can be connected to the first bit line BL1. The first source / drain of the second access transistor PG2 can be connected to the second node N2, and the second source / drain of the second access transistor PG2 can be connected to the second bit line BL2. The gates of the first access transistor PG1 and the second access transistor PG2 can be electrically connected to the word line WL.

[0184] Figure 16 yes Figure 15 Layout diagrams of some embodiments of SRAM cells.

[0185] Specifically, Figure 16 Some embodiments may be shown, according to which... Figure 15 The SRAM cell 330 is implemented. It can be implemented using integrated circuit semiconductor devices 10, 20, 40 and / or 60 according to embodiments of the present invention. Figure 16 The SRAM cell 330 may include a unit SRAM cell 330u.

[0186] exist Figure 16 In this context, the first direction (X direction) can be the channel length direction, and the second direction (Y direction) can be the channel width direction. The SRAM cell 330 may include a first region NR1, a second region PR, and a third region NR2. The first region NR1 and the third region NR2 may be located above and below the second region PR, respectively, in the second direction (Y direction). The first region NR1 and the third region NR2 may correspond to... Figure 1 and Figure 7 The first region NR. The second region PR can correspond to... Figure 1 and Figure 7 The second region PR.

[0187] The first region NR1 and the third region NR2 may include a first transistor and a third transistor, such as an N-type MOS transistor. The first region NR1 may include a first pull-down transistor PD1 and a first access transistor PG1 as the first transistor. The third region NR2 may include a second pull-down transistor PD2 and a second access transistor PG2 as the third transistor. In some embodiments, the first pull-down transistor PD1, the first access transistor PG1, the second pull-down transistor PD2, and the second access transistor PG2 may include multi-bridge channel transistors or fin transistors.

[0188] The second region PR may include a second transistor, such as a P-type MOS transistor. The second region PR may include a first pull-up transistor PU1 and a second pull-up transistor PU2 as the second transistor. The first pull-up transistor PU1 and the second pull-up transistor PU2 may be multi-bridge channel transistors or finned transistors.

[0189] The first pull-down transistor PD1 and the first access transistor PG1 may each include two first active fins 332a extending in a first direction (X direction). Although the first pull-down transistor PD1 and the first access transistor PG1 are illustrated to have two first active fins 332a, the inventive concept is not limited thereto. The first pull-down transistor PD1 and the first access transistor PG1 may each include a first gate electrode 334a extending in a second direction (Y direction).

[0190] The first pull-down transistor PD1 and the first access transistor PG1 may include a first active contact pattern 342a (source / drain contact pattern). The first active contact pattern 342a may include a first source / drain SD1a and a second source / drain SD2a. The second source / drain SD2a of the first pull-down transistor PD1 may be connected to ground voltage Vss, and the second source / drain SD2a of the first access transistor PG1 may be connected to the first bit line BL1. A first metal contact pattern 344a connected to the word line WL may be formed in the first gate electrode 334a of the first access transistor PG1.

[0191] The second pull-down transistor PD2 and the second access transistor PG2 may each include two third active fins 332c extending along a first direction (X direction). Although the second pull-down transistor PD2 and the second access transistor PG2 are illustrated to have two third active fins 332c, the inventive concept is not limited thereto. The second pull-down transistor PD2 and the second access transistor PG2 may each include a third gate electrode 334c extending in a second direction (Y direction).

[0192] The second pull-down transistor PD2 and the second access transistor PG2 may include a fourth active contact pattern 342c (source / drain contact pattern). The fourth active contact pattern 342c may include a first source / drain SD1c and a second source / drain SD2c. The second source / drain SD2c of the second pull-down transistor PD2 may be connected to ground voltage Vss, and the second source / drain SD2c of the second access transistor PG2 may be connected to the second bit line BL2. A fourth metal contact pattern 344c connected to the word line WL may be formed on the third gate electrode 334c in the second access transistor PG2.

[0193] The first pull-up transistor PU1 and the second pull-up transistor PU2 may each have a second active fin 332b extending in a first direction (X direction). Although the first pull-up transistor PU1 and the second pull-up transistor PU2 each have a second active fin 332b, the inventive concept is not limited thereto. The first pull-up transistor PU1 and the second pull-up transistor PU2 may each include a second gate electrode 334b ​​extending in a second direction (Y direction).

[0194] The first pull-up transistor PU1 may include a second active contact pattern 342b-1 (source / drain contact pattern). The second active contact pattern 342b-1 may include a first source / drain SD1b-1 and a second source / drain SD2b-1. The first source / drain SD1b-1 may be connected to the first source / drain SD1a of the first pull-down transistor PD1 and the first access transistor PG1. The first source / drain may be connected to the first node N1 via a second metal contact pattern 344b. The second source / drain SD2b-1 may be connected to the power supply voltage Vdd.

[0195] The second pull-up transistor PU2 may include a third active contact pattern 342b-2 (source / drain contact pattern). The third active contact pattern 342b-2 may include a first source / drain SD1b-2 and a second source / drain SD2b-2. The first source / drain SD1b-2 can be connected to the second pull-down transistor PD2 and the first source / drain SD1c of the second access transistor PG2. The first source / drain SD1b-2 can be connected to the second node N2 via a second metal contact pattern 344b. The second source / drain SD2b-2 can be connected to the power supply voltage Vdd.

[0196] A first boundary extending in a first direction (X direction), such as a first boundary line IF1, can be defined at the interface between the first region NR1 and the second region PR. Due to the aforementioned metal gate boundary effect, the threshold voltages of the first pull-down transistor PD1, the first access transistor PG1, and the first pull-up transistor PU1 may deviate from their design values ​​depending on their distance from the first boundary line IF1. Therefore, the first gate dielectric layer removal region R5 from which the gate dielectric layer is removed can be formed near or adjacent to the first boundary line IF1 between the first region NR1 and the second region PR.

[0197] A second boundary, such as a second boundary line IF2, extending along a first direction (X direction), can be defined at the interface between the second region PR and the third region NR2. Due to the aforementioned metal gate boundary effect, the threshold voltages of the second pull-down transistor PD2, the second access transistor PG2, and the second pull-up transistor PU2 may deviate from their design values ​​depending on their distance from the second boundary line IF2. Therefore, the second gate dielectric layer removal region R6 from which the gate dielectric layer is removed can be formed near or adjacent to the second boundary line IF2 between the second region PR and the third region NR2.

[0198] The first gate dielectric layer removal region R5 can be configured to be shifted or offset relative to the first boundary line IF1 towards the first region NR1 or the second region PR in a second direction. In some embodiments, the width of the first gate dielectric layer removal region R5 in the second direction can be W13. The edges of the first gate dielectric layer removal region R5 can have corresponding distances d11 and d12 from the first boundary line IF1 towards the first region NR1 and the second region PR in the second direction, respectively, wherein distance d12 can be greater than distance d11.

[0199] The second gate dielectric layer removal region R6 can be configured to be shifted or offset relative to the second boundary line IF2 towards the second region PR or the third region NR2 in the second direction. In some embodiments, the width of the second gate dielectric layer removal region R6 in the second direction can be W14. The edges of the second gate dielectric layer removal region R6 can have corresponding distances d13 and d14 in the second direction from the second boundary line IF2 toward the third region NR2 and the second region PR, respectively, wherein distance d14 can be greater than distance d13.

[0200] Furthermore, the first gate dicing region CT7 can be located in the first gate dielectric layer removal region R5, in which the first gate electrode 334a of the first access transistor PG1 and the second gate electrode 334b ​​of the second pull-up transistor PU2 are diced or separated in a second direction. The first gate dicing region CT7 can be more easily formed in the first gate dielectric layer removal region R5.

[0201] Furthermore, the second gate dicing region CT8 may be located in the second gate dielectric layer removal region R6, in which the third gate electrode 334c of the second access transistor PG2 and the second gate electrode 334b ​​of the first pull-up transistor PU1 are diced or separated in a second direction. The second gate dicing region CT8 can be more easily formed in the second gate dielectric layer removal region R6.

[0202] Furthermore, the widths (in the Y direction) of the first active fin 332a, the second active fin 332b, and the third active fin 332c can be the same or different from each other. Additionally, the widths (in the Y direction) of the active fins 332a and 332b of the first region NR1 and the second region PR, which are separated from each other due to the first gate cutting region CT7, can be the same or different from each other. Furthermore, the widths (in the Y direction) of the active fins 332b and 332c of the second region PR and the third region NR2, which are separated from each other due to the second gate cutting region CT8, can be the same or different from each other.

[0203] The integrated circuit semiconductor device according to the present invention includes a gate dielectric layer removal region near the boundary line between a first region including a first transistor and a second region including a second transistor, wherein the gate dielectric layer is removed. The gate dielectric layer removal region may be configured to be tilted or offset towards the first or second region based on the boundary line, or may be located in either the first or second region.

[0204] Therefore, by preventing the threshold voltage of the first transistor and the threshold voltage of the second transistor from deviating from the design value due to the metal gate boundary effect, the first transistor and the second transistor can be reliably formed in the integrated circuit semiconductor device of the present invention.

[0205] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit semiconductor device, comprising: A first region includes a first transistor, wherein the first transistor includes a first active fin extending in a first direction, a first gate dielectric layer extending from the first active fin to a first isolation layer in a second direction perpendicular to the first direction, and a first gate electrode on the first gate dielectric layer. A second region, which contacts the first region in the second direction, wherein the second region includes a second transistor, the second transistor including a second active fin extending in the first direction, a second gate dielectric layer extending from the second active fin onto a second isolation layer in the second direction, and a second gate electrode on the second gate dielectric layer; and The gate dielectric layer removal region is located near the boundary between the first region and the second region. Wherein, the gate dielectric layer removal region is offset toward the first region or the second region in the second direction relative to the boundary, or the gate dielectric layer removal region is disposed in either the first region or the second region.

2. The integrated circuit semiconductor device according to claim 1, wherein, The gate dielectric layer removal region separates the first gate dielectric layer and the second gate dielectric layer such that the distance from the boundary to the first gate dielectric layer is different from the distance from the boundary to the second gate dielectric layer.

3. The integrated circuit semiconductor device according to claim 1, wherein, The first width of the first active fin in the second direction is different from the second width of the second active fin in the second direction.

4. The integrated circuit semiconductor device according to claim 1, wherein The first channel width of the first transistor in the second direction is different from the second channel width of the second transistor in the second direction.

5. The integrated circuit semiconductor device according to claim 1, further comprising: A first threshold voltage adjustment layer is located on the second gate dielectric layer and extends along the surface of the second gate dielectric layer. Wherein, the first threshold voltage adjustment layer is not connected to the first gate dielectric layer, and A portion of the gate dielectric layer removal region is located between the first threshold voltage adjustment layer and the first gate dielectric layer.

6. The integrated circuit semiconductor device according to claim 5, further comprising: A second threshold voltage adjustment layer is located on the first gate dielectric layer and extends along the surface of the first gate dielectric layer. Wherein, the second threshold voltage adjustment layer is not connected to the second gate dielectric layer, and The portion of the gate dielectric layer removal region is located between the second threshold voltage adjustment layer and the second gate dielectric layer.

7. The integrated circuit semiconductor device according to claim 1, further comprising: A gate dicing region that separates the first gate electrode from the second gate electrode in the second direction, wherein the gate dicing region is located on the gate dielectric layer removal region.

8. The integrated circuit semiconductor device according to claim 7, wherein, The gate dicing pattern defining the gate dicing region includes a sidewall extending upward in a third direction perpendicular to the first direction and the second direction, wherein the sidewall slopes from the lower part of the sidewall toward the upper part of the sidewall, and the lower width of the gate dicing pattern is smaller than the upper width of the gate dicing pattern.

9. The integrated circuit semiconductor device according to claim 1, wherein, The first transistor is an N-type transistor, and the second transistor is a P-type transistor.

10. The integrated circuit semiconductor device according to claim 1, wherein, The first active fin includes a first fin protrusion portion protruding from a first surface of the first isolation layer, and the second active fin includes a second fin protrusion portion protruding from a second surface of the second isolation layer.

11. An integrated circuit semiconductor device, comprising: A first region includes a first multi-bridge channel transistor, wherein the first multi-bridge channel transistor includes a first active fin protruding from a substrate and extending in a first direction, a first gate dielectric layer extending from the first active fin to a first isolation layer in a second direction perpendicular to the first direction, a plurality of first nanosheets stacked spaced apart from the first gate dielectric layer, a third gate dielectric layer surrounding the plurality of first nanosheets, and a first gate electrode located on the first gate dielectric layer and the third gate dielectric layer and located between the plurality of first nanosheets; A second region, adjacent to the first region in the second direction, includes a second multi-bridge channel transistor. The second multi-bridge channel transistor includes a second active fin protruding from the substrate and extending in the first direction; a second gate dielectric layer extending from the second active fin onto a second isolation layer in the second direction perpendicular to the first direction; a plurality of second nanosheets stacked and spaced apart from the second gate dielectric layer; a fourth gate dielectric layer surrounding the plurality of second nanosheets; and a second gate electrode located on the second gate dielectric layer and the fourth gate dielectric layer and between the plurality of second nanosheets. A gate dielectric layer removal region, located on the substrate and adjacent to the boundary between the first region and the second region. Wherein, the gate dielectric layer removal region is offset toward the first region or the second region in the second direction relative to the boundary, or the gate dielectric layer removal region is disposed in either the first region or the second region.

12. The integrated circuit semiconductor device according to claim 11, wherein, The gate dielectric layer removal region separates the first gate dielectric layer and the second gate dielectric layer such that the distance from the boundary to the first gate dielectric layer is different from the distance from the boundary to the second gate dielectric layer.

13. The integrated circuit semiconductor device according to claim 11, wherein, The first width of the first active fin in the second direction is different from the second width of the second active fin in the second direction, and the first channel width of the first multi-bridge channel transistor in the second direction is different from the second channel width of the second multi-bridge channel transistor in the second direction.

14. The integrated circuit semiconductor device of claim 11, further comprising: A threshold voltage adjustment layer is located on the second gate dielectric layer and on the fourth gate dielectric layer surrounding the plurality of second nanosheets. Wherein, the threshold voltage adjustment layer is not connected to the first gate dielectric layer, and The gate dielectric layer removal region is located between the threshold voltage adjustment layer and the first gate dielectric layer.

15. The integrated circuit semiconductor device according to claim 11, further comprising: A gate dicing region that separates the first gate electrode from the second gate electrode in the gate dielectric layer removal region. The gate dicing pattern defining the gate dicing region includes a sidewall extending upward in a third direction perpendicular to the first direction and the second direction, wherein the sidewall slopes from the lower part of the sidewall toward the upper part of the sidewall, and the lower width of the gate dicing pattern is smaller than the upper width of the gate dicing pattern.

16. The integrated circuit semiconductor device according to claim 11, wherein, The first multi-bridge channel transistor is an N-type transistor, and the second multi-bridge channel transistor is a P-type transistor.

17. An integrated circuit semiconductor device, comprising: A first region includes a first fin transistor, wherein the first fin transistor includes a first active fin protruding from a substrate and extending in a first direction, a first gate dielectric layer extending from the first active fin to a first isolation layer in a second direction perpendicular to the first direction, and a first gate electrode on the first gate dielectric layer. A second region, which contacts the first region in the second direction, wherein the second region includes a second fin transistor, the second fin transistor including a second active fin protruding from the substrate and extending in the first direction, a second gate dielectric layer extending from the second active fin in the second direction onto a second isolation layer, and a second gate electrode on the second gate dielectric layer; and The gate dielectric layer removal region is located near the boundary between the first region and the second region. Wherein, the gate dielectric layer removal region is offset toward the first region or the second region in the second direction relative to the boundary, or the gate dielectric layer removal region is disposed in either the first region or the second region.

18. The integrated circuit semiconductor device according to claim 17, wherein, The gate dielectric layer removal region separates the first gate dielectric layer and the second gate dielectric layer such that the distance from the boundary to the first gate dielectric layer is different from the distance from the boundary to the second gate dielectric layer.

19. The integrated circuit semiconductor device according to claim 17, wherein, The first width of the first active fin in the second direction is different from the second width of the second active fin in the second direction, and the first channel width of the first fin transistor in the second direction is different from the second channel width of the second fin transistor in the second direction.

20. The integrated circuit semiconductor device of claim 17, further comprising: A first threshold voltage adjustment layer is disposed on and extends along the surface of the second gate dielectric layer, wherein the first threshold voltage adjustment layer is not connected to the first gate dielectric layer. A second threshold voltage adjustment layer is provided on the first gate dielectric layer and extends along the surface of the first gate dielectric layer, wherein the second threshold voltage adjustment layer is not connected to the second gate dielectric layer. A portion of the gate dielectric layer removal region is located between the first threshold voltage adjustment layer and the second threshold voltage adjustment layer.

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