Charge pump device and image sensor including the charge pump device

Abstract

A charge pump device and an image sensor including the charge pump device are provided. The charge pump device is configured to generate an output voltage from a square wave, wherein the charge pump device includes: a semiconductor layer; a first external well and a second external well; a first internal well formed in the first external well; a second internal well formed in the second external well; a first capacitor to which the input signal is applied and connected to the first external well; and a second capacitor connected to the first capacitor and the second external well, wherein the first voltage is applied to the first external well, and a voltage lower than the first voltage is applied to the second external well.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0062788 filed on May 28, 2019, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2019-0146183 filed on November 14, 2019, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a charge pump device and an image sensor including the same; more particularly, the present disclosure relates to a multi-stage charge pump and an image sensor having wells of the same conductivity type coupled to different charge pump potentials. Background Art

[0004] An image sensor is a semiconductor-based sensor that receives light and generates an electrical signal. Each image sensor may include a pixel array having a plurality of pixels and a circuit for driving the pixel array. An image sensor may be applied to a camera that captures still images or moving images, and is widely used in smart phones, tablet personal computers (PCs), laptop computers, televisions (TVs), and the like. As the demand for improved performance of camera devices increases, research has been conducted to improve the dark current characteristics of image sensors. Summary of the invention

[0005] The present disclosure provides a charge pump device for outputting a negative voltage having an absolute value greater than an input voltage. The present disclosure should not be limited to the above content, and a person of ordinary skill in the relevant art can more clearly understand the present disclosure based on the description set forth herein.

[0006] According to an aspect of the present disclosure, there is provided a charge pump device configured to generate an output voltage from an input signal, which may be a substantially square wave varying or alternating between a first voltage and a ground voltage.

[0007] The charge pump device includes: a semiconductor layer having a first conductivity type; a first external well and a second external well separated from each other in the semiconductor layer and having a second conductivity type; a first internal well formed in the first external well and having the first conductivity type; a second internal well formed in the second external well and having the first conductivity type; a first capacitor, a first terminal of the first capacitor being applied with the input signal and a second terminal thereof being connected to the first external well; and a second capacitor, a first terminal of the second capacitor being connected to the first capacitor and a second terminal thereof being connected to the second external well, wherein the first voltage is applied to the first external well and a voltage lower than the first voltage is applied to the second external well.

[0008] According to another aspect of the present disclosure, a charge pump device is provided, the charge pump device being configured to output a voltage lower than the ground voltage to an output terminal using an input signal that alternately provides a ground voltage and a first voltage higher than the ground voltage. The charge pump device comprises: a first stage comprising a first capacitor and a first transistor, the first terminal of the first capacitor being applied with the input signal, and the first transistor being connected to the second terminal of the first capacitor; and a second stage comprising a second capacitor and a second transistor, the first terminal of the second capacitor being connected to the second terminal of the first capacitor, and the second transistor being connected to the second terminal of the second capacitor, wherein the gate electrode of the first transistor may be alternately applied with the ground voltage and a second voltage lower than the ground voltage, and the gate electrode of the second transistor may be alternately applied with the second voltage and a third voltage lower than the ground voltage.

[0009] According to another aspect of the present disclosure, a charge pump device is provided, the charge pump device being configured to generate an output voltage using an input signal that alternately provides a first voltage and a ground voltage. The charge pump device includes: a first stage including a first capacitor and a first transistor, a first terminal of the first capacitor being applied with the input signal, and the first transistor being connected to a second terminal of the first capacitor; and a second stage including a second capacitor and a second transistor, a first terminal of the second capacitor being connected to the second terminal of the first capacitor, and the second transistor being connected to a second terminal of the second capacitor, wherein the first transistor may include a body to which the first voltage is applied, and the second transistor may include a body to which the ground voltage is applied.

[0010] According to another aspect of the present disclosure, an image sensor is provided, comprising: a plurality of pixels formed in a semiconductor layer having a first conductivity type and arranged in a matrix; an isolation film arranged at the same horizontal height as the semiconductor layer and constructed to isolate the plurality of pixels from each other; a timing generator configured to generate an input signal providing a first voltage and a ground voltage; and a charge pump device configured to provide an output voltage to the isolation film using the input signal, wherein the charge pump device may include: a first external well and a second external well both formed in the semiconductor layer and having a second conductivity type; a first internal well formed in the first external well and having the first conductivity type; and a second internal well formed in the second external well and having the first conductivity type, a second voltage lower than the ground voltage is applied to the first internal well, a third voltage lower than the second voltage may be applied to the second internal well, and the output voltage may be substantially equal to the third voltage.

[0011] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor layer having a first conductivity type; an isolation film arranged at the same horizontal height as the semiconductor layer; a timing generator configured to generate an input signal having a first voltage and a ground voltage; and a charge pump configured to provide an output voltage to the isolation film based on the input signal, the charge pump comprising: a first external well and a second external well both formed in the semiconductor layer and having a second conductivity type, a first internal well formed in the first external well and having the first conductivity type, and a second internal well formed in the second external well and having the first conductivity type, wherein a second voltage lower than the ground voltage is applied to the first internal well, wherein a third voltage lower than the second voltage is applied to the second internal well, and wherein the output voltage is substantially equal to the third voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The embodiments of the present disclosure will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram of a charge pump device according to an exemplary embodiment of the present disclosure;

[0014] Figure 2A and Figure 2B is a circuit diagram of a charge pump device according to an exemplary embodiment of the present disclosure;

[0015] Figure 3 is a graph for explaining a charge pump device according to an exemplary embodiment of the present disclosure;

[0016] Figures 4 to 5C is a cross-sectional view of a charge pump device according to an exemplary embodiment of the present disclosure;

[0017] Figure 6 is a block diagram of a charge pump apparatus according to an exemplary embodiment of the present disclosure;

[0018] Figure 7 is a circuit diagram of a charge pump device according to an exemplary embodiment of the present disclosure;

[0019] Figure 8 is a graph for explaining a charge pump device according to an exemplary embodiment of the present disclosure;

[0020] Fig. 9 is a block diagram of an image sensor according to an exemplary embodiment of the present disclosure;

[0021] Fig.10 is a circuit diagram for explaining a pixel included in an image sensor according to an exemplary embodiment of the present disclosure;

[0022] Fig.11 is a plan view for explaining a pixel included in an image sensor according to an exemplary embodiment of the present disclosure;

[0023] Fig.12 is along Fig.11 A cross-sectional view taken along line II' in FIG.

[0024] Fig.13 is a block diagram of a charge pump apparatus according to an exemplary embodiment of the present disclosure;

[0025] Fig.14 is a circuit diagram of a charge pump device according to an exemplary embodiment of the present disclosure;

[0026] Figures 15 to 16C is a cross-sectional view of a charge pump device according to an exemplary embodiment of the present disclosure;

[0027] Fig.17 is a block diagram of a charge pump apparatus according to an exemplary embodiment of the present disclosure; and

[0028] Fig.18 is a circuit diagram of a charge pump device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In an exemplary embodiment, a multi-stage charge pump is configured to solve dark current characteristics and prevent breakdown between at least an n-well and a pocket p-well in a complementary metal oxide semiconductor (CMOS) image sensor when a negative voltage is applied to a boron-doped polysilicon device. According to an exemplary embodiment, for example, a negative charge pump including at least two stages may apply a first voltage +VDDA to a first n-well NW1, -VDDA to a first pocket p-well PW1, GND to a second n-well NW2, and -2×VDDA to a second pocket p-well PW2.

[0030] Figure 1 A charge pump arrangement 10 according to an exemplary embodiment of the present disclosure is shown.

[0031] According to an exemplary embodiment, the charge pump device 10 may include a first stage 11 and a second stage 12 .

[0032] According to this exemplary embodiment, the input voltage Vin may be input to the first stage 11. According to an exemplary embodiment, the input voltage Vin may be a clock signal, but is not limited thereto. According to an exemplary embodiment, the clock signal is a periodic signal with different voltage magnitudes. The input voltage Vin may be a square wave or a substantially square wave varying between the first voltage V1 and the ground voltage GND.

[0033] It should be understood that a true square wave is a non-sinusoidal periodic waveform whose amplitude alternates between fixed minimum and maximum values ​​at a steady frequency, having the same duration at the minimum and maximum values, with the transition between the minimum and maximum values ​​being theoretically instantaneous. For the purposes of this disclosure, a basic square wave is a non-sinusoidal periodic waveform whose amplitude alternates between fixed minimum and maximum values ​​that are maintained together for a majority of each cycle.

[0034] According to an exemplary embodiment, the first stage 11 may output a first node voltage Vn1. The first node voltage Vn1 may be a square wave signal different from the input voltage Vin. The first node voltage Vn1 may be a square wave signal varying between a ground voltage GND and a second voltage V2 different from the first voltage V1.

[0035] The first node voltage Vn1 may be input to the second stage 12. The second stage 12 may output an output voltage Vout. The output voltage Vout may have a substantially constant voltage value. For example, the output voltage Vout may be substantially equal to the third voltage V3.

[0036] According to an exemplary embodiment, the first stage 11 may include a first external well NW1 and a first internal well PW1. The first internal well PW1 may be formed in the first external well NW1. According to an exemplary embodiment, the first external well NW1 may have a conductivity type opposite to that of the first internal well PW1. For example, when the first external well NW1 has n-type conductivity, the first internal well PW1 may have p-type conductivity. In another example, when the first external well NW1 has p-type conductivity, the first internal well PW1 may have n-type conductivity. Hereinafter, for ease of description, it is assumed that the first external well NW1 has n-type conductivity and the first internal well PW1 has p-type conductivity. However, it should be understood that, based on the description herein, a person of ordinary skill in the relevant art will be able to easily implement a charge pump device in which the first external well has p-type conductivity and the first internal well has n-type conductivity in a manner similar to that described herein.

[0037] Now continuing with the example that the first external well NW1 has n-type conductivity and the first internal well PW1 has p-type conductivity, the voltage applied to the first external well NW1 can be different from the voltage applied to the first internal well PW1. A first voltage V1 can be applied to the first external well NW1. A second voltage V2 different from the first voltage V1 can be applied to the first internal well PW1. In some examples, the second voltage V2 can have an opposite polarity to the first voltage V1.

[0038] According to an exemplary embodiment, the second stage 12 may include a second outer well NW2 and a second inner well PW2. The second inner well PW2 may be formed in the second outer well NW2. According to an exemplary embodiment, the second outer well NW2 may have a conductivity type opposite to that of the second inner well PW2. For example, when the second outer well NW2 has n-type conductivity, the second inner well PW2 may have p-type conductivity. In another example, when the second outer well NW2 has p-type conductivity, the second inner well PW2 may have n-type conductivity.

[0039] According to an exemplary embodiment, the voltage applied to the second external well NW2 may be different from the voltage applied to the first external well NW1. The ground voltage GND may be applied to the second external well NW2. According to an exemplary embodiment, the ground voltage GND is a reference point for other potentials and may be defined as having an electric potential of 0 V. However, the embodiment is not limited thereto, and a voltage higher than the ground voltage GND (e.g., a voltage equal to or higher than 1 V) may be applied to the second external well NW2.

[0040] According to an exemplary embodiment, a voltage applied to the second internal well PW2 may be different from a voltage applied to the first internal well PW1. According to an exemplary embodiment, a third voltage V3 may be applied to the second internal well PW2. According to an exemplary embodiment, the third voltage V3 may be substantially twice the second voltage V2, but is not limited thereto.

[0041] According to an exemplary embodiment, the voltage difference between the first external well NW1 and the first internal well PW1 may be substantially the same as the voltage difference between the second external well NW2 and the second internal well PW2, but the embodiment is not limited thereto. For example, the voltage difference between the first external well NW1 and the first internal well PW1 may be different from the voltage difference between the second external well NW2 and the second internal well PW2. According to an exemplary embodiment, the voltage difference between the second external well NW2 and the second internal well PW2 may be greater than the voltage difference between the first external well NW1 and the first internal well PW1.

[0042] Figure 2A and Figure 2B They are shown respectively Figure 1 The charge pump device 10 and 10' are circuits. Figure 2B The charge pump device 10' may be substantially similar to Figure 2A The charge pump device 10 may be omitted from repeated description.

[0043] Reference Figure 2A , the first stage 11 may include a first capacitor C1 and a first transistor T1, and the second stage 12 may include a second capacitor C2, a second transistor T2, and a third transistor T3.

[0044] According to an exemplary embodiment, the first transistor T1 and the second transistor T2 may include a p-type metal oxide semiconductor field effect transistor (MOSFET). According to an exemplary embodiment, the third transistor T3 may include an n-type MOSFET.

[0045] According to an exemplary embodiment, the first terminal of the first capacitor C1 may be connected to the input terminal "in". According to an exemplary embodiment, the input voltage Vin may be applied to the first terminal of the first capacitor C1. According to an exemplary embodiment, the first transistor T1 may be connected to the second terminal of the first capacitor C1. A node connected to the second terminal of the first capacitor C1 and the first transistor T1 is defined as a first node n1, and a potential difference between the first node n1 and the ground voltage GND is defined as a first node voltage Vn1.

[0046] According to an exemplary embodiment, at least a portion of the first external well NW1 may form a body of the first transistor T1. According to an exemplary embodiment, a first voltage V1 may be applied to the first external well NW1. A first switching signal SW1 may be applied to a gate (or control electrode) of the first transistor T1 as a control signal. A first electrode of the first transistor T1 may be connected to a second terminal of the first capacitor C1 at a first node n1, and a ground voltage GND may be applied to a second electrode of the first transistor T1.

[0047] The first terminal of the second capacitor C2 may be connected to the second terminal of the first capacitor C1. The first terminal of the second capacitor C2 may be connected to the first node n1. The first node voltage Vn1 may be applied to the first terminal of the second capacitor C2. The second transistor T2 and the third transistor T3 may be connected to the second terminal of the second capacitor C2.

[0048] A node connected to the second terminal of the second capacitor C2 and the second and third transistors T2 and T3 is defined as a second node n2 , and a potential difference between a potential of the second node n2 and the ground voltage GND is defined as a second node voltage Vn2 .

[0049] According to an exemplary embodiment, at least a portion of the second external well NW2 may form a body of the second transistor T2. A ground voltage GND may be applied to the second external well NW2. A second switching signal SW2 may be applied to the gate of the second transistor T2 as a control signal. A first electrode of the second transistor T2 may be connected to a second terminal of the second capacitor C2 at a second node n2. According to an exemplary embodiment, a second voltage V2 may be applied to a second electrode of the second transistor T2.

[0050] According to an exemplary embodiment, at least a portion of the second internal well PW2 may form a body of the third transistor T3. A third voltage V3 may be applied to the second internal well PW2. A third switching signal SW3 may be applied to the gate of the third transistor T3 as a control signal. A first electrode of the third transistor T3 may be connected to a second terminal of the second capacitor C2 at a second node n2. A second electrode of the third transistor T3 may be connected to an output terminal "out". According to an exemplary embodiment, a second electrode of the third transistor T3 may be connected to a node connected to the second internal well PW2, and therefore, a third voltage V3 may be applied to a second electrode of the third transistor T3.

[0051] Now refer to Figure 2B, the charge pump device 10' may further include an inverter I1 located between the input terminal "in" and the first capacitor C1. According to an exemplary embodiment, the ground voltage GND and the first voltage V1 may be applied to the inverter I1 as operating voltages. Next, the output voltage of the inverter I1 may be applied to the first terminal of the first capacitor C1. Therefore, the inverter I1 may have a high input impedance and a high current driving performance. Therefore, the operating characteristics of the charge pump device 10' may be improved, and the reliability may be enhanced.

[0052] Figure 3 Shown for illustration Figure 2A 1 is a graph of the charge pump device 10. In detail, the graph schematically shows the changes of the input voltage Vin, the first node voltage Vn1 and the second node voltage Vn2, the first to third switch signals SW1, SW2 and SW3, and the output voltage Vout over time. Although for the convenience of description Figure 3 SW2 and SW3 are shown together in FIG. 1 , but it should be understood that each of these control signals may be independently applied to the gates of transistors T2 and T3 , respectively.

[0053] Reference Figure 2A and Figure 3 , the input voltage Vin may be a square wave signal varying between a first voltage V1 and a ground voltage GND. The input voltage Vin may change periodically. From the reference time t0 to the first time t1, from the second time t2 to the third time t3, and from the fourth time t4 to the fifth time t5, the input voltage Vin may be maintained at the first voltage V1. From the first time t1 to the second time t2, and from the third time t3 to the fourth time t4, the input voltage Vin may be maintained at the ground voltage GND.

[0054] Therefore, the first node voltage Vn1 may be a square wave signal that periodically changes between the ground voltage GND and the second voltage V2. From the reference time t0 to the first time t1, from the second time t2 to the third time t3, and from the fourth time t4 to the fifth time t5, the voltage Vn1 may be maintained at the ground voltage GND. From the first time t1 to the second time t2 and from the third time t3 to the fourth time t4, the voltage Vn1 may be maintained at the second voltage V2.

[0055] Similarly, the second node voltage Vn2 may be a square wave signal that periodically changes between the second voltage V2 and the third voltage V3. From the reference time t0 to the first time t1, from the second time t2 to the third time t3, and from the fourth time t4 to the fifth time t5, the voltage Vn2 may be maintained at the second voltage V2. From the first time t1 to the second time t2 and from the third time t3 to the fourth time t4, the voltage Vn1 may be maintained at the third voltage V3.

[0056] According to an exemplary embodiment, the first time t1 to the fifth time t5 may be sequentially after the reference time t0. The time period between the sequentially adjacent times in time may be constant, but is not limited thereto. For example, the time period between the reference time t0 and the first time t1 at which the input voltage Vin is maintained at the first voltage V1 may be greater than or less than the time period between the first time t1 and the second time t2 at which the input voltage Vin is maintained at the ground voltage GND.

[0057] According to an exemplary embodiment, when the input voltage Vin is the first voltage V1, the first switch signal SW1 may be the second voltage V2. When the first switch signal SW1 is the second voltage V2, the first transistor T1 may be in an on state, and the first node voltage Vn1 may be substantially equal to the ground voltage GND. Therefore, the potential difference between the first terminal and the second terminal of the first capacitor C1 may be substantially equal to the first voltage V1.

[0058] When the input voltage Vin is the first voltage V1, the second switch signal SW2 may be the third voltage V3. When the second switch signal SW2 is the third voltage V3, the second transistor T2 may be in a turned-on state, and the second node voltage Vn2 may be substantially equal to the second voltage V2.

[0059] The third switch signal SW3 may be substantially the same as the second switch signal SW2. According to an exemplary embodiment, when the third switch signal SW3 is the third voltage V3, the third transistor T3 may be in an off state. Therefore, the output terminal "out" may not be directly connected to the second node n2, or the output terminal "out" may be short-circuited with the second node n2.

[0060] According to an exemplary embodiment, when the input voltage Vin is the ground voltage GND, the first switch signal SW1 may be the ground voltage GND. When the first switch signal SW1 is the ground voltage GND, the first transistor T1 may be in an off state, and the first node voltage Vn1 may be different from the ground voltage GND. According to an exemplary embodiment, the voltage between the first terminal and the second terminal of the first capacitor C1 continuously changes, and therefore, the potential difference between the first terminal and the second terminal of the first capacitor C1 may be maintained at the first voltage V1. Therefore, the first node voltage Vn1 may be substantially equal to the second voltage V2.

[0061] When the input voltage Vin is the ground voltage GND, the second switch signal SW2 may be a second voltage V2. When the second switch signal SW2 is the second voltage V2, the second transistor T2 may be in an off state. According to an exemplary embodiment, the voltage between the first terminal and the second terminal of the second capacitor C2 changes continuously, and therefore, the potential difference between the first terminal and the second terminal of the second capacitor C2 may be maintained at the first voltage V1. Therefore, the second node voltage Vn2 may be substantially equal to a third voltage V3 that is approximately twice the second voltage V2.

[0062] According to an exemplary embodiment, when the third switch signal SW3 is the second voltage V2, the third transistor T3 may be in an on state, and the output voltage Vout may be substantially equal to the second node voltage Vn2. Therefore, the third voltage V3 may be output. Although not shown, a load (e.g., a capacitor) may be connected to the output terminal "out". In this case, even when the third transistor T3 is in an off state, the output voltage Vout may be maintained at the third voltage V3.

[0063] Figure 4 Shows Figure 1 and Figure 2A 1 is a cross-sectional view of a charge pump device 10 .

[0064] According to an exemplary embodiment, the charge pump device 10 may include first and second internal wells PW1 and PW2 and first and second external wells NW1 and NW2. The first and second internal wells PW1 and PW2 and the first and second external wells NW1 and NW2 may be formed in an epitaxial layer Epi on a substrate Sb.

[0065] According to an exemplary embodiment, the substrate Sb may include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, or a silicon-germanium substrate, but is not limited thereto. According to an exemplary embodiment, the substrate Sb may include one selected from the group consisting of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof.

[0066] According to an exemplary embodiment, the substrate Sb may include a doped semiconductor layer. According to an exemplary embodiment, the substrate Sb may be doped with a p-type dopant, but is not limited thereto.

[0067] According to an exemplary embodiment, the epitaxial layer Epi may include a semiconductor material layer formed by selective epitaxial growth. According to an exemplary embodiment, the epitaxial layer Epi may be doped with a p-type dopant. According to an exemplary embodiment, the epitaxial layer Epi may be doped at a higher concentration than the substrate Sb, but is not limited thereto.

[0068] According to an exemplary embodiment, the first outer well NW1 and the second outer well NW2 may be doped with an n-type dopant. According to an exemplary embodiment, the first outer well NW1 and the second outer well NW2 may be arranged adjacent to each other, but are not limited thereto.

[0069] According to example embodiments, the first internal well PW1 may be formed in the first external well NW1, and the second internal well PW2 may be formed in the second external well NW2. According to example embodiments, the first internal well PW1 and the second internal well PW2 may be doped with a p-type dopant.

[0070] According to an exemplary embodiment, a p-type region P+ and an n-type region N+ formed in the first external well NW1 and a first gate electrode GE1 formed on the first external well NW1 may constitute a first transistor T1. According to an exemplary embodiment, a first switching signal SW1 (at Figure 2A ) may be applied to the first gate electrode GE1.

[0071] According to an exemplary embodiment, the p-type regions P+ in the first external well NW1 may respectively form different electrodes of the first transistor T1. According to an exemplary embodiment, the p-type regions P+ in the first external well NW1 may be the source and drain of the first transistor T1.

[0072] According to an exemplary embodiment, the n-type region N+ in the first external well NW1 may be a contact region for applying a voltage to the body of the first transistor T1. According to an exemplary embodiment, the first voltage V1 may be substantially constantly applied to the first external well NW1 through the n-type region N+ in the first external well NW1.

[0073] According to an exemplary embodiment, a p-type region P+ may be formed in the first internal well PW1. According to an exemplary embodiment, the second voltage V2 may be substantially constantly applied to the first internal well PW1 through the p-type region P+ in the first internal well PW1.

[0074] According to an exemplary embodiment, the p-type region P+ and the n-type region N+ formed in the second external well NW2 and the second gate electrode GE2 formed on the second external well NW2 may constitute the second transistor T2. According to an exemplary embodiment, the second switching signal SW2 (at Figure 2A ) may be applied to the second gate electrode GE2.

[0075] According to an exemplary embodiment, the p-type regions P+ in the second outer well NW2 may respectively form different electrodes of the second transistor T2. According to an exemplary embodiment, the p-type regions P+ in the second outer well NW2 may be the source and drain of the second transistor T2.

[0076] According to an exemplary embodiment, the n-type region N+ in the second external well NW2 may be a contact region for applying a voltage to the body of the second transistor T2. According to an exemplary embodiment, the ground voltage GND may be substantially constantly applied to the second external well NW2 through the n-type region N+ in the second external well NW2. According to an exemplary embodiment, a potential higher than the ground voltage GND (e.g., about 1V) may be substantially constantly applied to the second external well NW2 through the n-type region N+ in the second external well NW2.

[0077] According to an exemplary embodiment, the p-type region P+ and the n-type region N+ formed in the second internal well PW2 and the third gate electrode GE3 formed on the second internal well PW2 may constitute the third transistor T3. According to an exemplary embodiment, the n-type region N+ in the second internal well PW2 may respectively form different electrodes of the third transistor T3. According to an exemplary embodiment, the third switching signal SW3 (at Figure 2A ) may be applied to the third gate electrode GE3.

[0078] According to an exemplary embodiment, the n-type region N+ in the second internal well PW2 may be a source and a drain of the third transistor T3. According to an exemplary embodiment, the p-type region P+ in the second internal well PW2 may be a contact region for applying a voltage to the body of the third transistor T3. According to an exemplary embodiment, the third voltage V3 may be substantially constantly applied to the second internal well PW2 through the p-type region P+ in the second internal well PW2.

[0079] According to example embodiments, a voltage difference between the second outer well NW2 and the second inner well PW2 may be substantially the same as a voltage difference between the first outer well NW1 and the first inner well PW1 .

[0080] According to an exemplary embodiment, the charge pump device 10 may include two stages (i.e., the first stage 11 and the second stage 12), and a potential lower than that applied to the first external well NW1 may be applied to the second external well NW2 included in the second stage 12. Therefore, even when the third voltage V3 having an absolute value greater than the second voltage V2 is applied to the second internal well PW2, junction breakdown may be prevented. Therefore, the charge pump device 10 may have enhanced reliability.

[0081] According to an exemplary embodiment, the p-type region P+ in the first stage 11 and the second stage 12 may be a region doped with a p-type dopant at a high concentration. The n-type region N+ in the first stage 11 and the second stage 12 may be a region doped with an n-type dopant at a high concentration. According to an exemplary embodiment, the first to third gate electrodes GE1 to GE3 in the first stage 11 and the second stage 12 may include a structure in which a metal gate is formed on silicon oxide.

[0082] According to an exemplary embodiment, the first capacitor C1 and the second capacitor C2 may be formed at the same level as a wiring layer formed in a back-end-of-line (BEOL) process and / or a front-end-of-line (FEOL) process. According to an exemplary embodiment, the first capacitor C1 and the second capacitor C2 may be formed using a BEOL process and / or a FEOL process.

[0083] FIG. 5A to FIG. 5C Shows Figure 1 1 is a cross-sectional view of a charge pump device 10 .

[0084] Reference will be omitted Figure 4 , and the following description will focus on the differences.

[0085] Reference Figure 5A , the epitaxial layer Epi may be formed on the substrate Sba. According to an exemplary embodiment, the substrate Sba may be doped with an n-type dopant. According to an exemplary embodiment, similar to the above reference Figure 4 The epitaxial layer Epi described above may be doped with a p-type dopant.

[0086] Reference Figure 5B , the epitaxial layer Epi may be omitted. Therefore, the first internal well PW1 and the second internal well PW2 may be formed in the substrate Sbb. According to an exemplary embodiment, the substrate Sbb may be doped with a high concentration of a p-type dopant.

[0087] Reference Figure 5C , a fourth voltage V4 higher than the ground voltage GND may be applied to the second outer well NW2. According to an exemplary embodiment, a voltage difference between the second outer well NW2 and the second inner well PW2 may be different from a voltage difference between the first outer well NW1 and the first inner well PW1. According to an exemplary embodiment, a voltage difference between the second outer well NW2 and the second inner well PW2 may be greater than a voltage difference between the first outer well NW1 and the first inner well PW1.

[0088] Figure 6 A charge pump arrangement 15 according to an exemplary embodiment of the present disclosure is shown.

[0089] According to an exemplary embodiment, the charge pump device 15 may include a first stage 16 and a second stage 17 .

[0090] According to an exemplary embodiment, an input voltage Vin and a complementary input voltage VinB may be input to the first stage 16. According to an exemplary embodiment, Figure 6 The input voltage Vin can be compared with the reference Figures 1 to 3According to an exemplary embodiment, the complementary input voltage VinB may be a square wave clock signal having substantially the same amplitude as the input voltage Vin and an opposite phase to the input voltage Vin.

[0091] According to an exemplary embodiment, the first stage 16 may output a first node voltage Vn1 and a third node voltage Vn3 (as discussed below). Figure 7 As shown, the third node voltage Vn3 can be expressed as Figure 6 The first node voltage Vn1 can be the same as the voltage Vn1 output by the first stage 16 shown in FIG. Figure 1 and Figure 3 According to an exemplary embodiment, the third node voltage Vn3 may be a square wave signal having substantially the same amplitude as the first node voltage Vn1 and an opposite phase to the first node voltage Vn1.

[0092] According to an exemplary embodiment, the first node voltage Vn1 and the third node voltage Vn3 may be input to the second stage 17. According to an exemplary embodiment, the second stage 17 may output an output voltage Vout. According to an exemplary embodiment, the output voltage Vout may have a substantially constant voltage value. The output voltage Vout may be substantially equal to the third voltage V3.

[0093] According to an exemplary embodiment, the first stage 16 may include a first external well NW1 and a first internal well PW1. The first internal well PW1 and the first external well NW1 may be similar to those already mentioned with reference to Figure 1 The first inner well PW1 and the first outer well NW1 are described as being substantially identical.

[0094] According to an exemplary embodiment, the second stage 17 may include a second outer well NW2 and a second inner well PW2. The second inner well PW2 and the second outer well NW2 may be the same as those already mentioned. Figure 1 The second inner well PW2 and the second outer well NW2 are described to be substantially identical.

[0095] In an alternative embodiment, a charge pump device 15 ′ may be employed in which the first outer well has p-type conductivity and the first inner well has n-type conductivity.

[0096] Figure 7 Shows Figure 6 A circuit of the charge pump device 15.

[0097] Reference Figure 7, the first stage 16 may include a first capacitor C1, a third capacitor C3, a first transistor T1, a fourth transistor T4, a seventh transistor T7, and an eighth transistor T8. The second stage 17 may include a second capacitor C2, a fourth capacitor C4, a second transistor T2, a third transistor T3, a fifth transistor T5, a sixth transistor T6, a ninth transistor T9, and a tenth transistor T10.

[0098] According to an exemplary embodiment, the first transistor T1, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 may each be a p-type MOSFET. According to an exemplary embodiment, the third transistor T3 and the sixth to tenth transistors T6 to T10 may each be an n-type MOSFET.

[0099] According to an exemplary embodiment, the connections and operations of the first to third transistors T1, T2, and T3 and the first and second capacitors C1 and C2 are similar to those of the reference Figure 2A According to an exemplary embodiment, the voltage applied to each of the first and second external wells NW1 and NW2 and the first and second internal wells PW1 and PW2 is the same as that of the reference Figure 2A According to an exemplary embodiment, the input voltage Vin, the first to third switch signals SW1, SW2 and SW3, and the first node voltage Vn1 and the second node voltage Vn2 are the same as those described above. Figure 2A Same as those described.

[0100] Connections and operations of the fourth to sixth transistors T4 , T5 , and T6 and the third and fourth capacitors C3 and C4 are similar to those of the first to third transistors T1 , T2 , and T3 and the first and second capacitors C1 and C2 .

[0101] In detail, the first terminal of the third capacitor C3 may be connected to the complementary input terminal inB. The complementary input voltage VinB may be applied to the first terminal of the third capacitor C3. The fourth transistor T4 may be connected to the second terminal of the third capacitor C3. The node connected to the second terminal of the third capacitor C3 and the fourth transistor T4 is defined as a third node n3, and the potential difference between the third node n3 and the ground voltage GND is defined as a third node voltage Vn3.

[0102] According to an exemplary embodiment, at least a portion of the first external well NW1 may form a body of each of the first transistor T1 and the fourth transistor T4. The first complementary switch signal SW1B may be applied to the gate of the fourth transistor T4 as a control signal. According to an exemplary embodiment, a first electrode of the fourth transistor T4 may be connected to a second terminal of the third capacitor C3 at a third node n3, and a ground voltage GND may be applied to a second electrode of the fourth transistor T4.

[0103] According to an exemplary embodiment, at least a portion of the first internal well PW1 may form a body of the seventh transistor T7. The third node voltage Vn3 may be applied to the gate of the seventh transistor T7 as a control signal. The first electrode of the seventh transistor T7 may be connected to the second terminal of the first capacitor C1 at the first node n1, and the second electrode of the seventh transistor T7 may be connected to the first internal well PW1.

[0104] According to an exemplary embodiment, at least a portion of the first internal well PW1 may form a body of the eighth transistor T8. The first node voltage Vn1 may be applied to the gate of the eighth transistor T8 as a control signal. The first electrode of the eighth transistor T8 may be connected to the second terminal of the third capacitor C3 at the third node n3, and the second electrode of the eighth transistor T8 may be connected to the first internal well PW1.

[0105] According to an exemplary embodiment, a first terminal of the fifth capacitor C5 may be connected to the first internal well PW1. A ground voltage GND may be applied to a second terminal of the fifth capacitor C5. According to an exemplary embodiment, a first node voltage Vn1 and a third node voltage Vn3 may be alternately applied to the first terminal of the fifth capacitor C5. Therefore, the potential of the first internal well PW1 may be maintained at the second voltage V2.

[0106] The first terminal of the fourth capacitor C4 may be connected to the second terminal of the third capacitor C3 at the third node n3. The third node voltage Vn3 may be applied to the first terminal of the fourth capacitor C4. The fifth transistor T5 and the sixth transistor T6 may be connected to the second terminal of the fourth capacitor C4.

[0107] A node connected to the second terminal of the fourth capacitor C4 and the fifth and sixth transistors T5 and T6 is defined as a fourth node n4 , and a potential difference between the fourth node n4 and the ground voltage GND is defined as a fourth node voltage Vn4 .

[0108] According to an exemplary embodiment, at least a portion of the second external well NW2 may form a body of each of the second transistor T2 and the fifth transistor T5. The second complementary switch signal SW2B may be applied to the gate of the fifth transistor T5 as a control signal. The first electrode of the fifth transistor T5 may be connected to the second terminal of the fourth capacitor C4 at the fourth node n4, and the second voltage V2 may be applied to the second electrode of the fifth transistor T5.

[0109] According to an exemplary embodiment, at least a portion of the second internal well PW2 may form a body of each of the third transistor T3 and the sixth transistor T6. The third complementary switch signal SW3B may be applied to the gate of the sixth transistor T6 as a control signal. The first electrode of the sixth transistor T6 may be connected to the second terminal of the fourth capacitor C4 at the fourth node n4, and the second electrode of the sixth transistor T6 may be connected to the output terminal "out". According to an exemplary embodiment, the second electrode of the sixth transistor T6 may be connected to a node connected to the second internal well PW2, and therefore, the third voltage V3 may be applied to the second electrode of the sixth transistor T6.

[0110] According to an exemplary embodiment, at least a portion of the second internal well PW2 may form a body of the ninth transistor T9. The fourth node voltage Vn4 may be applied to the gate of the ninth transistor T9 as a control signal. The first electrode of the ninth transistor T9 may be connected to the second terminal of the second capacitor C2 at the second node n2, and the second electrode of the ninth transistor T9 may be connected to the second internal well PW2.

[0111] According to an exemplary embodiment, at least a portion of the second internal well PW2 may form a body of the tenth transistor T10. The second node voltage Vn2 may be applied to the gate of the tenth transistor T10 as a control signal. The first electrode of the tenth transistor T10 may be connected to the second terminal of the fourth capacitor C4 at the fourth node n4, and the second electrode of the tenth transistor T10 may be connected to the second internal well PW2.

[0112] According to an exemplary embodiment, the second internal well PW2 may also be connected to the first terminal of the sixth capacitor C6. The second voltage V2 may be applied to the second terminal of the sixth capacitor C6. The second node voltage Vn2 and the fourth node voltage Vn4 may be alternately applied to the first terminal of the sixth capacitor C6. Therefore, the voltage at each of the first terminal and the second terminal of the sixth capacitor C6 may remain substantially constant, and the potential of the second internal well PW2 may be maintained at the third voltage V3.

[0113] According to some embodiments, similar to the first capacitor C1 and the second capacitor C2 , the third through sixth capacitors C3 through C6 may be formed using at least one process selected from a FEOL process and a BEOL process.

[0114] Figure 8 Shown for illustration Figure 6 and Figure 7 Graph showing the operation of the charge pump device 15. In detail, Figure 8The graph shows changes in the input voltage Vin, the complementary input voltage VinB, the first to third switching signals SW1 to SW3, the first to third complementary switching signals SW1B to SW3B, the first to fourth node voltages Vn1 to Vn4, and the output voltage Vout over time.

[0115] According to an exemplary embodiment, the input voltage Vin, the first and second node voltages Vn1 and Vn2, and the first to third switching signals SW1 to SW3 are related to the reference voltage. Figure 3 According to an exemplary embodiment, the operations of the first to third transistors T1 to T3 are substantially the same as those described above. Figure 3 The operations described are essentially the same.

[0116] The complementary input voltage VinB, the third node voltage Vn3 and the fourth node voltage Vn4, and the first to third complementary switch signals SW1B to SW3B may be square wave signals complementary to the input voltage Vin, the first and second node voltages Vn1 and Vn2, and the first to third switch signals SW1 to SW3, respectively. According to an exemplary embodiment, the complementary square wave signals have the same voltage magnitude as each other and have opposite phases to each other.

[0117] Therefore, the operation of the fourth transistor T4 to the sixth transistor T6 can be the same as the operation of the first transistor T1 to the third transistor T3, but can be delayed by half a cycle. In detail, when the first transistor T1 is in an on or off state, the fourth transistor T4 can be in an off or on state. According to an exemplary embodiment, when the second transistor T2 is turned on or off, the fifth transistor T5 can be turned off or on. According to an exemplary embodiment, when the third transistor T3 is turned on or off, the sixth transistor T6 can be turned off or on.

[0118] When the first node voltage Vn1 is the ground voltage GND and the third node voltage Vn3 is the second voltage V2, the seventh transistor T7 may be in an off state and the eighth transistor T8 may be in an on state. Therefore, the second voltage V2 corresponding to the third node voltage Vn3 may be applied to the first terminal of the fifth capacitor C5.

[0119] When the first node voltage Vn1 is the second voltage V2 and the third node voltage Vn3 is the ground voltage GND, the seventh transistor T7 may be in an on state and the eighth transistor T8 may be in an off state. Therefore, the second voltage V2 corresponding to the first node voltage Vn1 may be applied to the first terminal of the fifth capacitor C5.

[0120] According to some embodiments, the second voltage V2 is substantially constantly applied to the first terminal of the fifth capacitor C5 through the first node n1 or the third node n3, and thus the potential difference between the first terminal and the second terminal of the fifth capacitor C5 can be kept constant. Therefore, the potential of the first internal well PW1 can be substantially constantly kept at the second voltage V2.

[0121] According to an exemplary embodiment, the gate of the third transistor T3 and the gate of the ninth transistor T9 may be connected to the fourth node n4. Therefore, the third transistor T3 and the ninth transistor T9 may be controlled by the fourth node voltage Vn4. According to an exemplary embodiment, the gate of the sixth transistor T6 and the gate of the tenth transistor T10 may be connected to the second node n2. Therefore, the sixth transistor T6 and the tenth transistor T10 may be controlled by the second node voltage Vn2.

[0122] When the second node voltage Vn2 is the second voltage V2 and the fourth node voltage Vn4 is the third voltage V3, the ninth transistor T9 may be in an off state and the tenth transistor T10 may be in an on state. Therefore, the third voltage V3 corresponding to the fourth node voltage Vn4 may be applied to the first terminal of the sixth capacitor C6.

[0123] When the second node voltage Vn2 is the third voltage V3 and the fourth node voltage Vn4 is the second voltage V2, the ninth transistor T9 may be in the on state and the tenth transistor T10 may be in the off state. Therefore, the third voltage V3 corresponding to the second node voltage Vn2 may be applied to the first terminal of the sixth capacitor C6.

[0124] Accordingly, the second voltage V2 is substantially constantly applied to the second terminal of the sixth capacitor C6, and thus the potential difference between the first and second terminals of the sixth capacitor C6 can be kept constant, and the second potential of the second internal well PW2 can be substantially constantly kept at the third voltage V3.

[0125] According to an exemplary embodiment, the third transistor T3 and the sixth transistor T6 may be connected to the output terminal "out". Therefore, when the third transistor T3 is in an off state and the sixth transistor T6 is in an on state, a third voltage V3 corresponding to the fourth node voltage Vn4 and complementary to the second node voltage Vn2 may be output as the output voltage Vout. When the third transistor T3 is in an on state and the sixth transistor T6 is in an off state, a third voltage V3 corresponding to the second node voltage Vn2 may be output as the output voltage Vout. Therefore, the output voltage Vout may be substantially constantly maintained at the third voltage V3.

[0126] Fig. 9 An exemplary embodiment according to the present disclosure includes Figure 1The charge pump device 10 or Figure 6 FIG. 1 is an exemplary device layout of the image sensor 1 of the charge pump device 15 .

[0127] Reference Fig. 9 The image sensor 1 may include a charge pump device 10 or 15, an active pixel sensor array 20, a row decoder 30, a row driver 40, a column decoder 50, a timing generator 60, a correlated double sampler (CDS) 70, an analog-to-digital converter (ADC) 80 and an input / output buffer 90.

[0128] The active pixel sensor array 20 may include a plurality of pixels arranged in two dimensions. The active pixel sensor array 20 may convert an optical signal into an electrical signal. The active pixel sensor array 20 may be driven by a plurality of driving signals (e.g., a pixel selection signal, a reset signal, and a charge transfer signal) of a row driver 40. The electrical signal generated by the conversion of the active pixel sensor array 20 may be provided to the CDS 70.

[0129] The row driver 40 may provide a plurality of driving signals for driving a plurality of pixels to the active pixel sensor array 20 according to the decoding result from the row decoder 30. When pixels included in the active pixel sensor array 20 are arranged in a matrix, a driving signal may be provided to each row.

[0130] The timing generator 60 may provide timing signals and control signals to the row decoder 30 and the column decoder 50. The timing generator 60 may provide an input voltage to the charge pump device 10 or 15 according to some embodiments.

[0131] The CDS 70 may receive an electrical signal from the active pixel sensor array 20 and may hold and sample the electrical signal. The CDS 70 may perform double sampling on a specific noise level and signal size of the electrical signal and output a differential level corresponding to the difference between the noise level and the signal level.

[0132] The ADC 80 may convert an analog signal corresponding to the differential level output from the CDS 70 into a digital signal.

[0133] The input / output buffer 90 may latch the digital signal and sequentially output the latched digital signal to an image signal processor (not shown) according to the decoding result from the column decoder 50 .

[0134] In alternative embodiments, a charge pump device 10 ″ or 15 ″ may be employed in which the first outer well has p-type conductivity and the first inner well has n-type conductivity.

[0135] Fig.10 Shown for description Fig. 9 A circuit of a pixel included in an image sensor.

[0136] Reference Fig. 9 and Fig.10 , the active pixel sensor array 20 may include a plurality of pixels PX that may be arranged in a matrix.

[0137] According to an exemplary embodiment, the pixel PX may include a transfer transistor TX and a logic transistor. According to an exemplary embodiment, the logic transistor may include a reset transistor RX, a selection transistor SX, and a drive transistor DX. The transfer transistor TX may include a transfer gate TG, a photoelectric conversion element PD, and a floating diffusion area FD.

[0138] The photoelectric conversion element PD can generate and accumulate photocharges proportional to the amount of incident light. The photoelectric conversion element PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof. The transfer gate TG may transfer the charge accumulated in the photoelectric conversion element PD to the floating diffusion area FD. The photocharges generated in the photoelectric conversion element PD may be stored in the floating diffusion area FD. The drive transistor DX may be controlled by the amount of photocharges accumulated in the photoelectric conversion element PD.

[0139] The reset transistor RX may periodically reset the charge accumulated in the floating diffusion area FD in response to the reset signal RG. The drain electrode of the reset transistor RX may be connected to the floating diffusion area FD, and the source electrode of the reset transistor RX may be connected to the power supply voltage VDD. When the reset transistor RX is turned on, the power supply voltage VDD connected to the source electrode of the reset transistor RX may be transmitted to the floating diffusion area FD. Therefore, when the reset transistor RX is turned on, the charge accumulated in the floating diffusion area FD may be released, and thus, the floating diffusion area FD may be reset.

[0140] The drive transistor DX can be combined with a constant current source outside the pixel PX, and thus can be used as a source follower buffer amplifier. The drive transistor DX can amplify the potential change in the floating diffusion region FD and output the amplified result to the output line Lout.

[0141] The selection transistor SX may select a pixel PX to be read in each row in response to a selection signal SG. When the selection transistor SX is turned on, the power supply voltage VDD may be transmitted to the source electrode of the driving transistor DX.

[0142] Fig.11 Shows Fig. 9 A plan view of an image sensor.

[0143] Fig.12 Shown along Fig.11 A cross-sectional view taken along line II' in FIG.

[0144] Reference Fig.11 and Fig.12 , the substrate 101 may include a first side 101a and a second side 101b facing each other. The first side 101a may be a front side of the substrate 101, and the second side 101b may be a back side of the substrate 101. The substrate 101 may include a reference Figure 4 and Figure 5A Epitaxial layer described or referenced Figure 5B Described substrate Sbb.

[0145] Two directions substantially parallel to the first side 101a and substantially perpendicular to each other are respectively defined as a first direction (e.g., X direction) and a second direction (e.g., Y direction), and a direction substantially perpendicular to the first side 101a is defined as a third direction (e.g., Z direction).

[0146] The pixels PX and the dummy pixels DPX may be formed in the substrate 101. The pixels PX and the dummy pixels DPX may be arranged in a matrix. According to an exemplary embodiment, the pixels PX may be arranged in a central portion of the matrix, and the dummy pixels DPX may be arranged in an edge portion of the matrix. According to an exemplary embodiment, the first isolation film 130 may extend between the pixels PX and the dummy pixels DPX in a first direction and a second direction (e.g., an X direction and a Y direction), so that each of the pixels PX and the dummy pixels DPX is horizontally isolated from adjacent pixels PX and dummy pixels DPX. According to an exemplary embodiment, the second isolation film 135 may be arranged between the first isolation film 130 and each of the pixels PX and the dummy pixels DPX.

[0147] The first isolation film 130 may include a material having a high gap filling property, for example, polysilicon. According to an exemplary embodiment, the first isolation film 130 may be doped with a p-type dopant (for example, boron (B)), but is not limited thereto. According to some embodiments, the first isolation film 130 may have the same length as the substrate 101 in a third direction (for example, the Z direction), so that each of the pixels PX and the dummy pixels DPX is isolated from adjacent pixels PX and dummy pixels DPX.

[0148] The second isolation film 135 may include an insulating material. According to an exemplary embodiment, the second isolation film 135 may include a material having a high dielectric constant, but is not limited thereto.

[0149] The substrate 101 and the first isolation film 130 may be used as electrodes, and the second isolation film 135 may be used as a dielectric layer, thereby forming a capacitor. Therefore, the voltage difference between the substrate 101 and the first isolation film 130 may be kept substantially constant.

[0150] According to an exemplary embodiment, a specific potential may be applied to the substrate 101 through the first contact via 116. According to some examples, the potential of the substrate 101 may be a reference potential (ie, a ground voltage GND) (eg, see Figure 1 ), but are not limited to them.

[0151] According to an exemplary embodiment, the output voltage Vout may be applied to the first isolation film 130 through the second contact via 117. According to an exemplary embodiment, the second contact via 117 may be formed along an edge of the first isolation film 130. Fig.12 , the second contact via 117 is adjacent to the second side 101b, but the embodiment is not limited thereto. For example, the second contact via 117 may be adjacent to the first side 101a or adjacent to each of the first side 101a and the second side 101b.

[0152] According to some embodiments, the first isolation film 130 includes doped polysilicon and thus may have a substantially uniform potential. According to some embodiments, the voltage applied to the first isolation film 130 may be a voltage determined by a reference voltage. Figures 1 to 7 One of the charge pump arrangements 10, 10' and 15 is depicted to generate an output voltage Vout.

[0153] According to an exemplary embodiment, an energy barrier between the first isolation film 130 and the substrate 101 may be increased by applying a voltage lower than a voltage applied to the substrate 101 to the first isolation film 130, and thus dark current may be reduced. As a result, reliability of the image sensor may be improved.

[0154] According to an exemplary embodiment, a photoelectric conversion element PD and a dummy photoelectric conversion element DPD (e.g., a photodiode) may be formed in the substrate 101. A gate electrode 115 may be disposed on the first side 101a of the substrate 101 and spaced apart from the other side. The gate electrode 115 may be, for example, one of a gate of a charge transfer element, a gate of a reset element, and a gate of a drive element.

[0155] Despite Fig.12 The middle gate electrode 115 is disposed on the first side 101 a of the substrate 101 , but the embodiment is not limited thereto. For example, the gate electrode 115 may be buried in the substrate 101 .

[0156] An interlayer dielectric film 111 and a front wiring 113 may be formed on the first side 101a of the substrate 101. The front wiring 113 may be covered by the interlayer dielectric film 111. The front wiring 113 may be protected and insulated by the interlayer dielectric film 111.

[0157] The interlayer dielectric film 111 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The front wiring 113 may include, for example, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), and / or ruthenium (Ru).

[0158] The front wiring 113 may include a plurality of wiring layers sequentially stacked on top of each other. Fig.12 The front-middle wiring 113 includes three wiring layers sequentially stacked on one another, but the embodiment is not limited thereto.

[0159] The insulating film 105 may be disposed between the first side 101a and the interlayer dielectric film 111. The insulating film 105 may cover the gate electrode 115 on the first side 101a.

[0160] According to exemplary embodiments, the insulating film 105 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0161] The passivation film 120 may be disposed on the second side 101b of the substrate 101. According to an exemplary embodiment, the passivation film 120 may be in contact with the second side 101b of the substrate 101. According to an exemplary embodiment, the passivation film 120 may include an amorphous high-k dielectric material, but is not limited thereto.

[0162] The color filter 150 and the capping insulating layer 140 covering the color filter 150 may be formed on the passivation film 120. The capping insulating layer 140 may include, for example, an oxide film, a nitride film, a low-k dielectric material and / or a resin. According to an exemplary embodiment, the capping insulating layer 140 may include a multi-layer structure.

[0163] The color filter 150 may be disposed on the passivation film 120. The color filter 150 may be disposed on the second side 101b of the substrate 101. The color filter 150 may transmit light having a specific wavelength bandwidth so that adjacent pixels receive light having wavelengths different from each other.

[0164] The microlens 160 may be disposed on the color filter 150. The microlens 160 may include an organic material (eg, a photosensitive resin) or an inorganic material. The microlens 160 may focus incident light on the pixel PX.

[0165] Fig.13 A charge pump arrangement 1000 according to an exemplary embodiment of the present disclosure is shown.

[0166] Reference Fig.13 , the charge pump device 1000 may include a first stage 1001 and a second stage 1002 .

[0167] The first stage 1001 may include a first external well NW1 and a first internal well PW1 formed in the first external well NW1. Figure 1The first stage 11 described is essentially the same.

[0168] The second stage 1002 may include a second outer well NW2 and a second inner well PW2. The second stage 1002 is similar to Figure 1 In the following, reference will be made to Fig.14 and Fig.15 Describe the second level 1002 and Figure 1 The difference between the second level 12 in.

[0169] Fig.14 Shows Fig.13 A circuit of a charge pump device 1000 is provided. Fig.15 Shows Fig.13 1 is a cross-sectional view of a charge pump device 1000 .

[0170] Reference Fig.14 and Fig.15 , the first stage 1001 may include a first capacitor C1 and a first transistor T1, and the second stage 1002 may include a second capacitor C2, a second transistor T2, and a third transistor T3.

[0171] The first transistor T1 and the second transistor T2 and the first capacitor C1 and the second capacitor C2 are connected to the reference Figure 2A Those described are essentially the same.

[0172] The epitaxial layer Epi may be formed on the substrate Sb, and the first external well NW1 and the second external well NW2 may be formed in the epitaxial layer Epi. The first internal well PW1 may be formed in the first external well NW1, and the second internal well PW2 may be formed in the second external well NW2.

[0173] According to some embodiments, Figure 2A and Figure 2B Differently, the body of the third transistor T3 may be electrically connected to the second node n2. Therefore, the body of the third transistor T3 and the first electrode of the second transistor T2 may be short-circuited.

[0174] According to some embodiments, the p-type region P+ formed in the second outer well NW2 may be electrically connected to the p-type region P+ formed in the second inner well PW2. Therefore, the p-type region P+ formed in the second outer well NW2 and the p-type region P+ formed in the second inner well PW2 may be short-circuited, and there may be no potential difference between them, or if there is a potential difference between them, the potential difference may be very small.

[0175] FIG. 16A to FIG. 16C According to an optional example Fig.13 1 is a cross-sectional view of a charge pump device 1000 .

[0176] Will omit references Fig.14 and Fig.15 The following description will focus on the differences.

[0177] Reference Fig.16A , an epitaxial layer Epi may be formed on the substrate Sba. According to an exemplary embodiment, the substrate Sba may be doped with an n-type dopant. According to an exemplary embodiment, the epitaxial layer Epi may be doped with a p-type dopant.

[0178] Reference Fig. 16B , the epitaxial layer Epi may be omitted. Therefore, the first internal well PW1 and the second internal well PW2 may be formed in the substrate Sbb. According to an exemplary embodiment, the substrate Sbb may be doped with a high concentration of a p-type dopant.

[0179] Reference Fig. 16C , a fourth voltage V4 higher than the ground voltage GND may be applied to the second outer well NW2. According to an exemplary embodiment, a voltage difference between the second outer well NW2 and the second inner well PW2 may be different from a voltage difference between the first outer well NW1 and the first inner well PW1. According to an exemplary embodiment, a voltage difference between the second outer well NW2 and the second inner well PW2 may be greater than a voltage difference between the first outer well NW1 and the first inner well PW1.

[0180] Fig.17 A charge pump arrangement 1005 is shown according to an exemplary embodiment of the present disclosure.

[0181] Reference Fig.17 , the charge pump device 1005 may include a first stage 1006 and a second stage 1007 .

[0182] The first stage 1006 may include a first external well NW1 and a first internal well PW1 formed in the first external well NW1. Figure 6 The first stage 16 described is essentially the same.

[0183] The second stage 1007 may include a second outer well NW2 and a second inner well PW2. The second stage 1007 is similar to Figure 6 The second level in 17.

[0184] In the following, reference will be made to Fig.18 Describe the second level 1007 and Figure 6 The difference between the second level 17.

[0185] Fig.18 Shows Fig.17 A circuit of the charge pump device 1005.

[0186] The first stage 1006 may include a first transistor T1, a fourth transistor T4, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, a third capacitor C3, and a fifth capacitor C5. The second stage 1007 may include a second transistor T2, a third transistor T3, a fifth transistor T5, a sixth transistor T6, a ninth transistor T9, a tenth transistor T10, a second capacitor C2, a fourth capacitor C4, and a sixth capacitor C6.

[0187] The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7 to the tenth transistor T10, and the first capacitor C1 to the fourth capacitor C4 are connected to the reference Figure 7 Those described are essentially the same.

[0188] According to some embodiments, the body of the third transistor T3 may be connected to the second node n2, and the body of the sixth transistor T6 may be connected to the fourth node n4. According to some embodiments, the body of the third transistor T3 may be short-circuited to the first electrode of the second transistor T2, and the body of the third transistor T3 may be short-circuited to the first electrode of the ninth transistor T9. According to some embodiments, the body of the sixth transistor T6 may be short-circuited to the first electrode of the fifth transistor T5, and the body of the sixth transistor T6 may be short-circuited to the first electrode of the tenth transistor T10.

[0189] In an alternative embodiment, a charge pump device 1005 ′ may be employed in which the first and second outer wells have p-type conductivity and the first and second inner wells have n-type conductivity.

[0190] In another alternative embodiment, a charge pump device 1005" may be used in which the first outer well has p-type conductivity, the first inner well has n-type conductivity, the second outer well has n-type conductivity, and the second inner well has p-type conductivity.

[0191] In yet another alternative embodiment, the charge pump device 1005″ may be implemented in a semiconductor layer of the first conductivity type, a plurality of outer wells may be implemented in the second conductivity type, and a plurality of inner wells within each outer well may be implemented in the first conductivity type.

[0192] While the present inventive concept has been particularly shown and described by way of example with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made by persons skilled in the relevant art without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A charge pump device, the charge pump device being configured to generate an output voltage from a square wave input signal varying between a first voltage and a ground voltage, the charge pump device comprising: a semiconductor layer having a first conductivity type; a first external well and a second external well separated from each other in the semiconductor layer and each having a second conductivity type; a first inner well formed in the first outer well and having the first conductivity type; a second inner well formed in the second outer well and having the first conductivity type; a first capacitor having a first terminal to which the square wave input signal is applied and a second terminal connected to the first external well; as well as a second capacitor having a first terminal connected to the second terminal of the first capacitor and a second terminal connected to the second external well, wherein the first voltage is applied to the first external well, and A voltage lower than the first voltage is applied to the second external well.

2. The charge pump device according to claim 1, wherein: The ground voltage is applied to the second external well.

3. The charge pump device according to claim 1, wherein: The output voltage is lower than the ground voltage.

4. The charge pump device according to claim 1, wherein: The output voltage is twice the first voltage.

5. The charge pump device according to claim 1, wherein: A second voltage lower than the ground voltage is applied to the first internal well.

6. The charge pump device according to claim 5, wherein: The magnitude of the first voltage is the same as the magnitude of the second voltage.

7. The charge pump device according to claim 5, wherein: A third voltage lower than the second voltage is applied to the second internal well.

8. The charge pump device according to claim 7, wherein: The third voltage is equal to the output voltage.

9. A charge pump device, the charge pump device being configured to output a voltage lower than the ground voltage to an output terminal using an input signal alternately providing a ground voltage and a first voltage higher than the ground voltage, the charge pump device comprising: a first stage including a first capacitor and a first transistor, a first terminal of the first capacitor to which the input signal is applied, the first transistor including a first electrode, a second electrode, a gate electrode, and a body, wherein the body of the first transistor is formed by at least a portion of a first external well, wherein the first electrode of the first transistor is connected to the second terminal of the first capacitor, the second electrode of the first transistor is connected to the ground voltage, and the body of the first transistor is applied with the first voltage; and a second stage including a second capacitor and a second transistor, a first terminal of the second capacitor being connected to the second terminal of the first capacitor, the second transistor including a first electrode, a second electrode, a gate electrode and a body, wherein the body of the second transistor is formed by at least a portion of a second external well, wherein the first electrode of the second transistor is connected to the second terminal of the second capacitor, the second electrode of the second transistor is connected to a second voltage lower than the ground voltage, and the body of the second transistor is applied with the ground voltage, wherein the ground voltage and the second voltage are applied alternately to the gate electrode of the first transistor, and The second voltage and a third voltage lower than the second voltage are alternately applied to a gate electrode of the second transistor.

10. The charge pump device according to claim 9, wherein: The magnitude of the second voltage is equal to the magnitude of the first voltage.

11. The charge pump device according to claim 9, wherein: The third voltage is equal to twice the second voltage.

12. The charge pump device according to claim 9, wherein: The second stage also includes a third transistor connected between the second terminal of the second capacitor and the output terminal, and The second voltage and the third voltage are alternately applied to the gate electrode of the third transistor.

13. The charge pump device according to claim 12, wherein: The negative second voltage is applied to a body of the third transistor, wherein the body of the third transistor is formed by at least a portion of an internal well.

14. A charge pump device, the charge pump device being configured to generate an output voltage using an input signal alternately providing a high voltage and a low voltage, the charge pump device comprising: a first stage including a first capacitor and a first transistor, a first terminal of the first capacitor being applied with the input signal, wherein a first electrode of the first transistor is connected to a second terminal of the first capacitor, a second electrode of the first transistor is connected to the low voltage, a body of the first transistor being applied with the high voltage, wherein the body of the first transistor is formed by at least a portion of a first external well; and A second stage comprising a second capacitor and a second transistor, a first terminal of the second capacitor being connected to the second terminal of the first capacitor, wherein a first electrode of the second transistor is connected to the second terminal of the second capacitor, a second electrode of the second transistor is connected to a second voltage lower than the low voltage, a body of the second transistor being applied with the low voltage, wherein the body of the second transistor is formed by at least a portion of a second external well.

15. The charge pump device according to claim 14, wherein: The second stage further includes a third transistor including a first electrode and a second electrode, the first electrode of the third transistor being connected to the second terminal of the second capacitor, and the second electrode of the third transistor being applied with a third voltage lower than the second voltage.

16. The charge pump device according to claim 15, wherein: The third transistor further includes a body to which a third voltage lower than the second voltage is applied, wherein the body of the third transistor is formed by at least a portion of the internal well.

17. The charge pump device according to claim 15, wherein: The charge pump device also generates the output voltage using a complementary input signal that alternately provides the high voltage and the low voltage and has an opposite phase to the input signal; The first stage further includes a third capacitor and a fourth transistor, a first terminal of the third capacitor being applied with the complementary input signal, a first electrode of the fourth transistor being connected to a second terminal of the third capacitor, and a second electrode of the fourth transistor being connected to the low voltage; and The second stage also includes a fourth capacitor, a fifth transistor and a sixth transistor, the first terminal of the fourth capacitor being applied with the complementary input signal, the first electrodes of the fifth transistor and the sixth transistor being respectively connected to the second terminal of the fourth capacitor, the second electrode of the fifth transistor being connected to a second voltage lower than the low voltage, and the second electrode of the sixth transistor being connected to an output terminal generating the output voltage and being applied with a third voltage lower than the second voltage.

18. The charge pump device according to claim 17, wherein: The fourth transistor includes a body to which the high voltage is applied; The fifth transistor includes a body to which the low voltage is applied; and the sixth transistor includes a body to which a third voltage lower than the second voltage is applied, Wherein a body of each of the fourth transistor, the fifth transistor and the sixth transistor is formed by at least a portion of a corresponding well.

19. An image sensor, comprising: a plurality of pixels formed in a semiconductor layer having a first conductivity type and arranged in a matrix; an isolation film disposed at the same level as the semiconductor layer and configured to isolate the plurality of pixels from each other; a timing generator configured to generate an input signal providing a first voltage and a ground voltage, wherein the first voltage is higher than the ground voltage; and a charge pump device configured to provide an output voltage to the isolation membrane using the input signal, Wherein, the charge pump device comprises: a first external well and a second external well, both formed in the semiconductor layer and both having a second conductivity type; a first inner well formed in the first outer well and having the first conductivity type; a second inner well formed in the second outer well and having the first conductivity type; a first capacitor having a first terminal to which the input signal is applied and a second terminal of which is connected to the first external well, and a second capacitor having a first terminal connected to the second terminal of the first capacitor and a second terminal connected to the second external well, wherein a second voltage lower than the ground voltage is applied to the first internal well, A third voltage lower than the second voltage is applied to the second internal well; and The output voltage is equal to the third voltage.

20. The image sensor according to claim 19, wherein: A voltage applied to the second external well is lower than a voltage applied to the first external well.

21. The image sensor according to claim 19, wherein: The ground voltage is applied to the second external well.

22. The image sensor according to claim 19, wherein: The first voltage is applied to the first external well.

23. A semiconductor device, comprising: a semiconductor layer having a first conductivity type; an isolation film arranged at the same level as the semiconductor layer; a timing generator configured to generate an input signal having a first voltage and a ground voltage, wherein the first voltage is higher than the ground voltage; and a charge pump configured to provide an output voltage to the isolation film based on the input signal, the charge pump comprising: a first external well and a second external well both formed in the semiconductor layer and both having a second conductivity type, a first internal well formed in the first external well and having the first conductivity type, a second internal well formed in the second external well and having the first conductivity type, a first capacitor, and a second capacitor, wherein a first terminal of the first capacitor is applied with the input signal and a second terminal thereof is connected to the first external well, wherein a first terminal of the second capacitor is connected to a second terminal of the first capacitor and a second terminal of the second capacitor is connected to the second external well, wherein a second voltage lower than the ground voltage is applied to the first internal well, wherein a third voltage lower than the second voltage is applied to the second internal well, and Wherein, the output voltage is equal to the third voltage.

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