A Phase-Locked Loop Circuit for Wideband Frequency Synthesizer

Abstract

The present invention discloses a phase-locked loop circuit for a broadband frequency synthesizer, comprising a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator VCO and a frequency divider; the source signal input terminal Ref of the frequency detector receives an external signal U ref The first signal output terminal Up and the second signal output terminal Dn of the frequency detector and phase detector are both connected to the charge pump, the output terminal of the charge pump is connected to the loop filter, the output terminal of the loop filter is connected to the voltage controlled oscillator VCO, and the voltage controlled oscillator VCO outputs a signal to the outside. At the same time, the signal output by the voltage controlled oscillator VCO is processed by the frequency divider to obtain a feedback signal U div , transmitted to the feedback input terminal Div of the frequency detector and phase detector. The present invention effectively avoids the occurrence of phase detection dead zone for the frequency detector and phase detector in the phase-locked loop circuit, thereby ensuring the normal operation of the phase-locked loop.

Description

Technical Field

[0001] The invention relates to a phase-locked loop, in particular to a phase-locked loop circuit used for a broadband frequency synthesizer. Background Art

[0002] Phase-locked loop circuits are widely used in frequency synthesizers. The Phase Frequency Detector (PFD) is a key component of the phase-locked loop. Its main function is to detect the phase difference and frequency difference between the input signal and the voltage-controlled oscillator feedback signal, and amplify them. The performance of the PFD determines the accuracy and stability of the phase-locked loop.

[0003] In the design of modern phase detectors, especially in large-scale communications and digital integrated circuits, people are more focused on designing CMOS digital phase detectors with high speed, low power consumption, low noise, no dead zone and wide linear phase range. When there is a small phase error between the reference signal and the feedback signal, the width of the PFD output pulse is too narrow to open the input switch tube of the subsequent charge pump, resulting in a phase dead zone, which affects the normal operation of the phase-locked loop. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a phase-locked loop circuit for a broadband frequency synthesizer, which effectively avoids the occurrence of a phase-locked loop dead zone for a phase-frequency detector in the phase-locked loop circuit, thereby ensuring the normal operation of the phase-locked loop.

[0005] The object of the present invention is achieved through the following technical solutions: A phase-locked loop circuit for a broadband frequency synthesizer, comprising a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator VCO and a frequency divider;

[0006] The frequency and phase detector comprises a source signal input terminal Ref, a feedback input terminal Div, a first signal output terminal Up, a second signal output terminal Dn, a delay component, and a first NAND gate K1 to a ninth NAND gate K9;

[0007] The source signal input terminal Ref of the frequency and phase detector receives an external signal U ref The first signal output terminal Up and the second signal output terminal Dn of the frequency detector and phase detector are both connected to the charge pump, the output terminal of the charge pump is connected to the loop filter, the output terminal of the loop filter is connected to the voltage controlled oscillator VCO, and the voltage controlled oscillator VCO outputs a signal to the outside. At the same time, the signal output by the voltage controlled oscillator VCO is processed by the frequency divider to obtain a feedback signal U div , transmitted to the feedback input terminal Div of the frequency and phase detector;

[0008] In the phase frequency detector:

[0009] A first input terminal of the first NAND gate K1 is connected to the source signal input terminal Ref, a second input terminal of the first NAND gate K1 is connected to the output terminal of the second NAND gate K2, and an output terminal of the first NAND gate K1 is respectively connected to a first input terminal of the second NAND gate K2, a first input terminal of the third NAND gate K3, and a first input terminal of the ninth NAND gate K9;

[0010] The second input terminal of the second NAND gate K2 is connected to the output terminal of the third NAND gate K3, the third input terminal of the second NAND gate K2 is connected to the output terminal of the delay component, and the output terminal of the second NAND gate K2 is also connected to the first signal output terminal Up;

[0011] The second input terminal of the third NAND gate K3 is connected to the output terminal of the fourth NAND gate K4, and the output terminal of the third NAND gate K3 is also connected to the first input terminal of the fourth NAND gate K4 and the second input terminal of the ninth NAND gate K9 respectively; the second input terminal of the fourth NAND gate K4 is connected to the output terminal of the delay component;

[0012] A first input terminal of the fifth NAND gate K5 is connected to the output terminal of the delay component, a second input terminal of the fifth NAND gate K5 is connected to the output terminal of the sixth NAND gate K6, and the output terminal of the fifth NAND gate K5 is connected to the first input terminal of the sixth NAND gate K6; a second input terminal of the sixth NAND gate K6 is connected to the output terminal of the eighth NAND gate K8, and the output terminal of the sixth NAND gate K6 is also connected to the third input terminal of the ninth NAND gate K9 and the second input terminal of the seventh NAND gate K7 respectively;

[0013] The first input terminal of the seventh NAND gate K7 is connected to the output terminal of the delay component, the third input terminal of the seventh NAND gate K7 is connected to the output terminal of the eighth NAND gate K8, and the output terminal of the seventh NAND gate K7 is respectively connected to the first input terminal and the second signal output terminal Dn of the eighth NAND gate K8; the second input terminal of the eighth NAND gate K8 is connected to the feedback input terminal Div, and the output terminal of the eighth NAND gate K8 is also connected to the fourth input terminal of the ninth NAND gate K9; the output terminal of the ninth NAND gate K9 is connected to the input terminal of the delay component.

[0014] Preferably, the delay component comprises a plurality of inverters connected in series, wherein the input end of the first inverter serves as the input end of the entire delay component, and the output end of the last inverter serves as the output end of the entire delay component. The number of the inverters is an even number, and the output end of each inverter is connected to a grounding capacitor.

[0015] Further, the voltage-controlled oscillator VCO includes a differential port, a power port, a differential-to-single-ended module and three differential oscillation units connected in parallel, the differential port includes a first port and a second port, and the power port includes a first power supply terminal and a second power supply terminal;

[0016] Each differential oscillation unit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a fourth MOS tube M4;

[0017] The drain of the first MOS tube M1 is connected to the first power supply terminal through the first inductor L1, and the source of the first MOS tube M1 is connected to the drain of the third MOS tube M3; a first capacitor C1 is connected between the source and drain of the first MOS tube M1; the drain of the second MOS tube M2 is connected to the first power supply terminal through the second inductor L2, and the source of the second MOS tube M2 is connected to the drain of the fourth MOS tube M4; a second capacitor C2 is connected between the source and drain of the second MOS tube M2;

[0018] The gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2, and a third capacitor C3 is further provided between the first MOS transistor M1 and the second MOS transistor, one end of the third capacitor C3 is connected to the drain of the first MOS transistor M1, and the other end of the third capacitor C3 is connected to the drain of the second MOS transistor M2 through a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6 in sequence; a common end of the fourth capacitor C4 and the fifth capacitor C5 is connected to the second power supply end through a first resistor R1;

[0019] The source of the third MOS tube M3 is connected to the source of the fourth MOS tube M4, and the common end of the sources of the third MOS tube M3 and the fourth MOS tube M4 is also connected to a grounded current source;

[0020] The gate of the third MOS tube M3 is connected to the drain of the fourth MOS tube M4 through the seventh capacitor C7; the gate of the fourth MOS tube M4 is connected to the drain of the third MOS tube through the eighth capacitor C8; the gate of the third MOS tube M3 is also connected to the gate of the fourth MOS tube M4 through the second resistor R2 and the third resistor R3 in sequence;

[0021] In each differential oscillation unit, a common end of the first inductor L1 and the drain of the first MOS tube M1 is connected to a first port of the differential port, and a common end of the second inductor L2 and the drain of the second MOS tube M2 is connected to a second port of the differential port; the first port and the second port of the differential port are both connected to a differential-to-single-ended module; the differential-to-single-ended module outputs a signal to the outside, and transmits the output signal to a frequency divider.

[0022] The first power supply terminal is connected to a fixed voltage of 4V, and the second power supply input terminal is connected to the output terminal of the loop filter. A first bias voltage input terminal is also provided at the common terminal of the gate of the first MOS tube M1 and the gate of the second MOS tube M2; and a second bias voltage input terminal is also provided between the second resistor R2 and the third resistor R3.

[0023] The beneficial effects of the present invention are as follows: the present invention designs a frequency detector and phase detector in a phase-locked loop circuit, effectively avoiding the occurrence of a phase-detection dead zone, thereby ensuring the normal operation of the phase-locked loop; at the same time, the voltage-controlled oscillator VCO is based on a stacked differential Colpitts oscillator structure, which can achieve a large output swing, and is helpful to suppress common-mode noise based on a differential method. A differential-to-single-ended module is added at the output, so that a single-ended signal can be output, thereby adapting to the operation of the phase-locked loop circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a principle block diagram of the present invention;

[0025] Figure 2 This is the principle diagram of the frequency and phase detector;

[0026] Figure 3 It is the principle block diagram of voltage controlled oscillator VCO;

[0027] Figure 4 Schematic diagram of the principle of the differential oscillation unit. DETAILED DESCRIPTION

[0028] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0029] like Figure 1~2 As shown, a phase-locked loop circuit for a broadband frequency synthesizer includes a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator VCO and a frequency divider;

[0030] The frequency and phase detector comprises a source signal input terminal Ref, a feedback input terminal Div, a first signal output terminal Up, a second signal output terminal Dn, a delay component, and a first NAND gate K1 to a ninth NAND gate K9;

[0031] The source signal input terminal Ref of the frequency and phase detector receives an external signal U ref The first signal output terminal Up and the second signal output terminal Dn of the frequency detector and phase detector are both connected to the charge pump, the output terminal of the charge pump is connected to the loop filter, the output terminal of the loop filter is connected to the voltage controlled oscillator VCO, and the voltage controlled oscillator VCO outputs a signal to the outside. At the same time, the signal output by the voltage controlled oscillator VCO is processed by the frequency divider to obtain a feedback signal U div , transmitted to the feedback input terminal Div of the frequency and phase detector;

[0032] In the phase frequency detector:

[0033] A first input terminal of the first NAND gate K1 is connected to the source signal input terminal Ref, a second input terminal of the first NAND gate K1 is connected to the output terminal of the second NAND gate K2, and an output terminal of the first NAND gate K1 is respectively connected to a first input terminal of the second NAND gate K2, a first input terminal of the third NAND gate K3, and a first input terminal of the ninth NAND gate K9;

[0034] The second input terminal of the second NAND gate K2 is connected to the output terminal of the third NAND gate K3, the third input terminal of the second NAND gate K2 is connected to the output terminal of the delay component, and the output terminal of the second NAND gate K2 is also connected to the first signal output terminal Up;

[0035] The second input terminal of the third NAND gate K3 is connected to the output terminal of the fourth NAND gate K4, and the output terminal of the third NAND gate K3 is also connected to the first input terminal of the fourth NAND gate K4 and the second input terminal of the ninth NAND gate K9 respectively; the second input terminal of the fourth NAND gate K4 is connected to the output terminal of the delay component;

[0036] A first input terminal of the fifth NAND gate K5 is connected to the output terminal of the delay component, a second input terminal of the fifth NAND gate K5 is connected to the output terminal of the sixth NAND gate K6, and the output terminal of the fifth NAND gate K5 is connected to the first input terminal of the sixth NAND gate K6; a second input terminal of the sixth NAND gate K6 is connected to the output terminal of the eighth NAND gate K8, and the output terminal of the sixth NAND gate K6 is also connected to the third input terminal of the ninth NAND gate K9 and the second input terminal of the seventh NAND gate K7 respectively;

[0037] The first input terminal of the seventh NAND gate K7 is connected to the output terminal of the delay component, the third input terminal of the seventh NAND gate K7 is connected to the output terminal of the eighth NAND gate K8, and the output terminal of the seventh NAND gate K7 is respectively connected to the first input terminal and the second signal output terminal Dn of the eighth NAND gate K8; the second input terminal of the eighth NAND gate K8 is connected to the feedback input terminal Div, and the output terminal of the eighth NAND gate K8 is also connected to the fourth input terminal of the ninth NAND gate K9; the output terminal of the ninth NAND gate K9 is connected to the input terminal of the delay component.

[0038] The delay component includes a plurality of inverters connected in series, wherein the input end of the first inverter serves as the input end of the entire delay component, and the output end of the last inverter serves as the output end of the entire delay component. The number of the inverters is an even number, and the output end of each inverter is connected to a grounding capacitor.

[0039] In the present application, the two outputs Up and Dn are used to control the charging and discharging of the loop capacitor by the charge pump (CP). When the Up signal is at a high level, the CP starts to charge the loop capacitor, causing the voltage at the voltage control terminal of the VCO to increase, and the VCO frequency increases accordingly. Similarly, when the Dn signal is at a high level, the VCO frequency is tuned downward. When both Up and Dn are at a low level, the CP output is in a high-impedance state. It can be seen that when the phase difference is within ±2π, the PFD works as a phase detector; and when the phase difference is greater than ±2π, the PFD works as a frequency detector. At the same time, the present application adds some inverters as delay components at the reset end to avoid the adverse effects of the phase detection dead zone on the frequency detection phase detector. The present invention is aimed at the frequency detection phase detector in the phase-locked loop circuit, and effectively avoids the occurrence of the phase detection dead zone, thereby ensuring the normal operation of the phase-locked loop.

[0040] like Figure 3 As shown, the voltage-controlled oscillator VCO includes a differential port, a power port, a differential-to-single-ended module and three differential oscillation units connected in parallel, the differential port includes a first port and a second port, and the power port includes a first power supply terminal and a second power supply terminal;

[0041] like Figure 4 As shown, each differential oscillation unit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a fourth MOS tube M4;

[0042] The drain of the first MOS tube M1 is connected to the first power supply terminal through the first inductor L1, and the source of the first MOS tube M1 is connected to the drain of the third MOS tube M3; a first capacitor C1 is connected between the source and drain of the first MOS tube M1; the drain of the second MOS tube M2 is connected to the first power supply terminal through the second inductor L2, and the source of the second MOS tube M2 is connected to the drain of the fourth MOS tube M4; a second capacitor C2 is connected between the source and drain of the second MOS tube M2;

[0043] The gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2, and a third capacitor C3 is further provided between the first MOS transistor M1 and the second MOS transistor, one end of the third capacitor C3 is connected to the drain of the first MOS transistor M1, and the other end of the third capacitor C3 is connected to the drain of the second MOS transistor M2 through a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6 in sequence; a common end of the fourth capacitor C4 and the fifth capacitor C5 is connected to the second power supply end through a first resistor R1;

[0044] The source of the third MOS tube M3 is connected to the source of the fourth MOS tube M4, and the common end of the sources of the third MOS tube M3 and the fourth MOS tube M4 is also connected to a grounded current source;

[0045] The gate of the third MOS tube M3 is connected to the drain of the fourth MOS tube M4 through the seventh capacitor C7; the gate of the fourth MOS tube M4 is connected to the drain of the third MOS tube through the eighth capacitor C8; the gate of the third MOS tube M3 is also connected to the gate of the fourth MOS tube M4 through the second resistor R2 and the third resistor R3 in sequence;

[0046] In each differential oscillation unit, a common end of the first inductor L1 and the drain of the first MOS tube M1 is connected to a first port of the differential port, and a common end of the second inductor L2 and the drain of the second MOS tube M2 is connected to a second port of the differential port; the first port and the second port of the differential port are both connected to a differential-to-single-ended module; the differential-to-single-ended module outputs a signal to the outside, and transmits the output signal to a frequency divider.

[0047] In an embodiment of the present application, the fourth capacitor C4 and the fifth capacitor C5 are variable capacitors, and the output frequency of the oscillator is adjusted by changing the size of C4 and C5. The first power supply terminal is connected to a fixed voltage of 4V, and the second power supply input terminal is connected to the output terminal of the loop filter. The common end of the gate of the first MOS tube M1 and the gate of the second MOS tube M2 is also provided with a first bias voltage input terminal, which is used to provide a bias voltage for the first MOS tube M1 and the second MOS tube M2. Generally, the voltage of the first bias voltage input terminal is 1.5~2V; a second bias voltage input terminal is also provided between the second resistor R2 and the third resistor R3, which is used to provide a bias voltage for the third MOS tube M3 and the fourth MOS tube M4. Generally, the voltage of the second bias voltage input terminal is also 1.5~2V.

[0048] In the entire voltage-controlled oscillator, a stacked Colpitts oscillator structure is used to achieve a large output swing, and the entire oscillator is designed based on a differential method, which helps to suppress common-mode noise. A differential-to-single-ended module is added at the output to output a single-ended signal, which is suitable for the operation of the phase-locked loop circuit.

[0049] Finally, it should be explained that the above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A phase-locked loop circuit for a broadband frequency synthesizer, characterized in that: Including frequency detector, charge pump, loop filter, voltage controlled oscillator VCO and frequency divider; The frequency and phase detector comprises a source signal input terminal Ref, a feedback input terminal Div, a first signal output terminal Up, a second signal output terminal Dn, a delay component, and a first NAND gate K1 to a ninth NAND gate K9; The source signal input terminal Ref of the frequency and phase detector receives an external signal U ref The first signal output terminal Up and the second signal output terminal Dn of the frequency detector and phase detector are both connected to the charge pump, the output terminal of the charge pump is connected to the loop filter, the output terminal of the loop filter is connected to the voltage controlled oscillator VCO, and the voltage controlled oscillator VCO outputs a signal to the outside. At the same time, the signal output by the voltage controlled oscillator VCO is processed by the frequency divider to obtain a feedback signal U div , transmitted to the feedback input terminal Div of the frequency and phase detector; In the phase frequency detector: A first input terminal of the first NAND gate K1 is connected to the source signal input terminal Ref, a second input terminal of the first NAND gate K1 is connected to the output terminal of the second NAND gate K2, and an output terminal of the first NAND gate K1 is respectively connected to a first input terminal of the second NAND gate K2, a first input terminal of the third NAND gate K3, and a first input terminal of the ninth NAND gate K9; The second input terminal of the second NAND gate K2 is connected to the output terminal of the third NAND gate K3, the third input terminal of the second NAND gate K2 is connected to the output terminal of the delay component, and the output terminal of the second NAND gate K2 is also connected to the first signal output terminal Up; The second input terminal of the third NAND gate K3 is connected to the output terminal of the fourth NAND gate K4, and the output terminal of the third NAND gate K3 is also connected to the first input terminal of the fourth NAND gate K4 and the second input terminal of the ninth NAND gate K9 respectively; the second input terminal of the fourth NAND gate K4 is connected to the output terminal of the delay component; A first input terminal of the fifth NAND gate K5 is connected to the output terminal of the delay component, a second input terminal of the fifth NAND gate K5 is connected to the output terminal of the sixth NAND gate K6, and the output terminal of the fifth NAND gate K5 is connected to the first input terminal of the sixth NAND gate K6; a second input terminal of the sixth NAND gate K6 is connected to the output terminal of the eighth NAND gate K8, and the output terminal of the sixth NAND gate K6 is also connected to the third input terminal of the ninth NAND gate K9 and the second input terminal of the seventh NAND gate K7 respectively; The first input end of the seventh NAND gate K7 is connected to the output end of the delay component, the third input end of the seventh NAND gate K7 is connected to the output end of the eighth NAND gate K8, and the output end of the seventh NAND gate K7 is respectively connected to the first input end and the second signal output end Dn of the eighth NAND gate K8; the second input end of the eighth NAND gate K8 is connected to the feedback input end Div, and the output end of the eighth NAND gate K8 is also connected to the fourth input end of the ninth NAND gate K9; the output end of the ninth NAND gate K9 is connected to the input end of the delay component; by adding an inverter as a delay component, the adverse effect of the phase dead zone on the frequency detector is avoided; The voltage-controlled oscillator VCO comprises a differential port, a power port, a differential-to-single-ended module and three differential oscillation units connected in parallel, the differential port comprises a first port and a second port, and the power port comprises a first power supply terminal and a second power supply terminal; Each differential oscillation unit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a fourth MOS tube M4; The drain of the first MOS tube M1 is connected to the first power supply terminal through the first inductor L1, and the source of the first MOS tube M1 is connected to the drain of the third MOS tube M3; a first capacitor C1 is connected between the source and drain of the first MOS tube M1; the drain of the second MOS tube M2 is connected to the first power supply terminal through the second inductor L2, and the source of the second MOS tube M2 is connected to the drain of the fourth MOS tube M4; a second capacitor C2 is connected between the source and drain of the second MOS tube M2; The gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2, and a third capacitor C3 is further provided between the first MOS transistor M1 and the second MOS transistor, one end of the third capacitor C3 is connected to the drain of the first MOS transistor M1, and the other end of the third capacitor C3 is connected to the drain of the second MOS transistor M2 through a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6 in sequence; a common end of the fourth capacitor C4 and the fifth capacitor C5 is connected to the second power supply end through a first resistor R1; The source of the third MOS tube M3 is connected to the source of the fourth MOS tube M4, and the common end of the sources of the third MOS tube M3 and the fourth MOS tube M4 is also connected to a grounded current source; The gate of the third MOS tube M3 is connected to the drain of the fourth MOS tube M4 through the seventh capacitor C7; the gate of the fourth MOS tube M4 is connected to the drain of the third MOS tube through the eighth capacitor C8; the gate of the third MOS tube M3 is also connected to the gate of the fourth MOS tube M4 through the second resistor R2 and the third resistor R3 in sequence; In each differential oscillation unit, a common end of the first inductor L1 and the drain of the first MOS tube M1 is connected to a first port of the differential port, and a common end of the second inductor L2 and the drain of the second MOS tube M2 is connected to a second port of the differential port; the first port and the second port of the differential port are both connected to a differential-to-single-ended module; the differential-to-single-ended module outputs a signal to the outside, and transmits the output signal to a frequency divider.

2. A phase-locked loop circuit for a broadband frequency synthesizer according to claim 1, characterized in that: The delay component includes a plurality of inverters connected in series in sequence, wherein the input end of the first inverter serves as the input end of the entire delay component, and the output end of the last inverter serves as the output end of the entire delay component.

3. A phase-locked loop circuit for a broadband frequency synthesizer according to claim 1, characterized in that: The number of the inverters is an even number, and the output end of each inverter is connected to a grounding capacitor.

4. The phase-locked loop circuit for a broadband frequency synthesizer according to claim 1, characterized in that: The first power supply terminal is connected to a fixed voltage of 4V, and the second power supply input terminal is connected to the output terminal of the loop filter.

5. A phase-locked loop circuit for a broadband frequency synthesizer according to claim 4, characterized in that: A first bias voltage input terminal is also provided at the common end of the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2; and a second bias voltage input terminal is also provided between the second resistor R2 and the third resistor R3.

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