A SOC chip automated QC method and device

Abstract

The present invention provides a method and device for automatic QC of SOC chips, wherein the device includes a QC motherboard, the QC motherboard includes a PMU power supply, an MCU main controller, a SOCKET socket, a QC sub-board, a combination switch, a TEST button, a DEBUG button, a functional module, and a result display module; the method is implemented on the device, and includes the following contents: the MCU main controller is connected to the SOC chip to be tested through the SWD bus, and then the CHIPID pre-burned in the SOC chip is read; according to the CHIPID, the MCU main controller loads the required QC code into the SOC chip to be tested according to the set priority order and controls it to perform functional testing; if the test passes, the result display module displays PASS information, and if the test fails, the result display module displays FAIL information; when FAIL occurs, the MCU main controller can also debug the SOC chip to be tested to quickly locate the fault position. The present invention proposes a method and device for automatic QC of SOC chips, which can realize fast automatic testing of SOC chips, effectively shorten the test time, and improve the test efficiency.

Description

Technical Field

[0001] The present invention relates to the field of SOC chip testing, and in particular to an automatic QC method and device for a SOC chip. Background Art

[0002] Before shipment, SOC chips usually need to be functionally tested according to the application scenario, and can only be delivered to customers after ensuring that there are no functional problems. To 100% guarantee that the chips provided to customers have no quality problems, all circuit functions must be covered as much as possible during testing. However, there are many functional modules inside the SOC chip, and the differences in various circuit functions will inevitably lead to different test methods and test conditions. If a large number of SOCs are QCed (Quality Control) and conditional environmental tests are established one by one according to the characteristics of each functional circuit, not only will the QC efficiency be low, but it will also be easy to make human errors. Summary of the invention

[0003] To solve the above problems, the present invention provides a SOC chip automatic QC method and device, which can complete the functional test of the SOC chip with just one start test button, greatly improving the chip test efficiency. The specific technical solutions of the present invention are as follows:

[0004] A SOC chip automatic QC device comprises a QC motherboard, wherein the QC motherboard comprises a PMU power supply, an MCU main controller, a SOCKET socket, a QC sub-board, a combination switch, a TEST button, a DEBUG button, a function module, and a result display module, wherein the PMU power supply is connected with the MCU main controller and a current test unit and is used for powering the entire QC motherboard; the MCU main controller is connected with the PMU power supply, the combination switch, the current test unit and the QC sub-board and is used for controlling the entire QC process; the SOCKET socket is connected with the QC sub-board and the SOC chip to be tested and is used for installing The SOC chip to be tested; the QC sub-board, connected to the MCU main controller, the SOCKET socket and the functional module, for installing the SOCKET socket; the combination switch, connected to the MCU main controller, for manually inputting the type of the SOC chip to be tested; the TEST button, connected to the MCU main controller, for starting the TEST mode; the DEBUG button, connected to the MCU main controller, for starting the DEBUG mode; the functional module, connected to the QC sub-board, for testing the various functions of the SOC chip to be tested; the result display module, connected to the MCU main controller, for displaying the test results. The SOC chip automatic QC device described in the present invention relies on the MCU main controller, and can perform automatic testing of the SOC chip without connecting to the PC and other traditional instruments, and has high portability; the MCU main controller can arbitrarily call the pre-stored QC code according to the CHIPID of the SOC chip, without spending time writing the required code before the test, which effectively shortens the test time and improves the work efficiency of the tester.

[0005] Furthermore, the SOCKET socket is mounted on the QC daughter board, the QC daughter board is mounted on the QC mother board, and both the SOCKET socket and the QC daughter board are detachable. By replacing different SOCKET sockets and QC daughter boards to be compatible with different types of SOC chips, it is avoided to develop QC devices for different types of chips separately, thereby improving the utilization rate of the QC device.

[0006] Furthermore, the combination switch is an 8-bit dip switch, which is connected to the 8 IO ports of the MCU main controller. The high and low levels are set by the dip switch, and the encoding is composed of 8 bits of data to represent the pre-defined SOC chip. It allows the user to manually set the CHIPID of the SOC chip to deal with the situation where the MCU main controller cannot read the CHIPID, which is more flexible.

[0007] Furthermore, the functional modules include: a current test unit for testing the power supply open-circuit and short-circuit test of the SOC chip to be tested; a USART docking self-test module for testing the serial communication interface of the SOC chip to be tested; a GPIO docking self-test module for testing the general input / output interface of the SOC chip to be tested; a GPTM docking self-test module for testing the general timer module of the SOC chip to be tested; an MCTM docking self-test module for testing the PWM wave output function of the control motor of the SOC chip to be tested; a PID docking self-test module for testing the PID motion control function of the SOC chip to be tested; PWM wave output function of the system; DAC test module, used to test the ADC analog-to-digital conversion function of the SOC chip to be tested; ADC test module, used to test the DAC analog-to-digital conversion function of the SOC chip to be tested; external NORFLASH device, used to test the SPI controller module of the SOC chip to be tested; external EEPROM device, used to test the I2C communication module of the SOC chip to be tested; external DDR2 / 3 memory chip, used to test the DDR controller circuit function of the SOC chip to be tested; external TF card, used to test the SDIO module circuit function of the SOC chip to be tested. According to the CHIPID of the SOC chip to be tested, the function module can be freely selected to be connected or not to meet the test requirements of different types of SOC chips.

[0008] A SOC chip automatic QC method, characterized in that the automatic QC method is implemented in a SOC chip automatic QC device, which comprises the following steps: step S1, after receiving TEST key information, the MCU main controller establishes a connection with the SOC chip to be tested, if the connection is successful, reads the CHIPID pre-burned into the SOC chip to be tested, and enters step S2; if the connection fails, the result display module issues an alarm; step S2, the MCU main controller loads the required QC code into the SOC chip to be tested according to the CHIPID of the SOC chip to be tested and in a set priority order; step S3, the MCU main controller controls the SOC chip to be tested The C chip executes the loaded QC code to perform functional testing according to the set priority order. If all tests pass, the result display module displays PASS information; if a test fails, the result display module displays FAIL information and enters step S4; step S4, when receiving FAIL information, if the MCU main controller receives DEBUG key information, it enters DEBUG mode; in DEBUG mode, each time the MCU main controller receives DEBUG key information, the result display module will be initialized first, and then a module test code will be run, and the result display module will display the test result of the current module until the DEBUG mode is exited. A SOC chip automatic QC method described in the present invention encapsulates the QC code of each module in the MCU main controller. According to the CHIPID of the SOC chip to be tested, the required QC code can be called at will without spending time to write before the test. This can quickly perform automatic testing of the SOC chip, effectively shorten the test time, and improve the test efficiency.

[0009] Furthermore, the method for establishing a connection between the MCU main controller and the SOC chip to be tested is that the MCU main controller establishes a connection with the SWD bus of the SOC chip to be tested through the GPIO port. The QC code can be automatically downloaded to the SOC chip to be tested through the SWD bus, no longer relying on the download environment of the PC-side IDE program, which is more convenient and quick.

[0010] Furthermore, the method for loading the QC code is that the MCU main controller automatically loads the QC code into the flash or sram storage of the SOC chip to be tested according to the set priority order through the SWD bus.

[0011] Further, the priority order is set as power on / off test> bootloader test> clock frequency test> flash / sram storage test> DDR2 / DDR3 control module test> ADC analog-to-digital conversion module test> MCTM control module test> GPTM general timer test> PID control module test> SPI control module test> UART serial communication test> I2C communication module test> general input / output interface test> SDIO module circuit test> DAC module circuit test> encryption / decryption module test> redundancy detection module test. The priority of the modules in the front is higher than that of the modules in the back. The test priority of the modules is set according to the size of the SOC chip area occupied by the modules and whether they are prone to failure. In the event of a fault, reasonable treatment measures can be taken and the fault position can be quickly located.

[0012] Furthermore, the MCU main controller obtains the test result obtained after the SOC chip to be tested runs the QC code to perform a functional test through the SWD bus, and the test result is stored in a preset address of the SRAM memory of the SOC chip. Compared with the interaction by reading the GPIO port level, the interaction between the MCU main controller and the SOC chip through the SRAM memory is more reliable. The former is prone to burr interference and thus causes misjudgment.

[0013] Furthermore, when the MCU main controller is in DEBUG mode in step S4, after the current QC code is executed, if TEST key information is received, the result display module is initialized, the current module QC code is executed again, and the test result is displayed again. This method allows the same functional module to be debugged repeatedly, avoids misjudgment, and improves the test accuracy.

[0014] Furthermore, the method for exiting the DEBUG mode is that all modules are debugged or the DEBUG button is pressed twice within 500ms.

[0015] Furthermore, the SOC chip automatic QC method has a pre-step, specifically, the MCU main controller obtains the QC code compiled and converted into a .h header file in the IDE, and stores the converted QC code in the flash space of the MCU main controller, and the QC code of each module is independent. Converting the QC code into a .h header file in bytes is not only convenient to call, but also can achieve byte alignment, half-word alignment or word alignment, which is more flexible; the QC code is independent and can be called at will, and the tests between different functional modules do not interfere with each other.

[0016] The beneficial effects of the present invention are as follows: the present invention proposes an automatic QC method and device for SOC chips, which integrates a number of functional test modules, can realize fast automatic testing of SOC chips, effectively shorten the testing time, and improve the testing efficiency; a DEBUG mode is provided, which can realize fast fault location; the device has its own processor, and can be tested without connecting to a PC, and does not rely on traditional instruments such as digital power supplies, multimeters, oscilloscopes, etc., and has high portability; independent QC codes are provided, and the required code combination can be selected according to different types of SOC chips for testing, avoiding the trouble of repeatedly developing QC codes for different types of SOC chips, saving manpower and time, and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of an automated QC device for SOC chips according to an embodiment of the present invention.

[0018] Figure 2 The SOC chip automated QC method process described in one embodiment of the present invention Figure 1 .

[0019] Figure 3 The SOC chip automated QC method process described in one embodiment of the present invention Figure 2 . DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the specific embodiments described below are only used to explain the present invention and are not used to limit the present invention.

[0021] In the following description, specific details are given to provide a thorough understanding of the embodiments. However, one of ordinary skill in the art will appreciate that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams so as not to obscure the embodiments in unnecessary detail. In other cases, well-known circuits, structures, and techniques may not be shown in detail in order not to obscure the embodiments.

[0022] like Figure 1As shown, a SOC chip automatic QC device includes a QC motherboard, wherein the QC motherboard includes a PMU power supply, an MCU main controller, a SOCKET socket, a QC sub-board, a combination switch, a TEST button, a DEBUG button, a function module, and a result display module, wherein the PMU power supply is connected to the MCU main controller and the current test unit for powering the entire QC motherboard; the MCU main controller is connected to the PMU power supply, the combination switch, the current test unit, and the QC sub-board for controlling the entire QC process; the SOCKET socket is connected to the QC sub-board and the SOC chip to be tested for The SOC chip to be tested is installed; the QC sub-board is connected with the MCU main controller, the SOCKET socket and the functional module, and is used to install the SOCKET socket; the combination switch is connected with the MCU main controller, and is used to manually input the type of the SOC chip to be tested; the TEST button is connected with the MCU main controller, and is used to start the TEST mode; the DEBUG button is connected with the MCU main controller, and is used to start the DEBUG mode; the functional module is connected with the QC sub-board, and is used to test various functions of the SOC chip to be tested; the result display module is connected with the MCU main controller, and is used to display the test results. The SOC chip automatic QC device described in this embodiment relies on the MCU main controller, and can perform automatic testing of the SOC chip without connecting to the PC and other traditional instruments, and has high portability; the MCU main controller can call the pre-stored QC code at will according to the CHIPID of the SOC chip, and there is no need to spend time writing the required code before the test, which effectively shortens the test time and improves the work efficiency of the tester.

[0023] As one implementation method, the SOCKET socket is mounted on the QC daughter board, the QC daughter board is mounted on the QC mother board, and both the SOCKET socket and the QC daughter board are detachable. The method described in this embodiment can be compatible with different types of SOC chips by replacing different SOCKET sockets and QC daughter boards, avoiding the need to develop QC devices separately for different types of chips, thereby improving the utilization rate of the QC device.

[0024] As one implementation method, the combination switch is an 8-bit dip switch connected to the 8 IO ports of the MCU main controller, and the high and low levels are set by the dip switch, and the encoding is composed of 8 bits of data to represent a predefined SOC chip. The method described in this embodiment allows the user to manually set the CHIPID of the SOC chip to cope with the situation where the MCU main controller cannot read the CHIPID, which is more flexible.

[0025] As one of the implementation modes, the functional modules include: a current test unit for testing the power supply open-circuit and short-circuit test of the SOC chip to be tested; a USART docking self-test module for testing the serial communication interface of the SOC chip to be tested; a GPIO docking self-test module for testing the general input / output interface of the SOC chip to be tested; a GPTM docking self-test module for testing the general timer module of the SOC chip to be tested; an MCTM docking self-test module for testing the PWM wave output function of the control motor of the SOC chip to be tested; a PID docking self-test module for testing the PID operation of the SOC chip to be tested; The functional modules described in this embodiment can freely choose to be connected or not according to the CHIPID of the SOC chip to be tested, so as to meet the test requirements of different types of SOC chips.

[0026] like Figure 2As shown, an automatic QC method for SOC chips is implemented in an automatic QC device for SOC chips, which includes the following steps: Step S1, after receiving TEST key information, the MCU main controller establishes a connection with the SOC chip to be tested. If the connection is successful, the CHIPID pre-burned into the SOC chip to be tested is read, and the process proceeds to Step S2; if the connection fails, the result display module issues an alarm; Step S2, the MCU main controller loads the required QC code into the SOC chip to be tested according to the CHIPID of the SOC chip to be tested and in a set priority order; Step S3, the MCU main controller controls the SOC chip to be tested to load the required QC code into the SOC chip to be tested according to the set priority order; Step S4, the MCU main controller controls the SOC chip to be tested to load the required QC code into the SOC chip to be tested according to the CHIPID of the SOC chip to be tested; Step S5, the MCU main controller controls the SOC chip to be tested to load the required QC code into the SOC chip to be tested according to the set priority order; Step S6, the MCU main controller controls the SOC chip to be tested to load the required QC code into the SOC chip to be tested according to the set priority order; Step S7, the MCU main controller controls the SOC chip to be tested to load the required QC code into the SOC chip to be tested according to the set priority order; Step S8, the MCU main controller controls the SOC chip to be tested to load the required QC code into the SOC chip to be tested according to the set priority order; Step S9, the MCU main controller controls the SOC chip to be tested to load the required QC code into the SOC chip to be tested according to the set priority order. The chip executes the loaded QC code for functional testing according to the set priority order. If all tests pass, the result display module displays PASS information; if a test fails, the result display module displays FAIL information and enters step S4; step S4, when receiving FAIL information, if the MCU main controller receives DEBUG key information, it enters DEBUG mode; in DEBUG mode, each time the MCU main controller receives DEBUG key information, the result display module will be initialized first, and then a module test code will be run, and the result display module will display the test result of the current module until the DEBUG mode is exited. The automatic QC method for SOC chips described in this embodiment encapsulates the QC code of each module in the MCU main controller. According to the CHIPID of the SOC chip to be tested, the required QC code can be called at will without spending time to write it before the test. This can quickly perform automatic testing of SOC chips, effectively shorten the test time, and improve test efficiency.

[0027] As one implementation manner, the method for establishing a connection between the MCU main controller and the SOC chip to be tested is that the MCU main controller establishes a connection with the SWD bus of the SOC chip to be tested through a GPIO port.

[0028] As one implementation method, the method for loading the QC code is that the MCU main controller automatically loads the QC code into the flash or sram memory of the SOC chip to be tested according to the set priority order through the SWD bus. The method described in this embodiment can automatically download the QC code to the SOC chip to be tested through the SWD bus, no longer relying on the download environment of the PC-side IDE program, which is more convenient and quick.

[0029] As one of the implementation modes, the priority order is set as power on / off test>bootloader test>clock frequency test>flash / sram storage test>DDR2 / DDR3 control module test>ADC analog-to-digital conversion module test>MCTM control module test>GPTM general timer test>PID control module test>SPI control module test>UART serial communication test>I2C communication module test>general input / output interface test>SDIO module circuit test>DAC module circuit test>encryption / decryption module test>redundancy detection module test. In the method described in this embodiment, the priority of the front module is higher than that of the rear module, and the test priority of the module is set according to the size of the SOC chip area occupied by the module and whether it is easy to fail. In the event of a fault, reasonable treatment measures can be taken and the fault location can be quickly located.

[0030] As one of the implementation modes, the MCU main controller obtains the test result obtained after the SOC chip to be tested runs the QC code to perform a functional test through the SWD bus, and the test result is stored in a preset address of the SRAM memory of the SOC chip. Compared with the method of reading the GPIO port level to interact, the interaction between the MCU main controller and the SOC chip through the SRAM memory is more reliable. The former is prone to burr interference and thus causes misjudgment.

[0031] As one implementation mode, when the MCU main controller is in DEBUG mode in step S4, after the current QC code is executed, if TEST key information is received, the result display module is initialized, the current module QC code is executed again, and the test result is displayed again. The method described in this embodiment allows the same functional module to be debugged repeatedly, avoids misjudgment, and improves the test accuracy.

[0032] As one implementation method, the method for exiting the DEBUG mode is that all modules are debugged or the DEBUG button is pressed twice within 500ms.

[0033] As one of the implementation methods, the SOC chip automatic QC method has a pre-step, specifically, the MCU main controller obtains the QC code compiled and converted into a .h header file in the IDE, and stores the converted QC code in the flash space of the MCU main controller, and the QC code of each module is independent. The method described in this embodiment converts the QC code into a .h header file in bytes, which is not only convenient to call, but also can achieve byte alignment, half-word alignment or word alignment, which is more flexible; the QC code is independent and can be called at will, and the tests between different functional modules do not interfere with each other.

[0034] The following is a detailed description of the test process of a certain type of SOC chip. Figure 3 , assuming that the test of the chip requires the use of all functional modules on the QC motherboard.

[0035] First, install the SOC chip of this model into a suitable SOCKET socket, install the socket into a suitable QC daughter board, install the QC daughter board into the QC mother board, turn on the power, and complete the preparation before testing.

[0036] The user presses the TEST button to enter the TEST mode, i.e. the test mode. The MCU main controller establishes a connection with the SWD bus of the SOC chip to be tested through the GPIO port. If the connection fails, if the chip is correctly installed, the CHIPID of the SOC chip to be tested can also be manually set through the combination switch connected to the MCU main controller, i.e. the chip model is manually entered. The combination switch is an 8-bit dip switch. If it is dialed up, it can be pulled up to VCC, and if it is dialed down, it can be pulled down to GND. The MCU main controller reads the IO port level to obtain the dip switch code value to know the CHIPID of the SOC chip to be tested, such as 0000_0001 for AM380S, 0000_0002 for AM380E, 0000_00003 for AM330, and so on; if it is not manually set and the connection fails all the time, the result display module will issue an alarm, such as by setting the LED light to display red and flash continuously, and the user can power off and test again; if the connection is successful, the MCU main controller directly reads the CHIPID pre-burned to the SOC chip to be tested.

[0037] After knowing the CHIPID of the SOC chip to be tested, the QC code required by the chip is loaded into the flash or sram storage inside the chip according to the pre-set priority order, and then the stack pointer content is modified, and the PC pointer points to the program start address. The SOC chip to be tested can start executing the code from the flash 0x0 address or the sram 0x20000000 address. The specific steps are as follows:

[0038] (1) Power open and short circuit test: The MCU main controller configures the gear of the current test unit through the I2C interface to accurately test the current of the power pin of the SOC chip to be tested. The current test unit calculates the power consumption of the SOC chip to be tested and transmits it to the MCU main controller in real time for judgment. If the measured current value is less than the maximum current specified in the specification, the test PASSes and then jumps directly to the next step; otherwise, the test FAILs and waits for user operation;

[0039] (2) Bootloader test: First, the TX pin of the bootloader serial port of the SOC chip to be tested is connected to the RX pin of the serial port of the MCU main controller. After the SOC chip to be tested is powered on, the bootloader program pre-existing in the flash is executed, and a character string with bootloader version information is sent through the serial port TX. The MCU main controller receives the character string through the serial port RX. If the bootloader version information is consistent with the expected version, the test is PASS, and then jumps directly to the next step. If the received version information is inconsistent, or the character string is not received due to timeout, the test is FAIL, waiting for user operation.

[0040] (3) Clock frequency test: First, the GPTM module of the MCU main controller, which serves as the clock measurement unit, is configured to capture input mode and connected to the CKOUT pin of the SOC chip to be tested. The low-frequency clock LSI, multiplier clock PLL, USB clock, and DDRPLL clock inside the SOC chip to be tested are released to the CKOUT pin in turn. The GPTM module of the MCU main controller captures the count value and calculates the specific frequency value of the above-mentioned clock to be tested with the GPTM working clock, and compares it with the test index. If it is within the index range, the test is PASS, and then directly jumps to the next step. If the test frequency value is outside the index range, the test is FAIL, and waits for user operation.

[0041] (4) Flash / SRAM storage test, write all A, read and compare, write all 5, read and compare, write all F, read and compare, write all 0, read and compare. If the read data is consistent with the written data, the test is PASS, and then jump directly to the next step. If the read data is inconsistent with the written data, the test is FAIL, waiting for user operation.

[0042] (5) DDR2 / DDR3 control module test: the address line, command line, clock line, and data line of the DDR2 / DDR3 controller of the SOC chip to be tested are connected to the address line, command line, clock line, and data line of the DDR2 / DDR3 memory particles on the QC motherboard respectively, and the memory particles are accessed and read and written at the set frequency speed. If there is no error in access and reading and writing, the test is PASS, and then jumps directly to the next step; if the memory address access is unsuccessful or the reading and writing are wrong, the test is FAIL, waiting for user operation;

[0043] (6) ADC analog-to-digital conversion module test: First, use the high-precision DAC chip on the QC motherboard to simulate the voltage output channel to generate several specific voltage values; then, the SOC chip to be tested collects these voltage values ​​through its ADC channel, and the voltage values ​​obtained after calculation are compared with the voltage values ​​generated by the high-precision DAC chip; if the voltage values ​​collected by the ADC channel are within the input voltage specification range, the test is PASS, and then jumps directly to the next step; if the voltage values ​​collected by the ADC channel are outside the input voltage specification range, the test is FAIL, waiting for user operation;

[0044] (7) MCTM control module test, QC code control signal switch IC connects two groups of MCTM interfaces; MT0_CH0 / 0N / 1 / 1N / 2 / 2N / 3 of Motortimer0 is connected to MT1_CH0 / 0N / 1 / 1N / 2 / 2N / 3 of Motor timer1 respectively; first MT0_CH0 / 0N / 1 / 1N / 2 / 2N / 3 outputs PWM waveform, MT1_CH0 / 0N / 1 / 1N / 2 / 2N / 3 receives and detects the frequency of PWM wave, then MT1_CH0 / 0N / 1 / 1N / 2 / 2N / 3 outputs PWM waveform, MT0_CH0 / 0N / 1 / 1N / 2 / 2N / 3 receives and detects the frequency of PWM wave; if both groups of MCTM interfaces can detect PWM waveform of correct frequency, the test is PASS, and then jumps directly to the next step; if any group of MCTM interfaces cannot detect PWM wave of correct frequency, the test is FAIL, waiting for user operation;

[0045] (8) General timer module test, QC code control signal switch IC connects two groups of GPTM interfaces; T0_CH0 / 1 / 2 / 3 of GPTMtimer0 is connected to T1_CH0 / 1 / 2 / 3 of GPTM timer1 respectively; first, T0_CH0 / 1 / 2 / 3 outputs PWM waveform, T1_CH0 / 1 / 2 / 3 receives and detects the frequency of PWM wave, then T1_CH0 / 1 / 2 / 3 outputs PWM waveform, T0_CH0 / 1 / 2 / 3 receives and detects the frequency of PWM wave; if both groups of GPTM interfaces can detect PWM waveform of correct frequency, the test is PASS, and then jumps directly to the next step; otherwise, if any group of GPTM interfaces cannot detect PWM waveform of correct frequency, the test is FAIL, waiting for user operation;

[0046] (9) PID control module test, QC code control signal switch IC connects two groups of PID module circuits; PID0_OUT is connected to PID1_IN, PID1_OUT is connected to PID0_IN; PID0_OUT and PID1_OUT output several groups of specific frequency PWM waveforms, PID1_IN and PID0_IN receive and detect the corresponding PWM waveforms respectively. If the frequencies of several groups are detected correctly, the test is PASS, and then jumps directly to the next step; otherwise, if any group of PID input interfaces cannot detect the PWM wave of the correct frequency, the test is FAIL, waiting for user operation;

[0047] (10) SPI controller module test: The QC code controls the signal switch IC to connect n groups of SPI interfaces with n norflash devices on the QC motherboard. The SOC chip to be tested sends erase, read and write commands to the n norflash devices respectively (n is the n SPI modules owned by the SOC to be tested). If the above commands are executed correctly, the test is PASS, and then jumps directly to the next step; otherwise, if any group of commands fails to execute successfully, the test is FAIL, waiting for user operation;

[0048] (11) Serial communication interface test: the QC code controls the signal switch IC to connect the TX interfaces of n groups of USART modules to the RX interfaces respectively (n is the number of USART modules owned by the SOC to be tested). If the n groups of RX interfaces can correctly receive the data sent by the TX interfaces, the test is PASS, and then the next step is directly executed; otherwise, if any group of commands fails to execute, the test is FAIL, and the user operation is waited for;

[0049] (12) I2C communication module test. The QC code controls the signal switch IC to connect n groups of I2C communication interfaces with n EEPROM devices on the QC motherboard. The SOC chip to be tested sends read and write commands to n EEPROM devices respectively (n is the n I2C module circuits owned by the SOC to be tested). If the read data is equal to the written EEPROM data, the test is PASS, and then jumps directly to the next step. If the read data is not equal to the written EEPROM data, the test is FAIL, waiting for user operation.

[0050] (13) General input / output interface test, QC code controls the signal switch IC to connect group A and group B GPIO interfaces; first, group A is used as output, outputting 1 / 0 high and low levels respectively, and group B is used as input to read the level of group A output, then group B is used as output and group A is used as input to perform the same operation; if both groups of GPIO interfaces can correctly read the level of each other's output, the test passes, the test is PASS, and then jumps directly to the next step; if any group of GPIO interfaces cannot read the correct level of the other group's output, the test is FAIL, waiting for user operation;

[0051] (14) SDIO module circuit function test: a TF-SD card is inserted into the QC motherboard. The command line, data line, and clock line of the SDIO module of the SOC chip to be tested are connected to the TF-SD card respectively. The TF-SD card is mounted, and the file system is created and read and write tests are performed. If there are no errors in the above tests, the test is PASS, and then jumps directly to the next step. If there is an error in file reading and writing, or the mounting of the TF-SD card fails, the test is FAIL, and waits for user operation.

[0052] (15) DAC digital-to-analog conversion module test: First, use the DAC analog voltage output channel of the SOC chip to be tested to generate several specific voltage values; then, the ADC channel on the QC motherboard collects these voltage values ​​and compares them with the voltage values ​​generated by the DAC analog voltage output channel of the SOC chip to be tested; if the voltage collected by the ADC channel is within the specification range of the DAC analog output voltage, the test is PASS, and then jumps directly to the next step; if the voltage collected by the ADC channel is outside the specification range of the DAC analog output voltage, the test is FAIL, waiting for user operation;

[0053] (16) Encryption and decryption module test: configure an encryption method, encrypt the input data, and then decrypt the encrypted data in reverse order. If the encrypted output data is equal to the decrypted data, the test is PASS, and then the next step is executed directly. If the encrypted data is not equal to the decrypted data, the test is FAIL, and the user operation is waited for.

[0054] (17) Redundancy detection module test: perform CRC check on the input data, compare the calculated CRC value with the expected value, if they are equal, the test is PASS, at which point all functional module tests have passed, the LED green light is on, and then the MCU main controller enters the standby state; if the calculated CRC value is not equal to the expected value, the test is FAIL, waiting for user operation;

[0055] For any of the above tests, the user can press the DEBUG button to enter the DEBUG mode, i.e., the debugging mode. After entering the DEBUG mode, press the DEBUG button again, the LED light will turn off, and then the test will be restarted from step (1). If the test in step (1) is PASS, the LED light will turn on green directly; if the test in step (1) is FAIL, the LED light will turn on red directly. Whether it is PASS or FAIL, it is necessary to wait for the user to perform the next operation: if the user presses the TEST button, the LED light will turn off again, and then the QC code in step (1) will be executed again, and the test result will be displayed; if the user presses the DEBUG button, the LED light will also turn off, and then the QC code in step (2) will be executed, and the test result will be displayed. Steps (1) to (16) all follow the same operation mode. In step (17), because there is no next test module, pressing the DEBUG button will exit the DEBUG mode, and the MCU main controller will enter the standby state. In the DEBUG mode, double-clicking the DEBUG button within 500ms can also exit the DEBUG mode.

[0056] The MCU main controller is equipped with a serial port for communicating with the PC. If the MCU main controller is connected to the PC through the serial port, after the TEST mode or DEBUG mode ends, the MCU main controller will first print the PASS / FAIL information to the PC and then enter the standby state.

[0057] In the embodiments provided by the present invention, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A SOC chip automated QC device, comprising a QC motherboard, characterized in that: The QC motherboard includes a PMU power supply, an MCU main controller, a SOCKET socket, a QC daughter board, a combination switch, a TEST button, a DEBUG button, a function module, and a result display module, wherein: PMU power supply, connected to the MCU main controller and current test unit, is used to power the entire QC motherboard; MCU main controller, connected with PMU power supply, combination switch, current test unit and QC daughter board, is used to control the whole QC process; A SOCKET socket is connected to the QC sub-board and the SOC chip to be tested, and is used to install the SOC chip to be tested; The QC daughter board is connected to the MCU main controller, the SOCKET socket and the functional module, and is used to install the SOCKET socket; Combination switch, connected to the MCU main controller, used to manually input the type of SOC chip to be tested; TEST button, connected to the MCU main controller, is used to start the TEST mode; DEBUG button, connected to the MCU main controller, used to start the DEBUG mode; Functional module, connected to the QC daughter board, used to test various functions of the SOC chip to be tested; The result display module is connected to the MCU main controller and is used to display the test results.

2. A SOC chip automated QC device according to claim 1, characterized in that: The SOCKET socket is installed on the QC daughter board, and the QC daughter board is installed on the QC mother board. Both the SOCKET socket and the QC daughter board are detachable.

3. A SOC chip automated QC device according to claim 1, characterized in that: The combination switch is an 8-bit dip switch, which is connected to the 8 IO ports of the MCU main controller. The high and low levels are set by toggling the dip switch, and the encoding is composed of 8-bit data to represent a predefined SOC chip.

4. A SOC chip automated QC device according to claim 1, characterized in that: The functional modules include: Current test unit, used for power open and short circuit test of the SOC chip to be tested; USART docking self-test module is used to test the serial communication interface of the SOC chip under test; GPIO docking self-test module, used to test the general input / output interface of the SOC chip under test; GPTM is connected to the self-test module to test the general timer module of the SOC chip to be tested; MCTM is connected to the self-test module to test the PWM wave output function of the control motor of the SOC chip under test; PID docking self-test module, used to test the PWM wave output function of the PID motion control of the SOC chip under test; DAC test module, used to test the ADC analog-to-digital conversion function of the SOC chip under test; ADC test module, used to test the DAC analog-to-digital conversion function of the SOC chip under test; External NORFLASH device is used to test the SPI controller module of the SOC chip under test; External EEPROM device, used to test the I2C communication module of the SOC chip under test; External DDR2 / 3 memory chip, used to test the DDR controller circuit function of the SOC chip under test; External TF card is used to test the SDIO module circuit function of the SOC chip to be tested.

5. A SOC chip automated QC method, characterized in that: The automated QC method is implemented in an automated QC device for SOC chips, which comprises the following steps: Step S1, after receiving the TEST key information, the MCU main controller establishes a connection with the SOC chip to be tested. If the connection is successful, the CHIPID pre-burned into the SOC chip to be tested is read and the process goes to step S2; if the connection fails, the result display module issues an alarm; Step S2, the MCU main controller loads the required QC code into the SOC chip to be tested according to the CHIPID of the SOC chip to be tested and in a set priority order; Step S3, the MCU main controller controls the SOC chip to be tested to execute the loaded QC code for functional testing according to the set priority order. If all tests pass, the result display module displays PASS information; if a test fails, the result display module displays FAIL information and enters step S4; Step S4, when receiving the FAIL information, if the MCU main controller receives the DEBUG key information, it enters the DEBUG mode; in the DEBUG mode, each time the MCU main controller receives the DEBUG key information, the result display module will be initialized first, and then a module test code will be run, and the result display module will display the test results of the current module until the DEBUG mode is exited.

6. A SOC chip automated QC method according to claim 5, characterized in that: The method for establishing a connection between the MCU main controller and the SOC chip to be tested is that the MCU main controller establishes a connection with the SWD bus of the SOC chip to be tested through the GPIO port.

7. The SOC chip automated QC method according to claim 5, characterized in that: The method for loading the QC code is that the MCU main controller automatically loads the QC code into the flash or sram storage of the SOC chip to be tested according to the set priority order through the SWD bus.

8. The SOC chip automated QC method according to claim 5, characterized in that: The set priority order is power open and short circuit test > bootloader test > clock frequency test > flash / sram storage test > DDR2 / DDR3 control module test > ADC analog-to-digital conversion module test > MCTM control module test > GPTM general timer test > PID control module test > SPI control module test > UART serial port communication test > I2C communication module test > general input / output interface test > SDIO module circuit test > DAC module circuit test > encryption and decryption module test > redundancy detection module test.

9. A SOC chip automated QC method according to claim 5 or 8, characterized in that: The MCU main controller obtains the test result obtained after the SOC chip to be tested runs the QC code to perform a functional test through the SWD bus, and the test result is stored in a preset address of the SRAM memory of the SOC chip.

10. The SOC chip automated QC method according to claim 5, characterized in that: When the MCU main controller is in the DEBUG mode in step S4, after the current QC code is executed, if the TEST key information is received, the result display module is initialized, the current module QC code is executed again, and the test result is displayed again.

11. The SOC chip automated QC method according to claim 5, characterized in that: The method for exiting the DEBUG mode is to complete debugging of all modules or press the DEBUG button twice within 500ms.

12. The SOC chip automated QC method according to claim 5, characterized in that: The SOC chip automatic QC method has a pre-step, specifically, the MCU main controller obtains the QC code compiled and converted into a .h header file in the IDE, and stores the converted QC code in the flash space of the MCU main controller. The QC code of each module is independent.

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