Column decoder circuit

Abstract

Various implementations described herein relate to a memory circuit having an array of bitcells and bitlines coupled to columns of the bitcells. Also, a column decoder circuit can be coupled to the bitcells via the bitlines, and the column decoder circuit can have read logic coupled to an output node. The column decoder circuit can have selection logic coupled between a voltage source and the read logic. An enable signal can be used to activate the selection logic to pass the voltage source to the read logic, and the bitlines provide a bitline signal that activates the read logic to pass the voltage source from the selection logic to the output node.

Description

BACKGROUND

[0001] This section is intended to provide background information that can be of possible relevance to understanding various technologies described herein. It is merely intended to provide a discussion of related technology. It should not be considered an acknowledgement that any of the related technology, taken individually or in any combination, is prior art to any of the technologies described herein. Accordingly, any statement herein as to activity of related technology should not be taken as an acknowledgement that any of the related technology forms part of the common general knowledge of the art.

[0002] In modern conventional designs, multiplexing circuitry and full-swing sensing are typically implemented in two different steps. This configuration can result in timing delays for both functions. This configuration also results in inefficient use of area. Accordingly, various improvements to the physical design of some circuit layouts are needed to improve timing characteristics and efficient use of area in modern memory designs. BRIEF DESCRIPTION OF DRAWINGS

[0003] Implementations of the various technologies described herein are described herein with reference to the accompanying drawings. However, it should be understood that the accompanying drawings illustrate only some implementations of the various technologies described herein and are not intended to limit the scope of the various technologies described herein.

[0004] Figure 1 A diagram of a memory circuit is shown in accordance with various implementations described herein.

[0005] Figures 2A-2B A diagram of a column decoder circuit is shown in accordance with various implementations described herein.

[0006] Figure 3 A process flow diagram of a method for providing a memory circuit is shown in accordance with various implementations described herein. DETAILED DESCRIPTION

[0007] Various implementations described herein relate to control architectures for implementing column decoding schemes and techniques. In some instances, various implementations described herein relate to high-speed column multiplexer circuitry for multi-port static random access memory (SRAM) with full-swing bit lines. Also, various implementations described herein refer to combining multiple functions (e.g., multiplexing of read bit lines and full-swing sensing) in a single circuit, which can improve read speed and area. As will be described below, various implementations described herein can provide for consolidating multiple circuit functions into a single transistor function. Also, this consolidation can provide for less timing delay and denser floorplan.

[0008] Reference will now be made to Figures 1-3 Various implementations of column decoding schemes and techniques are described in more detail.

[0009] Figure 1A diagram of a memory or memory circuit 100 according to implementations described herein is shown. In some cases, the memory circuit 100 can be implemented as a system of various circuit components arranged and coupled together as an assembly or combination forming part of a memory structure. Also, in some cases, the method of high speed column decoding can involve using various circuit components described herein to implement improved performance techniques.

[0010] The memory circuit 100 can include a plurality of arrays 104A, 104B of bitcells (BC) and bitlines (rbl) coupled to columns (col) of bitcells (BC). In some cases, the memory circuit 100 can include a multi-port memory, for example, a multi-port static random access memory (SRAM). In some implementations, the plurality of arrays 104A, 104B of bitcells (BC) can include a first array 104A of bitcells (BC) and a second array 104B of bitcells (BC). The first array 104A can be referred to as an upper (or top) array and the second array 104B can be referred to as a lower (or bottom) array. The bitlines (rbl) can be referred to as read bitlines (rbl), for example, full swing read bitlines. Also, the bitlines (rbl) can include first bitlines (rbl0_top, rbl1_top) and the bitlines (rbl) can include second bitlines (rbl0_bot, rbl1_bot).

[0011] In some implementations, the first array 104A (top_array) can have a plurality of bitcells (BC) arranged in a plurality of columns (col_0, col_1, col_2, col_3) and a plurality of rows (row_0, row_1, row_2, row_3). The second array 104A (top_array) can have a plurality of bitcells (BC) arranged in a plurality of columns (col_0, col_1, col_2, col_3) and a plurality of rows (row_0, row_1, row_2, row_3). Also, in some implementations, the memory circuit 100 can include wordlines (wl_0, wl_1, wl_2, wl_3) coupled to rows (row_0, row_1, row_2, row_3) of bitcells (BC) and the memory circuit 100 can include wordline driver circuits (108A, 108B) having wordline drivers (WLD) coupled to corresponding bitcells (BC) via wordlines (wl_0, wl_1, wl_2, wl_3).

[0012] As Figure 1As shown, the first array 104A and the second array 104B can include any number of bitcells (BC) arranged in various configurations, such as a two-dimensional (2D) storage array having any number of columns (N) and any number of rows of bitcells (BC). In general, each bitcell (BC) can be referred to as a data bitcell (or memory storage cell), and each bitcell (BC) can be configured to store at least one data bit value (e.g., a data value associated with a logical '0' or '1'). The first array 104A and the second array 104B can be referred to as data bitcell arrays. Also, the bitcells of the first array 104A and the second array 104B can be implemented in static random access memory (SRAM) circuitry, and each bitcell (BC) can include a multi-transistor SRAM cell, including various types of SRAM cells, such as, for example, a 6T CMOS SRAM and / or other types of CMOS SRAM cells, such as 4T, 8T, 10T, or more transistors. However, various other types of memory can be used.

[0013] The memory circuit 100 can include column decoder circuitry 110A, 110B coupled to corresponding bitcells (BC) via bitlines (rbl). The column decoder circuitry 110A, 110B can be referred to as read column multiplexer (colmux) circuitry. As shown, the column decoder circuitry 110A, 110B can include a first column multiplexer (colmux) 110A and a second column multiplexer (colmux) 110B. Also, the column decoder circuitry 110A, 110B can provide read output signals, such as global data line (GDL) signals, to global read column input / output (IO) circuitry 114A, 114B.

[0014] In some implementations, the first column multiplexer (colmux) 110A can be coupled to columns (col_0, col_1) of bitcells (BC) in the first or top array 104A via first bitlines (rbl0_top, rbl1_top), and the second column multiplexer (colmux) 110B can be coupled to columns (col_2, col_3) of bitcells (BC) in the first or top array 104A via first bitlines (rbl0_top, rbl1_top). Additionally, the first column multiplexer (colmux) 110A can be coupled to columns (col_0, col_1) of bitcells (BC) in the second or bottom array 104B via second bitlines (rbl0_bot, rbl1_bot), and the second column multiplexer (colmux) 110B can be coupled to columns (col_2, col_3) of bitcells (BC) in the second or bottom array 104B via second bitlines (rbl0_bot, rbl1_bot).

[0015] In some cases, a first column multiplexer (colmux) 110A can provide a first read out signal (e.g., a first global data line (GDL) signal) to a first global read column input / output (IO) circuit 114A. Also, a second column multiplexer (colmux) 110B can provide a second read out signal (e.g., a second global data line (GDL) signal) to a second global read column input / output (IO) circuit 114B.

[0016] The memory circuit 100 can include local read controls 120 coupled to the read column decoder circuits 110A, 110B. The memory circuit 100 can include master read controls 124 coupled to the global read column input / output (IO) circuits 114A, 114B. As shown, the first column multiplexer (colmux) 110A can include a read column multiplexer (read colmux) configured to provide a first global data line (GDL) signal to a first global read IO 114A, and the second column multiplexer (colmux) 110B can include a read column multiplexer (read colmux) configured to provide a second global data line (GDL) signal to a second global read IO 114B.

[0017] Figures 2A-2B Various diagrams of column decoder circuits 200A, 200B are shown in accordance with various implementations described herein. In particular, Figure 2A An implementation of a column decoder circuit 200A is shown, and Figure 2B Another implementation of a column decoder circuit 200B is shown.

[0018] Figure 2A A diagram of a column decoder circuit 200A is shown in accordance with various implementations described herein. The column decoder circuit 200A can be implemented as Figure 1 a column multiplexer (colmux) 110A, 110B in FIG. 1. In various implementations, the column decoder circuit 200A can include complementary metal-oxide-semiconductor (CMOS) devices, including, for example, P-type MOS (PMOS) devices and N-type MOS (NMOS) devices.

[0019] As Figure 2AAs shown, the column decoder circuit 200A can be coupled to bit lines (rblO_top, rbl l_top, rblO_bot, rbl l_bot). Also, the bit lines (rblO_top, rbl l_top, rblO_bot, rbl l_bot) can be referred to as read bit lines, and the bit lines (rblO_top, rbl l_top, rblO_bot, rbl l_bot) can be coupled to read logic (read_0_side, read l_side).

[0020] The column decoder circuit 200A can include read logic (read_0_side, read l_side) coupled to an output node (nand_out). The read logic (read_0_side, read l_side) can include read transistors (RP0, RP1, RP2, RP3). In some cases, the read transistors (RP0, RP1, RP2, RP3) can include PMOS transistors. However, in other cases, the read transistors (RP0, RP1, RP2, RP3) can include NMOS transistors.

[0021] The column decoder circuit 200A can include selection logic (sel_0_side, sel l_side) coupled between a voltage source (Vdd) and the read logic (read_0_side, read l_side). The selection logic (sel_0_side, sel l_side) can include selection transistors (SP0, SP1, SP2, SP3). In some cases, the selection transistors (SP0, SP1, SP2, SP3) can include PMOS transistors. However, in other cases, the read transistors can include NMOS transistors.

[0022] In some cases, the enable signals (selO b, sel l b) can be used to activate the selection logic (sel_0_side, sel l_side) to pass the voltage source (Vdd) to the read logic (read_0_side, read l_side). Likewise, the bit lines (rblO_top, rbl l_top, rblO_bot, rbl l_bot) can provide bit line signals that activate the read logic (read_0_side, read l_side) to pass the voltage source (Vdd) from the selection logic (sel_0_side, sel l_side) to the output node (nand_out).

[0023] The selection logic (sel_0_side, sel_1_side) can include the use of select transistors (SP0, SP1, SP2, SP3), and the enable signals (sel0b, sel1b) can be referred to as select activation signals. The select activation signals (sel0b, sel1b) can be used to activate the gates of the select transistors (SP0, SP1, SP2, SP3) in order to pass the voltage source (Vdd) to the read logic (read_0_side, read_1_side).

[0024] The read logic (read_0_side, read_1_side) can include the use of read transistors (RP0, RP1, RP2, RP3), and the bit lines (rbl0_top, rbl1_top, rbl0_bot, rbl1_bot) can be coupled to the gates of the read transistors. Also, the bit lines (rbl0_top, rbl1_top, rbl0_bot, rbl1_bot) can provide bit line signals to activate the gates of the read transistors (RP0, RP1, RP2, RP3) in order to pass the voltage source (Vdd) from the selection logic (sel_0_side, sel_1_side) to the output node (nand_out).

[0025] The column decoder circuit 200A can include precharge logic (precharge rbl0, precharge rbl1) coupled between the voltage source (Vdd) and the read logic (read_0_side, read_1_side). In some implementations, precharge activation signals (npch_bl_top, npch_bl_bot) can be used to activate the precharge logic (precharge rbl0, precharge rbl1) in order to pass the voltage source (Vdd) to the read logic (read_0_side, read_1_side). The voltage source (Vdd) can be used to precharge the bit lines (rbl0_top, rbl1_top, rbl0_bot, rbl1_bot) through the read logic (read_0_side, read_1_side).

[0026] The precharge logic (precharge rblO, precharge rbl1) can include precharge transistors (P0, P1, P2, P3) coupled between a voltage source (Vdd) and gates of the read transistors (RP0, RP1, RP2, RP3). Further, precharge activation signals (npch_bl_top, npch_bl_bot) can be used to activate gates of the precharge transistors (P0, P1, P2, P3) to pass the voltage source (Vdd) to the gates of the read transistors (RP0, RP1, RP2, RP3). The voltage source (Vdd) can be used to precharge the bitlines (rblO_top, rbl1_top, rblO_bot, rbl1_bot) at the gates of the read transistors (RP0, RP1, RP2, RP3). In some cases, the precharge transistors (P0, P1, P2, P3) can include PMOS transistors. However, in other cases, the read transistors can include NMOS transistors.

[0027] The column decoder circuit 200A can include output discharge logic (output_discharge) coupled to the output node (nand_out). Further, read logic (read_0_side, read_1_side) can be used to pass a voltage source (Vdd) to the output node (nand_out) to activate the output discharge logic (output_discharge). The output discharge logic (output_discharge) can be used to pass an output discharge signal to ground (Gnd or Vss). The output discharge logic (output_discharge) can include an output discharge transistor (NG) and the output node (nand_out) can be coupled to a gate of the output discharge transistor (NG). The read transistors (RP0, RP1, RP2, RP3) can be used to pass the voltage source (Vdd) to the output node (nand_out) to activate the gate of the output discharge transistor (NG) and the output discharge transistor (NG) when activated can be used to pass the output discharge signal to ground (Gnd or Vss). In some cases, the output discharge signal can include using a global data line (GDL) signal. In some cases, the output discharge transistor (NG) can include an NMOS transistor. However, in other cases, the output discharge transistor (NG) can include using a PMOS transistor.

[0028] Column decoder circuit 200A can include an output circuit (precharge_nand_out) having a plurality of transistors (N0, N1, N2, N3, N4, N5) coupled in series together in one or more stacks between an output node (nand_out) and ground (Gnd or Vss). The plurality of transistors (N0, N1, N2, N3, N4, N5) can be activated with an enable signal (sel0, sel1) or a bit line signal provided from a bit line (rbl0_top, rbl1_top, rbl0_bot, rbl1_bot). In some cases, the enable signal (sel0, sel1) is in addition to an enable signal (sel0b, sel1b).

[0029] In some cases, the plurality of transistors (N0, N1, N2, N3, N4, N5) can be arranged in a first stack and a second stack coupled in parallel between the output node (nand_out) and ground (Gnd or Vss). The first stack can include transistors (N0, N1, N2) coupled in series between the output node (nand_out) and ground (Gnd or Vss), and the second stack can include transistors (N3, N4, N5) coupled in series between the output node (nand_out) and ground (Gnd or Vss). Also, in some cases, the plurality of transistors (N0, N1, N2, N3, N4, N5) can include NMOS transistors. However, in other cases, the plurality of transistors can include PMOS transistors.

[0030] In some implementations, as Figure 2AAs shown, the column decoder circuit 200A has a set of transistors (RP0, SP0, P0) arranged and coupled to the output node (nand_out) and the corresponding bit line (rbl0_top). For example, the read transistor (RP0) can be coupled to the output node (nand_out), the select transistor (SP0) can be coupled between the voltage source (Vdd) and the read transistor (RP0), and a select activation signal (sel0b) activates the gate of the select transistor (SP0) to pass the voltage source (Vdd) as the output signal (nand_out) to the read transistor (RP0). The bit line (rbl0_top) can be coupled to the gate of the read transistor (RP0), and the bit line (rbl0_top) can provide the bit line signal that activates the gate of the read transistor (RP0) to pass the output signal (nand_out) from the select transistor (SP0) to the output node (nand_out). Furthermore, the precharge transistor (P0) can be coupled between the voltage source (Vdd) and the gate of the read transistor (RP0), and the precharge activation signal (npch_bl_top) activates the gate of the precharge transistor (P0) to deliver the voltage source (Vdd) to the gate of the read transistor (RP0). Therefore, the voltage source (Vdd) can be used to precharge the bit line (rbl0_top) at the gate of the read transistor (RP0).

[0031] In some implementations, the set of transistors (RP0, SP0, P0) may be a first set of transistors, and the column decoder circuit 200A may include a second set of transistors (RP1, SP1, P1), a third set of transistors (RP2, SP2, P2), and a fourth set of transistors (RP3, SP3, P3), wherein each set of transistors includes a transistor configuration similar to the first set. Thus, the column decoder circuit 200A can be implemented as a system of various circuit components (e.g., various transistors) arranged and coupled together as assemblies or combinations of parts to form a column decoding structure or similar structure.

[0032] Figure 2B A diagram of the column decoder circuit 200B according to various implementations described herein is shown. Figure 2B The column decoder circuit 200B in the middle has the same characteristics as... Figure 2A The column decoder circuit 200A in the series is similar to the circuit components in terms of range, operation and function.

[0033] like Figure 2B As shown, the arrangement of the circuit components of the column decoder circuit 200B is similar to... Figure 2Acolumn decoder circuit 200A, except for the swapping of the read transistors (RP0, RP1, RP2, RP3) and the select transistors (SP0, SP1, SP2, SP3). For example, as shown in Figure 2B

[0034] Figure 2A As with the column decoder circuit 200A of Figure 2B

[0035] Figure 3 A flow diagram illustrating a method 300 for providing a memory circuit in accordance with the various implementations described herein is shown.

[0036] It should be understood that even though operations are indicated as being performed in a particular order, various specific parts of the operations can be performed in different orders on different systems in some cases. In other cases, additional operations and / or steps can be added to the method 300 and / or omitted from the method 300. Also, the method 300 can be implemented in hardware and / or software. If implemented in hardware, the method 300 can be implemented with various components and / or circuits, as described herein with reference to Figures 1-2B

[0037] As described with reference to Figure 3 ​​​​As described and shown, the method 300 can be used to make and / or manufacture or cause to be made and / or manufactured an integrated circuit (IC) that implements various column decode schemes and techniques described herein related to providing column decode circuitry and / or various related devices, components, and circuitry.

[0038] At block 310, the method 300 can provide an array of bit cells having bit cells arranged in columns and rows. At block 320, the method 300 can provide word lines coupled to rows of the bit cells. At block 330, the method 300 can provide bit lines coupled to columns of the bit cells. Also, at block 340, the method 300 can provide column decoders coupled to the bit cells via the bit lines. In some implementations, the column decoders can have a read transistor coupled to an output node, and the column decoders can also have a select transistor coupled between a voltage source and the read transistor. A select activation signal can be used to activate a gate of the select transistor in order to pass the voltage source to the read transistor. The bit lines can be coupled to the gates of the read transistors, and the bit lines can provide bit line signals to activate the gates of the read transistors in order to pass the voltage source from the select transistor to the output node.

[0039] Various implementations of an integrated circuit are described herein. The integrated circuit can include a memory circuit having an array of bit cells and bit lines coupled to columns of the bit cells. The integrated circuit can include column decoder circuitry coupled to the bit cells via the bit lines. The column decoder circuitry can have read logic coupled to an output node, and the column decoder circuitry can have select logic coupled between a voltage source and the read logic. In some instances, an enable signal can activate the select logic to pass the voltage source to the read logic, and the bit lines can provide bit line signals that activate the read logic to pass the voltage source from the select logic to the output node.

[0040] Various implementations of a system having one or more circuit components are described herein. The system can include a read transistor coupled to an output node. The system can include a select transistor coupled between a voltage source and the read transistor. The system can include a select activation signal that activates a gate of the select transistor to pass the voltage source as an output signal to the read transistor. The system can include a bit line coupled to a gate of the read transistor. The bit line can provide a bit line signal that activates the gate of the read transistor in order to pass the output signal from the select transistor to the output node.

[0041] Described herein are various implementations of methods. The methods can include providing an array of bit cells having bit cells arranged in a column and a bit line coupled to the column of bit cells. The methods can include providing a column decoder coupled to the bit cells via the bit line, and the column decoder can have a read transistor and a select transistor coupled between a voltage source and an output node. The select transistor, when activated, can pass the voltage source to the read transistor. The bit line can be coupled to a gate of the read transistor so as to activate the gate of the read transistor, and when activated, pass the voltage source from the select transistor to the output node.

[0042] Implementations of the various techniques described herein can be operational with numerous general purpose or special purpose computing system environments or configurations. Examples of computing systems, environments, and / or configurations that can be suitable for use with the various techniques described herein include, but are not limited to, personal computers, server computers, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, smart phones, tablets, wearable computers, cloud computing systems, virtual computers, shipboard electronics, and the like.

[0043] The various techniques described herein can be implemented in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Moreover, each program module can be implemented in its own individual manner, without necessarily having to be implemented in the same manner as other program modules. While the program modules can be executed on a single computing system, it should be appreciated that in some implementations the program modules can be implemented on separate computing systems or devices that are adapted to communicate with one another. Program modules can also be some combination of hardware and software, where particular tasks are performed by the hardware, software, or some combination thereof.

[0044] The various techniques described herein can be implemented in a distributed computing environment, where tasks are performed by remote processing devices that are linked through a communications network, e.g., by hardwired links, wireless links, or various combinations thereof. In a distributed computing environment, program modules can be located in both local and remote computer storage media, including, e.g., memory storage devices.

[0045] Furthermore, the discussion provided herein is considered to be a discussion of certain specific implementations. It is understood that the discussion provided herein is intended to enable those with ordinary skill in the art to make and use any subject matter defined by the subject matter of the claims.

[0046] It is intended that the subject matter of the claims is not limited to the implementations and descriptions provided herein, but include modifications and variations of those implementations and descriptions. It is further intended that the subject matter of the claims include combinations of the implementations and features presented herein with other implementations and features not expressly mentioned or shown. It is understood that in the development of any such implementation or embodiment, numerous implementation-specific decisions can be made. These decisions will depend on a variety of factors, including, for example, specific requirements of a particular application, business-related considerations, as well as

[0047] Various implementations have been described in detail herein with reference to the accompanying drawings and graphics. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein can be practiced without these specific details. In some instances, well-known methods, procedures, components, circuits, and networks have not been described in detail in order to avoid unnecessarily obscuring aspects of the embodiments.

[0048] It should also be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

[0049] The terminology used in the description of the present disclosure provided herein is for the purpose of describing particular implementations only and is not intended to limit the present disclosure provided herein. As used in the description of the disclosure and the appended claims herein, the singular forms "a", "an" and "the" are intended to include plural forms as well, unless the context clearly indicates otherwise. As used herein, the term "and / or" means and encompasses any and all possible combinations of one or more of the associated listed items. As used in this specification, the terms "comprises", "comprising", "includes", "including", "has", "having" or variants thereof are not limited to a situation wherein, after the use of the terms "comprises", "comprising", "includes", "including", "has", "having" or variants thereof, the listed features are essential, mandatory or one of only a few possible features. Rather, these terms are intended to cover both the situation where features are essential, mandatory or one of only a few possible features, as well as the situation where features are not essential, mandatory or one of only a few possible features.

[0050] As used herein, the term “if’ can be interpreted to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if determined” or “if [stated condition or event] is detected” can be interpreted to mean “upon determining” or “in response to determining” or “upon detecting [stated condition or event]” or “in response to detecting [stated condition or event],” depending on the context. The terms “upper” and “lower,” “up” and “down,” “above” and “below,” and other like terms can be used in conjunction with the various techniques described herein; some implementations can use the terms “up” and “down,” “upper” and “lower,” “above” and “below,” and other like terms in connection with the various techniques described herein.

[0051] While the foregoing has described implementation of various techniques described herein, other and further implementations can be devised by those skilled in the art utilizing the disclosure provided herein, which can be determined by the appended claims.

[0052] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. An integrated circuit comprising: a memory circuit having an array of bit cells and bit lines coupled to columns of the bit cells; and a column decoder circuit coupled to the bit cells via the bit lines, the column decoder circuit having read logic coupled to an output node, the column decoder circuit having selection logic coupled between a voltage source and the read logic, wherein an enable signal activates the selection logic to pass the voltage source to the read logic, and wherein the bit lines provide a bit line signal that activates the read logic to pass the voltage source from the selection logic to the output node.

2. The integrated circuit of claim 1, wherein: the bit lines are read bit lines, and the bit lines are coupled to the read logic.

3. The integrated circuit of claim 1, wherein: the selection logic comprises a selection transistor, the enable signal comprises a selection activation signal, and the selection activation signal is used to activate a gate of the selection transistor to pass the voltage source to the read logic.

4. The integrated circuit of claim 1, wherein: the read logic comprises a read transistor, the bit lines are coupled to a gate of the read transistor, and the bit lines provide the bit line signal to activate the gate of the read transistor to pass the voltage source from the selection logic to the output node.

5. The integrated circuit of claim 1, further comprising: precharge logic coupled between the voltage source and the read logic; and a precharge activation signal used to activate the precharge logic to pass the voltage source to the read logic, wherein the voltage source is used to precharge the bit lines with the read logic.

6. The integrated circuit of claim 5, wherein: the read logic comprises a read transistor, the precharge logic comprises a precharge transistor, the precharge transistor is coupled between the voltage source and a gate of the read transistor, the precharge activation signal activates a gate of the precharge transistor to pass the voltage source to the gate of the read transistor, and the voltage source precharges the bit lines at the gate of the read transistor.

7. The integrated circuit of claim 1, further comprising: output discharge logic coupled to the output node, wherein the read logic passes the voltage source to the output node to activate the output discharge logic, and wherein the output discharge logic passes an output discharge signal to ground.

8. The integrated circuit of claim 7, wherein: the read logic comprises a read transistor, the output discharge logic comprises an output discharge transistor, the output node is coupled to a gate of the output discharge transistor, the read transistor passes the voltage source to the output node to activate the gate of the output discharge transistor, and the output discharge transistor passes the output discharge signal to ground when activated. the output discharge signal comprises a global data line (GDL) signal.

10. The integrated circuit of claim 1, further comprising:

9. The integrated circuit of claim 7, wherein, ​ ​ an output circuit having a plurality of transistors coupled together in series and arranged in a stack between the output node and ground, wherein the plurality of transistors are activated by the enable signal or the bit line signal.

11. The integrated circuit of claim 1, further comprising: a word line coupled to the row of bit cells; and a word line driver circuit coupled to the bit cells via the word line.

12. The integrated circuit of claim 1, wherein: the memory circuit comprises a multi-port memory, the bit line comprises a full-swing read bit line.

13. A system of circuit components, comprising: a read transistor coupled to an output node; a select transistor coupled between a voltage source and the read transistor; a select activation signal to activate a gate of the select transistor to pass the voltage source as an output signal to the read transistor; and a bit line coupled to a gate of the read transistor, the bit line to provide a bit line signal to activate the gate of the read transistor to pass the output signal from the select transistor to the output node.

14. The system of claim 13, further comprising: a pre-charge transistor coupled between the voltage source and the gate of the read transistor; and a pre-charge activation signal to activate a gate of the pre-charge transistor to pass the voltage source to the gate of the read transistor, wherein the voltage source pre-charges the bit line at the gate of the read transistor.

15. The system of claim 13, further comprising: an output discharge transistor coupled to the output node, wherein the output node is coupled to a gate of the output discharge transistor, wherein the read transistor passes the voltage source to the output node to activate the gate of the output discharge transistor, and the output discharge transistor passes an output discharge signal to ground when activated.

16. The system of claim 13, further comprising: an output circuit having a plurality of transistors coupled together in series and arranged in a stack between the output node and ground, wherein the plurality of transistors are activated by the select activation signal or the bit line signal. the column decoder circuit comprises the read transistor and the select transistor, and wherein the bit line comprises a full-swing read bit line.

18. A method for providing a memory circuit, comprising:

17. The system of claim 13, further comprising a column decoder circuit as part of a multi-port static random access memory (SRAM), wherein, providing an array of bit cells having bit cells arranged into columns and a bit line coupled to the columns of bit cells; and providing a column decoder coupled to the columns of bit cells via the bit line, the column decoder having a read transistor and a select transistor coupled between a voltage source and an output node, wherein the select transistor passes the voltage source to the read transistor when activated, and wherein the bit line is coupled to a gate of the read transistor to activate the gate of the read transistor and pass the voltage source from the select transistor to the output node when the gate of the read transistor is activated.

19. The method of claim 18, further comprising: ​ ​ A bit cell array is provided having bit cells arranged in columns and rows; and A word line is provided coupled to the rows of bit cells.

20. The method of claim 18, wherein, The select transistor is coupled between the voltage source and the read transistor.

21. The method of claim 18, wherein, The read transistor is coupled between the select transistor and the output node.

22. The method of claim 18, wherein, A select activation signal is used to activate the gate of the select transistor to pass the voltage source to the read transistor.

23. The method of claim 18, wherein, The bit line provides a bit line signal to activate the gate of the read transistor to pass the voltage source from the select transistor to the output node.

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