Power converter and method of operating a power converter

Abstract

According to a first aspect of the present disclosure, a power converter is disclosed, comprising: an input configured to receive an input voltage; an output configured to provide an output voltage; a power switch block coupled between the input and the output; and a controller configured to control the power switch block, wherein the controller is configured to open and close a switch included in the power switch block, and wherein the controller is further configured to control a resistance of the power switch block. According to a second aspect of the present disclosure, a corresponding method of operating a power converter is contemplated.

Description

Technical Field

[0001] The present disclosure relates to a power converter. Furthermore, the present disclosure relates to a corresponding method of operating a power converter. Background Art

[0002] Power converters have different uses. For example, a power converter can be used in a near field communication (NFC) device to convert the voltage received from the front-end circuit to a voltage that can be supplied to a secure element included in the device. It is important that the power converter operates reliably. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a power converter is disclosed, comprising: an input configured to receive an input voltage; an output configured to provide an output voltage; a power switch block coupled between the input and the output; and a controller configured to control the power switch block, wherein the controller is configured to open and close a switch included in the power switch block; wherein the controller is further configured to control the resistance of the power switch block.

[0004] In an embodiment, the controller is configured to control the resistance by controlling an on-state resistance of a switch included in the power switch block.

[0005] In an embodiment, the controller is configured to increase the resistance if the load on the output is low and to decrease the resistance if the load on the output is high.

[0006] In an embodiment, the controller is configured to determine that the load on the output is low by determining that the output voltage exceeds a high threshold, and to determine that the load on the output is high by determining that the output voltage is below a low threshold.

[0007] In an embodiment, the controller includes a finite state machine configured to enable or disable the power switch block in response to a digital control signal.

[0008] In an embodiment, the controller is configured to control the resistance of the power switching block using pulse width modulation.

[0009] In an embodiment, the controller includes a set-reset gate configured to provide a pulse width modulated clock.

[0010] In an embodiment, the controller is configured to initiate an increase in resistance if the output voltage exceeds a target set point after half a switching period.

[0011] In an embodiment, a near field communication device comprises a power converter of the kind set forth.

[0012] In an embodiment, the power converter is configured to provide an output voltage to a secure element included in the near field communication device.

[0013] In an embodiment, the near field communication device further comprises a front-end circuit configured to provide an input voltage.

[0014] According to a second aspect of the present disclosure, a method of operating a power converter is contemplated, the power converter comprising an input, an output, a controller, and a power switching block coupled between the input and the output, the method comprising: receiving an input voltage at the input; providing an output voltage at the output; controlling the power switching block by the controller by opening and closing a switch in the power switching block; and controlling a resistance of the power switching block by the controller.

[0015] In an embodiment, the resistance is controlled by controlling the on-state resistance of switches included in the power switch block.

[0016] In an embodiment, the controller increases the resistance if the load on the output is low and decreases the resistance if the load on the output is high.

[0017] In an embodiment, the controller determines that the load on the output is low by determining that the output voltage exceeds a high threshold, and determines that the load on the output is high by determining that the output voltage is below a low threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Embodiments will be described in more detail with reference to the accompanying drawings, in which:

[0019] Figure 1 An example of a power converter is shown;

[0020] Figure 2 shows an example of a signal timing diagram;

[0021] Figure 3A An illustrative embodiment of a power converter is shown;

[0022] Figure 3B An illustrative embodiment of a method of operating a power converter is shown;

[0023] Figure 3C Another illustrative embodiment of a power converter is shown;

[0024] Figure 4 shows a signal timing diagram;

[0025] Figure 5 Another signal timing diagram is shown;

[0026] Figure 6 Another signal timing diagram is shown;

[0027] Figure 7 Another signal timing diagram is shown;

[0028] Figure 8 The simulation results are shown;

[0029] Figure 9 Another illustrative embodiment of a power converter is shown;

[0030] Figure 10 Another simulation result is shown. DETAILED DESCRIPTION

[0031] Power converters have different uses. For example, a power converter can be used in a near field communication (NFC) device to convert the voltage received from the front-end circuit to a voltage that can be supplied to a secure element included in the device. It is important that the power converter operates reliably.

[0032] Figure 1 An example of a power converter 100 is shown. So-called step-down switching power supplies (SMPSs) are commonly used to power microcontrollers in radio frequency (RF) communication devices, specifically NFC devices. For example, a step-down SMPS can provide power to a secure element (SE). Using an SMPS helps reduce power dissipation and improve power efficiency. Such inductive DC-DC converters are typically used with a fixed switching frequency, which results in user-friendly operation in the case of RF front ends. However, disadvantages of inductive SMPSs are bill-of-material (BOM) cost and footprint, as they require an external coil. Using a switched-capacitive power converter (SCPC) instead of an SMPS offers improvements, as SCPCs use external capacitors. SCPCs can use "flying capacitors." These capacitors charge from the input voltage and then discharge to the load, thereby providing charge transfer and a constant output voltage.

[0033] Figure 11 shows a basic DC-DC converter of this type. The power converter 100 includes an input 102 through which an input voltage VIN is received, and an output 104 through which an output voltage VOUT is provided to an external device (not shown) represented by a capacitor CLOAD. The power converter includes a power switch block 106, which includes a plurality of switches S1, S2, S3, and S4 coupled to a flying capacitor CSW of the type described. In addition, the power converter 100 includes a comparator 108, an AND gate 110, and an inverter 112. More specifically, the power switch block 106 includes a first set of switches S1 and S2, a second set of switches S3 and S4, and a flying capacitor CSW. The first set of switches S1 and S2 includes a switch S1 coupled between the output 104 and the flying capacitor CSW, and a switch S2 coupled between the flying capacitor CSW and a ground device. The second set of switches S3, S4 includes a switch S3 coupled between the input 102 and the flying capacitor CSW, and a switch S3 coupled between the flying capacitor CSW and the output 104. In operation, the switches are controlled such that at a first moment, the first set of switches S1, S2 is closed and the second set of switches S3, S4 is opened, and at a second moment, the first set of switches S2, S2 is opened and the second set of switches S3, S4 is closed. These steps can then be repeated. Thus, the first set of switches S1, S2 and the second set of switches S3, S4 are alternately closed.

[0034] More specifically, the basic DC-DC converter 100 integrates switches and oscillators so that switches S1, S2 and S3, S4 operate alternately. The configuration shown divides the input voltage by two. This DC-DC converter 100 operates in two phases sequenced by a switch clock. In the first half cycle (storage phase), closing S1 and S2 and opening S3 and S4 will charge the flying capacitor (CSW) to VOUT. In the second half, closing switches S3 and S4 and opening switches S1 and S2 (loading phase). This action connects the negative terminal of CSW to the output 104 and the positive terminal of CSW to the input 102. If the voltage across CLOAD is less than the voltage across CSW, charge flows from CSW to CLOAD. The storage phase and the loading phase occur alternately, thereby raising the output voltage VOUT to its target value (VREF). When VOUT reaches VREF, the switching clock is stopped, and the DC-DC converter 100 then remains in the storage phase. Once VOUT becomes lower than VREF, DC-DC converter 100 resumes pumping, alternating between storage and loading phases until VOUT becomes higher than VREF.

[0035] Figure 2An example of a signal timing diagram 200 is shown. The output voltage VOUT of the DC-DC converter 100 should be regulated within a voltage window by using the voltage hysteresis (HYST) on the comparator 108. The output voltage VOUT is regulated between VREF and VREF+HYST. The threshold voltage for the rising edge of VOUT is VREF+HYST, and the threshold voltage for the falling edge is VREF. Figure 2 This operation of converter 100 is shown in Figure 1. During startup, converter 100 pumps energy from VIN to VOUT by alternately closing switches as explained above, causing output voltage VOUT to rise to VREF + HYST. Converter 100 then stops pumping and remains in a storage state. Output voltage VOUT then decreases linearly due to the output load current, reaching VREF, after which converter 100 resumes raising output voltage VOUT to VREF + HYST. However, a disadvantage of this basic capacitor DC-DC converter 100 is that the switching frequency is not fixed. Generally speaking, the switching frequency in an inverter or converter is the rate at which the switching device is turned on and off. More specifically, in this case, the switching frequency is the rate at which the power switch block is turned on (i.e., pumping energy) and off (i.e., not pumping energy). This, in turn, can generate subharmonic noise, adversely affecting RF performance. More specifically, once VOUT reaches the upper threshold of the hysteresis window, the power converter stops pumping. This asynchronous operation results in low-frequency noise (i.e., below the frequency of the input clock) on VOUT, which depends on the load. This frequency noise can be seen in the data bandwidth of the RF system. For example, for NFC applications, the data bandwidth can be from 100KHz to 1MHz (at a 13.56MHz carrier frequency); this noise within 100KHz to 1MHz can degrade RF performance.

[0036] Figure 3AAn illustrative embodiment of a power converter 300 is shown. The power converter 300 includes an input 304, an output 306, a power switch block 302, and a controller 308. The input 304 is configured to receive an input voltage VIN, for example, from an RF front-end circuit (not shown). The output is configured to provide an output voltage, for example, to a microcontroller (not shown). The power switch block 302 is coupled between the input 304 and the output 306. The controller 308 is configured to control the power switch block 302, specifically by opening and closing switches therein. According to the present disclosure, the controller 308 is also configured to control the resistance of the power switch block 302. The inventors have discovered that by controlling the resistance of the power switch block, the aforementioned subharmonic noise can be reduced. Thus, the aforementioned disadvantages are alleviated in this manner. In an embodiment, the controller is configured to control the resistance by controlling the on-state resistance of the switches included in the power switch block. In this manner, the resistance of the power switch block can be easily controlled. For example, the on-state resistance of an individual switch may be controlled by controlling the gate-to-source voltage (VGS) of a field-effect transistor (FET) included in the switch.

[0037] Figure 3B An illustrative embodiment of a method 310 of operating a power converter of the type described is shown. Method 310 includes: receiving an input voltage at an input at 312; providing an output voltage at an output at 314; controlling a power switch block by opening and closing switches in the power switch block at 316; and controlling a resistance of the power switch block at 318. As mentioned above, by controlling the resistance of the power switch block, the above-mentioned disadvantages are alleviated.

[0038] Figure 3CAnother illustrative embodiment of a power converter 320 is shown. Power converter 320 includes an input 322, an output 324, a power switch matrix 326 (i.e., a power switch block of the type described) coupled between input 322 and output 324, comparators 328, 330, AND gates 332, 338, a finite state machine (FSM) 334, a set-reset gate 336, and an inverter 340. Power converter 320 is an example of a practical and efficient implementation of the power converter disclosed herein. Power converter 320 is controlled using pulse width modulation (PWM). In addition, power switch matrix 326 is divided into several components to digitally control resistance (RON). Each component may include several switches coupled in parallel. Each switch may, in turn, include several field-effect transistors (FETs) coupled in parallel. For example, first switch S1 may be composed of several FETs coupled in parallel. The on-state resistance (RON) of the switch S1 can then be controlled by controlling the number of FETs that are enabled. The other switches S2, S3, S4 can similarly be composed of several FETs coupled in parallel and can be controlled in the same manner. The on-state resistance (RON) of the power switch is adjusted to keep the switching frequency fixed. Specifically, RON is increased at light loads to avoid pulse skipping and then decreased at high loads to avoid overload. Therefore, in a practical and effective embodiment, the controller is configured to increase the resistance when the load on the output is low and to decrease the resistance when the load on the output is high, and the controller includes Figure 3CSpecific components are shown, namely, comparators 328, 330, AND gates 332, 338, finite state machine (FSM) 334, set-reset gate 336, and inverter 340. Thus, the output voltage VOUT is maintained within the voltage window. If the low threshold is triggered, RON is reduced to allow for higher current capability. If the high threshold is triggered, switching activity is stopped to avoid overshoot voltage. Therefore, in a practical and effective embodiment, the controller is configured to determine that the load on the output is low by determining that the output voltage exceeds the high threshold, and to determine that the load on the output is high by determining that the output voltage is below the low threshold. Resistance RON is digitally increased using the main loop comparator. Advantageously, this operation can be triggered if the output voltage is still above the target set point after half a switching cycle. The resistance of the switches in the power switch matrix 326 is configurable because it is individually controlled by a clock provided via a digital bus. The two comparators 328 and 330 sense VOUT relative to the output voltage set point (V REF ) and the undervoltage threshold (V TH_UHV ), respectively. The set-reset gate 336 is configured to provide a PWM clock. A reset signal is provided by the VOUT sense comparator 328. Set is ensured at each clock cycle. The finite state machine 334 is configured to enable or disable the power switch matrix 326 in response to digital inputs RON_INC and RON_ENC. Specifically, the field-effect transistors (FETs) forming each switch can be enabled during the on-state of the switch. In this case, the finite state machine 334 can control the number of FETs enabled during the on-state.

[0039] Figure 4 400 is shown. Specifically, when Figure 3C , a signal timing diagram 400 for the power converter 320 is shown in FIG. 1 . More specifically, the PWM duty cycle is shown as being modulated to regulate the output voltage VOUT at the output voltage set point VREF. The frequency of the PWM duty cycle is fixed by a reference clock.

[0040] Figure 5 Another signal timing diagram 500 is shown. Specifically, it shows that at low load current, the output voltage VOUT remains above VREF after half a switching cycle. Subsequently, the resistance of the power switch is increased. More specifically, it shows that if the output voltage VOUT is still above the output voltage set point VREF after half a switching cycle, RON_INC is triggered.

[0041] Figure 6Another signal timing diagram 600 is shown. Specifically, it shows that under high load current, the output voltage VOUT drops below the undervoltage threshold voltage (VTH_UV). Subsequently, the resistance of the power switch is reduced. More specifically, it shows that RON_DEC is triggered if the output voltage VOUT drops below the undervoltage threshold voltage (VTH_UV).

[0042] Figure 7 Another signal timing diagram 700 is shown. Specifically, it illustrates transient load regulation for a power converter of the type described. Output voltage VOUT is plotted against a load current step. Since RON_DEC is triggered when output voltage VOUT falls below the undervoltage threshold voltage, resistance RON is reduced after the load ramp-up step. Resistance RON is increased after the load ramp-down edge to return to the initial RON value.

[0043] Figure 8 Simulation results 800 are shown. Due to the symmetry of the power converter's topology, two values ​​of the PWM duty cycle are possible. Figure 8 The output voltage VOUT versus PWM duty cycle, obtained from an open-loop simulation, is plotted for three load currents: 50mA, 100mA, and 150mA. The other conditions are: VIN = 2.2V; switching frequency = 3.87MHz; CSW = 400nF; COUT = 1μF; and RDSON is fixed at 350mΩ, where RDSON is the resistance of the power switch during the on state.

[0044] Using two duty cycle set points to regulate at 900mV at different load levels:

[0045] 5% and 95% duty cycle for 50mA load;

[0046] 10% and 90% duty cycle for a 100mA load;

[0047] 17% and 83% duty cycle for a 150mA load.

[0048] Figure 9 Another illustrative embodiment of a power converter 900 is shown. To avoid instability of the power converter, a reset can be forced at half the cycle. It should be noted that a PWM duty cycle higher than 50% cannot be used to regulate the output voltage VOUT. Figure 9In the power converter 900 shown in FIG, an additional AND gate 902 is introduced to facilitate reset. In a practical embodiment, the system can be implemented using power switches divided into four sections: Section 3 with R = 4 x 350 mΩ; Section 2 with R = 4 x 350 mΩ; Section 1 with R = 8 x 350 mΩ; and Section 0 with R = 16 x 350 mΩ. In this example, Section 3 consists of four switches coupled in parallel, and the on-state resistance of each switch is 1.4 Ω. The partitioning of the power switch matrix is ​​not linear to maximize the PWM load range.

[0049] Figure 10 Another simulation result 1000 is shown. Ideal components have been used. The output voltage VOUT is plotted against the transient load response (load from 0mA to 150mA with a 200us slope). Figure 10 (referred to as VDIG in this example). Other cases are: VIN = 2.2V; VOUT = 900mV, switching frequency = 3.87MHz; CFLY = 400nF; COUT = 1µF; fixed maximum RDSON at 350mΩ, VTH_UV = 890mV. In this example, maximum RDSON is the maximum RDSON at various process-voltage-temperature (PVT) conditions. In addition to LOAD and VOUT, eight other internal signals are plotted to illustrate the power converter's behavior:

[0050] CLKPWM: PWM switching frequency

[0051] BUCK_PWM_FREQUENCY: Switching frequency extracted from the PWM clock

[0052] EN_RON<5∶1>: Enable for each component (Note: Component 0 is always on)

[0053] RON_DEC: RON decreases

[0054] RON_INC: RON increase

[0055] Load current and current consumption

[0056] It should be noted that the above embodiments have been described with reference to different subject matters. Specifically, some embodiments may have been described with reference to method-type claims, while other embodiments may have been described with reference to apparatus-type claims. However, those skilled in the art will appreciate from the foregoing that, unless otherwise indicated, any combination of features relating to different subject matters, in addition to any combination of features belonging to one type of subject matter, and in particular, any combination of features from method-type claims with features from apparatus-type claims, are also considered disclosed by this document.

[0057] In addition, it should be noted that the drawings are schematic. Similar or identical elements are represented by the same reference numerals in different figures. In addition, it should be noted that in order to provide a concise description of the illustrative embodiments, implementation details that are customary practices of technicians may not be described. It should be understood that in the development process of any such implementation, as in any engineering or design project, a large number of implementation-specific decisions must be made in order to achieve the developer's specific goals, such as complying with system-related and business-related constraints, and different implementations may have different specific goals. In addition, it should be understood that such development work may be complex and time-consuming, but is nothing more than a routine task for those skilled in the art to carry out design, manufacturing and production.

[0058] Finally, it should be noted that the skilled person will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in the claim. The indefinite article "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The measures recited in the claims may be implemented by means of hardware comprising several different elements and / or by means of a suitably programmed processor. In a device claim listing several means, several of these means may be implemented by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0059] List of reference numerals

[0060] 100 Power Converters

[0061] 102 Input

[0062] 104 Output

[0063] 106 power switch block

[0064] 108 Comparator

[0065] 110 AND Gate

[0066] 112 Inverter

[0067] 200 Signal Timing Diagram

[0068] 300 Power Converter

[0069] 302 power switch block

[0070] 304 Input

[0071] 306 Output

[0072] 308 Controller

[0073] 310 Method of operating a power converter

[0074] 312 receives input voltage at input

[0075] 314 provides output voltage at output

[0076] 316 Controls the power switch block by alternately closing the switches in the power switch block

[0077] 318 Controls the resistance of the power switch block

[0078] 320 Power Converter

[0079] 322 Input

[0080] 324 output

[0081] 326 Power Switch Matrix

[0082] 328 Comparator

[0083] 330 Comparator

[0084] 332 AND Gate

[0085] 334 Finite State Machine

[0086] 336 Set-Reset Gate

[0087] 338 AND Gate

[0088] 340 Inverter

[0089] 400 Signal Timing Diagram

[0090] 500 Signal Timing Diagram

[0091] 600 Signal Timing Diagram

[0092] 700 Signal Timing Diagram

[0093] 800 simulation results

[0094] 900 Power Converter

[0095] 1000 simulation results

Claims

1. A power converter, characterized in that: include: an input configured to receive an input voltage; an output configured to provide an output voltage; a power switch block coupled between the input and the output; A controller, the controller comprising: a comparator configured to compare the output voltage with a reference voltage to generate a comparison result; a first logic circuit configured to receive a clock signal having a fixed frequency and the comparison result and provide a pulse width modulation signal having the fixed frequency; a power switch resistance circuit configured to provide a resistance control signal for controlling a resistance of the power switch block in response to detecting a change in the output voltage, the power switch resistance circuit including a finite state machine configured to open or close a switch in response to detecting a change in the output voltage; and A second logic circuit has a first input for receiving the pulse width modulated signal, a second input for receiving the resistance control signal, and an output for providing a switching control signal to open and close switches of the power switching block at the fixed frequency.

2. The power converter according to claim 1, wherein: The power switch block includes a plurality of switches coupled in parallel, and wherein the controller is configured to control the resistance by controlling how many of the plurality of switches coupled in parallel are in an on-state.

3. The power converter according to claim 1 or 2, characterized in that: The controller is configured to increase the resistance if the load on the output is low and to decrease the resistance if the load on the output is high.

4. The power converter according to claim 3, wherein: The controller is configured to determine that the load on the output is low by determining that the output voltage exceeds a high threshold, and to determine that the load on the output is high by determining that the output voltage is below a low threshold.

5. The power converter according to claim 1, wherein: The second logic circuit includes an AND gate logic function.

6. The power converter according to claim 5, characterized in that The first logic circuit includes a set-reset gate configured to provide the pulse width modulated signal.

7. The power converter according to claim 1, wherein: The controller is configured to initiate an increase in the resistance if the output voltage exceeds a target set point after half a switching period.

8. A near field communication device, characterized in that: Comprising a power converter according to any one of claims 1 to 7.

9. A method of operating a power converter, the power converter comprising an input, an output, a controller, and a power switch block coupled between the input and the output, characterized in that: The method comprises: receiving an input voltage at the input; providing an output voltage at the output; comparing the output voltage with a reference voltage to generate a comparison result; receiving a clock signal with a fixed frequency and the comparison result through a first logic circuit, and providing a pulse width modulation signal with the fixed frequency; In response to detecting a change in the output voltage, providing a resistance control signal for controlling a resistance of the power switch block through a power switch resistance circuit; receiving the pulse width modulation signal at a first input of a second logic circuit, receiving the resistance control signal at a second input of the second logic circuit, and providing a switching control signal at an output of the second logic circuit to open and close switches of the power switching block at the fixed frequency, Wherein, if the output voltage exceeds a target set point after half a switching period, the controller initiates an increase in the resistance.

Images