Semiconductor device including a data storage material pattern and method of manufacturing the same

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a base structure including a semiconductor substrate; a first conductive structure disposed on the base structure and extending in a first direction, the first conductive structure including a lower layer, and at least one of the lower layers including carbon; a data storage material pattern disposed on the first conductive structure. The semiconductor device further includes an intermediate conductive pattern disposed on the data storage material pattern and including an intermediate layer, at least one of the intermediate layers including carbon; a switching material pattern disposed on the intermediate conductive pattern; and a switching upper electrode pattern disposed on the switching material pattern and including carbon. The semiconductor device further includes a second conductive structure disposed on the switching upper electrode pattern and extending in a second direction intersecting the first direction; and a hole spacer disposed on a side surface of the data storage material pattern.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2019-0067441, filed on June 7, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The disclosure relates to a semiconductor device including a pattern of data storage material. Background Technology

[0003] To achieve high performance and low power consumption in semiconductor devices such as memory devices, next-generation memory devices such as phase-change random access memory (PRAM) and resistive random access memory (RRAM) have been developed. Such next-generation memory devices can have a resistance value that changes according to current or voltage, and are formed using data storage materials that can maintain the resistance value even when the current or voltage supply is interrupted. Summary of the Invention

[0004] According to an embodiment, a semiconductor device includes: a substrate structure including a semiconductor substrate; a first conductive structure disposed on the substrate structure and extending in a first direction, the first conductive structure including lower layers, and at least one of the lower layers including carbon; and a data storage material pattern disposed on the first conductive structure. The semiconductor device further includes: an intermediate conductive pattern disposed on the data storage material pattern and including an intermediate layer, at least one of the intermediate layers including carbon; a switching material pattern disposed on the intermediate conductive pattern; and a switch upper electrode pattern disposed on the switch material pattern and including carbon. The semiconductor device further includes: a second conductive structure disposed on the switch upper electrode pattern and extending in a second direction intersecting the first direction; and a via spacer disposed on a side surface of the data storage material pattern. The side surface of the data storage material pattern is disposed on the entire side surface of the via spacer.

[0005] According to an embodiment, a semiconductor device includes: a substrate structure including a semiconductor substrate; a first conductive structure disposed on the substrate structure and extending in a first direction, the first conductive structure including lower layers, and at least one of the lower layers including carbon; and a data storage material pattern disposed on the first conductive structure. The semiconductor device further includes: an intermediate conductive pattern disposed on the data storage material pattern and including intermediate layers, at least one of the intermediate layers including carbon; a switching material pattern disposed on the intermediate conductive pattern; and a switching upper electrode pattern disposed on the switching material pattern and including carbon. The semiconductor device further includes: a second conductive structure disposed on the switching upper electrode pattern and extending in a second direction intersecting the first direction. The width of the at least one intermediate layer including carbon is greater than the width of the switching upper electrode pattern.

[0006] According to an embodiment, a method of manufacturing a semiconductor device includes the steps of: forming a substrate structure including a semiconductor substrate; forming a first conductive structure on the substrate structure, the first conductive structure extending in a first direction, the first conductive structure including lower layers, and at least one of the lower layers including carbon; and forming an interlayer insulating layer on the first conductive structure. The method further includes the steps of: forming a hole through the interlayer insulating layer; forming a hole spacer on the inner wall of the hole; and forming a data storage material pattern on the first conductive structure and the hole spacer by filling the hole with a data storage material. The method further includes the steps of: forming an intermediate conductive pattern on the data storage material pattern, the intermediate conductive pattern including an intermediate layer, and at least one of the intermediate layers including carbon; forming a switching material pattern on the intermediate conductive pattern; and forming a switch upper electrode pattern on the switch material pattern. The method further includes: forming a second conductive structure on the switch upper electrode pattern, the second conductive structure extending in a second direction intersecting the first direction. Attached Figure Description

[0007] Figure 1 This is a plan view of a semiconductor device according to an embodiment.

[0008] Figure 2 It shows Figure 1 Semiconductor devices along respectively Figure 1 The sectional view taken by lines I-I' and II-II'.

[0009] Figure 3 yes Figure 2 Semiconductor devices made of Figure 2 A magnified view of the portion indicated by 'A' in the image.

[0010] Figure 4 yes Figure 3 A partially enlarged view of a modified example of a semiconductor device.

[0011] Figure 5 yes Figure 3 A partially enlarged view of a modified example of a semiconductor device.

[0012] Figure 6 yes Figure 3 A partially enlarged view of a modified example of a semiconductor device.

[0013] Figure 7 yes Figure 2 A cross-sectional view of a modified example of a semiconductor device.

[0014] Figure 8 yes Figure 2 A cross-sectional view of a modified example of a semiconductor device.

[0015] Figure 9 yes Figure 2 A cross-sectional view of a modified example of a semiconductor device.

[0016] Figure 10 yes Figure 2 A cross-sectional view of a modified example of a semiconductor device.

[0017] Figure 11A This is a cross-sectional view of a modified example of a semiconductor device according to an embodiment.

[0018] Figure 11B This is a cross-sectional view of a modified example of a semiconductor device according to an embodiment.

[0019] Figure 12 This is a cross-sectional view of a modified example of a semiconductor device according to an embodiment.

[0020] Figure 13 This is a cross-sectional view of a modified example of a semiconductor device according to an embodiment.

[0021] Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 and Figure 25 This is a cross-sectional view of a stage in a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0022] Throughout this disclosure, directional terms such as “upper,” “middle,” and “lower” may be used to describe the relationship between one element or feature and another element or feature, and embodiments may not be limited by these terms. Therefore, these terms such as “upper,” “middle,” and “lower” may be replaced by other terms such as “first,” “second,” and “third” to describe elements and features.

[0023] Figure 1 This is a plan view of a semiconductor device according to an embodiment, and Figure 2 It shows Figure 1 Semiconductor devices along respectively Figure 1 The sectional view taken by lines I-I' and II-II'.

[0024] Reference Figure 1 and Figure 2 The first conductive structure 12 can be disposed on the substrate structure 3.

[0025] In one embodiment, the substrate structure 3 may include a semiconductor substrate 6 and a circuit region 9 disposed on the semiconductor substrate 6. In another embodiment, the semiconductor substrate 6 may be formed of a semiconductor material (e.g., silicon). The circuit region 9 may be a region in which circuitry for driving memory cells is disposed.

[0026] In an embodiment, the first conductive structure 12 may include multiple layers 14, 16, and 18. The multiple layers 14, 16, and 18 may be referred to as lower layers. For example, the first conductive structure 12 may include a first lower layer 14, a second lower layer 16 disposed on the first lower layer 14, and a third lower layer 18 disposed on the second lower layer 16. Any layer or any combination of the multiple layers 14, 16, and 18 may include carbon. For example, the second lower layer 16 may include a carbon material layer (e.g., a carbonaceous material) or a material layer comprising carbon. In an embodiment, the material layer comprising carbon may be, for example, a material layer comprising a metallic element (such as tungsten (W)) and carbon (C). In an embodiment, the material layer comprising carbon may include other metallic elements, such as titanium (Ti), tantalum (Ta), ruthenium (Ru), etc., other than W. In an embodiment, the material layer comprising carbon may also include, for example, nitrogen (N) or boron (B), other than carbon and metallic elements. In an embodiment, the first lower layer 14 may be formed of a conductive material such as tungsten. In embodiments, the third lower layer 18 may be formed of a conductive material including, for example, W, TiN, TiAlN, TaN, WN, MoN, TiSiN, TiCN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TaSiN, TaAlN, TiON, TiAlON, WON, TaON, or combinations thereof. As used herein, the term "or" is not an exclusive term; for example, "A or B" would include A, B, or A and B.

[0027] The side or lateral surfaces of the plurality of layers 14, 16, and 18 of the first conductive structure 12 may be aligned with each other (e.g., coplanar, collinear, or otherwise continuous). The plurality of first conductive structures 12 may be included in a semiconductor device. The first conductive structure 12 may be in the form of a line or linear structure extending in a first direction X. The first direction X may be parallel to the upper surface 6s of the semiconductor substrate 6.

[0028] The gap-filling insulating pattern 27 can be disposed on the side surface of the first conductive structure 12. The gap-filling insulating pattern 27 can be formed of an insulating material (e.g., silicon oxide).

[0029] A buffer layer 21 may be disposed on the first conductive structure 12. In an embodiment, the buffer layer 21 may comprise one or both of a metal oxide (e.g., AlO) and a metal nitride (e.g., AlN). In an embodiment, the buffer layer 21 may be formed of an insulating material, a semiconductor material, or a metallic material. The side surface of the buffer layer 21 may be aligned with the side surface of the first conductive structure 12. A gap-filling insulating pattern 27 may extend to the side surface of the buffer layer 21 (e.g., it may be disposed on the side surface of the buffer layer 21).

[0030] An interlayer insulating layer 30 may be disposed on the buffer layer 21 and the gap-filling insulating pattern 27. The interlayer insulating layer 30 may have a thickness greater than the thickness of the buffer layer 21 (e.g., the thickness in the vertical direction Z perpendicular to the first direction X). The interlayer insulating layer 30 may be formed of an insulating material (e.g., SiO, SiN, SiCN, or SiON).

[0031] An etch stop layer 33 may be disposed on the interlayer insulating layer 30. The etch stop layer 33 may have a thickness smaller than that of the interlayer insulating layer 30 (thickness in the vertical direction Z). The etch stop layer 33 may be formed of an insulating material (e.g., AlO or AlN).

[0032] In one embodiment, a planarization stop layer 36 may be disposed on the etch stop layer 33. The planarization stop layer 36 may be formed of an insulating material (e.g., silicon nitride).

[0033] The hole 40 can penetrate the planarization stop layer 36, the etch stop layer 33, the interlayer insulating layer 30 and the buffer layer 21, and can expose the first conductive structure 12.

[0034] A data storage material pattern 45 may be disposed in the aperture 40. In an embodiment, the data storage material pattern 45 may be formed of a chalcogenide phase change memory material capable of changing the phase from an amorphous phase with high resistivity to a crystalline phase with low resistivity or from a crystalline phase to an amorphous phase, depending on the temperature and time heated by an applied current. In an embodiment, the data storage material pattern 45 may be formed of a phase change memory material such as a chalcogenide material (including, for example, germanium (Ge), antimony (Sb), and / or tellurium (Te)). In an embodiment, the data storage material pattern 45 may be formed of a phase change memory material including one or both of Te and Se, and any one or any combination of Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O, N, and In. In an embodiment, the data storage material pattern 45 may be formed by replacing the phase change material with a data storage material capable of storing data in another manner. The height of the data storage material pattern 45 can be kept constant throughout the semiconductor device due to the buffer layer 21, the etch stop layer 33 and the planarization stop layer 36, thereby improving the distribution of the semiconductor device.

[0035] The hole spacer 42 may be disposed between the data storage material pattern 45 and the interlayer insulating layer 30. In an embodiment, the hole spacer 42 may be disposed between the data storage material pattern 45 and the etch stop layer 33, and between the data storage material pattern 45 and the planarization stop layer 36. The hole spacer 42 may be spaced apart from the first conductive structure 12. The hole spacer 42 may be formed of an insulating material (e.g., silicon oxide or silicon nitride). The side surfaces of the data storage material pattern 45 may be disposed on the entire side surface of the hole spacer 42, and the bottom surface of the hole spacer 42 may be higher than the bottom surface of the data storage material pattern 45.

[0036] In one embodiment, the width of the data storage material pattern 45 (width in the second direction Y) may be smaller than the width of the first conductive structure 12 (width in the second direction Y). The second direction Y may be parallel to the upper surface 6s of the semiconductor substrate 6. The second direction Y may be perpendicular to the first direction X.

[0037] In an embodiment, the data storage material pattern 45 may include a portion extending at the same level as the buffer layer 21 (e.g., at the same distance from the semiconductor substrate 6 in the vertical direction Z) in a direction parallel to the upper surface 6s of the semiconductor substrate 6. For example, the data storage material pattern 45 may also include a portion extending between the lower surface of the hole spacer 42 and the upper surface of the first conductive structure 12.

[0038] An intermediate conductive pattern 48 may be disposed on a data storage material pattern 45. The intermediate conductive pattern 48 may include multiple layers 51 and 54. The multiple layers 51 and 54 may be referred to as intermediate layers. For example, the intermediate conductive pattern 48 may include a first intermediate layer 51 and a second intermediate layer 54 disposed on the first intermediate layer 51. One or both of the multiple layers 51 and 54 of the intermediate conductive pattern 48 may include carbon. In an embodiment, the second intermediate layer 54 may include a carbon material layer or a material layer comprising carbon. The first intermediate layer 51 may be formed of a conductive material including, for example, W, TiN, TiAlN, TaN, WN, MoN, TiSiN, TiCN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TaSiN, TaAlN, TiON, TiAlON, WON, TaON, or combinations thereof. The side surfaces of the multiple layers 51 and 54 of the intermediate conductive pattern 48 may be aligned (e.g., self-aligned). The intermediate conductive pattern 48 may have a width (width in the second direction Y) greater than the width (width in the second direction Y) of the data storage material pattern 45.

[0039] In an embodiment, the second intermediate layer 54 and the second lower layer 16, which may be formed of a carbon material layer or a material layer including carbon, may be spaced apart from the data storage material pattern 45.

[0040] A switching material pattern 57 may be disposed on an intermediate conductive pattern 48. A switch upper electrode pattern 60 may be disposed on a switching material pattern 57. The switch upper electrode pattern 60, the switching material pattern 57, and the intermediate conductive pattern 48 may constitute a switching device. For example, the switch upper electrode pattern 60, the switching material pattern 57, and the intermediate conductive pattern 48 may constitute a bidirectional threshold switch (OTS) device. In an embodiment, the switching material pattern 57 may be formed of a chalcogenide material different from the chalcogenide material of the data storage material pattern 45. In an embodiment, the data storage material pattern 45 may be formed of a phase change memory material (e.g., an alloy of Ge, Sb, and / or Te) capable of changing the phase from a crystalline phase to an amorphous phase or from an amorphous phase to a crystalline phase, and the switching material pattern 57 may be formed of a chalcogenide OTS material capable of maintaining an amorphous phase during operation of the semiconductor device. In embodiments, the switch material pattern 57 may be formed from an alloy material comprising, for example, two or more of As, S, Se, Te, and Ge, or from additional elements (e.g., Si, N, etc.) capable of maintaining an amorphous phase at higher temperatures, in addition to the alloy material. In embodiments, the switch material pattern 57 may be formed from an alloy material comprising Te, As, Ge, and Si; an alloy material comprising Ge, Te, and Pb; an alloy material comprising Ge, Se, and Te; an alloy material comprising Al, As, and Te; an alloy material comprising Se, As, Ge, and Si; an alloy material comprising Se, As, Ge, and C; an alloy material comprising Se, Te, Ge, and Si; an alloy material comprising Ge, Sb, Te, and Se; an alloy material comprising Ge, Bi, Te, and Se; an alloy material comprising Ge, As, Sb, and Se; an alloy material comprising Ge, As, Bi, and Te; and an alloy material comprising Ge, As, Bi, and Se. The switch upper electrode pattern 60 may be formed from a carbon material layer or a material layer comprising carbon.

[0041] In this embodiment, the side surfaces of the switch material pattern 57 and the switch upper electrode pattern 60 may be aligned. For example, the switch material pattern 57 and the switch upper electrode pattern 60 may have substantially the same width (width in the second direction Y).

[0042] In one embodiment, in the second direction Y, the width of the intermediate conductive pattern 48 including carbon is greater than the width of the upper electrode pattern 60 of the switch. Furthermore, in the second direction Y and in the region intercepted along line II-II', the width of the lower layers 14, 16, and 18 including carbon is smaller than the width of the intermediate conductive pattern 48 including carbon, and smaller than the width of the upper electrode pattern 60 of the switch.

[0043] In an embodiment, the switch material pattern 57 may have a width (width in the second direction Y) greater than the width (width in the second direction Y) of the data storage material pattern 45.

[0044] In one embodiment, at least a portion of the intermediate conductive pattern 48 may have a width (width in the second direction Y) greater than the width of the switching material pattern 57.

[0045] The second conductive structure 72a can be disposed on the electrode pattern 60 of the switch. The second conductive structure 72a can include a single layer or multiple layers.

[0046] The second conductive structure 72a can take the form of a line or a linear structure extending in the second direction Y.

[0047] In an embodiment, one of the first conductive structure 12 and the second conductive structure 72a may be a word line, while the other of the first conductive structure 12 and the second conductive structure 72a may be a bit line.

[0048] A first gap-filling insulating pattern 69 may be disposed between the second conductive structure 72a and the interlayer insulating layer 30. The first gap-filling insulating pattern 69 may be disposed on a side surface of the switching material pattern 57 (e.g., the surface facing the second direction Y). A second gap-filling insulating pattern 90 may be disposed on the interlayer insulating layer 30, the side surface of the switching material pattern 57 (e.g., the surface facing the first direction X), and the side surface of the second conductive structure 72a (e.g., the surface facing the first direction X). The first gap-filling insulating pattern 69 and the second gap-filling insulating pattern 90 may be formed of an insulating material (e.g., silicon oxide).

[0049] Insulating spacers 66 and 87 may be disposed on the intermediate conductive pattern 48. Insulating spacers 66 and 87 may be superimposed on the intermediate conductive pattern 48 (e.g., may cover the intermediate conductive pattern 48) (e.g., such that a portion of the intermediate conductive pattern 48 is positioned in the vertical direction Z between the insulating spacers 66 and 87 and the semiconductor substrate 6), and may cover the side surface of the switching material pattern 57. Insulating spacers 66 and 87 may be formed of an insulating material (e.g., silicon oxide or silicon nitride).

[0050] Specifically, insulating spacers 66 and 87 may include a first spacer 66 and a second spacer 87. The first spacer 66 may be positioned between the intermediate conductive pattern 48 and the second conductive structure 72a. The first spacer 66 may extend in the vertical direction Z from the upper surface of the intermediate conductive pattern 48 to cover the side surface of the switching material pattern 57 (e.g., the surface facing the second direction Y) and the side surface of the switch upper electrode pattern 60 (e.g., the surface facing the second direction Y). The vertical direction Z may be a direction perpendicular to the upper surface 6s of the semiconductor substrate 6. The first spacer 66 may be positioned in the second direction Y between the side surface of the switching material pattern 57 and the first gap-filling insulating pattern 69, and may also be positioned in the second direction Y between the side surface of the switch upper electrode pattern 60 and the first gap-filling insulating pattern 69.

[0051] The second spacer 87 may extend from the intermediate conductive pattern 48 in the vertical direction Z to cover the side surface of the switch material pattern 57 in the first direction X, the side surface of the switch upper electrode pattern 60 in the first direction X, and the side surface of the second conductive structure 72a in the first direction X. For example, the second spacer 87 may be positioned in the first direction X between the side surface of the switch material pattern 57 and the second gap-filling insulating pattern 90, between the side surface of the switch upper electrode pattern 60 and the second gap-filling insulating pattern 90, and between the side surface of the second conductive structure 72a and the second gap-filling insulating pattern 90.

[0052] The memory cell structure MC can be positioned between the first conductive structure 12 (the first conductive structure 12 extending in the first direction X) and the second conductive structure 72a (the second conductive structure 72a extending in the second direction Y). The memory cell structure MC may include the data storage material pattern 45, the intermediate conductive pattern 48, the switch material pattern 57, and the switch upper electrode pattern 60 as described above.

[0053] In one embodiment, the first conductive structure 12 below the data storage material pattern 45 (e.g., closer to the semiconductor substrate 6 in the vertical Z direction than the data storage material pattern 45) and the intermediate conductive pattern 48 above the data storage material pattern 45 (e.g., farther from the semiconductor substrate 6 in the vertical Z direction than the data storage material pattern 45) may include a carbon material layer or a carbon-containing material layer as described above. In another embodiment, the second lower layer 16 and the second intermediate layer 54 may include a carbon material layer or a carbon-containing material layer. As described above, the second lower layer 16, the second intermediate layer 54, and the switch upper electrode pattern 60, all including a carbon material layer or a carbon-containing material layer, can function as heat barriers during operation of the memory cell structure MC to significantly reduce heat loss generated in the data storage material pattern 45. Therefore, the performance of the semiconductor device including the memory cell structure MC can be improved.

[0054] In this embodiment, the hole spacer 42 in the hole 40 can reduce the width of the data storage material pattern 45. Therefore, the operating current of the semiconductor device, including the memory cell structure MC, can be reduced. Furthermore, the hole spacer 42 prevents the formation of one or more seams in the data storage material pattern 45 during its formation. Therefore, the conductive material or carbon material of the intermediate conductive pattern 48 does not fill such seams during its formation and does not cause bridging between different portions of the data storage material pattern 45 and the intermediate conductive pattern 48.

[0055] In an embodiment, the data storage material pattern 45 may include a portion extending between the lower surface of the hole spacer 42 and the top surface of the first conductive structure 12 (e.g., a portion extending in the vertical direction Z) to increase the contact area between the data storage material pattern 45 and the first conductive structure 12. For example, while operating the memory cell structure MC, the data storage material pattern 45 and the first conductive structure 12 can be in stable contact with each other to help prevent poor contact between the data storage material pattern 45 and the first conductive structure 12 that might otherwise occur due to repeated phase transitions of the data storage material pattern 45 from a crystalline phase to an amorphous phase or from an amorphous phase to a crystalline phase. Therefore, the durability and reliability of the semiconductor device can be improved.

[0056] In the following text, we will refer to... Figure 3 , Figure 4 , Figure 5 and Figure 6 Example of a data storage material pattern 45.

[0057] Figure 3 yes Figure 2 Semiconductor devices made of Figure 2 A magnified view of the portion indicated by 'A' in the image, and Figure 4 , Figure 5 and Figure 6 yes Figure 3 A partially enlarged view of a modified example of a semiconductor device.

[0058] In the implementation method, refer to Figure 3 The data storage material pattern 45a may include a first portion 45a_1 and a second portion 45a_2. The first portion 45a_1 of the data storage material pattern 45a may be defined (e.g., included) by a hole spacer 42, and the second portion 45a_2 of the data storage material pattern 45a may be disposed between the lower surface of the hole spacer 42 and the upper surface of the first conductive structure 12 (e.g., disposed between the lower surface of the hole spacer 42 and the upper surface of the first conductive structure 12 in the vertical direction Z). The first portion 45a_1 of the data storage material pattern 45a may be at the same level as the interlayer insulating layer 30, and the second portion 45a_2 of the data storage material pattern 45a may be at the same level as the buffer layer 21. The second portion 45a_2 of the data storage material pattern 45a may extend from the side surface of the first portion 45a_1 of the data storage material pattern 45a by a distance (e.g., extending outward in the first direction X) that distance is smaller than the thickness of the hole spacer 42 (thickness in the first direction X).

[0059] In the implementation method, refer to Figure 4 The data storage material pattern 45b may include a first portion 45b_1 at the same level as the interlayer insulating layer 30 and a second portion 45b_2 at the same level as the buffer layer 21. The second portion 45b_2 may extend from the side surface of the first portion 45b_1 of the data storage material pattern 45b by a certain distance (e.g., outward in the first direction X), which is greater than the thickness of the hole spacer 42 (thickness in the first direction X). For example, the second portion 45b_2 of the data storage material pattern 45b may be placed between the lower surface of the hole spacer 42 and the upper surface of the first conductive structure 12 (placed between the lower surface of the hole spacer 42 and the upper surface of the first conductive structure 12 in the vertical direction Z), and may also be placed between the lower surface of the interlayer insulating layer 30 and the upper surface of the first conductive structure 12 (placed between the lower surface of the interlayer insulating layer 30 and the upper surface of the first conductive structure 12 in the vertical direction Z).

[0060] In the implementation method, refer to Figure 5The data storage material pattern 45c can extend downward to contact the upper surface of the first conductive structure 12. For example, a first portion of the data storage material pattern 45c at the same level as the interlayer insulating layer 30 can have a width (width in the first direction X) that is the same as the width of a second portion of the data storage material pattern 45c extending downward from the first portion at the same level as the interlayer insulating layer 30 (e.g., towards the semiconductor substrate 6).

[0061] In the implementation method, refer to Figure 6 The data storage material pattern 45d may include a first portion 45d_1 and a second portion 45d_2 below the first portion 45d_1 and having a width greater than that of the first portion 45d_1. The first portion 45d_1 of the data storage material pattern 45d may include a portion at the same level as the interlayer insulating layer 30 and a portion at the same level as a portion of the buffer layer 21a. The second portion 45d_2 of the data storage material pattern 45d may be positioned between the lower surface of the hole spacer 42a and the upper surface of the first conductive structure 12 (e.g., positioned in the vertical direction Z between the lower surface of the hole spacer 42a and the upper surface of the first conductive structure 12). The thickness of the second portion 45d_2 of the data storage material pattern 45d in the vertical direction Z may be smaller than the thickness of the portion of the buffer layer 21a located between the interlayer insulating layer 30 and the first conductive structure 12 in the vertical direction Z. In the buffer layer 21a, the portion between the hole spacer 42a and the first conductive structure 12 (e.g., the portion in the vertical direction Z) can have a thickness smaller than the thickness of the portion of the buffer layer 21a between the interlayer insulating layer 30 and the first conductive structure 12. That is, the hole spacer 42a can be disposed in the top surface of the buffer layer 21a such that the bottom surface of the hole spacer 42a can be lower than the top surface of the buffer layer 21a.

[0062] Figure 7 , Figure 8 , Figure 9 and Figure 10 yes Figure 2 A cross-sectional view of a modified example of a semiconductor device. When referring to respectively... Figure 7 , Figure 8 , Figure 9 and Figure 10 When describing a modified example of a semiconductor device according to an embodiment, only the modified parts of the semiconductor device according to the embodiment will be described. Therefore, even without additional description, the modifications can be understood from the references. Figure 2 Understand the other parts of the description.

[0063] In the implementation method, refer to Figure 7A planarization stop layer (e.g., a lower planarization stop layer) 24 may be disposed between the buffer layer 21 and the interlayer insulating layer 30. The planarization stop layer 24 may be formed of an insulating material (e.g., silicon nitride). The side surfaces of the planarization stop layer 24, the buffer layer 21, and the first conductive structure 12 may be aligned.

[0064] In the implementation method, refer to Figure 8 The first gap-filling insulating pattern 69a and the second gap-filling insulating pattern 90a can extend downward (e.g., in the vertical direction Z) from the portion of the first gap-filling insulating pattern 69a and the second gap-filling insulating pattern 90a covering the side surface of the intermediate conductive pattern 48 (e.g., at the same level as the side surface of the intermediate conductive pattern 48) to sequentially penetrate the planarization stop layer 36 and the etch stop layer 33 to contact the interlayer insulating layer 30.

[0065] In the implementation method, refer to Figure 9 The sequentially stacked etch stop layer 33a and planarization stop layer 36a can extend outward from between the interlayer insulating layer 30 and the intermediate conductive pattern 48 to between the interlayer insulating layer 30 and the second gap-filling insulating pattern 90 and between the interlayer insulating layer 30 and the first gap-filling insulating pattern 69.

[0066] In the implementation method, refer to Figure 10 The flattening stop layer can be omitted. Figure 2 (36). For example, the etch stop layer 33 and the intermediate conductive pattern 48 may be in contact with each other (e.g., in direct contact).

[0067] In the following text, reference will be made to Figure 11A and Figure 11B An example is described in which the multiple memory cell structures MC described in the above embodiment are stacked in the vertical direction Z.

[0068] Figure 11A and Figure 11B This is a cross-sectional view of a modified example of a semiconductor device according to an embodiment. When describing an example in which multiple memory cell structures (MC) are stacked, descriptions of components identical to those described above will be omitted, and the description will focus on transformed or added components.

[0069] In the following text, reference will be made to Figure 11A Describe an example of the memory cell structure MC described above being stacked in two levels in the vertical direction Z.

[0070] Reference Figure 11AA first conductive structure 12 extending in the first direction X, a second conductive structure 72b extending in the first conductive structure 12 and in the second direction Y, and a third conductive structure 172 extending in the second conductive structure 72b and in the first direction X can be disposed with respect to a reference. Figure 2 The same substrate structure as described above is used on substrate structure 3. For example, the first memory cell structure MC1 can be placed between the first conductive structure 12 and the second conductive structure 72b, and the second memory cell structure MC2 can be placed between the second conductive structure 72b and the third conductive structure 172.

[0071] Among the first conductive structure 12, the second conductive structure 72b, and the third conductive structure 172, the conductive structure at a relatively lower position (e.g., closer to the semiconductor substrate 6 in the vertical direction Z) can have the same characteristics as the reference structure. Figure 2 The first conductive structure 12 described is the same structure. For example, each of the first conductive structure 12 and the second conductive structure 72b may include a reference to... Figure 2 The description includes multiple layers 14, 16, and 18.

[0072] The second memory cell structure MC2 can have a structure in which the first memory cell structure MC1 is rotated 90 degrees in a planar view. For example, in Figure 11A In the region indicated by line I-I', the second memory cell structure MC2 is substantially the same as the first memory cell structure MC1 in the region indicated by line II-II'. The second memory cell structure MC2 in the region indicated by line II-II' can be substantially the same as the first memory cell structure MC1 in the region indicated by line I-I'.

[0073] In the following text, reference will be made to Figure 11B Describe an example where the memory cell structure MC described above is stacked in three or more levels in the vertical direction Z. As an example, describe an example where the memory cell structure MC described above is stacked in four levels in the vertical direction Z.

[0074] Reference Figure 11B The third memory cell structure MC3 and the fourth memory cell structure MC4 can be stacked sequentially as shown in the reference. Figure 11A The first memory cell structure MC1 and the second memory cell structure MC2 are described.

[0075] As described above, the first memory cell structure MC1 can be placed between the first conductive structure 12 and the second conductive structure 72b. The second memory cell structure MC2 can be placed between the second conductive structure 72b and the third conductive structure 172b. The third memory cell structure MC3 can be placed between the third conductive structure 172b and the fourth conductive structure 272. The fourth memory cell structure MC4 can be placed between the fourth conductive structure 272 and the fifth conductive structure 372.

[0076] Among the first conductive structure 12, the second conductive structure 72b, the third conductive structure 172b, the fourth conductive structure 272, and the fifth conductive structure 372, each of the first conductive structure 12, the second conductive structure 72b, the third conductive structure 172b, and the fourth conductive structure 272 located at a relatively lower position may include a reference. Figure 2 The description includes multiple layers 14, 16, and 18.

[0077] The first conductive structure 12, the third conductive structure 172b, and the fifth conductive structure 372 can extend in the first direction X, and the second conductive structure 72b and the fourth conductive structure 272 can extend in the second direction Y. The first memory cell structure MC1 and the third memory cell structure MC3 can have the same structure, and the second memory cell structure MC2 and the fourth memory cell structure MC4 can have the same structure.

[0078] Figure 12 This is a cross-sectional view of a modified example of a semiconductor device according to an embodiment.

[0079] In the implementation method, refer to Figure 12 , as reference Figure 2 The description includes a substrate structure 3, a buffer layer 21, an interlayer insulating layer 30, an etch stop layer 33, a planarization stop layer 36, a data storage material pattern 45, a hole spacer 42, an intermediate conductive pattern 48, and a switch material pattern 57.

[0080] The switch upper electrode pattern 60a can be disposed on the switch material pattern 57. The switch upper electrode pattern 60a can include multiple layers stacked sequentially. For example, the switch upper electrode pattern 60a can include a first upper electrode layer 60a_1 and a second upper electrode layer 60a_2 disposed on the first upper electrode layer 60a_1. In an embodiment, the first upper electrode layer 60a_1 can be a carbon material layer or a carbon-containing material layer. The second upper electrode layer 60a_2 can include a conductive material layer, such as tungsten.

[0081] The side surfaces of the switch material pattern 57 and the switch upper electrode pattern 60a can be aligned. For example, the switch material pattern 57 and the switch upper electrode pattern 60a can have substantially the same width.

[0082] Spacer 166 may cover the sidewalls of the sequentially stacked switch material pattern 57 and the sidewalls of the switch upper electrode pattern 60a. Spacer 166 may be disposed on the intermediate conductive pattern 48. Spacer 166 may be formed of an insulating material (e.g., silicon oxide or silicon nitride).

[0083] The gap-filling insulating pattern 169 can be disposed on the interlayer insulating layer 30 and can cover the side surface of the intermediate conductive pattern 48 while extending upward (e.g., upward in the vertical direction Z). The spacer 166 can be placed between the sidewall of the switching material pattern 57 and the sidewall of the switch upper electrode pattern 60a and the gap-filling insulating pattern 169.

[0084] The second conductive structure 472 can be disposed on the upper electrode pattern 60a of the switch and can extend in the second direction Y. The upper gap filling insulating pattern 96 can cover the side surface of the second conductive structure 472.

[0085] The memory cell structure MC' can be placed between the first conductive structure 12 and the second conductive structure 472. The memory cell structure MC' may include the same data storage material pattern 45, intermediate conductive pattern 48, switch material pattern 57, and switch upper electrode pattern 60a as described above.

[0086] In the following text, reference will be made to Figure 13 Describe an example in which the memory cell structure MC' is stacked in the vertical direction Z.

[0087] Figure 13 This is a cross-sectional view of a modified example of a semiconductor device according to an embodiment.

[0088] Reference Figure 13 A first conductive structure 12 extending in the first direction X, a second conductive structure 472a extending in the first conductive structure 12 and in the second direction Y, and a third conductive structure 572 extending in the second conductive structure 472a and in the first direction X can be disposed with respect to a reference. Figure 12 On the same matrix structure 3 described. For example, with reference Figure 12 The same first memory cell structure MC' described can be placed between the first conductive structure 12 and the second conductive structure 472a, and the second memory cell structure MC" can be placed between the second conductive structure 472a and the third conductive structure 572.

[0089] Among the first conductive structure 12, the second conductive structure 472a, and the third conductive structure 572, the conductive structure at a relatively lower position (e.g., closer to the semiconductor substrate 6 in the vertical direction Z) can have the same characteristics as the reference structure. Figure 2The first conductive structure 12 described is the same structure. For example, each of the first conductive structure 12 and the second conductive structure 472a may include a reference structure. Figure 2 The multiple layers 14, 16, and 18 are described. The second memory cell structure MC' can have a first memory cell structure MC' in a plan view relative to a reference. Figure 11A The same structure is rotated 90 degrees in the same manner. For example, multiple memory cell structures MC' and MC' can be arranged stacked in the vertical direction Z.

[0090] In the following text, reference will be made to Figure 1 and Figures 14 to 25 A method for manufacturing a semiconductor device according to an embodiment is described.

[0091] Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 and Figure 25 This is a cross-sectional view of a stage in a method for manufacturing a semiconductor device according to an embodiment. In detail, Figures 14 to 25 It shows along Figure 1 The area intercepted by line I-I' and along Figure 1 A cross-sectional view of the area intercepted by line II-II'.

[0092] Reference Figure 1 and Figure 14 Structures 12, 21, and 24 with linear shapes or linear structures can be formed on the substrate structure 3. The substrate structure 3 may include a semiconductor substrate 6 and a lower circuit region 9 on the semiconductor substrate 6. The lower circuit region 9 may be a peripheral circuit region.

[0093] Structures 12, 21 and 24 may include a first conductive structure 12, a buffer layer 21 and a planarization stop layer 24 stacked in sequence.

[0094] In an embodiment, the first conductive structure 12 may include a plurality of layers 14, 16, and 18 stacked in sequence. For example, the first conductive structure 12 may include a first lower layer 14, a second lower layer 16, and a third lower layer 18 stacked in sequence.

[0095] In an embodiment, the buffer layer 21 may be formed of, for example, a metal oxide (such as AlO) or a metal nitride (such as AlN) or a material that can replace or perform the same function.

[0096] The planarization stop layer 24 can be formed of, for example, an insulating material (such as silicon nitride).

[0097] Reference Figure 1 and Figure 15 In the region intercepted along line II-II', a gap-filling layer can be deposited and planarized until a planarization stop layer is exposed. Figure 14 24), to form a gap-filling insulating pattern 27.

[0098] In this implementation, the planarization stop layer can be completely removed. Figure 14 24) to expose buffer layer 21.

[0099] In the implementation, the planarization stop layer ( Figure 14 24) can retain its reduced thickness.

[0100] Reference Figure 1 and Figure 16 An interlayer insulating layer 30, an etch stop layer 33, and a planarization stop layer 36 can be sequentially formed on the buffer layer 21 and the gap-filling insulating pattern 27. The interlayer insulating layer 30 can be formed of, for example, an insulating material (such as SiO, SiN, SiCN, or SiON). The etch stop layer 33 can be formed of, for example, an insulating material (such as AlO or AlN). The planarization stop layer 36 can be formed of, for example, an insulating material (such as silicon nitride).

[0101] Reference Figure 1 and Figure 17 Initial holes 39 can be formed that sequentially penetrate the planarization stop layer 36, the etch stop layer 33, and the interlayer insulating layer 30. Multiple initial holes 39 can be formed.

[0102] In an embodiment, the initial hole 39 may be stacked with the buffer layer 21.

[0103] The buffer layer 21 can help protect the first conductive structure 12 from the etching process in which the interlayer insulating layer 30 is etched to form the initial hole 39.

[0104] A hole spacer 42 can be formed on the sidewall of the initial hole 39. The step of forming the hole spacer 42 may include: forming a spacer layer covering the inner wall of the initial hole 39 and the upper surface of the planarization stop layer 36; and anisotropically etching the spacer layer. The buffer layer 21 can protect the first conductive structure 12 from the etching process in which the spacer layer is anisotropically etched to form the hole spacer 42. The initial hole 39 can be defined by the hole spacer 42. Therefore, the hole spacer 42 can reduce the width of the initial hole 39.

[0105] Reference Figure 1 and Figure 18 It can etch the initial hole ( Figure 17 The exposed buffer layer 21 (39) allows for the formation of holes 40 that expose the upper surface of the first conductive structure 12.

[0106] In one embodiment, at least a portion of the buffer layer 21 below the hole spacer 42 may be etched to allow the hole 40 to extend in the first direction X and the second direction Y (e.g., the horizontal direction).

[0107] Reference Figure 1 and Figure 19 The data storage material layer can be formed to cover the planarization stop layer 36 while filling the hole 40, and the planarization stop layer 36 can be used as a planarization stop layer to perform a planarization process to form a data storage material pattern 45 in the hole 40.

[0108] By performing tessellation to form a data storage material pattern 45, the durability of the data storage material pattern 45 is increased by, for example, two to three orders of magnitude.

[0109] In one implementation, the thickness of the planarization stop layer 36 can be reduced during the planarization process.

[0110] In one implementation, the planarization stop layer 36 can be completely removed to expose the etch stop layer 33.

[0111] In one embodiment, after filling the hole 40 with the data storage material layer, the data storage material layer can be reheated with a laser, causing the data storage material layer to flow back into the hole 40. Therefore, the data storage material pattern 45 can be formed with fewer defects in the second direction Y with a smaller width (e.g., 14 nm or 12 nm), thereby increasing the scalability of the semiconductor device.

[0112] Reference Figure 1 and Figure 20 Multiple intermediate layers 51 and 54, a switch material layer 56, and a switch upper electrode layer 59 can be sequentially stacked on the planarization stop layer 36 and the data storage material pattern 45.

[0113] Reference Figure 1 and Figure 21 In the region cut along line II-II', the sequentially stacked switching material layer 56 and switching upper electrode layer 59 can be patterned to form a first initial trench 63. The first initial trench 63 can be in the form of a line (e.g., it can extend linearly). The first initial trench 63 can expose the upper surfaces of a plurality of intermediate layers 51 and 54.

[0114] While forming the first initial trench 63, the switch material layer 56 and the switch upper electrode layer 59 can be etched to form a switch material pattern 57 and a switch upper electrode pattern 60.

[0115] A first spacer 66 may be formed on the side surfaces of the switch material pattern 57 and the switch electrode pattern 60 exposed by the first initial trench 63. The first spacer 66 may be formed of an insulating material.

[0116] Reference Figure 1 and Figure 22 In the region cut along line II-II', a plurality of intermediate layers 51 and 54 exposed by the first initial trench 63 can be etched to form the first trench 64.

[0117] In one implementation, the first trench 64 may expose the planarization stop layer 36.

[0118] In one embodiment, after etching the plurality of intermediate layers 51 and 54, the first trench 64 can expose the etch stop layer 33 by etching the planarization stop layer 36.

[0119] Reference Figure 1 and Figure 23 The gap-filling insulating pattern 69 can be formed to fill the first trench ( Figure 22 (64). An upper conductive layer 71, an upper buffer layer 80, and an upper planarization stop layer 82 may be formed sequentially on the gap-filling insulating pattern 69 and the switch upper electrode pattern 60.

[0120] In an embodiment, the upper conductive layer 71 may include a single layer or multiple layers.

[0121] In an embodiment, when the upper conductive layer 71 is used to form Figure 11A The second conductive structure between the first memory cell structure MC1 and the second memory cell structure MC2 described in the document ( Figure 11A In step 72b), the upper conductive layer 71 can be formed as a plurality of layers 14, 16, and 18 stacked sequentially. The upper conductive layer 71 can be formed from layers substantially the same as the first conductive structure 12. The upper buffer layer 80 can be connected to the reference layer. Figure 14 The described buffer layer ( Figure 14 21) is essentially the same, and the upper flattening stop layer 82 can be compared with the reference. Figure 14 The flattening stop layer 24 described is essentially the same.

[0122] In an embodiment, when the upper conductive layer 71 is used as Figure 11A The second memory cell structure described in ( Figure 11A The third conductive structure 172 of MC2) or is used as Figure 2 The memory cell structure described in ( Figure 2 In the second conductive structure 72a of the MC), the second lower layer 16 and the third lower layer 18 among the multiple layers 14, 16 and 18 can be omitted, and the upper buffer layer 80 can be omitted.

[0123] Reference Figure 1 and Figure 24 In the region intercepted along line I-I', in the upper conductive layers stacked sequentially ( Figure 23 After etching the upper buffer layer 80 and the upper planarization stop layer 82 (71), the switch upper electrode layer ( Figure 20 59) and switch material layer ( Figure 20 Sequential etching is performed on 56) to form the initial trench 84. The initial trench 84 may be in the form of a line. Simultaneously with the formation of the initial trench 84, the upper conductive layer ( Figure 23 71) can be etched to form a second conductive structure 72.

[0124] While forming the initial trench 84, the switch material layer 56 and the switch upper electrode layer 59 can be etched to form a switch material pattern 57 and a switch upper electrode pattern 60.

[0125] The second spacer 87 can be formed to cover the side surfaces of the switching material pattern 57, the upper electrode pattern 60, the second conductive structure 72, the upper buffer layer 80, and the upper planarization stop layer 82 exposed by the initial trench 84. The second spacer 87 can be heated at a temperature greater than or equal to 250 degrees Celsius and less than or equal to 350 degrees Celsius (a temperature lower than the conventional operating temperature). By heating the second spacer 87 at a low temperature, the performance of the switching material pattern 57 can be increased, and multiple semiconductor devices can be stacked on top of each other, such as, for example... Figure 11A , Figure 11B and Figure 13 As shown in the image.

[0126] Reference Figure 1 and Figure 25 In the region intercepted along line I-I', the initial trench can be etched ( Figure 24 Multiple intermediate layers 51 and 54 are formed below (e.g., at the bottom of the initial trench) to form a second trench 85. The multiple intermediate layers 51 and 54 can be etched simultaneously with the formation of the second trench 85 to form the multiple intermediate layers 51 and 54 as an intermediate conductive pattern 48.

[0127] In the implementation method, when the initial trench ( Figure 24 After etching the multiple intermediate layers 51 and 54 below 84), the second trench 85 can be etched down to the planarization stop layer 36 to expose the etch stop layer 33.

[0128] The etch stop layer 33 helps prevent etch damage to the data storage material pattern 45 that may occur while the multiple intermediate layers 51 and 54 are being etched.

[0129] return Figure 2 or Figure 11A This can form a gap-filling material layer to fill the second trench ( Figure 25 While covering the 85) with a planarization stop layer ( Figure 25 (82). The gap-filling material layer can be planarized to form a second gap-filling insulation pattern 90. The upper planarization stop layer can be removed ( Figure 25 (82).

[0130] like Figure 23 As described in the text, when the upper conductive layer ( Figure 23 71) was used to form Figure 11A The second conductive structure between the first memory cell structure MC1 and the second memory cell structure MC2 described in the document ( Figure 11A In step 72b), the layer above the upper conductive layer 71 is connected to... Figure 14 The buffer layer described in Figure 14 The upper buffer layer corresponding to 21 in the middle ( Figure 25 80% can be exposed.

[0131] As above Figure 23 As described in the text, when the upper conductive layer 71 is used as Figure 11A The second memory cell structure described in ( Figure 11A The third conductive structure 172 of MC2 in the middle is used as Figure 2 The memory cell structure described in ( Figure 2 In the second conductive structure 72a of the MC), the second lower layer 16 and the third lower layer 18 among the multiple layers 14, 16 and 18 can be omitted, and the upper conductive layer ( Figure 23 71) can be made of a third conductive structure ( Figure 11A 172) or Figure 2 The memory cell structure described in ( Figure 2 The second conductive structure of MC) Figure 2 It is formed by 72a).

[0132] In one embodiment, the data storage material pattern 45 can be formed in a separate process from the first conductive structure 12 (which can be used as the lower electrode of the data storage material pattern 45) and the intermediate conductive pattern 48 (which can be used as the upper electrode of the data storage material pattern 45). The height of the data storage material pattern 45 (e.g., the height in the vertical direction Z) can be determined by the height of the interlayer insulating layer 30 formed by the deposition process, and the variation in the height of the data storage material pattern 45 can be significantly reduced to help improve the dispersion of the semiconductor device.

[0133] An embodiment may provide a semiconductor device including a pattern of data storage material.

[0134] The embodiments may provide a method for manufacturing a semiconductor device including a pattern of data storage material.

[0135] As described above, according to the embodiments, data storage material patterns with reduced widths can help reduce the operating current of semiconductor devices.

[0136] According to an embodiment, a data storage material pattern with a constant height can help improve the distribution of semiconductor devices.

[0137] According to an embodiment, the data storage material pattern and the first conductive structure can be in stable contact with each other. For example, poor contact between the data storage material pattern and the first conductive structure can be prevented to help improve the durability and reliability of the semiconductor device.

[0138] According to embodiments, a carbon material layer or a carbon-containing material layer may be present above and below the data storage material pattern and may serve as a heat barrier to significantly reduce heat loss generated in the data storage material pattern during operation of the memory cell structure. As a result, the performance of the semiconductor device can be improved.

[0139] Embodiments have been disclosed herein, and although specific terminology has been used, it is used in a general and descriptive sense only and will be interpreted accordingly, not for limiting purposes. In some instances, it will be apparent to those skilled in the art, as of the date of filing of this application, that features, characteristics, and / or elements described in connection with the embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise indicated. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept set forth in the claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate structure, including semiconductor substrate; A first conductive structure is disposed on the substrate structure and extends in a first direction, the first conductive structure includes a lower layer, and at least one of the lower layers includes carbon. A buffer layer is disposed on a first portion of the top surface of the first conductive structure; An interlayer insulating layer is disposed on the top surface of the buffer layer; A data storage material pattern is disposed on the second portion of the top surface of the first conductive structure; An intermediate conductive pattern is disposed on the data storage material pattern and includes an intermediate layer, wherein at least one of the intermediate layers includes carbon. A switch material pattern is disposed on the intermediate conductive pattern; The electrode pattern on the switch is disposed on the switch material pattern and includes carbon. The second conductive structure is disposed on the electrode pattern on the switch and extends in a second direction intersecting the first direction; as well as A hole spacer is disposed between the side surface of the data storage material pattern and the side surface of the interlayer insulating layer. The buffer layer is located between the bottom surface of the interlayer insulating layer and a first portion of the top surface of the first conductive structure. The buffer layer extends in a first direction parallel to the top surface of the first conductive structure. The side surface of the buffer layer is aligned with the side surface of the first conductive structure. The data storage material pattern is in contact with the first conductive structure. The hole spacer is spaced apart from the first conductive structure. The bottom surface of the hole spacer is at a height higher than the bottom surface of the data storage material pattern.

2. The semiconductor device of claim 1, wherein, The spacer penetrates into the top surface of the buffer layer, and The bottom surface of the hole spacer is lower than the top surface of the buffer layer.

3. The semiconductor device of claim 1, further comprising: A planarization stop layer is placed between the buffer layer and the interlayer insulation layer. The hole spacer is positioned between the side surface of the planarization stop layer and the side surface of the data storage material pattern.

4. The semiconductor device of claim 3, further comprising: An etching stop layer is disposed on the interlayer insulating layer. The hole spacer is positioned between the side surface of the etch stop layer and the side surface of the data storage material pattern.

5. The semiconductor device of claim 4, further comprising: A planarization stop layer is placed between the etch stop layer and the intermediate conductive pattern. The hole spacer is positioned between the side surface of the planarization stop layer and the side surface of the data storage material pattern.

6. The semiconductor device of claim 5, wherein, The data storage material pattern extends upward, penetrates the etch stop layer and the planarization stop layer, and physically contacts the intermediate conductive pattern.

7. The semiconductor device of claim 1, wherein, The data storage material pattern also includes a portion extending between the bottom surface of the hole spacer and the top surface of the first conductive structure.

8. The semiconductor device of claim 1, wherein, The electrode pattern on the switch includes: The first upper electrode layer comprises carbon; and The second upper electrode layer is disposed on the first upper electrode layer.

9. A semiconductor device, the semiconductor device comprising: Substrate structure, including semiconductor substrate; A first conductive structure is disposed on the substrate structure and extends in a first direction, the first conductive structure including a lower layer, and at least one of the lower layers including carbon. A buffer layer is disposed on a first portion of the top surface of the first conductive structure; An interlayer insulating layer is disposed on the top surface of the buffer layer; A data storage material pattern is disposed on the second portion of the top surface of the first conductive structure; An intermediate conductive pattern is disposed on the data storage material pattern and includes an intermediate layer, wherein at least one of the intermediate layers includes carbon. A switch material pattern is disposed on the intermediate conductive pattern; The electrode pattern on the switch is disposed on the switch material pattern and includes carbon. The second conductive structure is disposed on the electrode pattern on the switch and extends in a second direction intersecting the first direction; as well as A hole spacer is disposed between the side surface of the data storage material pattern and the side surface of the interlayer insulating layer. Wherein, the width of at least one intermediate layer comprising carbon is greater than the width of the electrode pattern on the switch. The buffer layer is located between the bottom surface of the interlayer insulating layer and a first portion of the top surface of the first conductive structure. The buffer layer extends in a first direction parallel to the top surface of the first conductive structure. The side surface of the buffer layer is aligned with the side surface of the first conductive structure. The data storage material pattern is in contact with the first conductive structure. The hole spacer is spaced apart from the first conductive structure. The bottom surface of the hole spacer is at a height higher than the bottom surface of the data storage material pattern.

10. The semiconductor device of claim 9, wherein, In the second direction, the width of the at least one lower layer comprising carbon in the lower layer is smaller than the width of the at least one intermediate layer comprising carbon in the intermediate layer, and smaller than the width of the electrode pattern on the switch.

11. The semiconductor device of claim 9, wherein, The side surface of the data storage material pattern is disposed on the entire side surface of the hole spacer.

12. The semiconductor device of claim 9, wherein, The data storage material pattern also includes a portion extending between the bottom surface of the hole spacer and the top surface of the first conductive structure.

13. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a substrate structure including a semiconductor substrate; A first conductive structure is formed on the substrate structure, the first conductive structure extends in a first direction, the first conductive structure includes a lower layer, and at least one of the lower layers includes carbon. A buffer layer is formed on a first portion of the top surface of the first conductive structure; An interlayer insulating layer is formed on the top surface of the buffer layer; Forming holes through the interlayer insulation layer; A hole spacer is formed on the inner wall of the hole; A data storage material pattern is formed on the first conductive structure and the hole spacer by filling the hole with the data storage material. An intermediate conductive pattern is formed on the data storage material pattern, the intermediate conductive pattern including an intermediate layer, and at least one of the intermediate layers including carbon. A switching material pattern is formed on the intermediate conductive pattern; An upper electrode pattern for the switch is formed on the switch material pattern; as well as A second conductive structure is formed on the electrode pattern of the switch, and the second conductive structure extends in a second direction intersecting the first direction. The buffer layer is located between the bottom surface of the interlayer insulating layer and a first portion of the top surface of the first conductive structure. The buffer layer extends in a first direction parallel to the top surface of the first conductive structure. The side surface of the buffer layer is aligned with the side surface of the first conductive structure. The data storage material pattern is in contact with the first conductive structure. The hole spacer is spaced apart from the first conductive structure. The bottom surface of the hole spacer is at a height higher than the bottom surface of the data storage material pattern.

14. The method of claim 13, wherein, The electrode pattern on the switch includes carbon.

15. The method of claim 13, wherein, The step of forming the pattern of the data storage material further includes: after filling the hole with the data storage material, reheating the data storage material with a laser to cause the data storage material to flow back into the hole.

16. The method of claim 13, further comprising: An upper spacer is formed on the side surface of the switch material pattern and the side surface of the switch upper electrode pattern, and the upper spacer is heated at a temperature greater than or equal to 250 degrees Celsius and less than or equal to 350 degrees Celsius.

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