Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same. The method comprises: a first substrate having opposite first and second surfaces, and a plurality of first and second doped regions arranged in a vertical direction and separated from each other in the first substrate, and the first surface exposes the surface of the first doped regions; a gate in the first substrate, the gate extends from the first surface to the second surface, and each gate penetrates one first doped region and one second doped region; a plurality of word lines on the first surface; a plurality of bit lines on the first surface; a plurality of capacitors on the second surface, and the projection of each capacitor on the second surface at least partially overlaps with the projection of one second doped region on the second surface. Thus, the manufacturing difficulty of the memory is reduced, and the storage capacity of the memory is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of technology, semiconductor memories are widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory, and it is the most commonly used solution for applications that store large amounts of data.

[0003] Typically, dynamic random access memory (DRAM) consists of multiple memory cells. Each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected to each other through word lines and bit lines.

[0004] However, in existing memory structures, there are bit lines and conductive structures connected to the bit lines between the capacitors, word lines, and transistors. Therefore, in order to connect the capacitors to the word lines and transistors, the capacitor structure and the bit lines and conductive structures connected to the bit lines need to avoid each other. As a result, the circuit wiring in the memory array area is complex and the manufacturing process is difficult.

[0005] Furthermore, on the one hand, the complex circuitry within the memory array occupies a significant area due to the large footprint of circuitry other than capacitors, leading to a decrease in memory density and consequently, a reduction in capacitor capacity. On the other hand, the capacitor structure is also influenced by the memory's logic circuitry, such as the height of the connectors linking different circuits. This limits the capacitor's height, resulting in a smaller area and, consequently, a smaller storage capacity. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to reduce the manufacturing process difficulty of memory and increase the storage capacity of memory.

[0007] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure comprising: a first substrate having a first surface and a second surface opposite to each other, and further comprising a plurality of first doped regions and second doped regions arranged overlappingly and separately along a direction perpendicular to the surface of the first substrate, wherein the first surface exposes the surface of the first doped region; a gate located in the first substrate, the gate extending from the first surface toward the second surface, each gate penetrating one first doped region and one second doped region, the gate comprising an electrode layer and a dielectric layer located between the electrode layer and the first substrate, wherein the first surface exposes the top surface of the electrode layer; a plurality of word lines located on the first surface, each word line located on the top surface of at least one electrode layer; a plurality of bit lines located on the first surface, each bit line also located on the surface of at least one first doped region, and the plurality of word lines and bit lines are insulated from each other; and a plurality of capacitors located on the second surface, wherein the projection of each capacitor on the second surface at least partially coincides with the projection of one second doped region on the second surface.

[0008] Optionally, the capacitor includes a first capacitor electrode layer, a capacitor dielectric layer located on the surface of the first capacitor electrode layer, and a second capacitor electrode layer located on the surface of the capacitor dielectric layer.

[0009] Optionally, the first substrate has a plurality of capacitor openings, the projection of the capacitor openings on the second surface at least partially coincides with the projection of a second doped region on the second surface, and the first capacitor electrode layer is located on the inner wall surface of the capacitor openings.

[0010] Optionally, it further includes: an isolation structure located within the first substrate, the isolation structure extending from a first surface toward a second surface, the isolation structure being located between adjacent first doped regions, the isolation structure also being located between adjacent second doped regions, and the first surface exposing the top surface of the isolation structure.

[0011] Optionally, some of the word lines extend along a first direction, and some of the bit lines extend along a second direction, wherein the first direction and the second direction are perpendicular to each other.

[0012] Optionally, a plurality of the gates are arranged in an array along the first direction and the second direction, each word line is located on the top surface of an electrode layer of one column of open gates arranged along the first direction, and in the second direction, each bit line spans one row of gates.

[0013] Optionally, it may also include: a first dielectric structure located on the first surface, wherein the surface of the first dielectric structure is higher than the word line surface.

[0014] Optionally, the first dielectric structure has a plurality of second openings, each second opening exposing at least part or all of the surface of a first doped region, and the bit line is located within the second opening and on the surface of the first dielectric structure.

[0015] Optionally, the first substrate includes a memory region, and the word line, bit line, gate, and capacitor are located in the memory region.

[0016] Optionally, the first substrate further includes a first logic region, and the first logic circuit is located within the first logic region.

[0017] Optionally, the first logic circuit includes one or more of the following: a row address decoder, a data input buffer, a data output buffer, a sense amplifier, a column address decoder, and a driver circuit.

[0018] Optionally, it further includes: a second substrate bonded to the first substrate, the second substrate having opposing functional and non-functional surfaces, the first surface facing the functional surface, the second substrate having a second logic circuit, and the second logic circuit being electrically connected to the first logic circuit.

[0019] Optionally, it further includes: a second dielectric structure located on the bit line surface and the first surface, the surface of the second dielectric structure being higher than the bit line surface; a first conductive layer located within the second dielectric structure, the surface of the second dielectric structure exposing the first conductive layer, the first conductive layer being connected to the first logic circuit and the second logic circuit respectively.

[0020] Optionally, it further includes: a second substrate bonded to the first substrate, the second substrate having opposing functional and non-functional surfaces, the first surface facing the functional surface, and a second logic circuit within the second substrate, the second logic circuit being electrically connected to the bit line.

[0021] Optionally, it further includes: a second dielectric structure located on the bit line surface and the first surface, the surface of the second dielectric structure being higher than the bit line surface; a first conductive layer located within the second dielectric structure, the first conductive layer being connected to the bit line, and the surface of the second dielectric structure exposing the first conductive layer.

[0022] Optionally, it further includes: a third dielectric structure located on the functional surface; a second conductive layer located within the third dielectric structure, the second conductive layer being electrically connected to the second logic circuit, the surface of the third dielectric structure exposing the second interconnect layer, and the projection of the first conductive layer on the first surface at least partially overlapping the projection of the second conductive layer on the first surface.

[0023] Optionally, the second logic circuit includes one or more of the following: a row address decoder, a data input buffer, a data output buffer, a sense amplifier, a column address decoder, and a driver circuit.

[0024] Accordingly, the present invention also provides a method for forming the above-mentioned semiconductor structure, comprising: providing a first substrate, the first substrate having a first surface and a second surface opposite to each other, the first substrate further having a plurality of first doped regions and second doped regions arranged overlappingly and mutually discretely along a direction perpendicular to the surface of the first substrate, and the first surface exposing the surface of the first doped region; forming a plurality of gates extending from the first surface toward the second surface in the first substrate, each gate penetrating one first doped region and one second doped region, the gate including an electrode layer and a dielectric layer located between the electrode layer and the first substrate, the first surface exposing the top surface of the electrode layer; forming a plurality of word lines on the first surface, each word line located on the top surface of at least one electrode layer; forming a plurality of bit lines on the first surface, each bit line also located on the surface of at least one first doped region, and the plurality of word lines and bit lines being insulated from each other; forming a plurality of capacitors on the second surface, and the projection of each capacitor on the second surface at least partially coinciding with the projection of one second doped region on the second surface.

[0025] Optionally, the capacitor includes a first capacitor electrode layer, a capacitor dielectric layer located on the surface of the first capacitor electrode layer, and a second capacitor electrode layer located on the surface of the capacitor dielectric layer.

[0026] Optionally, the method of forming the capacitor includes: after forming a plurality of word lines and bit lines, etching the second surface to form a plurality of capacitor openings in the first substrate, wherein the projection of the capacitor openings on the second surface at least partially coincides with the projection of a second doped region on the second surface; forming a first capacitor electrode layer on the inner wall surface of each capacitor opening; forming a capacitor dielectric layer on the surface of the first capacitor electrode layer; and forming a second capacitor electrode layer on the surface of the capacitor dielectric layer.

[0027] Optionally, the second surface may be thinned after the word lines and bit lines are formed and before the capacitor openings are formed.

[0028] Optionally, the first substrate further includes an isolation structure extending from a first surface toward a second surface, the isolation structure being located between adjacent first doped regions and also between adjacent second doped regions, with the top surface of the isolation structure exposed by the first surface.

[0029] Optionally, the method of forming the gate includes: etching the first surface to form a plurality of first openings in the first substrate, each first opening penetrating a first doped region and a second doped region; forming a dielectric material layer in the first openings and the first surface; forming an electrode material layer on the surface of the dielectric material layer, wherein the surface of the electrode material layer is higher than the first surface; forming a plurality of first mask structures on the surface of the electrode material layer, each first mask structure covering at least one first opening and exposing at least a portion of the electrode material layer surface on the first doped region; using the plurality of first mask structures as masks, etching the electrode material layer and the dielectric material layer until the first surface is exposed.

[0030] Optionally, the method of forming a plurality of word lines includes: forming a word line material layer on the surface of the electrode material layer before forming a plurality of the first mask structures; and etching the word line material layer using the plurality of the first mask structures as masks until the surface of the electrode material layer is exposed before etching the electrode material layer.

[0031] Optionally, it further includes: after forming the word line and before forming the bit line, forming a first dielectric structure on the first surface, wherein the surface of the first dielectric structure is higher than the surface of the word line.

[0032] Optionally, the method for forming the bit line includes: forming a plurality of second openings within the first dielectric structure, each second opening exposing at least a portion or all of the surface of a first doped region; forming a bit line material layer within the second openings and on the surface of the first dielectric structure; forming a plurality of second mask structures on the surface of the bit line material layer, each second mask structure covering at least one second opening; and etching the bit line material layer using the second mask structures as masks until the surface of the first dielectric structure is exposed.

[0033] Optionally, it may also include forming a contact layer on the surface of a plurality of the first doped regions after the gate and word lines are formed and before the bit lines are formed.

[0034] Optionally, the top surface of the electrode layer is higher than the first surface; the method of forming the semiconductor structure further includes: forming a sidewall on the sidewall surface of the electrode layer on the first surface before forming the contact layer.

[0035] Optionally, the extension direction of the bit line is perpendicular to the extension direction of the word line.

[0036] Optionally, the first substrate includes a memory region, and the word line, bit line, gate, and capacitor are located in the memory region.

[0037] Optionally, the first substrate further includes a first logic region, and the first logic circuit is located within the first logic region.

[0038] Optionally, it further includes: providing a second substrate having a second logic circuit therein, the second substrate also having opposing functional and non-functional surfaces; bonding the first substrate and the second substrate after forming the gate, the word line, and the bit line, and before forming the capacitor, the first surface facing the functional surface, and the second logic circuit being electrically connected to the first logic circuit.

[0039] Optionally, it further includes: after forming the gate, the word line, and the bit line, and before bonding the first substrate and the second substrate, forming a second dielectric structure on the bit line surface and the first surface, the surface of the second dielectric structure being higher than the bit line surface; forming a first conductive layer within the second dielectric structure, the first conductive layer being connected to the first logic circuit, and the surface of the second dielectric structure exposing the first conductive layer.

[0040] Optionally, it further includes: providing a second substrate having a second logic circuit therein, the second substrate also having opposing functional and non-functional surfaces; bonding the first substrate and the second substrate after forming the gate, the word line, and the bit line, and before forming the capacitor, the first surface facing the functional surface, and the second logic circuit being electrically connected to the bit line.

[0041] Optionally, it further includes: after forming the gate, the word line, and the bit line, and before bonding the first substrate and the second substrate, forming a second dielectric structure on the bit line surface and a first surface, the surface of the second dielectric structure being higher than the bit line surface; forming a first conductive layer within the second dielectric structure, the first conductive layer being connected to the bit line, and the surface of the second dielectric structure exposing the first conductive layer.

[0042] Optionally, it further includes: forming a third dielectric structure on the functional surface before bonding the first substrate to the second substrate; forming a second conductive layer within the third dielectric structure, the second conductive layer being electrically connected to the second logic circuit, the surface of the third dielectric structure exposing the second conductive layer, and, after bonding the first substrate to the second substrate, the projection of the first conductive layer on the first surface at least partially overlaps with the projection of the second conductive layer on the first surface.

[0043] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0044] In the semiconductor structure formation method provided by the present invention, a plurality of gates extending from a first surface toward a second surface are formed in a first substrate. Word lines are formed on the top surface of the electrode layer exposed on the first surface, bit lines are formed on the surface of a first doped region exposed on the first surface, and a plurality of capacitors are formed on the second surface. The projection of each capacitor on the second surface at least partially overlaps with the projection of a second doped region on the second surface. Therefore, on the one hand, the structural correlation between the capacitor and the word lines, and between the capacitor and the bit lines, is small, thereby simplifying the wiring structure of the word lines and bit lines. Furthermore, the capacitors can be connected to the second doped region through a simple structure, thereby reducing the manufacturing process difficulty of the memory. On the other hand, since the capacitors are formed on the second surface, the area occupied by the wiring structure is reduced, thereby increasing the space used to form the capacitors, thereby improving the storage density and storage capacity of the memory. Attached Figure Description

[0045] Figures 1 to 20 This is a schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0046] As described in the background art, in existing memory structures, since there are bit lines and conductive structures connected to the bit lines between the capacitors, word lines, and transistors, in order to connect the capacitors with the word lines and transistors, the capacitor structure and the bit lines and conductive structures connected to the bit lines need to avoid each other. As a result, the circuit wiring in the memory array area is complex and the manufacturing process is difficult.

[0047] Furthermore, on the one hand, the complex circuitry within the memory array occupies a significant area due to the large footprint of circuitry other than capacitors, leading to a decrease in memory density and consequently, a reduction in capacitor capacity. On the other hand, the capacitor structure is also influenced by the memory's logic circuitry, such as the height of the connectors linking different circuits. This limits the capacitor's height, resulting in a smaller area and, consequently, a smaller storage capacity.

[0048] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, which involves forming a plurality of word lines and bit lines on a first surface of a first substrate, and forming a plurality of capacitors on a second surface of the first substrate. This reduces the manufacturing difficulty of the memory and increases the memory's storage capacity.

[0049] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0050] It should be noted that the term "surface" in this specification is used to describe the relative spatial relationship and is not limited to whether there is direct contact.

[0051] Figures 1 to 20 This is a schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0052] Please refer to Figure 1 and Figure 2 , Figure 1 yes Figure 2 A top view of the structure along direction A. Figure 2 yes Figure 1 A cross-sectional structural schematic diagram along the B1-B2 direction is provided, providing a first substrate 100, the first substrate 100 having a first surface 101 and a second surface 102 opposite to each other, the first substrate 100 also having a plurality of first doped regions 103 and second doped regions 104 arranged overlappingly and mutually discretely along a direction perpendicular to the surface of the first substrate 100, and the first surface 101 exposes the surface of the first doped region 103.

[0053] In this embodiment, the first substrate 100 also has an isolation structure 105, which extends from the first surface 101 toward the second surface 102. The isolation structure 105 is located between adjacent first doped regions 103 and between adjacent second doped regions 104. The first surface 101 exposes the top surface of the isolation structure 105.

[0054] In this embodiment, the method for forming the first doped region 103, the second doped region 104, and the isolation structure 105 includes: providing a substrate (not shown); forming an initial doped layer (not shown) on the substrate using an epitaxial growth process, wherein the initial doped layer contains first ions; performing an ion implantation process on the top of the initial doped layer to form a second doped layer and a first doped layer located on the second doped layer, wherein the second doped layer is the portion of the initial doped layer that has not undergone the ion implantation process, and the first doped layer is the initial doped layer after the ion implantation process (not shown), wherein the second doped layer contains second ions, and the first ions and the second ions have opposite conductivity types; etching the first doped layer and the second doped layer to form an isolation opening (not shown) within the first doped layer and the second doped layer, wherein the isolation opening penetrates the first doped layer and extends into the second doped layer; forming an isolation structure 105 within the isolation opening, and simultaneously forming a plurality of mutually discrete first doped regions 103 and second doped regions 104.

[0055] In other embodiments, the isolation structure also extends into the first substrate between the second doped region and the second surface.

[0056] The substrate is made of a semiconductor material. In this embodiment, the substrate is made of silicon. In other embodiments, the substrate material includes silicon carbide, silicon-germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0057] In other embodiments, after the gate and sidewalls are subsequently formed, the initial doped layer can be subjected to an ion implantation process to form the first doped region and the second doped region.

[0058] In this embodiment, the first substrate 100 includes a storage region I, and the isolation structure 105, the first doped region 103, and the second doped region 104 are located in the storage region I.

[0059] In this embodiment, the first substrate 100 also includes a first logic circuit (not shown), and the first substrate 100 further includes a first logic region (not shown), and the first logic circuit is located in the first logic region.

[0060] In this embodiment, the first logic circuit includes one or more of the following: row address decoder, data input buffer, data output buffer, sense amplifier, column address decoder, and driving circuit.

[0061] In another embodiment, the first logic circuit is electrically connected to the subsequently formed bit line.

[0062] In other embodiments, the first substrate does not include a first logic region and does not have a first logic circuit.

[0063] Next, a plurality of gates extending from the first surface 101 toward the second surface 102 are formed within the first substrate 100. Each gate penetrates a first doped region 103 and a second doped region 104. Each gate includes an electrode layer and a dielectric layer located between the electrode layer and the first substrate 100. The first surface 101 exposes the top surface of the electrode layer. Furthermore, a plurality of word lines are formed on the first surface 101, each word line located on the top surface of at least one electrode layer. For details on the formation of the gates and word lines, please refer to [link to documentation]. Figures 3 to 8 .

[0064] Please refer to Figure 3 and Figure 4 , Figure 3 yes Figure 4 A top view of the structure along direction A. Figure 4 yes Figure 3A cross-sectional view along the B1-B2 direction is shown. A first opening patterned layer (not shown) is formed on the first surface 101, exposing a portion of the surface of the first doped region 103. Using the first opening patterned layer as a mask, the first surface 101 is etched to form a plurality of first openings 106 in the first substrate 100. Each first opening 106 penetrates one first doped region 103 and one second doped region 104.

[0065] In this embodiment, the etching process for the first surface 101 includes at least one of dry etching or wet etching.

[0066] In this embodiment, after the first opening 106 is formed, the first opening patterning layer is removed.

[0067] In this embodiment, the first opening 106 is arranged in an array along the first direction X and the second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

[0068] It should be noted that, for ease of explanation, Figure 4 The diagram only schematically shows six first openings 106 arranged in three columns along the first direction X and two rows along the second direction Y. The number and arrangement of some of the first openings 106 are designed according to actual requirements for storage capacity, wiring structure, etc.

[0069] Please refer to Figure 5 and Figure 6 , Figure 5 yes Figure 6 A top view of the structure along direction A. Figure 6 yes Figure 5 A cross-sectional view along the B1-B2 direction shows that a dielectric material layer 110 is formed in the first opening 106 and the first surface 101; an electrode material layer 120 is formed on the surface of the dielectric material layer 110, and the electrode material layer 120 fills the first opening 106; a plurality of first mask structures 132 are formed on the surface of the electrode material layer 120, each first mask structure 132 covering at least one first opening 106 and exposing at least a portion of the surface of the electrode material layer 120 on the first doped region 103.

[0070] In this embodiment, the surface of the electrode material layer 120 is higher than the first surface 101.

[0071] It should be noted that, for ease of explanation, this embodiment takes as an example that each first mask structure 132 covers a column of first openings 106 arranged along the first direction X.

[0072] The dielectric material layer 110 provides material for the subsequent formation of the dielectric layer.

[0073] The dielectric material layer 110 is made of silicon oxide or other dielectric materials. Correspondingly, the dielectric layer is made of silicon oxide or other dielectric materials.

[0074] In this embodiment, the dielectric material layer 110 is made of silicon oxide. Accordingly, the dielectric layer is made of silicon oxide.

[0075] In this embodiment, the process of forming the dielectric material layer 110 includes oxidation or deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0076] The electrode material layer 120 provides material for the subsequent formation of the electrode layer.

[0077] The electrode material layer 120 is made of polycrystalline silicon or a metal material layer. Correspondingly, the electrode layer is made of polycrystalline silicon or a metal material layer.

[0078] In this embodiment, the electrode material layer 120 is made of polycrystalline silicon. Correspondingly, the electrode layer is made of polycrystalline silicon.

[0079] In this embodiment, the process of forming the electrode material layer 120 includes epitaxial growth, metal electroplating, selective metal growth, or deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0080] In this embodiment, a word line material layer 130 is formed on the surface of the electrode material layer 120 before forming a plurality of the first mask structures 132.

[0081] The word line material layer 130 provides material for the subsequent formation of word lines.

[0082] The process for forming the word line material layer 130 includes metal electroplating, selective metal growth, or deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0083] The material of the word line material layer 130 includes metallic materials, such as tungsten, aluminum, copper, etc. Correspondingly, the material of the word lines includes metallic materials, such as tungsten, aluminum, copper, etc.

[0084] In this embodiment, the material of the word line material layer 130 is tungsten. Accordingly, the material of the word lines is tungsten.

[0085] In this embodiment, the electrode material layer 120 is planarized before forming the word line material layer 130. Therefore, the flatness of the electrode material layer 120 surface is improved, which facilitates the formation of a higher quality word line material layer 130 and improves the pattern accuracy of the first mask structure 132.

[0086] In this embodiment, the process of planarizing the electrode material layer 120 includes a chemical mechanical polishing process.

[0087] In this embodiment, the method for forming the first mask structure 132 includes: forming a first mask structure material layer (not shown) on the surface of the word line material layer 130; and patterning the first mask structure material layer to form the first mask structure 132.

[0088] Please refer to Figure 7 and Figure 8 , Figure 7 yes Figure 8 A top view of the structure along direction A. Figure 8 yes Figure 7 A cross-sectional view along the B1-B2 direction shows that, using several first mask structures 132 as masks, the word line material layer 130 is etched until the surface of the electrode material layer 120 is exposed, forming several word lines 131 on the first surface 101. After forming several word lines 131, the electrode material layer 120 and the dielectric material layer 110 are etched again using the first mask structures 132 as masks until the first surface 101 is exposed, forming a gate 122. The gate 122 includes an electrode layer 121 and a dielectric layer 111, and each word line 131 is located on the top surface of at least one electrode layer 121.

[0089] The gate 122 is located within the first substrate 100 and extends from the first surface 101 toward the second surface 102. Each gate 122 penetrates a first doped region 103 and a second doped region 104.

[0090] The first surface 101 exposes the top surface of the electrode layer 121. In this embodiment, the top surface of the electrode layer 121 is higher than the first surface 101.

[0091] The dielectric layer 111 is located between the electrode layer 121 and the first substrate 100.

[0092] In this embodiment, a plurality of gates 122 are arranged in an array along the first direction X and the second direction Y, and a plurality of word lines 131 extend along the first direction X. Each word line 131 is located on the top surface of the electrode layer 121 of a column of open gates 122 arranged along the first direction X.

[0093] It should be noted that, for ease of explanation, Figure 7 The diagram only schematically shows six gates 122 arranged in three columns along the first direction X and two rows along the second direction Y, with one column of gates 122 along the first direction X connected to each other on the first surface 101. The number, arrangement, and connection method of the gates 122 on the first surface 101 are designed according to actual requirements for storage capacity, wiring structure, etc.

[0094] In this embodiment, the etching process of the letter line material layer 130, electrode material layer 120 and dielectric material layer 110 includes at least one of dry etching process or wet etching process.

[0095] In this embodiment, the word line 131 and the gate 122 are located in the memory area I.

[0096] Please refer to Figure 9 , Figure 9 and Figure 8 With the view direction consistent, a sidewall 123 is formed on the sidewall of the electrode layer 121 on the first surface 101; after the sidewall 123 is formed, a contact layer 124 is formed on the surface of a plurality of the first doped regions 103.

[0097] In this embodiment, the method for forming the sidewall 123 includes: depositing a sidewall material layer (not shown) on the surface of the electrode layer 121, the surface of the word line 131, and the first surface 101; and etching back the sidewall material layer to form the sidewall 123.

[0098] In this embodiment, the side wall 123 is also located on the side wall surface of the letter line 131.

[0099] The sidewall 123 can further enhance the insulation between the gate 122 and word line 131 and the subsequently formed bit line.

[0100] In this embodiment, the material of the sidewall 123 includes silicon oxide.

[0101] In this embodiment, the process of etching back the sidewall material layer includes an anisotropic dry etching process.

[0102] In this embodiment, the material of the contact layer 124 is a metal silicide.

[0103] The process for forming the contact layer 124 includes one or more combinations of metal electroplating, selective metal growth, deposition, and annealing processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0104] By forming the contact layer 124, the contact area with the first doped region 103 can be increased, thereby reducing the contact resistance between the subsequently formed bit line and the first doped region 103.

[0105] Please refer to Figure 10 , Figure 10 and Figure 9 With the view direction consistent, after the word line 131 is formed and before the subsequent bit line is formed, a first medium structure 140 is formed on the first surface 101, the surface of the first medium structure 140 being higher than the surface of the word line 131.

[0106] On the one hand, the first dielectric structure 140 is used to insulate the word line 131 from the subsequently formed bit line; on the other hand, the first dielectric structure 140 is also used to provide support for the subsequently formed bit line.

[0107] In this embodiment, the process of forming the first medium structure 140 includes a deposition process or a spin coating process, wherein the deposition process is, for example, at least one of chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0108] In this embodiment, the material of the first dielectric structure 140 includes silicon oxide.

[0109] Next, a plurality of bit lines are formed on the first surface 101, each bit line being located on at least one surface of a first doped region 103, and the plurality of word lines 131 and the bit lines are insulated from each other. For details on the process of forming the bit lines, please refer to [link to documentation]. Figures 11 to 15 .

[0110] Please refer to Figure 11 , Figure 11 and Figure 10 With the same view orientation, a plurality of second openings 141 are formed within the first dielectric structure 140, and each second opening 141 exposes at least part or all of the surface of a first doped region 103.

[0111] The second opening 141 provides space for the subsequent formation of bit lines.

[0112] In this embodiment, since a contact layer 124 is formed on the surface of the first doped region 103, each second opening 141 at least exposes a portion or all of the surface of the first doped region 103, meaning that each second opening 141 at least exposes a portion or all of the surface of the contact layer 124 on the first doped region 103.

[0113] The method of forming the second opening 141 includes: forming a second opening mask layer (not shown) on the surface of the first dielectric structure 140, the second opening mask layer exposing a portion of the surface of the first dielectric structure 140; using the second opening mask layer as a mask, etching the first dielectric structure 140 until the surface of the contact layer 124 is exposed.

[0114] The etching process for the first dielectric structure 140 includes at least one of dry etching or wet etching.

[0115] In this embodiment, the first dielectric structure 140 is planarized before forming the second opening 141. Therefore, the flatness of the surface of the first dielectric structure 140 is improved, which in turn improves the pattern accuracy of the second opening 141 and facilitates the subsequent filling of the bitline material layer within the second opening 141.

[0116] In this embodiment, the process of planarizing the first dielectric structure 140 includes a chemical mechanical polishing process.

[0117] In this embodiment, after the second opening 141 is formed, the second opening mask layer is removed.

[0118] Please refer to Figure 12 and Figure 13 , Figure 12 yes Figure 13 A top view of the structure along direction A. Figure 13 yes Figure 12 A cross-sectional view along the B1-B2 direction shows that a bit line material layer 150 is formed inside the second opening 141 and on the surface of the first dielectric structure 140; a plurality of second mask structures 152 are formed on the surface of the bit line material layer 150, and each second mask structure 152 covers at least one second opening 141.

[0119] In this embodiment, the second mask structure 152 extends along the second direction Y, and the second mask structure 152 also covers at least one first opening 106.

[0120] It should be noted that, for ease of explanation, this embodiment takes as an example that each second mask structure 152 covers a row of first openings 106 arranged along the second direction Y.

[0121] The bit line material layer 150 provides material for the subsequent formation of bit lines.

[0122] The process for forming the bit line material layer 150 includes metal electroplating, selective metal growth, or deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0123] The bit line material layer 150 is made of a metallic material, such as tungsten, aluminum, or copper. Similarly, the bit line material includes metallic materials, such as tungsten, aluminum, or copper.

[0124] In this embodiment, the bit line material layer 150 is made of tungsten. Correspondingly, the bit line is made of tungsten.

[0125] In this embodiment, the method for forming the second mask structure 152 includes: forming a second mask structure material layer (not shown) on the surface of the bit line material layer 150; and patterning the second mask structure material layer to form the second mask structure 152.

[0126] Please refer to Figure 14 and Figure 15 , Figure 14 yes Figure 15 A top view of the structure along direction A. Figure 15 yes Figure 14 A cross-sectional structural diagram along the B1-B2 direction is shown. Using the second mask structure 152 as a mask, the bit line material layer 150 is etched until the surface of the first dielectric structure 140 is exposed. A plurality of bit lines 151 are formed on the first surface 101. Each bit line 151 is also located on at least one surface of a first doped region 103, and the plurality of word lines 131 and bit lines 151 are insulated from each other.

[0127] In this embodiment, the bit line 151 extends along the second direction Y, and the extension direction of the bit line 151 is perpendicular to the extension direction of the word line 131. Furthermore, in the second direction Y, each bit line 151 spans one row of gates 122.

[0128] In other embodiments, the extension directions of the word lines and the extension directions of the bit lines are not perpendicular to each other.

[0129] In this embodiment, the bit line 151 is located in the storage area I.

[0130] In this embodiment, the etching process of the bit line material layer 150 includes at least one of dry etching process or wet etching process.

[0131] In this embodiment, after forming bit line 151, the second mask structure 152 is removed.

[0132] Please refer to Figure 16 , Figure 16 and Figure 15With the view orientation consistent, after the formation of the gate 122, the word line 131, and the bit line 151, and before the subsequent bonding of the first substrate 100 and the second substrate, a second dielectric structure 160 is formed on the surface of the bit line 151 and the first surface 101, the surface of the second dielectric structure 160 being higher than the surface of the bit line 151; a first conductive layer 161 is formed within the second dielectric structure 161, the first conductive layer 161 being connected to the bit line 151, and the surface of the second dielectric structure 160 exposing the first conductive layer 161.

[0133] The process for forming the second medium structure 160 includes spin coating or deposition processes.

[0134] In this embodiment, the material of the second dielectric structure 160 includes a dielectric material, such as silicon oxide.

[0135] The method for forming the first conductive layer 161 includes: forming a first conductive layer mask structure (not shown) on the surface of the second dielectric structure 160; exposing a portion of the surface of the second dielectric structure 160 on the bit line 151 using the first conductive layer mask structure as a mask; etching the second dielectric structure 160 using the first conductive layer mask structure as a mask until the top surface of the bit line 151 is exposed, forming a first conductive opening (not shown); forming a first conductive material layer (not shown) in the first conductive opening and on the surface of the second dielectric structure 160; planarizing the first conductive material layer until the surface of the second dielectric structure 160 is exposed, forming the first conductive layer 161.

[0136] The process for forming the first conductive material layer includes metal electroplating, selective metal growth, or deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0137] The process for planarizing the first conductive material layer includes chemical mechanical polishing or etching back.

[0138] In this embodiment, after the first conductive layer 161 is formed and before the capacitor opening is subsequently formed, the second surface 102 is thinned.

[0139] The thinning process for the second surface 102 includes physical mechanical polishing, chemical mechanical polishing, or wet etching.

[0140] Please refer to Figure 17 , Figure 17 and Figure 16With the view orientation consistent, a second substrate 200 is provided, the second substrate 200 having a second logic circuit (not shown), and the second substrate 200 also having opposing functional surfaces 201 and non-functional surfaces 202.

[0141] In this embodiment, the second logic circuit includes one or more of the following: row address decoder, data input buffer, data output buffer, sense amplifier, column address decoder, and driving circuit.

[0142] Please continue to refer to this. Figure 17 A third dielectric structure 210 is formed on the functional surface 201; a second conductive layer 211 is formed in the third dielectric structure 210, the second conductive layer 211 is electrically connected to the second logic circuit, and the second conductive layer 211 is exposed on the surface of the third dielectric structure 210.

[0143] The process for forming the third medium structure 210 includes spin coating or deposition processes.

[0144] In this embodiment, the material of the third dielectric structure 210 includes a dielectric material, such as silicon oxide.

[0145] The method for forming the second conductive layer 211 includes: forming a second conductive layer mask structure (not shown) on the surface of the third dielectric structure 210; exposing a portion of the functional surface 201 in the second conductive layer mask structure; etching the third dielectric structure 210 using the second conductive layer mask structure as a mask until the functional surface 201 is exposed, forming a second conductive opening (not shown); forming a second conductive material layer (not shown) in the second conductive opening and on the surface of the third dielectric structure 210; planarizing the second conductive material layer until the surface of the third dielectric structure 210 is exposed, forming the second conductive layer 211.

[0146] The process for forming the second conductive material layer includes metal electroplating, selective metal growth, or deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0147] The process for planarizing the second conductive material layer includes chemical mechanical polishing or etching back.

[0148] Please refer to Figure 18 , Figure 18 and Figure 17With the same viewing direction, after forming the gate 122, the word line 131, and the bit line 151, and before forming the capacitor, the first substrate 100 and the second substrate 200 are bonded together, the first surface 101 faces the functional surface 201, and the second logic circuit is electrically connected to the bit line 151.

[0149] Specifically, after the first substrate 100 and the second substrate 200 are bonded, the projection of the first conductive layer 161 onto the first surface 101 at least partially overlaps with the projection of the second conductive layer 211 onto the first surface 101. This achieves an electrical connection between the first conductive layer 161 and the second conductive layer 211, and consequently, an electrical connection between the second logic circuit and the bit line 151.

[0150] In another embodiment, the second logic circuit is electrically connected to the first logic circuit. Specifically, after forming the gate, the word line, and the bit line, and before bonding the first substrate and the second substrate, a second dielectric structure is formed on the bit line surface and the first surface, the surface of the second dielectric structure being higher than the bit line surface; a first conductive layer is formed within the second dielectric structure, the first conductive layer being connected to the first logic circuit, and the surface of the second dielectric structure exposing the first conductive layer. After bonding the first substrate and the second substrate, the first conductive layer is connected to the second logic circuit, thereby achieving the electrical connection between the second logic circuit and the first logic circuit.

[0151] Next, a plurality of capacitors are formed on the second surface 102, and the projection of each capacitor on the second surface 102 at least partially overlaps with the projection of a second doped region 104 on the second surface 102. The capacitors include a first capacitor electrode layer, a capacitor dielectric layer located on the surface of the first capacitor electrode layer, and a second capacitor electrode layer located on the surface of the capacitor dielectric layer. For details on the process of forming the capacitors, please refer to [link to documentation]. Figures 19 to 20 .

[0152] Please refer to Figure 19 After thinning the second surface 102, the second surface 102 is etched to form a plurality of capacitor openings 170 in the first substrate 100. The projection of the capacitor openings 170 on the second surface 102 at least partially overlaps with the projection of a second doped region 104 on the second surface 102.

[0153] The capacitor opening 170 provides space for the subsequent formation of the capacitor.

[0154] The method of forming the capacitor opening 170 includes: forming a capacitor opening mask layer (not shown) on the second surface 102, the capacitor opening mask layer exposing a portion of the second surface 102; using the capacitor opening mask layer as a mask, etching the second surface 102 until a plurality of the capacitor openings 170 are formed in the first substrate 100.

[0155] The etching process for the second surface 102 includes at least one of dry etching or wet etching.

[0156] In this embodiment, after the capacitor opening 170 is formed, the capacitor opening mask layer is removed.

[0157] Please refer to Figure 20 A first capacitor electrode layer 171 is formed on the inner wall surface of each capacitor opening 170; a capacitor dielectric layer 172 is formed on the surface of the first capacitor electrode layer 171; a second capacitor electrode layer 173 is formed on the surface of the capacitor dielectric layer 172, so as to form a plurality of capacitors on the second surface 102, and the projection of each capacitor on the second surface 102 at least partially overlaps with the projection of a second doped region 104 on the second surface 102.

[0158] Specifically, the fact that the projection of each capacitor on the second surface 102 at least partially overlaps with the projection of a second doped region 104 on the second surface 102 means that the projection of the first capacitor electrode layer 171 on the second surface 102 at least partially overlaps with the projection of a second doped region 104 on the second surface 102.

[0159] Since a plurality of gates 122 extending from the first surface 101 toward the second surface 102 are formed in the first substrate 100, and word lines 131 are formed on the top surface of the electrode layer 121 exposed on the first surface 101, bit lines 151 are formed on the surface of the first doped region 103 exposed on the first surface 101, and a plurality of capacitors are formed on the second surface 102, and the projection of each capacitor on the second surface 102 at least partially overlaps with the projection of a second doped region 104 on the second surface 102, on the one hand, the structural correlation between the capacitor and the word lines 131 and between the capacitor and the bit lines 151 is small, thereby simplifying the wiring structure of the word lines 131 and the bit lines 151, and the capacitors can be connected to the second doped region 104 through a simple structure, thereby reducing the manufacturing process difficulty of the memory; on the other hand, since the capacitors are formed on the second surface 102, the area occupied by the wiring structure is reduced, thereby increasing the space for forming capacitors, thereby improving the memory storage density and the memory storage capacity.

[0160] Furthermore, since the capacitor is formed on the second surface 102, when other circuits, such as the first logic circuit, are also present in the first substrate 100, the structural correlation between the capacitor and other circuits is reduced. This reduces the restriction on the overall height of the capacitor imposed by these other circuits, resulting in a smaller restriction on the capacitor's height. Consequently, the storage capacity of the memory can be increased by increasing the capacitor's height and thus its area. Specifically, the restriction on the overall height of the capacitor by these other circuits may occur, for example, when forming conductive plugs in other circuits, to reduce defects generated during the etching process of forming the conductive plug opening and the material filling process of the conductive plug, resulting in a high-quality conductive plug, the aspect ratio of the conductive plug may be limited, thereby limiting the capacitor height.

[0161] In this embodiment, several of the capacitors are located in the storage area I.

[0162] In this embodiment, the method for forming the first capacitor electrode layer 171 includes: depositing a first capacitor electrode material layer (not shown) on the inner wall surface of the capacitor opening 170 and the second surface 102; planarizing the first capacitor electrode material layer until the second surface 102 is exposed.

[0163] In this embodiment, the material of the first capacitor electrode layer 171 includes tungsten.

[0164] In this embodiment, the process for forming the capacitor dielectric layer 172 includes at least one of chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0165] In this embodiment, the material of the capacitor dielectric layer 172 includes high-k dielectric constant materials, aluminum oxide, etc.

[0166] In this embodiment, the process for forming the second capacitor electrode layer 173 includes at least one of chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0167] In this embodiment, the material of the second capacitor electrode layer 173 includes tungsten.

[0168] In this embodiment, each of the gate 122, the first doped region 103 penetrated by the gate 122, the second doped region 104 penetrated by the gate 122, and the portion of the first substrate 100 located between the second doped region 104 and the capacitor constitute a trench transistor.

[0169] Specifically, by applying a voltage to the word line 131 to open the channel of the trench transistor, the first doped region 103, the second doped region 104, and the first substrate 100 between the capacitor and the bit line 151 are turned on, so that the capacitor and the bit line 151 are turned on.

[0170] In other embodiments, after forming the second capacitor electrode layer, the capacitor dielectric layer and the second capacitor electrode layer may be planarized until the second surface is exposed.

[0171] In other embodiments, a second substrate may not be provided, and the first and second substrates may not be bonded.

[0172] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed by the above method. Please refer to [further details]. Figure 20 The system includes: a first substrate 100 having opposing first surfaces 101 and second surfaces 102; a plurality of first doped regions 103 and second doped regions 104 arranged overlappingly and discretely along a direction perpendicular to the surface of the first substrate 100, with the first surface 101 exposing the surface of the first doped regions 103; and a gate 122 located within the first substrate 100, extending from the first surface 101 toward the second surface 102, each gate 122 penetrating one first doped region 103 and one second doped region 104, the gate 122 including an electrode layer 121, and... A dielectric layer 111 is located between the electrode layer 121 and the first substrate 100, and the first surface 101 exposes the top surface of the electrode layer 121; a plurality of word lines 131 are located on the first surface 101, each word line 131 being located on the top surface of at least one electrode layer 121; a plurality of bit lines 151 are located on the first surface 101, each bit line 151 also being located on the surface of at least one first doped region 103, and the plurality of word lines 131 and bit lines 151 are insulated from each other; a plurality of capacitors are located on the second surface 102, and the projection of each capacitor on the second surface 102 at least partially coincides with the projection of a second doped region 104 on the second surface 102.

[0173] In this embodiment, the first substrate 100 includes a storage region I, and the word line 131, bit line 151, gate 122, and capacitor are located in the storage region I.

[0174] In this embodiment, the first substrate 100 further includes a first logic region (not shown), and the first substrate also has a first logic circuit (not shown), and the first logic circuit is located in the first logic region.

[0175] In another embodiment, the first logic circuit is electrically connected to the bit line.

[0176] In other embodiments, the first substrate does not include a first logic region and does not have a first logic circuit.

[0177] In this embodiment, the first logic circuit includes one or more of the following: row address decoder, data input buffer, data output buffer, sense amplifier, column address decoder, and driving circuit.

[0178] In this embodiment, the capacitor includes a first capacitor electrode layer 171, a capacitor dielectric layer 172 located on the surface of the first capacitor electrode layer 171, and a second capacitor electrode layer 173 located on the surface of the capacitor dielectric layer 172.

[0179] In this embodiment, the first substrate 100 has a plurality of capacitor openings 170 (e.g., Figure 17 As shown, the projection of each capacitor opening 170 onto the second surface 102 at least partially overlaps with the projection of a second doped region 104 onto the second surface 102, and the first capacitor electrode layer 171 is located on the inner wall surface of the capacitor opening 170.

[0180] In this embodiment, a plurality of word lines 131 extend along a first direction X, and a plurality of bit lines 151 extend along a second direction Y, wherein the first direction X and the second direction Y are perpendicular to each other.

[0181] In other embodiments, the extension directions of the word lines and the extension directions of the bit lines are not perpendicular to each other.

[0182] In this embodiment, a plurality of gates 122 are arranged in an array along the first direction X and the second direction Y. Each word line 131 is located on the top surface of the electrode layer 121 of a column of gates 122 arranged along the first direction X. In the second direction Y, each bit line 151 spans a row of gates 122.

[0183] In this embodiment, the semiconductor structure further includes an isolation structure 105 located within the first substrate 100. The isolation structure 105 extends from the first surface 101 toward the second surface 102. The isolation structure 105 is located between adjacent first doped regions 103 and also between adjacent second doped regions 104. The first surface 101 exposes the top surface of the isolation structure 105.

[0184] In other embodiments, the isolation structure also extends into the first substrate between the second doped region and the second surface.

[0185] In this embodiment, the semiconductor structure further includes a first dielectric structure 140 located on the first surface 101, the surface of the first dielectric structure 140 being higher than the surface of the word line 131.

[0186] The first medium structure 140 has a plurality of second openings 141 (e.g. Figure 11 As shown), each second opening 141 exposes at least part or all of the surface of a first doped region 103, and the bit line 151 is located within the second opening 141 and on the surface of the first dielectric structure 140.

[0187] In this embodiment, the semiconductor structure further includes: a second dielectric structure 160 located on the surface of the bit line 151 and the first surface 101, wherein the surface of the second dielectric structure 160 is higher than the surface of the bit line 151; and a first conductive layer 161 located within the second dielectric structure 160, wherein the first conductive layer 161 is connected to the bit line 151, and the surface of the second dielectric structure 160 exposes the first conductive layer 161.

[0188] In this embodiment, the semiconductor structure further includes a second substrate 200 bonded to the first substrate 100. The second substrate 200 has opposing functional surfaces 201 and non-functional surfaces 202. The first surface 101 faces the functional surface 201. The second substrate 200 has a second logic circuit (not shown) within it. The second logic circuit is electrically connected to the bit line 151.

[0189] In another embodiment, the second logic circuit is electrically connected to the first logic circuit. Specifically, the semiconductor structure further includes: a second dielectric structure located on the bit line surface and the first surface, the surface of the second dielectric structure being higher than the bit line surface; a first conductive layer located within the second dielectric structure, with the surface of the second dielectric structure exposing the first conductive layer, the first conductive layer being connected to the first logic circuit and the second logic circuit respectively.

[0190] In this embodiment, the second logic circuit includes one or more of the following: row address decoder, data input buffer, data output buffer, sense amplifier, column address decoder, and driving circuit.

[0191] In this embodiment, the semiconductor structure further includes: a third dielectric structure 210 located on the functional surface 201; a second conductive layer 211 located within the third dielectric structure 210, the second conductive layer 211 being electrically connected to the second logic circuit, the surface of the third dielectric structure 210 exposing the second interconnect layer 211, and the projection of the first conductive layer 161 onto the first surface 101 at least partially coinciding with the projection of the second conductive layer 211 onto the first surface 101.

[0192] In other embodiments, there is no second substrate bonded to the first substrate.

[0193] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A first substrate has a first surface and a second surface opposite to each other. The first substrate also has a plurality of first doped regions and second doped regions that are overlapped and mutually independent along a direction perpendicular to the surface of the first substrate, and the first surface exposes the surface of the first doped region. A gate located within the first substrate extends from a first surface toward a second surface, each gate penetrating a first doped region and a second doped region. The gate includes an electrode layer and a dielectric layer located between the electrode layer and the first substrate, with the first surface exposing the top surface of the electrode layer. A plurality of word lines are located on the first surface, each word line being located on the top surface of at least one electrode layer, the word lines being in direct contact with the top surface of the electrode layer, and a plurality of gates being arranged in an array along a first direction and a second direction; The plurality of bit lines are located on the first surface, each bit line is also located on at least one first doped region surface, and the plurality of word lines and bit lines are insulated from each other; A plurality of capacitor openings are located within a first substrate, the top of the capacitor openings are exposed on the second surface, and the width of the capacitor openings is greater than the width of the gate. The capacitor comprises a plurality of capacitors located on the second surface, wherein the projection of each capacitor on the second surface at least partially overlaps with the projection of a second doped region on the second surface. The capacitor includes: a first capacitor electrode layer located on the sidewall surface and bottom surface of the capacitor opening, a capacitor dielectric layer located on the surface of the first capacitor electrode layer, and a second capacitor electrode layer located on the surface of the capacitor dielectric layer.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: An isolation structure is located within the first substrate, the isolation structure extending from a first surface toward a second surface, the isolation structure being located between adjacent first doped regions, the isolation structure also being located between adjacent second doped regions, and the first surface exposing the top surface of the isolation structure.

3. The semiconductor structure as described in claim 1, characterized in that, A plurality of the word lines extend along a first direction, and a plurality of the bit lines extend along a second direction, wherein the first direction and the second direction are perpendicular to each other.

4. The semiconductor structure as described in claim 3, characterized in that, Each word line is located on the top surface of an electrode layer of one column of open gates arranged along a first direction, and in the second direction, each bit line spans one row of gates.

5. The semiconductor structure as described in claim 4, characterized in that, Also includes: A first medium structure located on the first surface, wherein the surface of the first medium structure is higher than the surface of the word line.

6. The semiconductor structure as described in claim 5, characterized in that, The first dielectric structure has a plurality of second openings, each second opening exposing at least part or all of the surface of a first doped region, and the bit line is located within the second opening and on the surface of the first dielectric structure.

7. The semiconductor structure as described in claim 1, characterized in that, The first substrate includes a memory region, and the word line, bit line, gate, and capacitor are located in the memory region.

8. The semiconductor structure as described in claim 7, characterized in that, The first substrate further includes a first logic region, and the first logic circuit is located within the first logic region.

9. The semiconductor structure as described in claim 8, characterized in that, The first logic circuit includes one or more of the following: row address decoder, data input buffer, data output buffer, sense amplifier, column address decoder, and driver circuit.

10. The semiconductor structure as described in claim 8, characterized in that, Also includes: A second substrate bonded to the first substrate, the second substrate having opposing functional and non-functional surfaces, the first surface facing the functional surface, the second substrate having a second logic circuit, the second logic circuit being electrically connected to the first logic circuit.

11. The semiconductor structure as claimed in claim 10, characterized in that, Also includes: A second dielectric structure located on the bit line surface and the first surface, wherein the surface of the second dielectric structure is higher than the bit line surface; A first conductive layer is located within the second dielectric structure, and the first conductive layer is exposed on the surface of the second dielectric structure. The first conductive layer is connected to the first logic circuit and the second logic circuit, respectively.

12. The semiconductor structure as claimed in claim 1, characterized in that, Also includes: A second substrate bonded to the first substrate, the second substrate having opposing functional and non-functional surfaces, the first surface facing the functional surface, and a second logic circuit within the second substrate, the second logic circuit being electrically connected to the bit line.

13. The semiconductor structure as described in claim 11, characterized in that, Also includes: A second dielectric structure located on the bit line surface and the first surface, wherein the surface of the second dielectric structure is higher than the bit line surface; A first conductive layer is located within the second dielectric structure, the first conductive layer is connected to the bit line, and the surface of the second dielectric structure exposes the first conductive layer.

14. The semiconductor structure as described in claim 13, characterized in that, Also includes: A third medium structure located on the functional surface; A second conductive layer is located within the third dielectric structure and is electrically connected to the second logic circuit. The second conductive layer is exposed on the surface of the third dielectric structure. The projection of the first conductive layer onto the first surface at least partially overlaps with the projection of the second conductive layer onto the first surface.

15. The semiconductor structure as described in claim 10 or 12, characterized in that, The second logic circuit includes one or more of the following: row address decoder, data input buffer, data output buffer, sense amplifier, column address decoder, and driver circuit.

16. A method for forming a semiconductor structure, characterized in that, include: A first substrate is provided, the first substrate having a first surface and a second surface opposite to each other, and the first substrate further having a plurality of first doped regions and second doped regions that are overlapped and mutually independent along a direction perpendicular to the surface of the first substrate, and the first surface exposes the surface of the first doped region. A plurality of gates extending from a first surface toward a second surface are formed in the first substrate. Each gate penetrates a first doped region and a second doped region. The gate includes an electrode layer and a dielectric layer located between the electrode layer and the first substrate. The first surface exposes the top surface of the electrode layer. A plurality of word lines are formed on the first surface, each word line being located on the top surface of at least one electrode layer, the word lines being in direct contact with the top surface of the electrode layer, and a plurality of gates being arranged in an array along a first direction and a second direction; A plurality of bit lines are formed on the first surface, each bit line being located on at least one first doped region surface, and the plurality of word lines and bit lines are insulated from each other; A plurality of capacitor openings are formed in a first substrate, and the top of the capacitor openings is exposed on the second surface. The width of the capacitor openings is greater than the width of the gate. A plurality of capacitors are formed within the capacitor opening, and the projection of each capacitor on the second surface at least partially overlaps with the projection of a second doped region on the second surface. The formation of the capacitors includes: forming a first capacitor electrode layer on the sidewall surface and bottom surface of the capacitor opening; forming a capacitor dielectric layer on the surface of the first capacitor electrode layer; and forming a second capacitor electrode layer on the surface of the capacitor dielectric layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the capacitor includes: after forming a plurality of word lines and bit lines, etching the second surface to form a plurality of capacitor openings in the first substrate, wherein the projection of the capacitor openings on the second surface at least partially overlaps with the projection of a second doped region on the second surface; forming a first capacitor electrode layer on the inner wall surface of each capacitor opening; forming a capacitor dielectric layer on the surface of the first capacitor electrode layer; and forming a second capacitor electrode layer on the surface of the capacitor dielectric layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, Also includes: After forming several word lines and bit lines, and before forming several capacitor openings, the second surface is thinned.

19. The method for forming a semiconductor structure as described in claim 16, characterized in that, The first substrate also has an isolation structure extending from a first surface toward a second surface. The isolation structure is located between adjacent first doped regions and between adjacent second doped regions. The first surface exposes the top surface of the isolation structure.

20. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method of forming the gate includes: etching the first surface to form a plurality of first openings in the first substrate, each first opening penetrating a first doped region and a second doped region; forming a dielectric material layer in the first openings and the first surface; forming an electrode material layer on the surface of the dielectric material layer, wherein the surface of the electrode material layer is higher than the first surface; forming a plurality of first mask structures on the surface of the electrode material layer, each first mask structure covering at least one first opening and exposing at least a portion of the electrode material layer surface on the first doped region; and etching the electrode material layer and the dielectric material layer using the plurality of first mask structures as masks until the first surface is exposed.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The method of forming a plurality of word lines includes: forming a word line material layer on the surface of the electrode material layer before forming a plurality of the first mask structures; and etching the word line material layer using the plurality of the first mask structures as masks until the surface of the electrode material layer is exposed before etching the electrode material layer.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, Also includes: After the word line is formed but before the bit line is formed, a first dielectric structure is formed on the first surface, the surface of the first dielectric structure being higher than the surface of the word line.

23. The method for forming a semiconductor structure as described in claim 22, characterized in that, The method for forming the bit line includes: forming a plurality of second openings within the first dielectric structure, each second opening exposing at least a portion or all of the surface of a first doped region; forming a bit line material layer within the second openings and on the surface of the first dielectric structure; forming a plurality of second mask structures on the surface of the bit line material layer, each second mask structure covering at least one second opening; and etching the bit line material layer using the second mask structures as masks until the surface of the first dielectric structure is exposed.

24. The method for forming a semiconductor structure as described in claim 16, characterized in that, Also includes: After the gate and word lines are formed, and before the bit lines are formed, a contact layer is formed on the surface of a plurality of the first doped regions.

25. The method for forming a semiconductor structure as described in claim 24, characterized in that, The top surface of the electrode layer is higher than the first surface; The method for forming the semiconductor structure further includes: forming a sidewall on the electrode layer sidewall surface on the first surface before forming the contact layer.

26. The method for forming a semiconductor structure as described in claim 16, characterized in that, The extension direction of the bit line is perpendicular to the extension direction of the word line.

27. The method for forming a semiconductor structure as described in claim 16, characterized in that, The first substrate includes a memory region, and the word line, bit line, gate, and capacitor are located in the memory region.

28. The method for forming a semiconductor structure as described in claim 27, characterized in that, The first substrate further includes a first logic region, and the first logic circuit is located within the first logic region.

29. The method for forming a semiconductor structure as described in claim 28, characterized in that, Also includes: A second substrate is provided, wherein a second logic circuit is present in the second substrate, and the second substrate also has opposing functional and non-functional surfaces; After the gate, word line, and bit line are formed, and before the capacitor is formed, the first substrate and the second substrate are bonded together, the first surface faces the functional surface, and the second logic circuit is electrically connected to the first logic circuit.

30. The method for forming a semiconductor structure as described in claim 29, characterized in that, Also includes: After the gate, the word line, and the bit line are formed, and before the first substrate and the second substrate are bonded, a second dielectric structure is formed on the bit line surface and the first surface, the surface of the second dielectric structure being higher than the bit line surface; A first conductive layer is formed within the second dielectric structure, the first conductive layer is connected to the first logic circuit, and the surface of the second dielectric structure exposes the first conductive layer.

31. The method for forming a semiconductor structure as described in claim 16, characterized in that, Also includes: A second substrate is provided, wherein a second logic circuit is present in the second substrate, and the second substrate also has opposing functional and non-functional surfaces; After the gate, word line, and bit line are formed, and before the capacitor is formed, the first substrate and the second substrate are bonded together, the first surface facing the functional surface, and the second logic circuit is electrically connected to the bit line.

32. The method for forming a semiconductor structure as described in claim 31, characterized in that, Also includes: After the gate, the word line, and the bit line are formed, and before the first substrate and the second substrate are bonded, a second dielectric structure is formed on the bit line surface and the first surface, the surface of the second dielectric structure being higher than the bit line surface; A first conductive layer is formed within the second dielectric structure, the first conductive layer is connected to the bit line, and the surface of the second dielectric structure exposes the first conductive layer.

33. The method for forming a semiconductor structure as described in claim 32, characterized in that, Also includes: A third dielectric structure is formed on the functional surface before the first substrate is bonded to the second substrate; A second conductive layer is formed within the third dielectric structure, the second conductive layer is electrically connected to the second logic circuit, the surface of the third dielectric structure exposes the second conductive layer, and after the first substrate and the second substrate are bonded, the projection of the first conductive layer on the first surface at least partially overlaps with the projection of the second conductive layer on the first surface.

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