Semiconductor structure and manufacturing method

Abstract

This invention relates to a semiconductor structure and a method for manufacturing the same. The method includes: providing a substrate; forming a stacked layer over the substrate, the stacked layer including a core memory region and a step region, the step region including a connection region and at least one partitioned step region, the connection region connecting each partitioned step region and the core memory region; forming an initial mask pattern covering the connection region and each partitioned step region, and the initial mask pattern forming an opening in each partitioned step region; forming an initial step structure in each partitioned step region that gradually increases in elevation from the opening; and dividing the initial step structure in each partitioned step region into N sub-step regions, and processing the N sub-step regions to form N sub-step structures, wherein the N sub-step structures have different depths in the stacked layer. The manufacturing method according to this invention can simultaneously form multi-layered step structures on a limited wafer area, with low process complexity and cost savings.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and more particularly to a semiconductor device comprising multiple sub-step structures in a partitioned step region and a method for manufacturing the same. Background Technology

[0002] To overcome the limitations of two-dimensional memory devices, the industry has developed memory devices with three-dimensional (3D) structures, which improve integration by arranging memory cells three-dimensionally on a substrate.

[0003] In three-dimensional memory such as 3D NAND flash memory, the memory array may include a core region and a staircase step region. The staircase step region includes multiple steps, each used to lead contacts from the control gate layer in the memory array, thereby connecting the memory array to the gate control line. However, as the number of layers in 3D NAND flash memory increases, from 32 to 128 layers in the manufacturing process, forming the steps requires a large wafer area, resulting in a waste of effective wafer area. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a semiconductor device comprising multiple sub-step structures in a partitioned step region and a method thereof.

[0005] The present invention provides a method for manufacturing a semiconductor structure to solve the aforementioned technical problems, comprising: providing a substrate; forming a stacked layer on the substrate, the stacked layer including a core memory region and a step region, the step region including a connection region and at least one partitioned step region, the connection region being used to connect each partitioned step region and the core memory region; forming an initial mask pattern covering the connection region and each partitioned step region, and the initial mask pattern forming an opening in each partitioned step region; forming an initial step structure in each partitioned step region that gradually rises from the opening to the surrounding areas; and dividing the initial step structure in each partitioned step region into N sub-step regions, and processing the N sub-step regions to form N sub-step structures, wherein the N sub-step structures are at different depths in the stacked layer.

[0006] In one embodiment of the present invention, the step of processing the N sub-step regions to form N sub-step structures includes: forming a first mask pattern that covers the connection region and a portion of the N sub-step regions and exposes the remaining sub-step regions in the N sub-step regions; and etching the exposed sub-step regions to reduce the exposed sub-step regions by a first predetermined number of layers.

[0007] In one embodiment of the present invention, the step of processing the N sub-step regions to form N sub-step structures further includes: forming a second mask pattern, the second mask pattern covering the connection region and a portion of the N sub-step regions, and exposing the remaining sub-step regions, wherein the sub-step regions covered by the second mask pattern partially overlap with the sub-step regions covered by the first mask pattern; and etching the exposed sub-step regions to reduce the exposed sub-step regions by a second predetermined number of layers.

[0008] In one embodiment of the present invention, the step region includes at least two partitioned step regions, and the step of processing the N sub-step regions in each partitioned step region to form N sub-step structures in each partitioned step region further includes: forming a third mask pattern that covers the connection region and a portion of the partitioned step regions in the at least two partitioned step regions, exposing the remaining partitioned step regions; and etching the exposed partitioned step regions to reduce the exposed partitioned step regions by a third predetermined number of layers.

[0009] In one embodiment of the present invention, N=4, and the four sub-step regions located in the same partition step region are distributed in a matrix array. The first mask pattern covers the connecting region and two sub-step regions located in one row, and the second mask covers the connecting region and two sub-step regions located in one column.

[0010] In one embodiment of the present invention, the first predetermined number of layers, the second predetermined number of layers, and the third predetermined number of layers are all equal to the current total number of steps in the partitioned step area.

[0011] In one embodiment of the present invention, the at least two partitioned step areas are distributed on both sides of the connecting area.

[0012] To address the aforementioned technical problems, this invention also proposes a semiconductor structure, characterized in that it comprises: a substrate; a stacked layer located above the substrate, the stacked layer including a core memory region and a step region, the step region including a connection region and at least one partitioned step region, the connection region connecting each partitioned step region and the core memory region; each partitioned step region including N sub-step regions, each sub-step region forming a sub-step structure that gradually rises from the interior of the partitioned step region to the surrounding area, and the N sub-step structures within the same partitioned step region having different depths in the stacked layer.

[0013] In one embodiment of the present invention, the connecting area divides the step area into multiple partitioned step areas distributed in a matrix array.

[0014] In one embodiment of the present invention, the number of steps in the N sub-step structures is equal.

[0015] In one embodiment of the present invention, the N sub-step regions have equal coverage areas.

[0016] In one embodiment of the present invention, N=4, and the four sub-step areas located in the same partition step area are distributed in a matrix array.

[0017] In one embodiment of the present invention, the step region includes at least two partitioned step regions, wherein the sub-step structures in the at least two different partitioned step regions are at different depths in the stacked layer.

[0018] In one embodiment of the present invention, the partitioned step area is circular or rectangular.

[0019] In one embodiment of the present invention, the semiconductor structure includes a three-dimensional memory, and the stepped region is used to lead out word lines.

[0020] According to the semiconductor structure manufacturing method of the present invention, a multi-layer stepped structure can be formed simultaneously on a limited wafer area; no special hard mask is required to cover the connection area, reducing the complexity, difficulty and cost of the process; the formed semiconductor structure includes sub-step structures that gradually rise from the inside of the partitioned step area to the surrounding area, and the multiple sub-step structures are compactly distributed, so that a multi-layer stepped structure can be realized in a limited area, which greatly saves wafer area; multiple sub-step structures can be connected to the core memory area through the connection area. Attached Figure Description

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0022] Figure 1A It is a top view of a three-dimensional memory;

[0023] Figure 1B yes Figure 1A The three-dimensional memory shown is a side sectional view along AA'.

[0024] Figure 2A-2C This is a schematic diagram illustrating the process of forming a stepped structure in a semiconductor structure.

[0025] Figure 3 This is an exemplary flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention;

[0026] Figures 4A-4C This is a schematic diagram of a manufacturing method for a three-dimensional memory according to an embodiment of the present invention;

[0027] Figures 5A-5F This is a schematic diagram of a manufacturing method for a three-dimensional memory according to an embodiment of the present invention;

[0028] Figures 6A-6CThis is a schematic diagram of a manufacturing method for a three-dimensional memory according to an embodiment of the present invention;

[0029] Figures 7A-7C This is a schematic diagram of a manufacturing method for a three-dimensional memory according to an embodiment of the present invention;

[0030] Figures 8A-8C This is a schematic diagram of a manufacturing method for a three-dimensional memory according to an embodiment of the present invention;

[0031] Figures 9A-9C This is a schematic diagram of a manufacturing method for a three-dimensional memory according to an embodiment of the present invention;

[0032] Figures 10A-10C This is a schematic diagram of a method for manufacturing a semiconductor structure according to another embodiment of the present invention;

[0033] Figure 11 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0034] Figure 12 This is a schematic diagram of a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Numerous specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the invention is not limited to the specific embodiments disclosed below.

[0037] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0038] In describing the embodiments of the present invention in detail, for ease of explanation, the cross-sectional views illustrating the device structure will be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0039] For ease of description, spatial relation terms such as “below,” “below,” “lower than,” “below,” “above,” “upper,” etc., may be used herein to describe the relationship of an element or feature shown in the accompanying drawings to other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, the orientation of an element described as “below,” “below,” or “below” to other elements or features will change to “above” said other elements or features. Thus, the exemplary terms “below” and “below” can encompass both upward and downward directions. The device may also have other orientations (rotated 90 degrees or in other orientations), and therefore the spatial relation descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between.

[0040] In the context of this application, the structure described above the second feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0041] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be construed as limiting the scope of protection of this application.

[0042] As used herein, the term "three-dimensional (3D) memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0043] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations may be added to these processes, or one or more steps may be removed from these processes.

[0044] As used herein, "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0045] As used in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes thereon. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0046] Figure 1A It is a top view of a three-dimensional memory. Figure 1B yes Figure 1A The three-dimensional memory shown is a side sectional view along AA'. (Refer to reference...) Figure 1A and 1B As shown, the three-dimensional memory includes a core storage area 110 and a step area 120. Figure 1A The diagram shows mutually perpendicular X and Y directions. (For example...) Figure 1A As shown, step regions 120 are distributed around the core memory region 110. Specifically, two step regions 121 and 122 are distributed on the left and right sides of the core memory region 110 along the X direction, respectively, and two virtual step regions 123 and 124 are distributed on the top and bottom sides of the core memory region 110 along the Y direction, respectively. The virtual step regions 123 and 124 are formed along with the step regions 121 and 122 during the process of forming step regions 120. The virtual step regions 123 and 124 do not serve any actual function, thus resulting in a waste of wafer area. (Reference) Figure 1B As shown, the step regions 121 and 122 are not actually fully utilized, and their area can be further reduced to save wafer area and improve the integration density of the three-dimensional memory.

[0047] Figure 2A-2C This is a schematic diagram illustrating the process of forming a stepped structure in a semiconductor structure. (Reference) Figure 2AAs shown, the semiconductor structure 201 includes a stacked structure 210 formed on a substrate, which may be formed by alternating stacks of a first material layer and a second material layer. For example, it may be formed by alternating stacks of a gate layer (also called a "sacrificial layer") and a dielectric layer. A gate layer and a dielectric layer may form a dielectric layer pair. The stacked structure 210 may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0048] The stacked structure 210 is divided at its upper surface 211 into a stepped region 220 for forming a stepped structure and a connection region for connecting the stepped region 220 and the core storage area (not shown). Figure 2A The semiconductor structure 201 shown includes three connection regions, each elongated in shape. A step region 220 separates two adjacent connection regions. To form the step structure within the step region 220, a hard mask 230 is needed to cover the connection regions to prevent unnecessary damage. Figure 2A As shown, this includes three hard masks 230, each of which is also elongated and covers the three connecting regions respectively. The hard masks 230 protrude from the upper surface 211.

[0049] refer to Figure 2B As shown, to form the stepped structure, a photoresist layer 221 is applied to the stepped region 220. This photoresist layer 221 not only covers the stepped region 220 but also overlaps the hard mask 230. Figure 2A and Figure 2B As shown, Figure 2A The semiconductor structure 201 shown is Figure 2B A portion of the semiconductor structure 202 shown. (As shown) Figure 2B As shown, in the semiconductor structure 202, multiple step regions 220 are covered under multiple photoresist layers 221 to facilitate the simultaneous formation of step structures in multiple step regions 220.

[0050] In embodiments of the present invention, the method for forming the step structure can be a trim / etch cycle process, also known as a trim-etch process, an etch trim process, etc. This trim-etch cycle process includes alternating cycles of etching and trimming processes. During the etching process, a portion of each step with an exposed surface can be obtained. The etching depth is determined by the thickness of the step. In some embodiments, the thickness of the step can be the thickness of an alternating pair of dielectric layers. In this example, the etching process for the dielectric layer can have high selectivity relative to the sacrificial layer, and / or vice versa. Accordingly, the underlying alternating pair of dielectric layers can act as an etching stop layer. Therefore, one step can be formed during each trim-etch cycle.

[0051] In some embodiments, anisotropic etching, such as reactive ion etching (RIE) or other dry etching processes, can be used to etch the stepped structure. In some embodiments, the dielectric layer is silicon oxide. In this example, etching of silicon oxide may include RIE using a fluorine-based gas and / or any other suitable gas, for example, the fluorine-based gas may be carbon fluoride (CF4), hexafluoroethane (C2F6), CHF3, or C3F6. In some embodiments, the silicon oxide layer can be removed by a wet chemical agent, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etching scheme can be used. In some embodiments, the sacrificial layer is silicon nitride. In this example, etching of silicon nitride may include RIE using O2, N2, CF4, NF3, Cl2, HBr, BCl3, and / or combinations of gases. The methods and etchants used to remove individual stacks should not be limited to the embodiments of the present invention.

[0052] The trimming process includes performing an appropriate etching process (e.g., isotropic dry etching or wet etching) on ​​the photoresist layer 221 in a direction parallel to the surface of the substrate. The trimming process gradually trims the boundary of the photoresist layer 221 from the outside to the inside. Figure 2B As shown, the photoresist layer 221 gradually shrinks in the X direction after being trimmed. The trimmed photoresist layer 221 is then used to perform the etching process described above on the stacked structure of the step region 220. The step formed after this etching step forms a continuous step structure with the step formed in the previous etching step.

[0053] After the above-described trimming and etching cycle process, a result such as Figure 2C The stepped structures 222 and 223 are shown. Also, as... Figure 2C As shown, a connecting area 231 is included between the step structures 222 and 223.

[0054] exist Figure 2A-2CThe step structure formation process shown requires the use of a hard mask to protect the connection area and prevent it from being damaged during the formation of the step structure. This method involves complex process steps and increases the difficulty of the manufacturing process.

[0055] Figure 3 This is an exemplary flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention. Figures 4A-4C This is a schematic diagram illustrating the manufacturing process of a three-dimensional memory according to an embodiment of the present invention. The following is in conjunction with... Figure 3 and Figures 4A-4C The manufacturing method of this embodiment will be described. (See reference...) Figure 3 As shown, the manufacturing method of this embodiment includes the following steps:

[0056] Step S310: Provide a substrate.

[0057] refer to Figure 4A As shown, the semiconductor structure 401 includes a substrate 411, which can be a silicon substrate (Si), a germanium substrate (Ge), a silicon germanide substrate (SiGe), silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. In some embodiments, the substrate 411 can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc. It can also be a stacked structure, such as Si / SiGe, etc. It can also include other epitaxial structures, such as silicon-germanium-on-insulator (SGOI), etc. In some embodiments, the substrate 411 can be made of a non-conductive material, such as glass, plastic, or sapphire wafer, etc. The substrate 411 shown in FIG. 5 may have undergone some necessary processing, such as forming a common active region and undergoing necessary cleaning, etc.

[0058] Step S320: A stacked layer is formed over the substrate, the stacked layer including a core memory region and a step region, the step region including a connection region and at least one partitioned step region, the connection region being used to connect each partitioned step region and the core memory region.

[0059] refer to Figure 4AAs shown, a stacked layer 410 is formed above the substrate 411. The stacked layer 410 may be a stack of alternating first and second material layers. The first and second material layers may be selected from materials including at least one insulating medium, such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and combinations thereof. The first and second material layers have different etching selectivity. For example, they may be a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polycrystalline or amorphous silicon, or a combination of silicon oxide or silicon nitride and amorphous carbon. The deposition method of the first and second material layers of the stacked structure may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE), thermal oxidation, evaporation, sputtering, and various other methods. The first material layer may be a gate layer or a dummy gate layer, and the second material layer may be a dielectric layer. The material used as the gate sacrificial layer may be, for example, a silicon nitride layer. The material used as the gate layer can be a conductive material such as tungsten, cobalt, copper, nickel, etc., or it can be polycrystalline silicon, doped silicon, or any combination thereof. The material used as the dielectric layer can be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc.

[0060] In embodiments of the present invention, the substrate 411 is made of, for example, silicon. The first material layer and the second material layer are, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, silicon nitride and silicon oxide can be alternately deposited on the substrate 411 sequentially using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods to form a stacked layer 410. The pair of film layers consisting of the first material layer and the second material layer is referred to as a dielectric layer pair.

[0061] Although an exemplary configuration of the initial semiconductor structure has been described herein, it is understood that one or more features may be omitted, substituted, or added to this semiconductor structure. For example, various well regions may be formed in the substrate as needed. Furthermore, the materials of the layers described are merely exemplary; for example, substrate 411 could also be other silicon-containing substrates, such as SOI (silicon-on-insulator), SiGe, Si:C, etc. The gate layer could also be other conductive layers, such as tungsten, cobalt, nickel, etc. The second material layer could also be other dielectric materials, such as aluminum oxide, hafnium oxide, tantalum oxide, etc.

[0062] In an embodiment of the present invention, the stack layer 410 includes a core storage area and a step area. Figure 4A This diagram primarily illustrates the method for forming a stepped structure; therefore, the core storage area is omitted, and only the stepped area is shown. The core storage area can be formed around this stepped area.

[0063] In one embodiment, reference Figure 4AAs shown, the step area includes a connecting area 420 and two partitioned step areas, which means that the connecting area 420 divides the step area into two partitioned step areas. Figure 4A Taking two partitioned step regions as an example, this method is also applicable to semiconductor structures that include one or more partitioned step regions.

[0064] Figure 4A The approximate location of the connection area 420 is outlined with a dashed box. Because... Figure 4A The semiconductor structure 401 also includes an initial mask pattern 440 covering the stacked layer 410. Therefore, the connection region 420 is actually the area in the stacked layer 410 defined by the dashed box. Figure 4A It is not used to limit the number and location of the connection areas 420. In other embodiments, it can be as follows: Figure 2A-2C The diagram shows multiple connection zones, with adjacent connection zones separated by partitioned step zones.

[0065] Figure 4A The diagram shows two partition step areas 431 and 432, which are located on opposite sides of the connection area 420. In other embodiments, the two partition step areas may also be located on the same side of the connection area 420. The connection area 420 is used to connect the at least two partition step areas 431 and 432 and the core storage area.

[0066] Step S330: Form an initial mask pattern that covers the connection area and each partition step area, and form an opening in each partition step area.

[0067] refer to Figure 4A As shown, an initial mask pattern 440 is formed above the stacked layer 410. The initial mask pattern 440 covers the connection area 420 and two partition step areas 431 and 432. The initial mask pattern 440 forms an opening 441 in the partition step area 431 and an opening 442 in the partition step area 432.

[0068] The initial mask pattern 440 can be a photoresist layer with the desired opening pattern.

[0069] exist Figure 4A In the embodiment shown, openings 441 and 442 are located at the center of partitioned step areas 431 and 432, respectively, and openings 441 and 442 are square.

[0070] In other embodiments, the opening may not be located at the center of the partitioned step area, but the location of the opening should ensure that there are enough stacked layers extending outwards from the opening to form the desired step structure.

[0071] Figure 4AThe shapes of openings 441 and 442 are not used to limit the shape of the openings. In other embodiments, openings 441 and 442 can also be circular, elliptical, rectangular, or other shapes.

[0072] Step S340: In each partitioned step area, an initial step structure is formed that gradually rises from the opening in all directions.

[0073] This step can be implemented using the trimming etching cycle described above, and will not be repeated here.

[0074] refer to Figure 4B As shown, according to Figure 4A The initial mask pattern 440 shown is subjected to a trimming etching cycle at the opening of the partitioned step area, thereby forming initial step structures 451 and 452 that gradually rise outwards from the openings 441 and 442, respectively. Figure 4A The semiconductor structure 402 is shown. Since the openings 441 and 442 are square, the resulting initial stepped structures 451 and 452 expand outwards from the square openings, forming a structure similar to a football stadium stands. Taking the square opening 441 as an example, the initial stepped structure 451 formed around this opening 441 includes four sides: 451a, 451b, 451c, and 451d. After etching, arc-shaped fan-shaped boundary regions are formed at the intersections of the four sides. For example, the fan-shaped boundary region 451ad at the intersection of sides 451a and 451d.

[0075] For a circular opening, the resulting initial stepped structure is still roughly circular.

[0076] In this embodiment, the thickness of each step is the thickness of a dielectric layer pair. A layer or a step refers to a step obtained by etching a dielectric layer pair.

[0077] In this step, a predetermined number of trimming etching cycles can be performed to obtain a corresponding number of initial steps. The present invention does not limit the predetermined number of initial trimming etching cycles. In some embodiments, the predetermined number can be 2-8 times. Preferably, the predetermined number is 8 times, which is equivalent to sequentially trimming the initial mask pattern 440 7 times, and sequentially etching 8 times according to the total of 8 mask patterns (the initial mask pattern 440 plus the 7 trimmed mask patterns), thereby forming an initial step structure with 8 steps.

[0078] Step S350: Divide the initial step structure in each partition step area into N sub-step areas, and process the N sub-step areas to form N sub-step structures, wherein the N sub-step structures have different depths in the stacking layer.

[0079] refer to Figure 4CAs shown, in this embodiment, N=4. Taking the initial step structure 451 as an example, the initial step structure 451 is divided into four sub-step regions, namely sub-step regions 461, 462, 463, and 464. These four sub-step regions 461, 462, 463, and 464 are processed to form four sub-step structures, which have different depths in the stacked layer 410. Figure 4C As shown, the depth of the four sub-step structures decreases sequentially in the stacked layer 410.

[0080] In some embodiments, the number of steps in the N sub-step structures is the same.

[0081] exist Figure 4C In the embodiment shown, the four sub-step structures of the four sub-step areas 461, 462, 463, and 464 have the same number of steps, for example, eight steps each.

[0082] The depth of a sub-step structure refers to its overall position within the stacked layer 410. For example, the sub-step structures in sub-step region 461 are located at layers 1-8, those in sub-step region 462 at layers 9-16, those in sub-step region 463 at layers 17-24, and those in sub-step region 464 at layers 25-32. The depths of each sub-step structure do not overlap within the stacked layer 410. In this invention, the position or number of steps is defined as layer 1, located at the top of the semiconductor structure, with the number of steps increasing sequentially downwards along a direction perpendicular to the substrate.

[0083] In some embodiments, the N sub-step structures are at different depths in the stacking layer 410, but may partially overlap. For example, the sub-step structures in one sub-step area are located at layers 1-8, and the sub-step structures in another sub-step area are located at layers 5-12, etc.

[0084] In embodiments of the present invention, the depth of the sub-step structures in different partitioned step areas within the stacked layer may also be different.

[0085] exist Figure 4C In the illustrated embodiment, the depth of the four sub-step structures formed according to the initial step structure 451 in the stacked layer 410 in the partitioned step region 431 differs from the depth of the four sub-step structures formed according to the initial step structure 452 in the stacked layer 410 in the partitioned step region 432. For example, the depth of the four sub-step structures in the stacked layer 410 in the partitioned step region 431 is 1-32 layers, while the depth of the four sub-step structures in the stacked layer 410 in the partitioned step region 432 is 33-64 layers. The depths of the step structures in the partitioned step regions 431 and 432 do not overlap in the stacked layer 410.

[0086] In other embodiments, the step structures in different partitioned step areas have different depths in the stacked layer 410, but may partially overlap.

[0087] In other embodiments, the number of steps in the N sub-step structures can also be different. For example, some sub-step structures may have the same number of steps, some may have different numbers of steps, or all of them may be different.

[0088] exist Figure 4C In the embodiment shown, the connection area 420 is located between two partition step areas and is connected to the core storage area so that the two partition step areas are connected to the core storage area.

[0089] Figures 4A-4C This is not intended to limit the number of partitioned step regions in the three-dimensional memory of the present invention, the number of sub-step regions included in each partitioned step region, and the number of steps in the sub-step structures formed in the sub-step regions.

[0090] This invention does not limit the method of processing N sub-step regions to form N sub-step structures. Those skilled in the art can use methods in the field based on this idea to form the sub-step structure claimed by this invention.

[0091] In some embodiments, the step of processing N sub-step regions to form N sub-step structures includes:

[0092] Step S352: Form a first mask pattern, which covers the connecting area and a portion of the N sub-step areas, and exposes the remaining sub-step areas among the N sub-step areas.

[0093] In some embodiments, N is an even number, and the first mask pattern in this step covers the connection area and half of the N sub-step areas, while exposing the other half of the sub-step areas. In some embodiments, N=4, and the four sub-step areas located in the same partition step area are distributed in a matrix array, with the first mask pattern covering the connection area and two sub-step areas located in one row.

[0094] refer to Figure 5A As shown, the semiconductor structure 501 is equivalent to Figure 4BThe semiconductor structure 402 shown includes two partitioned step regions 511 and 512, each of which has an initial step structure already formed. In this embodiment, N=4, and each initial step structure is divided into four sub-step regions. These four sub-step regions are distributed in a 2*2 matrix array within the partitioned step regions. A first mask pattern 520 covers half of the sub-step regions 521 in partitioned step region 511, that is, it covers two sub-step regions located in one row, exposing the other half of the sub-step regions in partitioned step region 511. Simultaneously, the first mask pattern 520 covers half of the sub-step regions 522 in partitioned step region 512, that is, it covers two sub-step regions located in one row, exposing the other half of the sub-step regions in partitioned step region 512. Figure 5A As shown, half-step region 521 includes two sub-step regions, which are located in the same row of the matrix array; half-step region 522 also includes two sub-step regions, which are located in the same row of the matrix array. Half-step regions 521 and 522, covered by the first mask pattern 520, are distributed on both sides of the connecting region 530. Therefore, the first mask pattern 520 also covers the connecting region 530. Etching the sub-step regions according to the first mask pattern 520 can protect the connecting region 530 from etching damage.

[0095] Figure 5A In the illustrated embodiment, the first mask pattern 520 is rectangular. In other embodiments, the first mask pattern 520 may also be other shapes.

[0096] Step S354: Etch the exposed sub-step region to reduce the exposed sub-step region by a first predetermined number of layers.

[0097] refer to Figure 5B As shown, after etching, Figure 5A After the first mask pattern 520 is removed, the height of the other half of the sub-step region 523 exposed in the partitioned step region 511 is obviously lower than that of the sub-step region 521 covered by the first mask pattern 520 after etching; the height of the other half of the sub-step region 524 exposed in the partitioned step region 512 is obviously lower than that of the sub-step region 522 covered by the first mask pattern 520 after etching.

[0098] The present invention does not limit the number of the first predetermined layers. It can be 2-8 layers. In a preferred embodiment, the first predetermined layer number is equal to the current total number of steps in the partitioned step area. In this specification, taking a predetermined number of times equal to 8 as an example, the total number of steps in the partitioned step area before etching in step S354 is 8 layers, so the first predetermined layer number in step S354 is also 8.

[0099] After this etching step, the number of steps in sub-step regions 521 and 522 is 1-8, and the number of steps in sub-step regions 523 and 524 is 9-16. That is, the number of steps in sub-step regions 523 and 524 is 8 steps lower than the number of steps in sub-step regions 521 and 522.

[0100] In some embodiments, the step of processing N sub-step regions to form N sub-step structures may further include:

[0101] Step S356: Form a second mask pattern, which covers the connecting area and a portion of the N sub-step areas, and exposes the remaining half of the sub-step areas. The sub-step areas covered by the second mask pattern partially overlap with the sub-step areas covered by the first mask pattern.

[0102] In some embodiments, if N is an even number, the second mask pattern in this step covers the connection area and half of the N sub-step areas, and exposes the other half of the sub-step areas.

[0103] In some embodiments, N=4, and the four sub-step regions located in the same partition step region are distributed in a matrix array. The first mask pattern covers the connecting region and two sub-step regions located in one row, and the second mask covers the connecting region and two sub-step regions located in one column.

[0104] refer to Figure 5C As shown, the second mask pattern 540 covers half of the sub-step region 541 in the partitioned step region 511, exposing the other half of the sub-step region 511. Simultaneously, the second mask pattern 540 covers half of the sub-step region 542 in the partitioned step region 512, exposing the other half of the sub-step region 512. It should be noted that the half of the sub-step region 541 here is relative to... Figure 5A For half of the sub-step region 521, it is located in the same column of the matrix array; for half of the sub-step region 542, it is relative to Figure 5A For half of the sub-step region 522, it is located in the same column of the matrix array. Since N=4 in this embodiment, the half of the sub-step region 541 covered by the second mask pattern 540 includes 2 sub-step regions, and the half of the sub-step region 542 also includes 2 sub-step regions. The half of the sub-step region 541 and the half of the sub-step region 542 covered by the second mask pattern 540 are distributed on both sides of the connecting region 530.

[0105] According to this step, the second mask pattern 540 and the first mask pattern 520 overlap in one of their covered sub-step regions. (See reference) Figure 5DAs shown, both the first mask pattern 520 and the second mask pattern 540 cover the sub-step regions 541a and 542a. Furthermore, both the first mask pattern 520 and the second mask pattern 540 cover the connecting region 530.

[0106] In some embodiments, the N sub-step regions have equal areas. Accordingly, the size and shape of the portion 540a of the sub-step region covered by the first mask pattern 520 and the second mask pattern can be the same.

[0107] Step S358: Etch the exposed sub-step region, causing the exposed sub-step region to descend by a second predetermined number of layers.

[0108] refer to Figure 5D As shown, after etching, Figure 5C The second mask pattern 540 is removed, and after etching, the height of the other half of the sub-step region 543 exposed in the partitioned step region 511 is obviously lower than that of the sub-step region 541 covered by the second mask pattern 540; after etching, the height of the other half of the sub-step region 544 exposed in the partitioned step region 512 is obviously lower than that of the sub-step region 542 covered by the second mask pattern 540.

[0109] In some embodiments, the second predetermined number of layers is equal to the current total number of steps in the partitioned step area.

[0110] exist Figure 5A In the illustrated embodiment, the total number of existing steps in each partition step area is 8, therefore the first predetermined number of etching layers is also 8. Figure 5C In the embodiment shown, the total number of steps already existing in each partition step area is 16, therefore the second predetermined number of etching layers is 16.

[0111] refer to Figure 5D As shown, after etching in step S358, the number of steps in sub-step regions 541 and 542 is 1-16, and the number of steps in sub-step regions 543 and 544 is 17-32. Further subdivided, in sub-step area 541, sub-step area 541a is located at step levels 1-8, and sub-step area 541b is located at step levels 9-16; in sub-step area 542, sub-step area 542a is located at step levels 1-8, and sub-step area 542b is located at step levels 9-16; in sub-step area 543, sub-step area 543a is located at step levels 17-24, and sub-step area 543b is located at step levels 25-32; in sub-step area 544, sub-step area 544a is located at step levels 17-24, and sub-step area 544b is located at step levels 25-32. Each sub-step area can be connected to the core storage area through connection area 530.

[0112] Thus, the following was formed: Figure 5D The semiconductor structure 504 shown is a compact stepped structure that makes full use of the space of the stacked layers, reducing the waste of wafer area.

[0113] exist Figure 5C and 5D In the illustrated embodiment, N = 4. In other embodiments, such as N = 6, the partition step is divided into 6 sub-step areas with equal areas. Steps S356 and S358 are repeated twice, each time changing the position of the mask pattern. Each time, the mask pattern partially overlaps with the sub-step area covered by the previous mask pattern, thus forming a corresponding sub-step structure within the 6 sub-step areas. When N = 8, the partition step is divided into 8 sub-step areas with equal areas. Steps S356 and S358 are repeated four times, each time changing the position of the mask pattern. Each time, the mask pattern partially overlaps with the sub-step area covered by the previous mask pattern, thus forming a corresponding sub-step structure within the 8 sub-step areas. And so on.

[0114] For cases where N is odd, such as N=3, the partition step is divided into 3 sub-step regions. S356 and S358 can be executed repeatedly, changing the position of the mask pattern each time and etching one of the 3 sub-step regions each time. And so on.

[0115] In some embodiments, for cases comprising at least two partitioned step regions, the step of processing N sub-step regions in each partitioned step region to form N step structures in each partitioned step region may further include:

[0116] Step S360: Form a third mask pattern that covers the connection area and a portion of the at least two partitioned step areas, exposing the remaining partitioned step areas.

[0117] refer to Figure 5E As shown, the third mask pattern 550 covers one of the two partitioned step areas 511, exposing the other partitioned step area 512. Since the partitioned step areas in this embodiment are formed by square openings, the portion of the third mask pattern 550 that exposes the partitioned step area 512 is also a square opening, the size of which exposes all the sub-step structures formed in the partitioned step area 512.

[0118] like Figure 5E As shown, the third mask pattern 550 simultaneously covers the connecting area 530.

[0119] Step S362: Etch the exposed partition step area, causing the exposed partition step area to descend by a third predetermined number of layers.

[0120] exist Figure 5E In the embodiment shown, the current total number of steps in the partitioned step area 512 is 32, therefore, the third predetermined number of layers to be etched in step S362 is 32.

[0121] refer to Figure 5F As shown, after etching, the steps in the partitioned step area 512 are etched downwards in 32 layers. Among them, the number of step layers in sub-step area 551 is 33-40, the number of step layers in sub-step area 552 is 41-48, the number of step layers in sub-step area 553 is 49-56, and the number of step layers in sub-step area 554 is 57-64.

[0122] After the above steps, the number of steps in partitioned step area 511 is 1-32, and the number of steps in partitioned step area 512 is 33-64. Together, partitioned step area 511 and partitioned step area 512 form a step area with a 64-layer step structure.

[0123] According to the manufacturing method of the present invention, a multi-layered stepped structure can be formed simultaneously on a limited wafer area; it eliminates the need for a special hard mask to cover the connection area, reducing the complexity and difficulty of the process and lowering costs; the formed stepped structure is compact, greatly saving wafer area.

[0124] The following describes the manufacturing method of the semiconductor structure of the present invention using an example of a step region comprising four partitioned step regions, where N=4. Since the manufacturing method of the four partitioned step regions is similar to the manufacturing method of the two partitioned step regions described above, the preceding description can be used to illustrate the specific embodiments below, and repeated content will not be elaborated upon.

[0125] Step S370: Provide a substrate.

[0126] Step S372: A stacked layer is formed on the substrate. The stacked layer includes a core memory region and a step region. The step region includes a connection region and four partitioned step regions. The connection region is used to connect the four partitioned step regions and the core memory region.

[0127] refer to Figure 6A As shown, the semiconductor structure 601 includes a substrate 611 and a stacked layer 610 formed on the substrate 611. In this semiconductor structure 601, the step region includes a connection region 620 and four partitioned step regions 631, 632, 633, and 634, wherein partitioned step regions 631 and 633 are located on one side of the connection region 620, and step regions 632 and 634 are located on the other side of the connection region 620. Due to Figure 6AThe semiconductor structure 601 also includes an initial mask pattern 640 covering the stacked layer 610. Therefore, the connection region 620 is actually the area in the stacked layer 610 defined by the dashed box.

[0128] Step S374: Form an initial mask pattern that covers the connection area and the four partition step areas, and form an opening in each partition step area.

[0129] refer to Figure 6A As shown, an initial mask pattern 640 is formed above the stacked layer 610. The initial mask pattern 640 covers the connection area 420 and four partition step areas 631, 632, 633, and 634. The initial mask pattern 640 forms an opening 641 in the partition step area 631, an opening 642 in the partition step area 632, an opening 643 in the partition step area 633, and an opening 644 in the partition step area 634.

[0130] exist Figure 6A In the embodiment shown, openings 641, 642, 643, and 644 are located at the center of partitioned step areas 631, 632, 633, and 634, respectively, and openings 641, 642, 643, and 644 are all square.

[0131] Step S376: In each partitioned step area, an initial step structure is formed that gradually rises from the opening in all directions.

[0132] refer to Figure 6B As shown, according to Figure 6A The initial mask pattern 640 shown undergoes a predetermined number of trimming etching cycles at the openings of the partitioned step areas, thereby forming initial step structures 651, 652, 653, and 654 that gradually rise outwards from the openings 641, 642, 643, and 644. Since the openings 641, 642, 643, and 644 are square, the resulting initial step structures 651, 652, 653, and 654 correspondingly expand outwards from the square openings, forming a structure similar to the stands of a football stadium.

[0133] In this embodiment, the predetermined number of times is 8, so the initial step structures 651, 652, 653, and 654 all include 8 steps.

[0134] Figure 6C yes Figure 6B A top view of the semiconductor structure 602 shown. (Reference) Figure 6C As shown, it includes Figure 6B The diagram shows an initial stair structure 651, 652, 653, 654 with 8 steps, and a connecting area 620.

[0135] This invention does not limit the semiconductor structure to include only one step region. (See reference) Figure 6C As shown, the semiconductor structure in this embodiment includes a step region 660 and a step region 670, wherein the step region 660 is... Figure 6A and 6B The step area shown is step area 670, which is another step area adjacent to step area 660. Step area 670 includes two partitioned step areas 671 and 672 and a connecting area 673, wherein step areas 671 and 672 are located on the same side of connecting area 673. It can be understood that step area 670 can be extended to have the same structure as step area 660, that is, it also includes a step area located on the other side of connecting area 673.

[0136] The step region in the semiconductor structure of the present invention may also include multiple connection regions, and multiple partitioned step regions located on the same side or opposite side of the multiple connection regions. For example... Figure 6C As shown, step area 660 and step area 670 can be considered as one step area.

[0137] like Figure 6C As shown, more partitioned step areas can be included along the extension direction parallel to the connection area 620. The initial mask pattern is adaptively modified for different numbers of partitioned step areas. The specific process will not be elaborated here.

[0138] Step S378: Divide the initial step structure in each partition step area into 4 sub-step areas, and process the 4 sub-step areas to form 4 sub-step structures, wherein the 4 sub-step structures have different depths in the stacking layer.

[0139] The specific method for processing the four sub-step regions includes the following steps:

[0140] Step S380: Form a first mask pattern that covers half of the four sub-step regions, exposing the other half. The four sub-step regions are arranged in a matrix array, and the first mask pattern covers two sub-step regions located in one row.

[0141] refer to Figure 7A As shown, the semiconductor structure 701 is equivalent to... Figure 6B A first mask pattern 710 is formed on the semiconductor structure 602 shown. The semiconductor structure 701 includes four partitioned step regions 631, 632, 633, and 634, and an initial step structure has been formed in each partitioned step region. Each initial step structure is divided into four sub-step regions. In this embodiment, the four sub-step regions have equal areas; that is, the partitioned step region is divided equally into four sub-step regions.

[0142] The first mask pattern 710 covers the two sub-step areas closest to the connecting area 620 in the four partitioned step areas, and exposes the two sub-step areas far from the connecting area 620. The first mask pattern 710 also covers the connecting area 620. The first mask pattern 710 is rectangular.

[0143] Etching the sub-step area according to the first mask pattern 710 can protect the connecting area 620 from being damaged by etching.

[0144] Step S382: Etch the exposed sub-step region to reduce the exposed sub-step region by a first predetermined number of layers.

[0145] refer to Figure 7B As shown, after etching, Figure 7A The first mask pattern 710 is removed, and after etching, the height of the two exposed sub-step areas in the four partitioned step areas is obviously lower than that of the other two sub-step areas covered by the first mask pattern 710. In this embodiment, the first predetermined number of layers is equal to the total number of steps in the partitioned step areas before etching, i.e., 8 layers.

[0146] like Figure 7B As shown, after this etching step, in the four sub-step areas of partitioned step area 631, sub-step areas 631a and 631b have 1-8 step layers, and sub-step areas 631c and 631d have 9-16 step layers. Correspondingly, in the four sub-step areas of partitioned step area 632, sub-step areas 632a and 632b have 1-8 step layers, and sub-step areas 632c and 632d have 9-16 step layers. In the four sub-step areas of partitioned step area 633, sub-step areas 633a and 633b have 1-8 step layers, and sub-step areas 633c and 633d have 9-16 step layers. Of the four sub-step areas in partition step area 634, sub-step areas 634a and 634b have 1-8 step levels, while sub-step areas 634c and 634d have 9-16 step levels. Each sub-step area can be connected to the core storage area via connection area 620.

[0147] Figure 7C yes Figure 7B The top view of the semiconductor structure 702 shown. Figure 7A As shown, each of the four zoned staircase areas is further divided into four sub-zones. The number of steps in each sub-zone is as follows: Figure 7BAs described above, after the above steps, the sub-step areas 631a, 631b, 632a, 632b, 633a, 633b, 634a, and 634b located on both sides of the connecting area 620 have the same number of steps and the same height in the stacked layer. The sub-step areas 631c, 631d, 632c, 632d, 633c, 633d, 634c, and 634d located away from the connecting area 620 have the same number of steps and the same height in the stacked layer.

[0148] Step S384: Form a second mask pattern that covers half of the four sub-step regions, exposing the other half. The four sub-step regions are arranged in a matrix array, and the second mask pattern covers two sub-step regions located in one column.

[0149] refer to Figure 8A As shown, the semiconductor structure 801 is equivalent to... Figure 7B A second mask pattern 810 is formed on the semiconductor structure 702 shown. A portion 810a of the second mask pattern 810 is a rectangle similar to the first mask pattern 710, and another portion 810b of the second mask pattern 810 covers the connection region 620. The sub-step region covered by the second mask pattern 810 partially overlaps with the sub-step region covered by the first mask pattern 710. (See reference...) Figure 8B As shown, both the first mask pattern 710 and the second mask pattern 810 cover the sub-step regions 631b, 632b, 633b, and 634b. Both the first mask pattern 710 and the second mask pattern 810 also cover the connecting region 620.

[0150] like Figure 8A As shown, for two partitioned step areas located on the same side of the connecting area 620, the second mask pattern 810 covers four adjacent sub-step areas of the two partitioned step areas, exposing the four sub-step areas located on both sides of the two partitioned step areas. (Reference) Figure 8B As shown, the second mask pattern 810 covers sub-step regions 631b, 631d, 632b, 632d, 633b, 633d, 634b, and 634d, and exposes sub-step regions 631a, 631c, 632a, 632c, 633a, 633c, 634a, and 634c.

[0151] Step S386: Etch the exposed sub-step region to reduce the exposed sub-step region by a second predetermined number of layers.

[0152] In this step, the second predetermined number of etched layers is the total number of steps in the current partition step area, i.e., 16 layers.

[0153] like Figure 8BAs shown, after etching in step S386, in the four sub-step regions of partitioned step region 631, sub-step region 631a has 17-24 step layers, sub-step region 631b has 1-8 step layers, sub-step region 631c has 25-32 step layers, and sub-step region 631d has 9-16 step layers. Correspondingly, in the four sub-step regions of partitioned step region 632, sub-step region 632a has 17-24 step layers, sub-step region 632b has 1-8 step layers, sub-step region 632c has 25-32 step layers, and sub-step region 632d has 9-16 step layers. In partitioned step area 633, the four sub-step areas are as follows: sub-step area 633a has 17-24 steps; sub-step area 633b has 1-8 steps; sub-step area 633c has 25-32 steps; and sub-step area 633d has 9-16 steps. Similarly, in partitioned step area 634, the four sub-step areas are as follows: sub-step area 634a has 17-24 steps; sub-step area 634b has 1-8 steps; sub-step area 634c has 25-32 steps; and sub-step area 634d has 9-16 steps. Each sub-step area can be connected to the core storage area via connection area 620.

[0154] Figure 8C yes Figure 8B The diagram shows a top view of the semiconductor structure 802. Figure 8C As shown, each of the four zoned staircase areas is further divided into four sub-zones. The number of steps in each sub-zone is as follows: Figure 8B As mentioned above. After the above steps, sub-step areas 631a, 632a, 633a, and 634a have the same number of steps and the same height in the stacked layers, all ranging from 17 to 24 layers; sub-step areas 631b, 632b, 633b, and 634b have the same number of steps and the same height in the stacked layers, all ranging from 1 to 8 layers; sub-step areas 631c, 632c, 633c, and 634c have the same number of steps and the same height in the stacked layers, all ranging from 25 to 32 layers; sub-step areas 631d, 632d, 633d, and 634d have the same number of steps and the same height in the stacked layers, all ranging from 9 to 16 layers.

[0155] Step S388: Form a third mask pattern, which covers half of the partition step area and the partition step area, exposing the other half of the partition step area.

[0156] refer to Figure 9A As shown, the semiconductor structure 901 is equivalent to... Figure 8BA third mask pattern 910 is formed on the semiconductor structure 802 shown. The third mask pattern 910 covers two of the four partitioned step regions 632 and 633, and exposes two of the four partitioned step regions 631 and 634. Since the partitioned step regions in this embodiment are formed by square openings, the portion of the third mask pattern 910 exposing partitioned step regions 631 and 634 is also a square opening, the size of which exposes the sub-step structures formed in partitioned step regions 631 and 634.

[0157] like Figure 9A As shown, the third mask pattern 910 simultaneously covers the connecting area 620.

[0158] exist Figure 9A In the embodiment shown, the partition step areas 631 and 634 exposed by the third mask pattern 910 are located on both sides of the connecting area 620, and the two partition step areas 631 and 634 are not adjacent to each other.

[0159] Step S390: Etch the sub-step structure of the exposed half of the step area a predetermined number of layers.

[0160] exist Figure 9A In the embodiment shown, the total number of steps in the partitioned step regions 631 and 634 of the semiconductor structure 901 is 32. Therefore, the predetermined number of layers to be etched in step S390 is 32, and the steps in the partitioned step regions 631 and 634 are etched downwards in 32 layers.

[0161] refer to Figure 9B As shown, after etching in step S390, in the four sub-step regions of partitioned step region 631, sub-step region 631a has 49-56 step layers, sub-step region 631b has 33-40 step layers, sub-step region 631c has 57-64 step layers, and sub-step region 631d has 41-48 step layers. In the four sub-step regions of partitioned step region 634, sub-step region 634a has 49-56 step layers, sub-step region 634b has 33-40 step layers, sub-step region 634c has 57-64 step layers, and sub-step region 634d has 41-48 step layers.

[0162] The sub-step structures in the partitioned step areas 632, 632 covered by the third mask pattern 910 and Figure 8BThe same applies as shown. In partitioned step area 632, the four sub-step areas have the same number of steps: sub-step area 632a has 17-24 steps, sub-step area 632b has 1-8 steps, sub-step area 632c has 25-32 steps, and sub-step area 632d has 9-16 steps. Similarly, in partitioned step area 633, the four sub-step areas have the same number of steps: sub-step area 633a has 17-24 steps, sub-step area 633b has 1-8 steps, sub-step area 633c has 25-32 steps, and sub-step area 633d has 9-16 steps. Each sub-step area can be connected to the core storage area via connection area 620.

[0163] like Figure 9B As shown, the semiconductor structure 902 formed by the above steps includes a 64-layer stepped structure, which can be used for a 64-layer three-dimensional memory.

[0164] Figure 9C yes Figure 9B The top view of the semiconductor structure 902 shown. Figure 9C As shown, the sub-step structures in partitioned step areas 632 and 633 include 1-32 layers, and the sub-step structures in partitioned step areas 631 and 634 include 33-64 layers. Specifically, sub-step areas 631a and 634a have the same number of steps and the same height in the stacked layers, both being 49-56 layers; sub-step areas 631b and 634b have the same number of steps and the same height in the stacked layers, both being 33-40 layers; sub-step areas 631c and 634c have the same number of steps and the same height in the stacked layers, both being 57-64 layers; and sub-step areas 631d and 634d have the same number of steps and the same height in the stacked layers, both being 41-48 layers.

[0165] Figures 10A-10C This is a schematic diagram illustrating a method for manufacturing a semiconductor structure according to another embodiment of the present invention. Figure 6A-9C The difference between the embodiments shown is that in this embodiment, the sub-step areas divided by the partitioned step area are triangular. Figures 10A-10C Only a top view of the semiconductor structure is shown. Those skilled in the art can obtain the semiconductor structure of this embodiment by following the steps described above.

[0166] like Figure 10A As shown, the semiconductor structure 1001 includes four partitioned step regions 1011, 1012, 1013, and 1014, and a connection region 1020. Each partitioned step region is divided into four triangular sub-step regions. Figure 10AAs shown, taking the partitioned step area 1011 as an example, this partitioned step area 1011 is divided into four triangular sub-step areas 1011a, 1011b, 1011c, and 1011d. The shapes and areas of these four sub-step areas are not equal, among which sub-step areas 1011a and 1011c have the same shape and area, and sub-step areas 1011b and 1011d have the same shape and area.

[0167] After performing a predetermined number of etching cycles on each partition step area using the initial mask pattern, an initial step structure is formed in the four partition step areas 1011, 1012, 1013, and 1014. This initial step structure is consistent with... Figure 6B The same as shown.

[0168] To etch each sub-step region, the mask pattern used should correspond to the shape of the sub-step region. For example... Figure 10A As shown, the dashed box represents the first mask pattern 1030. This first mask pattern 1030 covers half of the sub-step area in each partitioned step area, while exposing the other half of the sub-step area. At the same time, the first mask pattern 1030 also covers the connecting area 1020.

[0169] The exposed half of the sub-step region is etched using the first mask pattern 1030. The predetermined number of etched layers is the total number of steps in the current partitioned step region. The number of step layers in the resulting sub-step structure can be deduced from the previous description.

[0170] like Figure 10B As shown, after etching according to the first mask pattern 1030, a second mask pattern 1031 is used to cover half of the sub-step region in each partition step region, while exposing the other half of the sub-step region. Simultaneously, the second mask pattern 1031 also covers the connection region 1020. (Comparison) Figure 10A and 10B As shown, the half of the sub-step region covered by the second mask pattern 1031 does not completely overlap with the half of the sub-step region covered by the first mask pattern 1030; both cover one of the sub-step regions. Taking the partitioned step region 1011 as an example, the first mask pattern 1030 covers sub-step regions 1011c and 1011d, and the second mask pattern 1031 covers sub-step regions 1011a and 1011d. Both the first mask pattern 1030 and the second mask pattern 1031 cover sub-step region 1011d.

[0171] The exposed half of the sub-step region is etched using a second mask pattern 1031. The predetermined number of etched layers is the total number of steps in the current partitioned step region. The number of step layers in the resulting sub-step structure can be deduced from the previous description.

[0172] refer to Figure 10CAs shown, after etching according to the second mask pattern 1031, a third mask pattern 1032 is used to cover half of the partitioned step area, namely partitioned step areas 1011 and 1014, while exposing the other half of the partitioned step area, namely partitioned step areas 1012 and 1013. The third mask pattern 1032 also covers the connection area 1020.

[0173] The exposed half of the sub-step region is etched using a third mask pattern 1032. The predetermined number of etched layers is the total number of steps in the current partitioned step region. The number of step layers in the resulting sub-step structure can be deduced from the previous description.

[0174] Figure 11 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. The semiconductor structure 1101 can be manufactured by the semiconductor structure manufacturing method described above; therefore, the above descriptions can all be used to illustrate the semiconductor structure of this embodiment.

[0175] refer to Figure 11 As shown, the semiconductor structure 1101 includes a substrate 1110 and a stacked layer 1120 above the substrate 1110. The stacked layer 1120 includes a core memory region (not shown) and a step region. The step region in the semiconductor structure of the present invention includes a connection region and at least one partitioned step region. Each partitioned step region includes N sub-step regions, and each sub-step region includes a sub-step structure that gradually rises from the interior of the partitioned step region to the periphery. The N sub-step structures within the same partitioned step region have different depths in the stacked layer.

[0176] In some embodiments, the connection region divides the step region into multiple partitioned step regions arranged in a matrix array. The semiconductor structure of the present invention includes at least two partitioned step regions distributed on both sides of the connection region.

[0177] Figure 11 The semiconductor structure 1101 shown includes a step region 1121 and four partitioned step regions 1131, 1132, 1133, and 1134. Partitioned step regions 1131 and 1133 are located on one side of the connection region 1121, and partitioned step regions 1132 and 1134 are located on the other side of the connection region 1121. The multiple partitioned step regions 1131, 1132, 1133, and 1134 are arranged in a 2*2 matrix array. The connection region 1121 is used to connect the four partitioned step regions 1131, 1132, 1133, and 1134 to the core memory region. Each partitioned step region includes four sub-step regions. Figure 11As shown, partitioned step area 1131 includes sub-step areas 1131a, 1131b, 1131c, and 1131d; partitioned step area 1132 includes sub-step areas 1132a, 1132b, 1132c, and 1132d; partitioned step area 1133 includes sub-step areas 1133a, 1133b, 1133c, and 1133d; and partitioned step area 1134 includes sub-step areas 1134a, 1134b, 1134c, and 1134d. Each sub-step area includes a sub-step structure that gradually rises from the center of the partitioned step area outwards. The four sub-step structures within the same partitioned step area have different depths in the stacking layer 1120. The four sub-step areas in each partitioned step area are distributed in a 2*2 matrix array. The specific depth of each sub-step structure can be referenced. Figure 8B And related explanatory content.

[0178] In some embodiments, the number of steps in each sub-step area within the same partitioned step area is equal. Figure 11 In the illustrated embodiment, the four sub-step zones within the partitioned step area all have the same number of steps, eight in total. In other embodiments, this number of steps can be set as needed.

[0179] In some embodiments, the number of steps in the N sub-step areas located within the same partitioned step area may be different.

[0180] In some embodiments, the coverage areas of the N sub-step regions are equal, such as Figure 11 The illustrated embodiment. In other embodiments, the coverage areas of the N sub-step regions may be unequal.

[0181] In some embodiments, the partitioned step area is circular or rectangular. For example... Figure 11 As shown, the stepped area of ​​this partition is square.

[0182] according to Figure 11 The semiconductor structure shown, combined with the semiconductor structure manufacturing method described above, uses a mask with a rectangular opening to form the partitioned step region. Therefore, the formed partitioned step region is approximately rectangular, and from a top view, the step structures in the N sub-step regions within each partitioned step region form a U-shaped structure centered on the center of the partitioned step region. In an embodiment where the partitioned step region is circular, the mask used to form the partitioned step region has a circular opening, and the step structures in the N sub-step regions within each partitioned step region form a concentric ring structure centered on the center of the partitioned step region.

[0183] exist Figure 11 In the illustrated embodiment, the depths of each sub-step structure do not overlap in the stack layer 1120. In other embodiments, the N sub-step structures have different depths in the stack layer 1120, but may partially overlap.

[0184] Figure 12 This is a schematic diagram of a semiconductor structure according to another embodiment of the present invention. The semiconductor structure 1102 can be manufactured using the semiconductor structure manufacturing method described above; therefore, all of the above descriptions can be used to illustrate the semiconductor structure of this embodiment.

[0185] refer to Figure 12 As shown, the semiconductor structure 1201 includes a substrate 1210 and a stacked layer 1220 above the substrate 1210. The stacked layer 1220 includes a core memory region (not shown) and at least one step region. Figure 12 The semiconductor structure 1201 shown includes a stepped region. This stepped region includes a connection region 1221 and four partitioned stepped regions 1231, 1232, 1233, and 1234. The connection region 1221 connects the four partitioned stepped regions 1231, 1232, 1233, and 1234 to the core memory region. Each partitioned stepped region includes four sub-stepped regions. Figure 12 As shown, partitioned step area 1231 includes sub-step areas 1231a, 1231b, 1231c, and 1231d; partitioned step area 1232 includes sub-step areas 1232a, 1232b, 1232c, and 1232d; partitioned step area 1233 includes sub-step areas 1233a, 1233b, 1233c, and 1233d; and partitioned step area 1234 includes sub-step areas 1234a, 1234b, 1234c, and 1234d. Each sub-step area includes a sub-step structure that gradually rises from the interior to the periphery of the partitioned step area. The four sub-step structures located within the same partitioned step area have different depths in the stacking layer 1220. Specific depths can be found in [reference needed]. Figure 9B And related explanatory content.

[0186] In some embodiments, the step region includes at least two partitioned step regions, and the sub-step structures in the at least two different partitioned step regions have different depths in the stacked layers.

[0187] In some embodiments, the sub-step structures in two adjacent partitioned step regions located on opposite sides of the connection area have different depths in the stacked layers. For example... Figure 12 As shown, partitioned step areas 1231 and 1232 are located on opposite sides of connecting area 1221. The number of step layers in the sub-step structure of partitioned step area 1231 ranges from 33 to 64, while the number of step layers in the sub-step structure of partitioned step area 1232 ranges from 1 to 32. Clearly, the number of step layers in the sub-step structure of partitioned step area 1231 is different from the number of step layers in the sub-step structure of partitioned step area 1232.

[0188] In some embodiments, the sub-step structures in two adjacent partitioned step areas located on the same side of the connection area have different depths in the stacked layers. For example... Figure 12 As shown, partitioned step areas 1231 and 1233 are located on the same side of connecting area 1221. The number of steps in the sub-step structure of partitioned step area 1231 ranges from 33 to 64, while the number of steps in the sub-step structure of partitioned step area 1233 ranges from 1 to 32. Clearly, the number of steps in the sub-step structure of partitioned step area 1231 is different from the number of steps in the sub-step structure of partitioned step area 1233.

[0189] exist Figure 12 In the illustrated embodiment, the depths of each sub-step structure do not overlap in the stack layer 1220. In other embodiments, the N sub-step structures have different depths in the stack layer 1220, but may partially overlap. The depths of the step structures in different partitioned step areas may partially overlap in the stack layer 1220.

[0190] In an embodiment of the present invention, the sub-step structures in the four partitioned step areas can all be connected to the core storage area through the connection area 1221, and the height of the connection area 1221 is greater than or equal to the sum of the step thicknesses of all the sub-step structures.

[0191] In some embodiments, the semiconductor structure of the present invention includes a three-dimensional memory, such as 3D NAND flash memory, wherein the stepped region is used to lead out word lines. The sub-stepped structure in the semiconductor structure can serve as a control gate layer lead-out contact in the three-dimensional memory.

[0192] The semiconductor structure according to the present invention includes a sub-step structure that gradually rises from the center of the partitioned step region. The sub-step structure is compactly distributed, and a multi-layer step structure can be realized within a limited area, which greatly saves wafer area. Combined with the connection region, multiple sub-step structures can be connected to the core memory region.

[0193] Although the present invention has been described with reference to specific embodiments, those skilled in the art should recognize that the above embodiments are merely illustrative of the invention, and various equivalent changes or substitutions can be made without departing from the spirit of the invention. Therefore, any changes or modifications to the above embodiments within the scope of the essential spirit of the invention will fall within the scope of the claims of this application.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Provide substrate; A stacked layer is formed on the substrate. The stacked layer includes a core storage region and a step region. The step region includes a connection region and at least two partitioned step regions. The connection region is used to connect each partitioned step region and the core storage region. The connection region is located between the at least two partitioned step regions and divides the plurality of partitioned step regions into two parts. An initial mask pattern is formed, which covers the connection area and each of the partition step areas, and the initial mask pattern forms an opening in each of the partition step areas; In each of the partitioned step areas, an initial step structure is formed that gradually rises outwards from the opening; and The initial step structure in each partition step area is divided into N sub-step areas, and the N sub-step areas are processed to form N sub-step structures. The N sub-step structures are at different depths in the stacked layer, the step layers of the N sub-step areas are continuous, each sub-step area is connected to the core memory area through a connection area, and the thickness of each step is the thickness of a dielectric layer pair. A layer or a step refers to a step obtained by etching a dielectric layer pair. The connecting area divides the step area into multiple partitioned step areas arranged in a matrix array; Among them, multiple sub-step areas located in the same partition step area are distributed in a matrix array.

2. The manufacturing method as described in claim 1, characterized in that, The steps of processing the N sub-step regions to form the N sub-step structure include: A first mask pattern is formed, which covers the connection area and a portion of the N sub-step areas, and exposes the remaining sub-step areas of the N sub-step areas; and The exposed sub-step region is etched down by a first predetermined number of layers.

3. The manufacturing method as described in claim 2, characterized in that, The step of processing the N sub-step regions to form the N sub-step structure further includes: A second mask pattern is formed, which covers the connection area and a portion of the N sub-step areas, exposing the remaining sub-step areas. The sub-step areas covered by the second mask pattern partially overlap with those covered by the first mask pattern. The exposed sub-step region is etched down by a second predetermined number of layers.

4. The manufacturing method as described in claim 3, characterized in that, The step area includes at least two partitioned step areas, and the step of processing the N sub-step areas in each partitioned step area to form N sub-step structures in each partitioned step area further includes: A third mask pattern is formed, which covers the connection area and a portion of the at least two partitioned step areas, exposing the remaining partitioned step areas; and The exposed partition step area is etched down by a third predetermined number of layers.

5. The manufacturing method as described in claim 3, characterized in that, N=4, the first mask pattern covers the connection area and two sub-step areas located in one row, and the second mask covers the connection area and two sub-step areas located in one column.

6. The manufacturing method as described in claim 4, characterized in that, The first predetermined number of layers, the second predetermined number of layers, and the third predetermined number of layers are all equal to the current total number of steps in the partitioned step area.

7. The manufacturing method as described in claim 4, characterized in that, The at least two partitioned step areas are distributed on both sides of the connecting area.

8. A semiconductor structure, characterized in that, include: Substrate; A stacked layer located above the substrate, the stacked layer including a core storage region and a step region, the step region including a connection region and at least two partitioned step regions, the connection region connecting each of the partitioned step regions and the core storage region, wherein the connection region is located between the at least two partitioned step regions and divides the plurality of partitioned step regions into two parts; Each partition step region includes N sub-step regions, each sub-step region forming a sub-step structure that gradually rises from the inside of the partition step region to the surrounding area. The N sub-step structures within the same partition step region have different depths in the stacked layer. The number of step layers in which the N sub-step regions are located is continuous. Each sub-step region is connected to the core memory region through a connection region. The thickness of each step is the thickness of a dielectric layer pair. A layer or a step refers to a step obtained by etching a dielectric layer pair. The connection region divides the step region into multiple partition step regions distributed in a matrix array. Among them, the multiple sub-step regions located in the same partition step region are distributed in a matrix array.

9. The semiconductor structure as described in claim 8, characterized in that, The number of steps in the N sub-step structures is equal.

10. The semiconductor structure as described in claim 8, characterized in that, The coverage areas of the N sub-step regions are equal.

11. The semiconductor structure as described in claim 8, characterized in that, N＝4。 12. The semiconductor structure as described in claim 8, characterized in that, The step area includes at least two partitioned step areas, and the sub-step structures in the at least two different partitioned step areas are at different depths in the stacked layer.

13. The semiconductor structure as described in claim 8, characterized in that, The partitioned step area is circular or rectangular.

14. The semiconductor structure as described in claim 8, characterized in that, The semiconductor structure includes a three-dimensional memory, and the stepped region is used to bring out word lines.

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