Semiconductor device and method for forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same, comprising: providing a substrate, on which fins are formed; forming a dummy gate structure on the substrate, the dummy gate structure spanning the fins; etching the fins on both sides of the dummy gate structure to form grooves in the fins; filling the grooves with stress layers; forming an interlayer dielectric layer on the stress layer; etching and removing the interlayer dielectric layer and a portion of the thickness of the stress layer; and forming a conductive layer on the etched stress layer. The formation method of the present invention increases the contact area between the formed stress layer and the conductive layer, thereby reducing the contact resistance between the stress layer and the conductive layer, reducing the heat generation caused by the contact resistance during use of the semiconductor device, and improving the stability of the performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration. As the most basic semiconductor device, the device is currently being widely used. However, the control ability of traditional planar devices for channel current has weakened, resulting in short channel effects and leakage current, which ultimately affects the electrical performance of semiconductor devices.

[0003] In order to overcome the short channel effect of the device and suppress leakage current, the existing technology has proposed a fin field effect transistor (Fin FET). The fin field effect transistor is a common multi-gate device. The structure of the fin field effect transistor includes: a fin and an isolation structure located on the surface of a semiconductor substrate, the isolation structure covering a portion of the sidewall of the fin, a gate structure located on the substrate and across the fin; and a source region and a drain region within the fin located on both sides of the gate structure.

[0004] However, as the size of semiconductor devices decreases and the device density increases, the performance of the resulting fin field-effect transistors becomes unstable. Summary of the Invention

[0005] The problem solved by the present invention is to provide a semiconductor device and a method for forming the same, so that the performance of the formed semiconductor device is stable.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, on which a fin is formed; forming a dummy gate structure on the substrate, wherein the dummy gate structure spans the fin; etching the fins on both sides of the dummy gate structure to form grooves in the fins; filling the grooves with a stress layer; forming an interlayer dielectric layer on the stress layer; etching to remove the interlayer dielectric layer and a portion of the thickness of the stress layer; and forming a conductive layer on the etched stress layer.

[0007] Optionally, the surface of the stress layer after etching is in a “W” shape or a “wave” shape.

[0008] Optionally, the stress layer is a single-layer structure or a stacked-layer structure.

[0009] Optionally, when the stress layer is a stacked structure, the stress layer includes a first stress layer, a second stress layer and a third stress layer. The first stress layer is formed in the groove, the second stress layer is formed on the first stress layer, and the third stress layer is formed on the second stress layer.

[0010] Optionally, the material of the stress layer includes silicon germanium.

[0011] Optionally, the concentration of germanium in the material of the second stress layer is greater than the concentration of germanium in the materials of the first stress layer and the third stress layer.

[0012] Optionally, the stress layer is formed by epitaxial growth.

[0013] Optionally, the material of the conductive layer includes one or more of copper, titanium, tungsten, and aluminum.

[0014] Optionally, after forming an interlayer dielectric layer on the stress layer and before etching away the interlayer dielectric layer and a portion of the thickness of the stress layer, the method further includes removing the dummy gate structure to form a metal gate structure.

[0015] Optionally, a sidewall spacer is further included, formed on the sidewall of the dummy gate structure.

[0016] Optionally, a hard mask layer is further included, formed on the top of the dummy gate structure.

[0017] A semiconductor device formed using the above method includes: a substrate; a fin located on the substrate; a dummy gate structure located on the substrate and spanning the fin; a trench located in the fin on both sides of the dummy gate structure; a stress layer filled in the trench; and a conductive layer located on the stress layer.

[0018] Optionally, the top surface of the stress layer is in a “W” shape or a “wave” shape, and the bottom of the conductive layer is embedded in the top surface of the stress layer.

[0019] Optionally, the stress layer is a stacked structure, comprising a first stress layer, a second stress layer and a third stress layer, wherein the first stress layer is located on the sidewalls and bottom of the groove, the second stress layer is located on the bottom and sidewalls of the first stress layer, and the third stress layer is located on the second stress layer.

[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0021] After forming a trench in the fin, a stress layer is filled in the trench as a source / drain region. At this time, an interlayer dielectric layer is formed on the stress layer. After etching away the interlayer dielectric layer and a portion of the thickness of the stress layer, a conductive layer is formed on the stress layer as a conductive plug. The semiconductor device formed in this way has a low contact resistance. This is because the surface morphology of the stress layer becomes flat after the formation of the interlayer dielectric layer. At this time, after etching away the interlayer dielectric layer and a portion of the thickness of the stress layer, the surface morphology of the stress layer becomes rugged and uneven. When the conductive layer is formed on the stress layer, the contact area between the conductive layer and the stress layer becomes larger, thereby reducing the contact resistance between the stress layer and the conductive layer. The phenomenon of semiconductor device heating caused by contact resistance during use is reduced, so that the performance stability of the formed semiconductor device is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1 to 9 It is a structural schematic diagram of the process of forming a semiconductor device;

[0023] Figures 10 to 18 is a structural schematic diagram of a semiconductor device forming process according to a first embodiment of the present invention;

[0024] Figures 19 to 27 It is a structural diagram of the semiconductor device forming process in the second embodiment of the present invention. DETAILED DESCRIPTION

[0025] In the semiconductor devices currently formed, the contact resistance between the stress layer and the conductive plug is relatively large. Due to the large interference effect caused by the contact resistance, the semiconductor device is prone to heating during use, affecting the stability of the performance of the semiconductor device. For the specific formation process, please refer to Figures 1 to 9 .

[0026] Figures 1 to 9 It is a structural schematic diagram of the semiconductor device formation process.

[0027] refer to Figure 1 , providing a substrate 1 on which a fin 2 is formed.

[0028] refer to Figures 2 to 3 A dummy gate structure 3 is formed on the substrate 1 , wherein the dummy gate structure 3 spans the fin 2 , and a sidewall spacer 31 is formed on the sidewall of the dummy gate structure 3 .

[0029] refer to Figure 3 yes Figure 2 Section view at section line AA.

[0030] refer to Figure 4 , the fin 2 on both sides of the sidewall 31 is etched to form a trench 4 in the fin 2 .

[0031] refer to Figure 5 , the groove 4 is fully filled with a stress layer 5 .

[0032] refer to Figure 6 , an interlayer dielectric layer 6 is formed on the stress layer 5 .

[0033] refer to Figure 7 , remove the dummy gate structure 3 to form a metal gate structure 7.

[0034] refer to Figure 8 , the interlayer dielectric layer 6 is removed by etching to form an opening 8.

[0035] refer to Figure 9 , a conductive layer 9 is formed in the opening 8 .

[0036] The inventors discovered that the performance stability of the semiconductor device formed by this method is poor, the contact resistance between the stress layer and the conductive layer is large, and the semiconductor device is prone to heat up, which limits the use of the semiconductor device. This is because after the interlayer dielectric layer is formed on the stress layer, the interlayer dielectric layer is etched away to form a conductive layer on the stress layer. At this time, the morphology of the surface of the stress layer is flat, so the contact area between the surface of the stress layer and the surface of the conductive layer is small, and the contact resistance between the stress layer and the conductive layer is large, which makes the formed semiconductor device prone to heat up, affecting the stability of the performance of the formed semiconductor device.

[0037] The inventors discovered that after forming an interlayer dielectric layer on the stress layer, etching away the interlayer dielectric layer also removes a portion of the thickness of the stress layer, making the surface of the stress layer rugged. When a conductive layer is formed on the stress layer, the surface of the conductive layer and the surface of the stress layer change from a flat surface to a curved surface, thereby increasing the contact area between the two, thereby reducing the contact resistance between the stress layer and the conductive layer, reducing the heat generation of the semiconductor device during use, and thus ensuring that the formed semiconductor device has stable usability.

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] First embodiment

[0040] Figures 10 to 18 It is a structural diagram of the semiconductor device forming process in the first embodiment of the present invention.

[0041] First reference Figure 10 , providing a substrate 100 on which a plurality of fins 200 are formed and arranged separately.

[0042] In this embodiment, the material of the substrate 100 is single crystal silicon; in other embodiments, the substrate 100 can be single crystal silicon, polycrystalline silicon or amorphous silicon; the substrate 100 can also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, etc.

[0043] In this embodiment, the method for forming the fin 200 includes: forming a hard mask layer (not shown in the figure) on the substrate 100, the hard mask layer covering the position where the fin 200 is formed, and using the hard mask layer as a mask to etch a partial thickness of the substrate 100 to form a plurality of discretely arranged fins 200 on the substrate 100.

[0044] In other embodiments, a fin material may be formed on the substrate 100 ; the fin material may be patterned to form the fin 200 , and the material of the fin 200 may be a semiconductor material such as silicon germanium (SiGe) or gallium arsenide.

[0045] In this embodiment, no isolation structure is formed on the substrate 100 ; in other embodiments, an isolation structure may be formed on the substrate 100 , and the isolation structure covers a portion of the sidewall of the fin 200 .

[0046] refer to Figures 11 to 12 A dummy gate structure 300 is formed on the substrate 100 , and the dummy gate structure 300 spans the fin 200 .

[0047] Figure 12 yes Figure 11 Section view along section line AA.

[0048] In this embodiment, no hard mask layer is formed on the top of the dummy gate structure 300 ; in other embodiments, a hard mask layer may be formed on the top of the dummy gate structure.

[0049] In this embodiment, no sidewall spacers are formed on the sidewalls of the dummy gate structure 300 ; in other embodiments, sidewall spacers may be formed on the sidewalls of the dummy gate structure.

[0050] In this embodiment, the dummy gate structure 300 includes a dummy gate dielectric layer (not shown in the figure) and a dummy gate electrode layer located on the dummy gate dielectric layer.

[0051] In this embodiment, the material of the dummy gate electrode layer is polysilicon.

[0052] In this embodiment, the dummy gate structure 300 is formed by a conventional process, which will not be further described here.

[0053] refer to Figure 13 , etching the fins 200 on both sides of the dummy gate structure 300 , and forming trenches 400 in the fins 200 .

[0054] In this embodiment, the process for etching the fin 200 is anisotropic dry etching. Parameters of the dry etching include: etching gases including HBr and Ar, wherein the flow rate of HBr is 10 sccm to 1000 sccm, and the flow rate of Ar is 10 sccm to 1000 sccm.

[0055] refer to Figure 14 , the trench 400 is fully filled with a stress layer 500 .

[0056] In this embodiment, the stress layer 500 adopts a single-layer structure.

[0057] In this embodiment, the stress layer 500 is used as a source and drain region.

[0058] In this embodiment, the material of the stress layer 500 is silicon germanium; in other embodiments, the material of the stress layer 500 may also be semiconductor materials such as silicon.

[0059] In this embodiment, the stress layer 500 is formed by epitaxial growth. In other embodiments, the stress layer 500 may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer vapor deposition.

[0060] In this embodiment, the stress layer 500 is formed by epitaxial growth because the stress layer formed by epitaxial growth has few defects and high purity.

[0061] In this embodiment, the process parameters for epitaxial growth to form the stress layer 500 include: the reaction gas is a combination of silane (SiH4) and germanium hydrogen (GeH4) gas; the reaction temperature is controlled between 500 and 800°C, the chamber pressure is controlled between 1 and 100 Torr, and the reaction time is controlled between 3 and 120s.

[0062] refer to Figure 15 , an interlayer dielectric layer 600 is formed on the stress layer 500 .

[0063] In this embodiment, the interlayer dielectric layer (ILD) 600 is formed on the stress layer 500 by chemical vapor deposition.

[0064] In other embodiments, the interlayer dielectric layer 600 may be formed by physical vapor deposition or atomic layer deposition.

[0065] In this embodiment, the material of the interlayer dielectric layer 600 is silicon oxide; in other embodiments, the material of the interlayer dielectric layer 600 may also be silicon carbide, silicon oxynitride, or silicon nitride.

[0066] In this embodiment, the process parameters for forming the interlayer dielectric layer 600 include: the gases used include oxygen, ammonia (NH3), and N(SiH3)3 gas, the flow rate of oxygen is 20sccm~10000sccm, the flow rate of ammonia (NH3) gas is 20sccm~10000sccm, the flow rate of N(SiH3)3 gas is 20sccm~10000sccm, the chamber pressure is 0.01~10 Torr, and the temperature is 30℃~90℃.

[0067] refer to Figure 16 , remove the dummy gate structure 300 to form a metal gate structure 700.

[0068] In this embodiment, a wet etching process is used to remove the dummy gate structure 300. The wet etching process parameters include:

[0069] In other embodiments, dry etching may be used to remove the dummy gate structure 300 .

[0070] In this embodiment, the metal gate structure 700 includes a gate dielectric layer (not shown) and a gate electrode layer located on the gate dielectric layer.

[0071] In this embodiment, the material of the gate dielectric layer is a high-k dielectric constant material (dielectric constant greater than 3.9); the high-k dielectric constant material includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0072] In this embodiment, the gate electrode layer is made of metal, and the metal material includes one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum.

[0073] refer to Figure 17 , the interlayer dielectric layer 600 and a portion of the stress layer 500 are etched away.

[0074] In this embodiment, dry etching is used to etch the interlayer dielectric layer 600 and a partial thickness of the stress layer 500. The process parameters of the dry etching include: selecting helium (He), ammonia (NH3) and NF3 gas as the etching atmosphere, wherein the gas flow range of the helium (He) is 600sccm~2000sccm, the gas flow range of the ammonia (NH3) is 200sccm~5000sccm, the NF3 gas flow range is 20sccm~2000sccm, the etching pressure is 2~100 mTorr, and the etching processing time is 20~1000s.

[0075] In other embodiments, wet etching may be used to etch the interlayer dielectric layer 600 and a portion of the stress layer 500 .

[0076] In this embodiment, the surface of the stress layer 500 is "wavy" after etching. The purpose of this design is to change the contact area between the conductive layer and the stress layer 500 from a flat surface to a curved surface when the conductive layer is subsequently formed. In this way, the contact area between the conductive layer and the stress layer 500 is increased, thereby reducing the contact resistance between the conductive layer and the stress layer 500. In this way, the probability of heat generation in the semiconductor device due to contact resistance is reduced, thereby improving the stability of the performance of the formed semiconductor device.

[0077] refer to Figure 18 , forming a conductive layer 800 on the etched stress layer 500 .

[0078] In this embodiment, the conductive layer 800 is formed by chemical vapor deposition. In other embodiments, the conductive layer 800 may be formed by atomic layer vapor deposition or physical vapor deposition.

[0079] In this embodiment, the material of the conductive layer 800 is tungsten; in other embodiments, the material of the conductive layer 800 may also be copper, titanium, cobalt, aluminum, etc.

[0080] In this embodiment, a buffer layer is first filled using a chemical vapor deposition method or a physical vapor deposition process, in order to ensure good adhesion of the conductive layer 800 formed subsequently.

[0081] In this embodiment, since the surface of the stress layer 500 is uneven and "wavy" after being etched, the contact surface between the stress layer 500 and the conductive layer 800 is changed from a flat surface to a curved surface, thereby increasing the contact area between the conductive layer 800 and the stress layer 500, thereby reducing the contact resistance between the stress layer 500 and the conductive layer 800, reducing the heat generation of the semiconductor device during use, and improving the reliability and stability of the semiconductor device during use.

[0082] A semiconductor device formed using the above method includes: a substrate 100; a fin 200 located on the substrate 100; a metal gate structure 700 located on the substrate 100 and spanning the fin 200; a trench 400 located in the fin 200 on both sides of the metal gate structure 700; a stress layer 500 filling the trench 400; and a conductive layer 800 located on the stress layer 500.

[0083] In this embodiment, the surface of the stress layer 500 is "wavy" and the bottom of the conductive layer 800 is embedded in the surface of the stress layer 500. This structure allows the stress layer 500 and the conductive layer 800 to have a larger contact area, thereby reducing the contact resistance between the two, reducing the heat generation of the semiconductor device during use, and improving the stability of the performance of the semiconductor device.

[0084] Second embodiment

[0085] refer to Figures 19 to 27 It is a structural diagram of the semiconductor device forming process in the second embodiment of the present invention.

[0086] refer to Figure 19 , providing a substrate 100 on which a plurality of fins 200 are formed and arranged separately.

[0087] In this embodiment, the substrate 100 is made of single crystal silicon.

[0088] refer to Figures 20 to 21 A dummy gate structure 300 is formed on the substrate 100 , and the dummy gate structure 300 spans the fin 200 .

[0089] Figure 21 yes Figure 20 Section view at section line AA.

[0090] In this embodiment, a hard mask layer 310 is formed on the top of the dummy gate structure 300 ; in other embodiments, the hard mask layer 310 may not be formed on the top of the dummy gate structure 300 .

[0091] In this embodiment, the hard mask layer 310 is formed on the top of the dummy gate structure 300 to protect the top of the gate structure from being damaged in subsequent processes, thereby ensuring the quality of the formed gate structure.

[0092] In this embodiment, a sidewall spacer 320 is formed on the sidewall of the dummy gate structure 300 .

[0093] In this embodiment, the material of the hard mask layer 310 is silicon nitride; in other embodiments, the material of the hard mask layer 310 may also be silicon carbide, silicon oxide, etc.

[0094] In this embodiment, the material of the sidewall 320 is silicon carbide; the sidewall 320 is a single-layer structure; in other embodiments, the material of the sidewall 320 may also be a single layer or a stacked structure of silicon nitride, silicon oxide, etc.

[0095] In this embodiment, the spacer 320 is used to define the position where the source and drain are subsequently formed.

[0096] refer to Figure 22 , the fin 200 on both sides of the sidewall 320 is etched to form a trench 400 in the fin 200 .

[0097] In this embodiment, the process of etching the fin 200 is the same as that in the first embodiment.

[0098] refer to Figure 23 , the trench 400 is fully filled with a stress layer 500 .

[0099] In this embodiment, the stress layer 500 adopts a stacked structure, including a first stress layer 501 , a second stress layer 502 and a third stress layer 503 .

[0100] In other embodiments, the stress layer 500 may also adopt a two-layer stacked structure, a four-layer stacked structure, etc.

[0101] In this embodiment, the material of the stress layer 500 is silicon germanium (SiGe).

[0102] In this embodiment, the concentration of germanium (Ge) contained in the materials of the first stress layer 501 and the third stress layer 503 is lower than the concentration of germanium (Ge) contained in the material of the second stress layer 502 .

[0103] In this embodiment, the concentration of germanium in the material of the first stress layer 501 is the same as the concentration of germanium in the material of the third stress layer 503. In other embodiments, the concentration of germanium in the material of the first stress layer 501 and the concentration of germanium in the material of the third stress layer 503 may be different.

[0104] In this embodiment, the process parameters for forming the first stress layer 501 and the third stress layer 503 include: the reaction gas is a combination of silane (SiH4) and germanium hydrogen (GeH4) gas, the mass percentage of germanium hydrogen (GeH4) gas is between 10% and 25%, the reaction temperature is controlled between 500 and 800°C, the chamber pressure is controlled between 1 and 100 Torr, and the reaction time is controlled between 3 and 120 seconds.

[0105] In this embodiment, the process parameters for forming the second stress layer 502 include: the reaction gas is a combination of silane (SiH4) and germanium hydrogen (GeH4) gas, the mass percentage of germanium hydrogen (GeH4) gas is between 35% and 45%, the reaction temperature is controlled between 500 and 800°C, the chamber pressure is controlled between 1 and 100 Torr, and the reaction time is controlled between 3 and 120 seconds.

[0106] In this embodiment, the purpose of forming the stress layer 500 with a concentration gradient is to facilitate the subsequent etching of the stress layer 500 so that the second stress layer 502 containing a higher germanium concentration can be selectively etched, so that the surface of the stress layer 500 forms a "W" shape, simplifying the formation process and making the shape formed on the surface of the stress layer 500 controllable.

[0107] refer to Figure 24 , the interlayer dielectric layer 600 is formed on the stress layer 500 .

[0108] In this embodiment, the process of forming the interlayer dielectric layer 600 is the same as that in the first embodiment.

[0109] refer to Figure 25 , remove the dummy gate structure 300 to form the metal gate structure 700.

[0110] In this embodiment, dry etching is used to remove the dummy gate structure 300 . At the same time, a relatively high etching solution needs to be selected for etching to ensure that minimal damage is caused to the gate oxide layer at the bottom of the dummy gate structure 300 .

[0111] In this embodiment, HBr gas is used as the etching gas; in other embodiments, SF6 gas may also be used as the etching gas.

[0112] In this embodiment, the metal gate structure 700 is formed by a conventional process.

[0113] refer to Figure 26 , the interlayer dielectric layer 600 and a portion of the stress layer 500 are etched away.

[0114] In this embodiment, wet etching is used to remove the interlayer dielectric layer 600 and a portion of the stress layer 500. The wet etching solution has a good selectivity for silicon and silicon germanium. After etching, the surface of the stress layer 500 has a "W" shape.

[0115] In this embodiment, the parameters of the wet etching include: the etching liquid is a solution of HCl gas, the temperature is 25 degrees Celsius to 300 degrees Celsius, and the volume percentage of the HCl gas solution is 20% to 90%.

[0116] refer to Figure 27 , forming a conductive layer 800 on the etched stress layer 500 .

[0117] In this embodiment, the conductive layer 800 is made of copper.

[0118] A semiconductor device formed using the above method includes: a substrate 100; a fin 200 located on the substrate 100; a metal gate structure 700 located on the substrate 100 and spanning the fin 200; a hard mask layer 310 located on top of the metal gate structure 700; a sidewall 320 located on the sidewall of the metal gate structure 700; a trench 400 located in the fin 200; a stress layer 500 filling the trench 400, wherein: a first stress layer 501 is located on the sidewall and bottom of the trench 400; a second stress layer 502 is located on the bottom and sidewall of the first stress layer 501; a third stress layer 503 is on the second stress layer 502; and a conductive layer 800 is located on the stress layer 500.

[0119] In this embodiment, the surface layer of the stress layer 500 is "W"-shaped, and the bottom of the conductive layer 800 is embedded in the stress layer 500, thereby increasing the contact area between the two and reducing the contact resistance between the two.

[0120] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: providing a substrate, wherein a fin is formed on the substrate; forming a dummy gate structure on the substrate, wherein the dummy gate structure spans the fin; Etching the fins on both sides of the dummy gate structure and forming trenches in the fins; Filling the trench with stress layers, the stress layers comprising a first stress layer, a second stress layer, and a third stress layer, wherein the concentration of germanium contained in the first stress layer and the third stress layer is lower than the concentration of germanium contained in the second stress layer; forming an interlayer dielectric layer on the stress layer; Etching and removing the interlayer dielectric layer and a portion of the stress layer, wherein the surface of the etched stress layer is in a "W" shape, wherein the "W" shape connects the first stress layer, the second stress layer, and the third stress layer, the top surface of the third stress layer is higher than the top surface of the second stress layer, and when etching the stress layer, the second stress layer can be selectively etched; A conductive layer is formed on the etched stress layer.

2. The method for forming a semiconductor device according to claim 1, wherein: The first stress layer is formed in the trench, the second stress layer is formed on the first stress layer, and the third stress layer is formed on the second stress layer.

3. The method for forming a semiconductor device according to claim 1, wherein: The material of the stress layer includes silicon germanium.

4. The method for forming a semiconductor device according to claim 1, wherein: The stress layer is formed by epitaxial growth.

5. The method for forming a semiconductor device according to claim 1, wherein: The material of the conductive layer includes one or more of copper, titanium, tungsten and aluminum.

6. The method for forming a semiconductor device according to claim 1, wherein: After forming an interlayer dielectric layer on the stress layer, and before etching away the interlayer dielectric layer and a portion of the stress layer, the method further includes removing the dummy gate structure to form a metal gate structure.

7. The method for forming a semiconductor device according to claim 1, wherein: It also includes sidewall spacers formed on the sidewalls of the dummy gate structure.

8. The method for forming a semiconductor device according to claim 1, wherein: The invention also includes a hard mask layer formed on the top of the dummy gate structure.

9. A semiconductor device formed by the method according to any one of claims 1 to 8, characterized in that: include: substrate; a fin portion located on the substrate; a metal gate structure located on the substrate and spanning the fin; trenches located within the fin on both sides of the metal gate structure; a stress layer filled in the trench, wherein a top surface of the stress layer is W-shaped, the stress layer comprising a first stress layer, a second stress layer, and a third stress layer, wherein the W-shape connects the first stress layer, the second stress layer, and the third stress layer, a top surface of the third stress layer is higher than a top surface of the second stress layer, and a concentration of germanium contained in both the first stress layer and the third stress layer is lower than a concentration of germanium contained in the second stress layer; The conductive layer is located on the stress layer.

10. The semiconductor device according to claim 9, wherein The bottom of the conductive layer is embedded in the top surface of the stress layer.

11. The semiconductor device according to claim 9, wherein The first stress layer is located on the sidewalls and the bottom of the trench, the second stress layer is located on the bottom and the sidewalls of the first stress layer, and the third stress layer is located on the second stress layer.

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