Semiconductor Structure and Method for Manufacturing the Same

Abstract

A semiconductor structure includes a substrate, an interconnect structure, a pad, a protective layer, and a bonding structure. The interconnect structure is disposed on the substrate. The pad is disposed on the interconnect structure and electrically connected to the interconnect structure. The top surface of the pad has a probe mark and the probe mark has a concave surface. The protective layer conformally covers the top surface of the pad and the probe mark. The bonding structure is disposed on the protective layer. The bonding structure includes a bonding dielectric layer and a first bonding metal layer, and the first bonding metal layer penetrates through the bonding dielectric layer and the protective layer to electrically connect to the pad. A method of manufacturing a semiconductor structure is also provided.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor structure and a method of manufacturing the same. Background Art

[0002] In recent years, the semiconductor industry has experienced rapid growth due to the continuous increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This increase in integration density is mostly attributed to the repeated reduction of the minimum feature size, which enables more components to be integrated into a given area.

[0003] Compared with previous packages, these smaller electronic components also require smaller packages with smaller areas. Some types of semiconductor packages include quad flatpack (QFP), pin grid array (PGA), ball grid array (BGA), flip chip (FC), three dimensional integrated circuit (3DIC), wafer level package (WLP), and package on package (PoP) devices. Some 3DICs are fabricated by placing chips on top of chips at the semiconductor wafer level. Due to the reduction in the length of the interconnects between the stacked chips, 3DICs offer increased integration density and other advantages such as faster speed and higher bandwidth. However, there are many challenges to be addressed for 3DIC technology. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor structure, including a substrate, an interconnect structure, a pad, a protective layer, and a bonding structure. The interconnect structure is disposed on the substrate. The pad is disposed on the interconnect structure and electrically connected to the interconnect structure. The top surface of the pad has a probe mark and the probe mark has a concave surface. The protective layer conformally covers the top surface of the pad and the probe mark. The bonding structure is disposed on the protective layer. The bonding structure includes a bonding dielectric layer and a first bonding metal layer, and the first bonding metal layer penetrates through the bonding dielectric layer and the protective layer to electrically connect to the pad.

[0005] An embodiment of the present invention provides a semiconductor structure including a substrate, an interconnect structure, a pad, a protective layer, and a bonding structure. The interconnect structure is disposed on the substrate. The pad is disposed on the interconnect structure and electrically connected to the interconnect structure. The protective layer is disposed on the pad. The top surface of the pad has a probe mark and the probe mark has a concave surface. The bonding structure is disposed on the protective layer. The bonding structure includes a bonding dielectric layer and a first bonding metal layer, and the first bonding metal layer penetrates through the bonding dielectric layer and the protective layer to electrically connect to the pad.

[0006] An embodiment of the present invention provides a method of manufacturing a semiconductor structure, including: forming an interconnect structure on a substrate; forming a pad electrically connected to the interconnect structure on the interconnect structure; performing a circuit probe (CP) test on the pad to form a probe mark on the top surface of the pad; forming a protective layer on the top surface of the pad; and forming a bonding structure on the protective layer, wherein forming the bonding structure includes forming a bonding dielectric layer and forming a first bonding metal layer, and the first bonding metal layer penetrates through the bonding dielectric layer and the protective layer to electrically connect to the pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure are best understood when read in conjunction with the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1A to 1F is a cross-sectional view of a method of forming a semiconductor structure according to a first embodiment.

[0009] Figures 2A to 2B is a cross-sectional view of a method of forming a 3DIC structure according to a second embodiment.

[0010] Figures 3A to 3D is a cross-sectional view of a method of forming a semiconductor structure according to a third embodiment.

[0011] Figures 4A to 4D is a cross-sectional view of a method of forming a semiconductor structure according to a fourth embodiment.

[0012] Figure 5 is a cross-sectional view showing a semiconductor structure according to a fifth embodiment.

[0013] Figure 6 is a cross-sectional view showing a semiconductor structure according to a sixth embodiment.

[0014] Figure 7 is a cross-sectional view showing a semiconductor structure according to another embodiment. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature "on" or "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the disclosure may reuse reference numerals and / or letters in various examples. Such reuse is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0017] Other features and processes may also be included. For example, test structures may be included to assist in verification testing of three-dimensional packages or 3DIC devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate to enable testing of three-dimensional packages or 3DICs, use of probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. Additionally, the structures and methods disclosed herein may be used in combination with test methods that include intermediate verification of known good dies to improve yield and reduce cost.

[0018] Figures 1A to 1F is a cross-sectional view of a method of forming a semiconductor structure according to a first embodiment.

[0019] Referring to Figure 1A , a method of forming a semiconductor structure 100 (as shown in Figure 1F ) includes the following steps. First, an initial structure is provided as shown in Figure 1A . The initial structure includes a semiconductor substrate 102, a device layer 103, an interconnect structure 104, a passivation layer 110, a conductive material 112, and a capping material 114.

[0020] In some embodiments, the semiconductor substrate 102 may comprise silicon or other semiconductor materials. As an alternative or in addition, the semiconductor substrate 102 may comprise other elemental semiconductor materials, such as germanium. In some embodiments, the semiconductor substrate 102 is made of a compound semiconductor (such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide). In some embodiments, the semiconductor substrate 102 is made of an alloy semiconductor (such as silicon germanium, silicon carbide germanium, gallium arsenide phosphide, or gallium indium phosphide). In some embodiments, the semiconductor substrate 102 includes an epitaxial layer. For example, the semiconductor substrate 102 has an epitaxial layer overlying a bulk semiconductor.

[0021] In some embodiments, the device layer 103 is formed over the semiconductor substrate 102 by a front-end-of-line (FEOL) process. The device layer 103 includes a variety of devices. In some embodiments, the devices include active components, passive components, or a combination thereof. In some embodiments, the devices may include integrated circuit devices. For example, the devices are transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. In some embodiments, the device layer 103 includes gate structures, source and drain regions, and isolation structures (e.g., shallow trench isolation (STI) structures (not shown in the figure)). In the device layer 103, various N-type metal-oxide semiconductor (NMOS) devices and / or P-type metal-oxide semiconductor (PMOS) devices (such as transistors or memories, etc.) may be formed, and the devices may be interconnected to perform one or more functions. Other devices, such as capacitors, resistors, diodes, photodiodes, fuses, etc., may also be formed over the semiconductor substrate 102. The functions of the devices may include memory, processor, sensor, amplifier, power distribution, input and / or output circuitry, etc.

[0022] Refer to Figure 1A, an interconnect structure 104 is formed over the device layer 103. Specifically, the interconnect structure 104 includes an insulating material 106 and a plurality of metal features 108. The metal features 108 are formed in the insulating material 106 and are electrically connected to the device layer 103. A portion of the metal features 108 (e.g., the top metal feature 108a) is exposed by the insulating material 106. In some embodiments, the insulating material 106 includes an inner-layer dielectric (ILD) layer on the device layer 103 and at least one inter-metal dielectric (IMD) layer on the ILD layer. In some embodiments, the insulating material 106 includes silicon oxide, silicon nitride, silicon oxynitride, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG)), low dielectric constant dielectric materials, other suitable dielectric materials, or combinations thereof. Exemplary low dielectric constant dielectric materials include FSG, carbon-doped silicon oxide, Black (Applied Materials, Inc. of Santa Clara, California), Xerogel, Aerogel, amorphous fluorocarbon, parylene, bis-benzocyclobutenes (BCB), SiLK (Dow Chemical of Midland, Michigan), polyimide, other low dielectric constant dielectric materials, or combinations thereof. In some alternative embodiments, the insulating material 106 can be a single layer or multiple layers. In some embodiments, the metal features 108 include plugs and metal lines. The plugs can include contacts formed in the ILD layer and vias formed in the IMD layer. The contacts are formed between the device layer 103 and the bottom metal line and connect the device layer 103 and the bottom metal line. The vias are formed between two metal lines and connect the two metal lines. The metal features 108 can be made of tungsten (W), copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or combinations thereof. In some alternative embodiments, a barrier layer (not shown in the figure) can be formed between the metal features 108 and the insulating material 106 to prevent the material of the metal features 108 from migrating or diffusing into the device layer 103. For example, the material of the barrier layer includes tantalum, tantalum nitride, titanium, titanium nitride, cobalt-tungsten (CoW), or combinations thereof.

[0023] Reference Figure 1A , a passivation layer 110 is formed over the interconnect structure 104. In some embodiments, the passivation layer 110 comprises silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO), or a combination thereof and is formed by a suitable process (such as spin coating, chemical vapor deposition (CVD), etc.). In an embodiment, the passivation layer 110 can be a single-layer structure, a double-layer structure, or a multi-layer structure. As Figure 1A shown, the passivation layer 110 includes a passivation material 110a and a passivation material 110b formed over the passivation material 110a. The passivation material 110a and the passivation material 110b have different materials. For example, the passivation material 110a can comprise silicon nitride, while the passivation material 110b can comprise polyimide (PI) or any material different from silicon nitride.

[0024] Reference Figure 1A , a conductive material 112 is formed over the passivation layer 110 and is electrically connected to the top metal feature 108a through a plug 111 that penetrates through the passivation layer 110. The conductive material 112 and the metal feature 108 can have different materials. In some embodiments, the conductive material 112 is softer than the metal feature 108. The conductive material 112 and the plug 111 can have the same material. In some embodiments, the conductive material 112 and the plug 111 respectively comprise a metal material (such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof), and the conductive material 112 and the plug 111 can be formed by the following steps: patterning the passivation layer 110 to form a plurality of openings reaching the metal feature 108; depositing a metal material layer by a suitable process (such as an electroless plating process, CVD, atomic layer deposition (ALD), PVD, etc.) to fill in the openings and cover the passivation layer 110; and then patterning the metal material layer.

[0025] Reference Figure 1A, a top cover material 114 is formed on the conductive material 112. For example, the top cover material 114 can be a dielectric material. In some embodiments, the top cover material 114 includes a nitrogen-containing material (such as silicon oxynitride, silicon nitride, or a combination thereof) and has a thickness of 50 nm to 100 nm. In another embodiment, the top cover material 114 is referred to as an anti-reflective coating (ARC) layer, and the top cover material 114 can include an organic ARC material (such as a polymer resin), an inorganic ARC material (such as SiON), or a combination thereof. In some alternative embodiments, the top cover material 114 can be a single layer or multiple layers and can be formed by a suitable process (such as CVD, ALD, etc.).

[0026] Referring to Figure 1B , a mask pattern 116 is formed on the top cover material 114. In some embodiments, the mask pattern 116 is used to define the position of the pad 122 to be formed (as Figure 1C shown). In one embodiment, the mask pattern 116 includes a photoresist and is formed by a suitable process (such as spin coating and photolithography processes).

[0027] Referring to Figure 1B and Figure 1C , after the mask pattern 116 is formed, the first etching process is performed using the mask pattern 116 as an etching mask to remove a portion of the top cover material 114 and a portion of the conductive material 112, thereby exposing the passivation material 110b. In some embodiments, the first etching process can include a dry etching process, a wet etching process, or a combination thereof. In this case, as Figure 1C shown, a pad 122 and a top cover layer 124 disposed on the pad 122 are formed. The pad 122 is electrically connected to the top metal feature 108a through the plug 111. In some embodiments, the pad 122 can be aligned with or partially overlap the top metal feature 108a. Although only one pad 122 and one top cover layer 124 are shown in Figure 1C , the embodiments of the present disclosure are not limited thereto. In other embodiments, the number of pads 122 and top cover layers 124 can be adjusted as needed. After the pad 122 and the top cover layer 124 are formed, the mask pattern 116 is removed.

[0028] Referring to Figure 1C and Figure 1D, a second etching process is performed on the top cover layer 124 to expose the pad 122. In one embodiment, the second etching process may include an isotropic etching process. In another embodiment, the second etching process may include a wet etching process or a combination of a wet etching process and a dry etching process. The wet etching process may be performed using an etching solution containing a halogen (such as F, Cl, Br, or a combination thereof). For example, the etching solution may include an HF solution, an HCl solution, an HBr solution, or a combination thereof. The dry etching process may be performed using an etching gas containing a halogen (such as F, Cl, Br, or a combination thereof). In this case, as Figure 1D shown, the top surface or the top portion 122t of the pad 122 is modified so that the resistance value of the top portion 122t of the pad 122 is greater than the resistance value of the bottom portion 122b of the pad 122.

[0029] In an alternative embodiment, some residues 123 may be formed in or on the pad 122. Herein, the residue 123 may be a chemical residue during the second etching process. Therefore, the residue 123 may be from the top cover layer 124 and the pad 122, and the residue 123 may have a nitrogen-containing material (such as silicon oxynitride, silicon nitride, or a combination thereof) and a metal material (such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof). In some alternative embodiments, the resistance value of the pad 122 having the residue 123 is greater than the resistance value of other pads without residues (as Figure 7 shown). In one embodiment, the residue 123 may cover the pad 122 in a blanket or continuous manner. As an alternative, the residue 123 may cover the pad 122 partially or discontinuously. In other embodiments, charge accumulation may occur on the top surface or the top portion 122t of the pad 122, which may affect the resistance value of the top portion 122t of the pad 122.

[0030] As Figure 1D shown, after removing the top cover layer 124, a circuit probing (CP) test is performed on the pad 122. Specifically, the probe 128 may be used to electrically couple to the pad 122 for wafer or die testing to check whether the die is a good die. In some embodiments, the CP test is also referred to as wafer acceptance testing (WAT). In some embodiments, the pad 122 is used for electrical testing to check Figure 1Dwhether the first die 101 shown is a good die, but the present disclosure is not limited thereto. The first die 101 can be selected to test different properties of the wafer or die, such as leakage current, breakdown voltage, threshold voltage, and effective channel length, saturation current, contact resistance, and connection. It should be noted that when the first die 101 is identified as a known good die (KGD), the first die 101 is selected for the following processes. In this case, as Figure 1D shown, a probe mark 127 is formed at the top portion 122t of the pad 122, and the probe mark 127 can be a recess or a groove recessed into the top surface 122t of the pad 122. That is, the probe mark 127 has a concave surface or a downwardly recessed curve. Since the probe 128 can press or squeeze the residue 123 during the CP test to electrically connect to the pad 122, after the CP test, the residue 123 under the probe mark 127 can be squeezed to both sides of the probe mark 127, as Figure 1D shown. That is, the top portion 122t under the probe mark 127 can have a lower resistance than the top portion 122t beside the probe mark 127. In some embodiments, the probe mark 127 can have a depth D1 of 50 nm to 2000 nm and a width W1 of 1000 nm to 50000 nm. In some alternative embodiments, the ratio of the width W1 to the depth D1 is 0.5 to 1000. Herein, the depth D1 is the vertical distance between the apex (or the top surface 122t) and the bottom point of the probe mark 127.

[0031] Referring to Figure 1E, after the CP test, a protective layer 125 is formed over the pad 122. Specifically, the protective layer 125 conformally covers and directly contacts the top surface 122t and the sidewalls 122s of the pad 122, the probe mark 127, and the top surface of the passivation layer 110. In this case, the protective layer 125 that conformally covers the probe mark 127 has another concave surface corresponding to the concave surface of the probe mark 127. Herein, when a layer is described as "conformally covering", the layer is formed to have a uniform thickness and extends along the surface topography of the underlying layer or structure. In some embodiments, the protective layer 125 may include a dielectric layer (e.g., silicon nitride, silicon oxynitride, or a combination thereof) and has a thickness of 50 nm to 100 nm. When the thickness of the protective layer 125 is greater than the depth D1 of the probe mark 127, the protective layer 125 may fill the probe mark 127. That is, the lowest point of the top surface of the protective layer 125 directly above the probe mark 127 may be higher than the top surface 122t of the pad 122. On the other hand, when the thickness of the protective layer 125 is less than the depth D1 of the probe mark 127, the protective layer 125 may not fill the probe mark 127. That is, the lowest point of the top surface of the protective layer 125 directly above the probe mark 127 may be lower than the top surface 122t of the pad 122. In other embodiments, the lowest point of the top surface of the protective layer 125 directly above the probe mark 127 and the top surface 122t of the pad 122 may be at the same horizontal level.

[0032] In another embodiment, the protective layer 125 is referred to as an anti-reflection coating (ARC) layer. The protective layer 125 may include an organic ARC material (e.g., a polymer resin), an inorganic ARC material (e.g., SiON), or a combination thereof. In some alternative embodiments, the protective layer 125 may be a single layer or multiple layers and may be formed by a suitable process (e.g., CVD, ALD, etc.). In other embodiments, the protective layer 125 and the capping layer 124 may have different materials.

[0033] After forming the protective layer 125, a first bonding structure 135 is formed over the protective layer 125 (as Figure 1F shown). Specifically, as Figure 1E shown, after the first die 101 is identified as a known good die, a bonding dielectric material 130a (or referred to as the first bonding dielectric material) is disposed over the front surface 101a of the first die 101. In some embodiments, as Figure 1E shown, the bonding dielectric material 130a covers the protective layer 125 and fills in the probe mark 127. In some embodiments, the bonding dielectric material 130a includes silicon oxide, silicon nitride, a polymer, or a combination thereof. The bonding dielectric material 130a is formed by a suitable process (e.g., spin coating, CVD, etc.).

[0034] In Figure 1ETherein, a barrier layer 130b is then formed to cover the bonding dielectric material 130a. In some embodiments, the barrier layer 130b comprises a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof) and is formed by a suitable process (e.g., CVD, ALD, etc.). In some embodiments, the thickness of the barrier layer 130b is from 50 nm to 100 nm.

[0035] In Figure 1E therein, another bonding dielectric material 130c (or referred to as the second bonding dielectric material) is formed over the barrier layer 130b. That is, the barrier layer 130b is disposed between the bonding dielectric material 130a and the bonding dielectric material 130c. In some embodiments, the material of the barrier layer 130b is different from the materials of the bonding dielectric materials 130a and 130c. For example, the barrier layer 130b may comprise silicon nitride, while the bonding dielectric materials 130a and 130c may comprise silicon oxide. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the bonding dielectric materials 130a and 130c have different materials from the barrier layer 130b. In some embodiments, the bonding dielectric material 130c comprises silicon oxide, silicon nitride, a polymer, or a combination thereof. The bonding dielectric material 130c is formed by a suitable process (e.g., spin coating, CVD, etc.). Thereafter, a planarization process may be performed on the bonding dielectric material 130c such that the top surface of the bonding dielectric material 130c has a flat surface, in some embodiments. In alternative embodiments, the planarization process includes a chemical mechanical polish (CMP) process, an etch-back process, or a combination thereof.

[0036] After forming the bonding dielectric layer 130 including the bonding dielectric materials 130a and 130c and the barrier layer 130b disposed between the bonding dielectric materials 130a and 130c, a bonding metal layer 132 is formed in the bonding dielectric layer 130, thereby completing the semiconductor structure 100, as Figure 1F shown. In some embodiments, the semiconductor structure 100 may include a semiconductor die, a semiconductor chip, a semiconductor wafer, or a combination thereof. In the embodiments, the semiconductor structure 100 includes a first die 101 and a first bonding structure 135 over the front surface 101a of the first die 101. For example, the first die 101 may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, or a memory chip.

[0037] In Figure 1FIn [the figure], the bonding metal layer 132 corresponds to the pad 122 and is electrically connected to the pad 122. Herein, the bonding metal layer 132 can land on the pad 122 and contact the pad 122. In some embodiments, the bonding metal layer 132 includes a via plug 134 and a metal feature 136. For example, the metal feature 136 is a via plug with a larger area than the via plug 134. As Figure 1F shown, the via plug 134 penetrates through the bonding dielectric material 130a and the protective layer 125 to land on and contact the pad 122. The metal feature 136 penetrates through the bonding dielectric material 130c and the barrier layer 130b to connect to the via plug 134. In other words, the metal feature 136 is electrically connected to the pad 122 through the via plug 134. The bonding metal layer 132 is electrically connected to the top metal feature 108a through the pad 122 and the plug 111. In some embodiments, the bonding metal layer 132 is formed by a dual damascene process. Additionally, although Figure 1F only one bonding metal layer 132 is shown in [the figure], the embodiments of the present disclosure are not limited thereto. In other embodiments, the number of the bonding metal layers 132 can be adjusted as needed. For example, the number of the bonding metal layers 132 is multiple, and the bonding metal layers 132 can be arranged as an array landing on the pad 122.

[0038] Generally, the bonding metal layer 132 can be formed by a trench first process, a via hole first process, or a self-aligned process, as will be elaborated in detail below.

[0039] In some embodiments, the bonding metal layer 132 is formed according to the following steps (referred to as a trench-first process). The bonding dielectric material 130c and the barrier layer 130b are patterned by a lithography process and an etching process to form trenches 137 in the bonding dielectric material 130c and the barrier layer 130b. The trenches 137 correspond to the pads 122, which means that the trenches 137 can be aligned with the pads 122 or partially overlap the pads 122. During the etching process, the barrier layer 130b serves as an etch stop layer, and thus the barrier layer 130b is exposed or penetrated by the trenches 137. Next, the bonding dielectric material 130a is patterned by another lithography process and an etching process using the protective layer 125 as an etch stop layer, and then the protective layer 125 is etched to form via openings 133 in the protective layer 125. In an embodiment, the protective layer 125 is referred to as an etch stop layer for forming the via openings 133. In one embodiment, the etching process may include an anisotropic etching process having a plurality of etching steps for removing a plurality of layers having different materials. That is, the bonding dielectric material 130a and the protective layer 125 can be removed by a plurality of etching steps using different etching gases. In another embodiment, the etching process may include a dry etching process. The dry etching process can be performed using an etching gas (including O2, N2, CH4, or a combination thereof). In this case, the dry etching process can further remove a part of the residue 123 so that the via openings 133 contact the pads 122, and the protective layer 125 can be used to control the depth of the via openings 133 and avoid damage to the pads 122 during the etching process. The via openings 133 may expose the pads 122. Thereafter, a conductive material layer and a barrier material layer (not shown) are formed on the bonding dielectric material 130c, and the conductive material layer and the barrier material layer are filled into the trenches 137 and the via openings 133. Then, the conductive material layer on the bonding dielectric material 130c is removed by a planarization process (such as a CMP process), and thus via plugs 134 and metal features 136 are formed in the via openings 133 and the trenches 137, respectively. In some alternative embodiments, the trenches 137 may be referred to as via openings larger than the via openings 133.

[0040] In some other embodiments, the bonding metal layer 132 is formed according to the following steps (referred to as the via opening first process). The bonding dielectric materials 130a and 130c, the barrier layer 130b, and the protective layer 125 are patterned by a photolithography process and an etching process to form via openings 133. In this case, the protective layer 125 is referred to as an etch stop layer for forming the via openings 133. In one embodiment, the etching process may include an anisotropic etching process. In another embodiment, the etching process may include a dry etching process. The dry etching process may be performed using an etching gas (including O2, N2, CH4, or a combination thereof). Next, the bonding dielectric material 130c and the barrier layer 130b are patterned by a photolithography process and an etching process to form trenches 137 in the bonding dielectric material 130c and the barrier layer 130b. During the etching process, the barrier layer 130b serves as an etch stop layer, and thus the barrier layer 130b is exposed or penetrated by the trenches 137. Thereafter, a conductive material layer is formed and a planarization process is performed.

[0041] In an alternative embodiment, the bonding metal layer 132 is formed according to the following steps (referred to as the self-alignment process). After the bonding dielectric material 130a is formed, the barrier layer 130b is formed and patterned by a photolithography process and an etching process to form a via opening pattern in the barrier layer 130b. Next, the bonding dielectric material 130c is formed over the barrier layer 130b using the via opening pattern. The bonding dielectric material 130c fills into the via opening pattern of the barrier layer 130b and contacts the bonding dielectric material 130a. Thereafter, a patterned mask having a trench pattern is formed over the bonding dielectric material 130c by a photolithography process, and the trench pattern in the trench pattern corresponds to the via opening pattern of the barrier layer 130b. Thereafter, an etching process is performed on the bonding dielectric material 130c using the barrier layer 130b as an etch stop layer to form trenches 137. In one embodiment, the etching process may include an anisotropic etching process. In another embodiment, the etching process may include a dry etching process. The dry etching process may be performed using an etching gas (including O2, N2, CH4, or a combination thereof). At the same time, the bonding dielectric material 130a and the protective layer 125 are etched using the barrier layer 130b having the via opening pattern as a hard mask so that via openings 133 are formed in the bonding dielectric material 130a and the protective layer 125 and are self-aligned with the trenches 137. In this case, the protective layer 125 is referred to as an etch stop layer for forming the via openings 133. Thereafter, a conductive material layer is formed and a planarization process is performed.

[0042] In Figure 1FIn [the figure], the barrier layer 130b has the same pattern as the bonding dielectric material 130c, and both the barrier layer 130b and the bonding dielectric material 130c have trenches 137. However, depending on the process, the barrier layer 130b may have the same pattern as the bonding dielectric material 130a, and both the barrier layer 130b and the bonding dielectric material 130a have via openings 133 as shown by the dashed lines. In other words, the bottom of the trench 137 above the pad 122 exposes a portion of the barrier layer 130b, and the barrier layer 130b below the bottom of the trench 137 has the pattern of the via opening 133.

[0043] As Figure 1F shown, in one embodiment, a portion of the pad 122 (the partial pad 122 having the probe mark 127) may be referred to as a test pad for CP testing, and another portion of the pad 122 (the partial pad 122 without the probe mark 127) may be referred to as a connection pad that is electrically connected to or in contact with the bonding metal layer 132. Specifically, the bonding metal layer 132 lands on the other portion of the pad 122 and is spaced apart from the probe mark 127 by a distance 122d greater than zero. That is, the bonding metal layer 132 does not directly contact the probe mark 127. In this case, the connection pad can transmit signals from the first die 101 to the overlying die. In some embodiments, the distance 122d may be less than the width of the pad 122; however, the embodiments of the present disclosure are not limited thereto.

[0044] Figures 2A to 2B is a cross-sectional view of a method for forming a 3DIC structure according to a second embodiment.

[0045] Referring Figure 2A to [the figure], a semiconductor structure 200 is provided. Specifically, the semiconductor structure 200 includes a second die 201 and a second bonding structure 235 disposed on the front surface 201a of the second die 201. In some embodiments, the semiconductor structure 200 may include a semiconductor die, a semiconductor chip, a semiconductor wafer, or a combination thereof. For example, the second die 201 may be an application specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, or a memory chip. The second die 201 and the first die 101 may be the same type of die or different types of dies.

[0046] In some embodiments, the second die 201 is similar to the first die 101. That is, the second die 201 includes a semiconductor substrate 202, a device layer 203, an interconnect structure 204 (including an insulating material 206 and a plurality of metal features 208), a passivation layer 210 (including passivation materials 210a and 210b), bond pads 222, probe marks 227 at the top of the bond pads 222, and a protective layer 225. The arrangement, materials, and formation method of the second die 201 are similar to those of the first die 101. Therefore, the details thereof are omitted herein. Figure 1F The first die 101 and the second die 201 shown may have different sizes. As used herein, the term "size" refers to length, width, or area. For example, as Figure 1F and Figure 2A shown, the length of the second die 201 is greater than the length of the first die 101. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the size of the second die 201 may be the same as the size of the first die 101.

[0047] In some embodiments, the second bonding structure 235 includes a bonding dielectric layer 230, a first bonding metal layer 232, a second bonding metal layer 242, and dummy metal features 238. Specifically, the first bonding metal layer 232 includes via plugs 234 and metal features 236. The via plugs 234 penetrate through the bonding dielectric material 230a and the protective layer 225 to land on the second bond pad 222 and contact the second bond pad 222. The metal features 236 penetrate through the bonding dielectric material 130c and the barrier layer 130b to connect to the via plugs 234. In other words, the first bonding metal layer 232 is electrically connected to the top metal feature 208a (or the interconnect structure 204) through the bond pad 222 and the plug 211.

[0048] Similarly, the second bonding metal layer 242 includes via plugs 244 and metal features 246. The via plugs 244 penetrate through the bonding dielectric material 230a, the protective layer 225, and the passivation layer 210 to land on the top metal feature 208b and contact the top metal feature 208b. The metal features 246 penetrate through the bonding dielectric material 130c and the barrier layer 130b to connect to the via plugs 244. That is, the second bonding metal layer 242 is electrically connected or physically connected to the top metal feature 208b (or the interconnect structure 204). In this case, the height of the second bonding metal layer 242 is greater than the height of the first bonding metal layer 232. In this embodiment, as Figure 2A shown, the height of the via plug 244 is greater than the height of the via plug 234, and the height of the metal feature 246 is equal to the height of the metal feature 236.

[0049] On the other hand, the dummy metal feature 238 may be formed beside the first bonding metal layer 232 as needed. The dummy metal feature 238 is disposed in the bonding dielectric material 230c and the barrier layer 230b and is exposed by the bonding dielectric material 230c. Herein, when an element is described as "dummy", the element is electrically floating or electrically isolated from other elements. For example, as Figure 2A shown, the dummy metal feature 238 is electrically floating. In some embodiments, the dummy metal feature 238 is formed by a single damascene method.

[0050] In some embodiments, the dummy metal feature 238 is at substantially the same horizontal height as the metal features 236 and 246. That is, the top surface of the dummy metal feature 238, the top surfaces of the metal features 236 and 246, and the top surface of the bonding dielectric material 230c are substantially coplanar.

[0051] In some embodiments, the first bonding metal layer 232 and the second bonding metal layer 242 may include copper, copper alloy, nickel, aluminum, tungsten, or a combination thereof. The dummy metal feature 238 may include copper, copper alloy, nickel, aluminum, tungsten, or a combination thereof. In some embodiments, the first bonding metal layer 232, the second bonding metal layer 242, and the dummy metal feature 238 may have the same material. In some alternative embodiments, the first bonding metal layer 232, the second bonding metal layer 242, and the dummy metal feature 238 may have different materials.

[0052] In some embodiments, the first bonding metal layer 232, the second bonding metal layer 242, and the dummy metal feature 238 are formed simultaneously. In some other embodiments, the first bonding metal layer 232, the second bonding metal layer 242, and the dummy metal feature 238 are formed successively. The first bonding metal layer 232, the second bonding metal layer 242, and the dummy metal feature 238 are formed by a trench-first process, a via-mouth-first process, or a self-alignment process.

[0053] For example, the first bonding metal layer 232, the second bonding metal layer 242, and the dummy metal feature 238 are formed according to the following steps (referred to as the trench-first process). The bonding dielectric material 230c and the barrier layer 230b are patterned by a photolithography process and an etching process to form trenches 237, 247, and 239 in the bonding dielectric material 230c and the barrier layer 230b. The trench 237 corresponds to the pad 222 and the trench 247 corresponds to the top metal feature 208b. During the etching process, the barrier layer 230b serves as an etch stop layer, and thus the barrier layer 230b is exposed or penetrated by the trenches 237, 247, and 239. Next, the bonding dielectric material 230a is patterned by another photolithography process and an etching process using the protective layer 225 as an etch stop layer, and then the protective layer 225 is etched to form via openings 233 in the protective layer 225. At the same time, the bonding dielectric material 230a, the protective layer 225, and the passivation layer 210 are patterned by the same photolithography process and etching process to form via openings 243 in the bonding dielectric material 230a, the protective layer 225, and the passivation layer 210. In this embodiment, the etching process may include a dry etching process having a plurality of etching steps for removing a plurality of layers having different materials. That is, the protective layer 225 is referred to as an etch stop layer for forming the via openings 233 and 243. Specifically, the via opening 233 may stop on the protective layer 225 until the via opening 243 reaches the protective layer 225 during the first etching step. Then a second etching step is performed to remove a portion of the protective layer 225 and a portion of the passivation layer 210. In the second etching step, the pad 222 is referred to as an etch stop layer, that is, the via opening 233 may stop on the pad 222 until the via opening 243 reaches the top metal feature 208b. In addition, the second etching step can further remove a portion of the residue 223 to contact the pad 222. As described above, the protective layer 225 can be used to control the depths of the via openings 233 and 243 such that the via openings 233 and 243 having different depths are formed simultaneously. In other embodiments, the first bonding metal layer 232, the second bonding metal layer 242, and the dummy metal feature 238 may be formed simultaneously in a via-first process and a self-alignment process and are shown in the above embodiments. Therefore, the details thereof are omitted herein.

[0054] From another perspective, the semiconductor structure 200 may include a first region R1 and a second region R2. The pad 222 and the first bonding metal layer 232 contacting the pad 222 are located in the first region R1. The second bonding metal layer 242 is located in the second region R2. The structure in the first region R1 is similar to Figure 1F the semiconductor structure 100 shown. However, the embodiments of the present disclosure are not limited thereto. The structure in the first region R1 may be replaced by another structure (such as Figure 6 shown).

[0055] Referring to Figure 2B , another semiconductor structure 200' is provided. Specifically, the semiconductor structure 200' includes another second die 201' and another second bonding structure 235' disposed on the front surface 201a' of the second die 201'. The second die 201 and the second die 201' may be the same type of die or different types of dies. The arrangement, materials, and formation methods of the second die 201' and the second bonding structure 235' are similar to those of the second die 201 and the second bonding structure 235. Therefore, the details thereof are omitted herein.

[0056] Referring to Figure 2B , the semiconductor structure 200' is further flipped upside down and mounted on the semiconductor structure 200. That is, the second die 201' and the second die 201 are face-to-face bonded together through the second bonding structure 235' and the second bonding structure 235 to form a 3DIC structure 10 (or a die stack structure 10). However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the second die 201' and the second die 201 may be face-to-back bonded together. Hereinafter, the second die 201' of the semiconductor structure 200' is referred to as the top die 201', and the second die 201 of the semiconductor structure 200 is referred to as the bottom die 201.

[0057] In some embodiments, before bonding the top die 201' to the bottom die 201, the second bonding structure 235' and the second bonding structure 235 are aligned such that the dummy metal features 238 are bonded together, the first bonding metal layer 232 is bonded together, the second bonding metal layer 242 is bonded together, and the bonding dielectric layer 230 is bonded together. In some embodiments, the alignment of the second bonding structure 235' and the second bonding structure 235 can be achieved using an optical sensing method. After achieving the alignment, the second bonding structure 235' and the second bonding structure 235 are bonded together by hybrid bonding to form a hybrid bonding structure 35.

[0058] The second bonding structure 235' and the second bonding structure 235 are hybrid bonded together by applying pressure and heat. It should be noted that hybrid bonding involves at least two types of bonding, and the at least two types of bonding include metal-to-metal bonding and non-metal-to-non-metal bonding (e.g., dielectric-to-dielectric bonding or fusion bonding). As Figure 2AAs shown, the hybrid bonding structure 35 includes dummy metal features 238 joined together by metal-to-metal bonding, a first bonding metal layer 232 joined together by metal-to-metal bonding, a second bonding metal layer 242 joined together by metal-to-metal bonding, and a bonding dielectric layer 230 joined together by non-metal-to-non-metal bonding. However, embodiments of the present disclosure are not limited thereto. In other embodiments, the second bonding structure 235' and the second bonding structure 235 may be joined together by other bonding (such as fusion bonding).

[0059] Figures 3A to 3D is a cross-sectional view of a method of forming a semiconductor structure according to a third embodiment.

[0060] Referring to Figure 3A and Figure 3B , the structure 301' is a structure that follows the Figure 1C shown structure. After forming the structure 301', a circuit probe (CP) test is performed on the pad 122 with the capping layer 124 thereon. Specifically, the probe 128 can penetrate the capping layer 124 to be electrically coupled to the pad 122 for wafer or die testing, thereby checking whether the die is a good die. In some embodiments, the pad 122 is used for electrical testing to check Figure 3B whether the third die 301 shown is a good die, but the present disclosure is not limited thereto. It should be noted that when the third die 301 is identified as a known good die (KGD), the third die 301 is selected for the following process. In this case, as Figure 3B shown, a probe mark 327 is formed on the top portion 122t of the pad 122, and the probe mark 327 can be a groove recessed or indented from the top surface 124t of the capping layer 124 into the pad 122. In some embodiments, the probe mark 327 can have a depth D2 of 50 nm to 2000 nm and a width W2 of 1000 nm to 50000 nm. Herein, the depth D2 is the vertical distance between the topmost point (or the top surface 124t of the capping layer 124) and the bottommost point of the probe mark 327. In some alternative embodiments, by using the same probe in the same CP test apparatus, the depth D2 can be greater than Figure 1D the depth D1 shown, and the width W2 can be greater than or equal to Figure 1D the width W1 shown.

[0061] Referring to Figure 3C, after the CP test, a protective layer 125 is formed over the pad 122 and the top cover layer 124. Specifically, the protective layer 125 conformally covers and directly contacts the top surface 124t of the top cover layer 124, the probe mark 127, the sidewall 122s of the pad 122, and the top surface of the passivation layer 110. In some embodiments, the protective layer 125 may include a dielectric layer (such as silicon nitride, silicon oxynitride, or a combination thereof) and have a thickness of 50 nm to 100 nm. When the thickness of the protective layer 125 is greater than the depth D2 of the probe mark 327 (as Figure 3B shown), the protective layer 125 may fill the probe mark 327. That is, the lowest point of the top surface of the protective layer 125 directly above the probe mark 327 may be higher than the top surface 124t of the top cover layer 124. On the other hand, when the thickness of the protective layer 125 is less than the depth D2 of the probe mark 327, the protective layer 125 may not fill the probe mark 327. That is, the lowest point of the top surface of the protective layer 125 directly above the probe mark 327 may be lower than the top surface 124t of the top cover layer 124. In other embodiments, the lowest point of the top surface of the protective layer 125 directly above the probe mark 327 and the top surface of the top cover layer 124 may be at the same level.

[0062] In another embodiment, the protective layer 125 is referred to as an anti-reflection coating (ARC) layer. The protective layer 125 may include an organic ARC material (such as a polymer resin), an inorganic ARC material (such as SiON), or a combination thereof. In some alternative embodiments, the protective layer 125 may be a single layer or multiple layers and may be formed by a suitable process (such as CVD, ALD, etc.). In other embodiments, the protective layer 125 and the top cover layer 124 may have different materials. That is, an interface may be formed between the protective layer 125 and the top cover layer 124. In this case, as Figure 3C shown, the dielectric material covering the top surface 122t of the pad 122 may have a thickness T1, where the dielectric material includes the protective layer 125 and the top cover layer 124. Another dielectric material covering the sidewall 122s of the pad 122 may have a thickness T2, where the another dielectric material includes the protective layer 125. Another dielectric material covering the probe mark 327 may have a thickness T3, where the another dielectric material includes the protective layer 125. In the embodiment, the thickness T1 may be greater than the thickness T2 or T3, and the thickness T2 may be equal to or less than the thickness T3.

[0063] Referring to Figure 3D, after forming the protective layer 125, a first bonding structure 135 is formed over the protective layer 125 or the front surface 301a of the third die 301, thereby forming the semiconductor structure 300. The first bonding structure 135 includes a bonding metal layer 132 formed in the bonding dielectric layer 130. The bonding metal layer 132 penetrates the bonding dielectric layer 130, the protective layer 125, and the capping layer 124 to land on and contact the pad 122. The arrangement, material, and formation method of the bonding metal layer 132 and the bonding dielectric layer 130 are shown in the above embodiments. Therefore, the details thereof are omitted here.

[0064] Figures 4A to 4D is a cross-sectional view of a method of forming a semiconductor structure according to a fourth embodiment.

[0065] Referring to Figure 4A , the structure 401' is similar to the Figure 1B shown structure. The difference between the structure 401' and the Figure 1B shown structure is that the structure 401' includes a protective material 115 disposed between the conductive material 112 and the capping material 114. In some embodiments, the protective material 115 may include a dielectric layer (such as silicon nitride, silicon oxynitride, or a combination thereof) and have a thickness of 50 nm to 100 nm. In another embodiment, the protective material 115 is referred to as an anti-reflection coating (ARC) layer, and the protective material 115 may include an organic ARC material (such as a polymer resin), an inorganic ARC material (such as SiON), or a combination thereof. In some alternative embodiments, the protective material 115 may be a single layer or multiple layers and may be formed by a suitable process (such as CVD, ALD, etc.). In other embodiments, the protective material 115 and the capping material 114 may have different materials.

[0066] Referring to Figure 4A and Figure 4B , after forming the mask pattern 116, a first etching process is performed using the mask pattern 116 as an etching mask to remove a portion of the capping material 114, a portion of the protective material 115, and a portion of the conductive material 112, thereby exposing the passivation material 110b. In some embodiments, the first etching process may include a dry etching process, a wet etching process, or a combination thereof. In this case, as Figure 4B shown, a pad 122, a capping layer 124, and a protective layer 125 disposed between the pad 122 and the capping layer 124 are formed. The pad 122 is electrically connected to the top metal feature 108a through the plug 111. In some embodiments, the pad 122 may be aligned with or partially overlap the top metal feature 108a. Although in Figure 4BOnly one pad 122, one protective layer 125, and one top layer 124 are shown, however, embodiments of the present disclosure are not limited thereto. In other embodiments, the number of pads 122, protective layers 125, and top layers 124 can be adjusted as needed.

[0067] Referring to Figure 4B and Figure 4C , after removing the mask pattern 116, a circuit probe (CP) test is performed on the pad 122. Specifically, the probe 128 can penetrate the top layer 124 and the protective layer 125 to be electrically coupled to the pad 122 for wafer or die testing, thereby checking whether the die is a good die. In some embodiments, the pad 122 is used for electrical testing to check Figure 4C whether the fourth die 401 shown is a good die, but the present disclosure is not limited thereto. It should be noted that when the fourth die 401 is identified as a known good die (KGD), the fourth die 401 is selected for the following process. In this case, as Figure 4C shown, a probe mark 427 is formed on the top surface 122t of the pad 122, and the probe mark 427 can be a groove that is recessed or indented from the top surface 124t of the top layer 124 through the protective layer 125 and then recessed or indented into the pad 122. In some embodiments, the probe mark 427 can have a depth D3 of 100 nm to 2000 nm and a width W3 of 1000 nm to 50000 nm. Herein, the depth D3 is the vertical distance between the topmost point (or the top surface 124t of the top layer 124) and the bottommost point of the probe mark 427. In some alternative embodiments, by using the same probe in the same CP test device, the depth D3 can be greater than Figure 3B the depth D2 shown, and the width W3 can be greater than or equal to Figure 3B the width W2 shown.

[0068] Referring to Figure 4D , after the CP test, a first bonding structure 135 is formed over the front surface 401a of the fourth die 401, thereby forming a semiconductor structure 400. The first bonding structure 135 includes a bonding metal layer 132 formed in a bonding dielectric layer 130. In some embodiments, the bonding dielectric layer 130 (or the bonding dielectric material 130a) is formed over the pad 122 and fills the probe mark 427. In this case, the bonding dielectric material 130a contacts the pad 122 exposed by the probe mark 427. That is, the bonding dielectric material 130a fills the probe mark 427 and directly contacts the probe mark 427. The bonding metal layer 132 penetrates the bonding dielectric layer 130, the top layer 124, and the protective layer 125 to land on the pad 122 and contact the pad 122. The arrangement, materials, and formation methods of the bonding metal layer 132 and the bonding dielectric layer 130 are shown in the above embodiments. Therefore, the details thereof are omitted herein.

[0069] Figure 5 is a cross-sectional view showing a semiconductor structure according to the fifth embodiment.

[0070] Referring to Figure 5 , the semiconductor structure 500 is similar to the Figure 4D shown semiconductor structure 400. The difference between the semiconductor structure 500 and the semiconductor structure 400 is that the semiconductor structure 500 includes a fifth die 501, and there is a pad 122 above the front surface 501a of the fifth die 501 and a protective layer 125 located above the pad 122. A probe mark 527 is formed on the top surface 122t of the pad 122, and the probe mark 527 can be a groove recessed or sunken from the top surface 125t of the protective layer 125 into the pad 122. In some embodiments, the probe mark 527 can have a depth D4 of 50 nm to 2000 nm and a width W4 of 1000 nm to 50000 nm. Herein, the depth D4 is the vertical distance between the topmost point of the probe mark 527 (or the top surface 125t of the protective layer 125) and the bottommost point. In some alternative embodiments, by using the same probe in the same CP test device, the depth D4 can be less than Figure 4C the shown depth D3, and the width W4 can be less than or equal to Figure 4C the shown width W3.

[0071] Figure 6 is a cross-sectional view showing a semiconductor structure according to the sixth embodiment.

[0072] Referring to Figure 6 , the semiconductor structure 600 is similar to the Figure 2B shown semiconductor structure 200. The difference between the semiconductor structure 600 and the semiconductor structure 200 is that Figure 6 the structure in the shown first region R1 is replaced by Figure 3D the shown structure 300. In this case, a probe mark 627 is formed on the top surface 222t of the pad 222, and the probe mark 627 can be a groove recessed or sunken from the top surface 224t of the top cover layer 224 into the pad 222. However, the embodiments of the present disclosure are not limited thereto. The structure in the first region R1 can be replaced by Figure 4D the shown structure 400 or Figure 5replaced by the structure 500 shown. On the other hand, one of the semiconductor structures 100, 300, 400, and 500 may have a second bonding metal layer 242 and / or dummy metal features 238. The second bonding metal layer 242 penetrates through the bonding dielectric layer 230, the protective layer 225, and the passivation layer 210 to land on and contact the top metal feature 208b. The dummy metal features 238 are disposed in the bonding dielectric material 230c and the barrier layer 230b and are exposed by the bonding dielectric material 230c.

[0073] It should be noted that in some embodiments, any two of the semiconductor structures 100, 200, 200', 300, 400, 500, and 600 may be bonded together by a hybrid bonding structure 35 to form a 3DIC structure. In some alternative embodiments, one of the semiconductor structures 100, 300, 400, and 500 may optionally have a second bonding metal layer and / or dummy metal features disposed beside the first bonding metal layer 132, where the number and arrangement of the first bonding metal layer 132, the second bonding metal layer, and the dummy metal features are not limited thereto.

[0074] In summary, a part of the pad is called a test pad for CP testing, and another part of the pad is called a connection pad for signal transmission. In this case, the semiconductor structure with pads having multiple functions can efficiently increase the usable area. Additionally, a protective layer covering at least the top surface of the pad can be used as an etch stop layer to enable the first bonding metal layer to land on the pad and the second bonding metal layer to land on the top metal feature simultaneously. In this case, the protective layer can better control the process without over-etching the pad.

[0075] According to some embodiments, a semiconductor structure includes a substrate, an interconnect structure, a pad, a protective layer, and a bonding structure. The interconnect structure is disposed on the substrate. The pad is disposed on the interconnect structure and is electrically connected to the interconnect structure. The top surface of the pad has a probe mark and the probe mark has a concave surface. The protective layer conformally covers the top surface of the pad and the probe mark. The bonding structure is disposed on the protective layer. The bonding structure includes a bonding dielectric layer and a first bonding metal layer that penetrates through the bonding dielectric layer and the protective layer to electrically connect to the pad.

[0076] In some embodiments, the semiconductor structure further includes a passivation layer disposed between the pad and the interconnect structure and between the bonding structure and the interconnect structure, wherein the protective layer extends to cover the sidewalls of the pad and the top surface of the passivation layer. The bonding structure includes a second bonding metal layer located beside the pad, and the second bonding metal layer penetrates through the bonding dielectric layer, the protective layer, and the passivation layer to electrically connect to the interconnect structure. The height of the second bonding metal layer is greater than the height of the first bonding metal layer. The first bonding metal layer lands on the pad and is spaced apart from the probe mark by a distance greater than zero. The protective layer directly contacts the probe mark, and the protective layer covering the probe mark has another concave surface. The semiconductor structure further includes a top cover layer disposed between the top surface of the pad and the protective layer, wherein the probe mark is recessed from the top surface of the top cover layer into the top surface of the pad. The semiconductor structure further includes a passivation layer disposed between the pad and the interconnect structure and between the bonding structure and the interconnect structure, wherein the protective layer conformally covers the top surface of the top cover layer and the probe mark, and extends to cover the sidewalls of the pad and the top surface of the passivation layer.

[0077] According to some embodiments, a semiconductor structure includes a substrate, an interconnect structure, a pad, a protective layer, and a bonding structure. The interconnect structure is disposed on the substrate. The pad is disposed on the interconnect structure and electrically connected to the interconnect structure. The protective layer is disposed on the pad. The top surface of the pad has a probe mark and the probe mark has a concave surface. The bonding structure is disposed on the protective layer. The bonding structure includes a bonding dielectric layer and a first bonding metal layer, and the first bonding metal layer penetrates through the bonding dielectric layer and the protective layer to electrically connect to the pad.

[0078] In some embodiments, the semiconductor structure further includes a top cover layer disposed over the top surface of the protective layer, wherein the probe mark is recessed from the top surface of the top cover layer into the top surface of the pad. The first bonding metal layer penetrates through the top cover layer and the protective layer to electrically connect to the pad. The semiconductor structure further includes a passivation layer disposed between the pad and the interconnect structure and between the bonding structure and the interconnect structure. The bonding dielectric layer includes: a first bonding dielectric material covering the pad; a second bonding dielectric material disposed over the first bonding dielectric material; and a barrier layer disposed between the first bonding dielectric material and the second bonding dielectric material. The first bonding dielectric material directly contacts the probe mark. The bonding structure includes a second bonding metal layer disposed beside the pad, and the second bonding metal layer penetrates through the bonding dielectric layer and the passivation layer to electrically connect to the interconnect structure. The height of the second bonding metal layer is greater than the height of the first bonding metal layer.

[0079] According to some embodiments, a method of manufacturing a semiconductor structure includes: forming an interconnect structure over a substrate; forming a pad electrically connected to the interconnect structure over the interconnect structure; performing a circuit probe (CP) test on the pad to form a probe mark over the top surface of the pad; forming a protective layer over the top surface of the pad; and forming a bonding structure over the protective layer, wherein forming the bonding structure includes forming a bonding dielectric layer and forming a first bonding metal layer that penetrates through the bonding dielectric layer and the protective layer to electrically connect to the pad.

[0080] In some embodiments, forming the protective layer is performed after performing the circuit probe test, and the protective layer conformally covers and directly contacts the probe mark. The method further includes forming a top cover layer over the top surface of the pad before performing the circuit probe test, wherein the protective layer conformally covers and directly contacts the top cover layer. Forming the protective layer is performed before performing the circuit probe test, and the bonding dielectric layer directly contacts the probe mark. The method further includes forming a top cover layer over the protective layer before performing the circuit probe test, wherein the bonding dielectric layer directly contacts the probe mark.

[0081] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should know that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, comprising: An interconnect structure disposed on a substrate; A pad disposed on the interconnect structure and electrically connected to the interconnect structure, wherein a top surface of the pad has a probe mark and the probe mark has a concave surface; A protective layer conformally covering the top surface of the pad and the probe mark; And A bonding structure disposed on the protective layer, wherein the bonding structure includes a bonding dielectric layer and a first bonding metal layer, and the first bonding metal layer penetrates the bonding dielectric layer and the protective layer to electrically connect to the pad; A passivation layer disposed between the pad and the interconnect structure and between the bonding structure and the interconnect structure; And A second bonding metal layer located beside the pad, wherein the second bonding metal layer penetrates the bonding dielectric layer, the protective layer, and the passivation layer to electrically connect to the interconnect structure.

2. The semiconductor structure according to claim 1, Wherein the protective layer extends to cover a sidewall of the pad and a top surface of the passivation layer.

3. The semiconductor structure according to claim 1, wherein a height of the second bonding metal layer is greater than a height of the first bonding metal layer.

4. The semiconductor structure according to claim 1, wherein the first bonding metal layer lands on the pad and is spaced from the probe mark by a distance greater than zero.

5. The semiconductor structure according to claim 1, wherein the protective layer directly contacts the probe mark, and the protective layer covering the probe mark has another concave surface.

6. The semiconductor structure according to claim 1, further comprising: A top cover layer disposed between the top surface of the pad and the protective layer, wherein the probe mark is recessed from a top surface of the top cover layer into the top surface of the pad.

7. The semiconductor structure according to claim 6, further comprising: A passivation layer disposed between the pad and the interconnect structure and between the bonding structure and the interconnect structure, wherein the protective layer conformally covers the top surface of the top cover layer and the probe mark, and extends to cover a sidewall of the pad and a top surface of the passivation layer.

8. A semiconductor structure, comprising: An interconnect structure disposed on a substrate; A pad disposed on the interconnect structure and electrically connected to the interconnect structure; A protective layer disposed on the pad, wherein a top surface of the pad has a probe mark and the probe mark has a concave surface; And A bonding structure disposed on the protective layer, wherein the bonding structure includes a bonding dielectric layer and a first bonding metal layer, and the first bonding metal layer penetrates the bonding dielectric layer and the protective layer to electrically connect to the pad, and The bonding dielectric layer at least includes a first bonding dielectric material covering the pad and directly contacting the probe mark.

9. The semiconductor structure according to claim 8, further comprising: A top cover layer disposed on a top surface of the protective layer, wherein the probe mark is recessed from a top surface of the top cover layer into the top surface of the pad.

10. The semiconductor structure according to claim 9, wherein the first bonding metal layer penetrates the top cover layer and the protective layer to electrically connect to the pad.

11. The semiconductor structure according to claim 8, further comprising: A passivation layer disposed between the pad and the interconnect structure and between the bonding structure and the interconnect structure.

12. The semiconductor structure according to claim 11, wherein the bonding dielectric layer further comprises: A second bonding dielectric material disposed on the first bonding dielectric material; And A barrier layer disposed between the first bonding dielectric material and the second bonding dielectric material.

13. The semiconductor structure according to claim 11, wherein the bonding structure includes a second bonding metal layer disposed beside the pad, and the second bonding metal layer penetrates the bonding dielectric layer and the passivation layer to electrically connect to the interconnect structure.

14. The semiconductor structure according to claim 13, wherein the height of the second bonding metal layer is greater than the height of the first bonding metal layer.

15. A method of manufacturing a semiconductor structure, comprising: Forming an interconnect structure on a substrate; Forming a pad electrically connected to the interconnect structure on the interconnect structure; Performing a circuit probe test on the pad to form a probe mark on the top surface of the pad; Before performing the circuit probe test, forming a protective layer on the top surface of the pad; And Forming a bonding structure on the protective layer, wherein forming the bonding structure includes forming a bonding dielectric layer and forming a first bonding metal layer, the first bonding metal layer penetrates the bonding dielectric layer and the protective layer to electrically connect to the pad, wherein the bonding dielectric layer directly contacts the probe mark.

16. The method of manufacturing a semiconductor structure according to claim 15, wherein forming the bonding structure further comprises: Forming a second bonding metal layer beside the pad.

17. The method of manufacturing a semiconductor structure according to claim 16, wherein the height of the second bonding metal layer is greater than the height of the first bonding metal layer.

18. The method of manufacturing a semiconductor structure according to claim 15, wherein the probe mark is recessed from the top surface of the protective layer into the top surface of the pad.

19. The method of manufacturing a semiconductor structure according to claim 15, further comprising: Forming a top cover layer on the protective layer before performing the circuit probe test, wherein the probe mark is recessed from the top surface of the top cover layer into the top surface of the pad.

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