Vertical semiconductor devices

Abstract

The present invention provides a vertical semiconductor device. The vertical semiconductor device includes: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the channel; and a gate pattern on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction and extend in a second direction substantially parallel to the upper surface of the substrate.

Description

Technical Field

[0001] Example embodiments of the inventive concept relate to a semiconductor device including a memory cell storing multiple-bit data and a method of operating the semiconductor device. Background Art

[0002] In order to increase the storage capacity of semiconductor devices, a multi-level cell (MLC) for storing at least two bits of data in one memory cell has been developed. Examples of MLCs include a three-level cell storing three bits of data, a four-level cell storing four bits of data, or a five-level cell storing five bits of data. Therefore, a method of storing a plurality of bits of data in one memory cell and a method of reading the stored data from the memory cell without error are being developed. Summary of the invention

[0003] According to an exemplary embodiment of the present invention, a vertical semiconductor device is provided, comprising: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the channel; and a gate pattern on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction and the gate pattern extends in a second direction substantially parallel to the upper surface of the substrate.

[0004] According to an exemplary embodiment of the present invention, a vertical semiconductor device is provided, which includes: gate patterns stacked on a substrate, wherein the gate patterns are spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate; a channel passing through the gate patterns, wherein the channel is electrically connected to the substrate, and the channel has a cylindrical shape; a first data storage structure contacting a first sidewall of the channel; and a second data storage structure on a second sidewall of the channel opposite to the first sidewall, wherein the second data storage structure contacts the channel.

[0005] According to an exemplary embodiment of the present invention, a vertical semiconductor device is provided, which includes: a channel on a substrate; a first data storage structure formed on a first side of the channel; a second data storage structure formed on a second side of the channel opposite to the first side; and a gate pattern on the second data storage structure.

[0006] According to an exemplary embodiment of the present invention, a method for operating a semiconductor device is provided. The method may include: storing first data in a first data storage structure of the semiconductor device, the semiconductor device including storage cells, each storage cell including a first data storage structure and a second data storage structure; storing second data in a second data storage structure; reading the first data; and reading the second data.

[0007] According to an exemplary embodiment of the present invention, a vertical semiconductor device includes: a first gate pattern and a second gate pattern arranged in a vertical direction on a substrate, wherein an insulating layer is disposed between the first gate pattern and the second gate pattern; a channel layer disposed on the substrate; a first data storage element disposed on a first side of the channel layer; and a second data storage element disposed on a second side of the channel layer, wherein the second data storage element is disposed between the second side of the channel layer and the first gate pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view illustrating a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0009] Figure 2A , Figure 2B and Figure 2C is an enlarged cross-sectional view of a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0010] Figure 3 is a circuit diagram of a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0011] Figure 4 illustrates gate voltage-drain current according to states in a memory cell according to an exemplary embodiment of the inventive concept;

[0012] Figure 5 and Figure 6 are circuit diagrams illustrating a method of storing data in a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0013] Fig. 7A , Figure 7B , Fig. 8A and Figure 8B The number of states for storing a plurality of bits of data in a memory cell are respectively shown;

[0014] Fig. 9 , Fig.10 , Fig.11 and Fig.12is a view for explaining a method of reading data of a memory cell in a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0015] Fig.13 , Fig.14 , Fig.15 and Fig.16 are cross-sectional views illustrating various stages of a method of manufacturing a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0016] Fig.17 is a cross-sectional view illustrating a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0017] Fig.18 is an enlarged cross-sectional view of a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0018] Fig.19 is a circuit diagram of a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0019] Fig. 20 , Fig.21 and Fig. 22 are cross-sectional views illustrating various stages of a method of manufacturing a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0020] Fig.23 is a cross-sectional view illustrating a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0021] Fig.24 is an enlarged cross-sectional view of a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0022] Fig.25 is a cross-sectional view illustrating a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0023] Fig.26 is an enlarged cross-sectional view of a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept;

[0024] Fig. 27 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0025] Fig.28 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0026] Fig.29is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept; and

[0027] Fig.30 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0028] Exemplary embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Hereinafter, a direction substantially perpendicular to the upper surface of the substrate may be a first direction, a direction substantially parallel to the upper surface of the substrate may be a second direction, and a direction substantially perpendicular to the second direction and substantially parallel to the upper surface of the substrate may be a third direction.

[0030] Figure 1 is a cross-sectional view illustrating a vertical semiconductor device according to an exemplary embodiment of the inventive concept. Figure 2A , Figure 2B and Figure 2C is an enlarged cross-sectional view of a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept. Figure 3 is a circuit diagram of a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept.

[0031] Reference Figure 1 , Figure 2A and Figure 3 , the vertical semiconductor device may include a stack structure 142 formed on a substrate 100 and a vertical structure 126 including a channel 118 and passing through the stack structure 142. In addition, a bit line structure 156 may be formed on the stack structure 142. The bit line structure 156 may be electrically connected to the channel 118 of the vertical structure 126.

[0032] The substrate 100 may include a semiconductor material based on a group IV element (e.g., silicon, germanium, silicon germanium) or a group III-V semiconductor compound (e.g., GaP, GaAs, GaSb, etc.). In an exemplary embodiment of the present inventive concept, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0033] The stack structure 142 may include the insulating layers 102 and the gate patterns 140 that are alternately and repeatedly stacked. Therefore, the gate patterns 140 may be spaced apart from each other in the first direction.

[0034] The gate pattern 140 may serve as a gate of a cell transistor. In an exemplary embodiment of the present inventive concept, at least one gate pattern formed at the lowermost layer may serve as a gate of a ground selection transistor, and at least one gate pattern formed at the uppermost layer may serve as a gate of a string selection transistor.

[0035] The upper insulating layer 150 may be formed on the stack structure 142 . The stack structure 142 may extend in the second direction. A plurality of stack structures 142 may be arranged in the third direction, and the first trench 130 extending in the second direction may be formed between the stack structures 142 .

[0036] In exemplary embodiments of the present inventive concepts, the insulating pattern 144 may fill the first trench 130 .

[0037] In an exemplary embodiment of the present inventive concept, the common source line ( Figure 1 A common source line (not shown) may be formed in the first trench 130, and the common source line may be insulated from the sidewalls of the stack structure 142.

[0038] In an exemplary embodiment of the present inventive concept, the gate pattern 140 may include a barrier layer and a gate conductive layer. The gate conductive layer may include a metal having excellent gap filling performance and low resistivity. The gate conductive layer may include, for example, tungsten, titanium, tantalum, platinum, etc. The barrier layer may include, for example, a metal nitride, such as tungsten nitride, titanium nitride, tantalum nitride, etc.

[0039] The vertical structure 126 may pass through the stack structure 142 and may have a pillar shape. The vertical structure 126 may be formed in a channel hole 106 that passes through the stack structure 142 and extends to the upper surface of the substrate 100.

[0040] In exemplary embodiments of the present inventive concepts, the semiconductor pattern 108 may be formed on a lower surface of the channel hole 106 , and the semiconductor pattern 108 may contact an upper surface of the substrate 100 .

[0041] In an exemplary embodiment of the present inventive concept, the semiconductor pattern 108 may not be formed. In this case, a channel connection pattern may be formed on the substrate 100 to be electrically connected to the channel 118 and the substrate 100. The channel connection pattern may surround a lower portion of each channel 118 in the vertical structure 126.

[0042] The vertical structure 126 may include a second data storage structure 116, a channel 118, a first data storage structure 120, a filling insulation pattern 122, and an upper conductive pattern 124. The second data storage structure 116, the channel 118, the first data storage structure 120, and the filling insulation pattern 122 may be sequentially stacked on the sidewall of the channel hole 106. The upper conductive pattern 124 may be formed at an upper portion of the channel hole 106 to be electrically connected to the channel 118.

[0043] The second data storage structure 116 may include a blocking layer 110, a charge storage layer 112, and a tunnel insulating layer 114 sequentially stacked on the sidewalls of the channel hole 106. The blocking layer 110 may contact the gate pattern 140.

[0044] In exemplary embodiments of the present inventive concepts, the tunnel insulating layer 114 and the barrier layer 110 may include silicon oxide.

[0045] In exemplary embodiments of the present inventive concepts, the charge storage layer 112 may include a charge trapping layer or a charge floating layer.

[0046] For example, when data is stored in the charge storage layer 112 by the charges trapped in the charge storage layer 112, the charge storage layer 112 may include silicon nitride, metal oxide, etc. The metal oxide may include, for example, aluminum oxide. For example, when data is stored in the charge storage layer 112 by floating the charges in the charge storage layer 112, the charge storage layer 112 may include silicon. The charge storage layer 112 may include, for example, doped silicon, undoped silicon, etc.

[0047] The channel 118 may contact the tunnel insulating layer 114 and may be electrically connected to the substrate 100. In an exemplary embodiment of the present inventive concept, the channel 118 may have a cylindrical shape within the channel hole 106. In addition, a lower surface of the channel 118 may contact an upper surface of the semiconductor pattern 108. In an exemplary embodiment of the present inventive concept, the channel 118 may include polysilicon.

[0048] The first data storage structure 120 may be formed on the inner sidewall of the trench 118. In an exemplary embodiment of the inventive concept, the first data storage structure 120 may cover the inner sidewall of the trench 118. The first data storage structure 120 may extend in the first direction. For example, the first data storage structure 120 may have a cylindrical shape.

[0049] The first data storage structure 120 may include a variable resistance material. In other words, data may be written into the first data storage structure 120 by changing the resistance of the first data storage structure 120 .

[0050] In an exemplary embodiment of the present inventive concept, the first data storage structure 120 may include a resistive switching material. For example, the first data storage structure 120 may include a perovskite material such as STO (SrTiO 3 )、BTO(BaTiO 3 )、PCMO(Pr 1-X Ca X MnO 3 ), or metal oxides such as zirconium oxide, hafnium oxide, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, etc.

[0051] In an exemplary embodiment of the present invention, the first data storage structure 120 may include a phase change material, the phase of which may be changed into an amorphous state or a crystalline state by Joule heat. In this case, the resistance of the first data storage structure 120 may be changed by phase change. The phase change material may include, for example, a GST material, in which germanium (Ge), antimony (Sb) and / or tellurium (Te) may be combined in a predetermined ratio. In an exemplary embodiment of the present invention, the first data storage structure 120 may have a superlattice structure having a repeated stacking structure of GeTe-SbTe. In an exemplary embodiment of the present invention, the first data storage structure 120 may include an In-Sb-Te (IST) material or a Bi-Sb-Te (BST) material.

[0052] In exemplary embodiments of the present inventive concepts, the first data storage structure 120 may include a GeSe material.

[0053] In exemplary embodiments of the present inventive concepts, the first data storage structure 120 may include a chalcogenide-based omni-directional threshold switch (OTS) material.

[0054] The filling insulating pattern 122 may be formed on the first data storage structure 120 to fill most of the remaining portion of the channel hole 106. The remaining portion of the channel hole 106 may correspond to a portion of the channel hole 106 that has not been filled with anything after forming the first data storage structure 120. The filling insulating pattern 122 may include, for example, silicon oxide. The filling insulating pattern 122 may have a pillar shape.

[0055] The first data storage structure 120 , the channel 118 , the second data storage structure 116 , and the gate pattern 140 may be sequentially formed to surround the sidewall of the filling insulating pattern 122 .

[0056] like Figure 2AAs shown, the second data storage structure 116, the channel 118, the first data storage structure 120 and the filling insulating pattern 122 sequentially stacked on the sidewall of one of the gate patterns 140 may serve as one memory cell. Therefore, a plurality of memory cells may be stacked in the first direction.

[0057] The stack of layers formed on the sidewall of each gate pattern 140 may be variously modified.

[0058] In an exemplary embodiment of the present inventive concept, Figure 2B As shown, the first data storage structure 120 may have a structure in which two or more layers (e.g., 121a and 121b) may be stacked. For example, the first data storage structure 120 may include a layer 121a having a low oxygen vacancy density at a portion contacting the channel 118 and a layer 121b having a high oxygen vacancy density at a portion close to the filling insulating pattern 122. The layer 121a may directly contact the channel 118, and the layer 121b may directly contact the filling insulating pattern 122.

[0059] In an exemplary embodiment of the present inventive concept, Figure 2C As shown, an interface oxide layer 119a and an amorphous oxide layer 119b may be formed between the channel 118 and the first data storage structure 120. Alternatively, the interface oxide layer 119a may not be formed. Additional filament paths may be generated along the grain boundaries of the interface oxide layer 119a, thereby reducing electrical characteristic variations in the first data storage structure 120.

[0060] As described above, the one storage unit may include the first data storage structure 120 and the second data storage structure 116. Therefore, the one storage unit may include two data storage units in which data is stored in different mechanisms. For example, the one storage unit may include the first data storage unit through the first data storage structure 120 and include the second data storage unit through the second data storage structure 116.

[0061] A plurality of gate patterns 140 may be formed on sidewalls of the vertical structures 126 to be spaced apart from each other in the first direction. One of the vertical structures 126 and the plurality of gate patterns 140 may constitute one cell string.

[0062] Each memory cell included in the cell string may have a Figure 3 The circuit configuration shown.

[0063] exist Figure 3In each cell string shown, the channel 118 may extend in the first direction. The memory cell may be divided by a gate pattern 140 formed on the channel 118. The top of the cell string may be connected to the bit line B / L, and the bottom of the cell string may be connected to the common source line CSL. In addition, the transistor adjacent to the bit line B / L may be connected to the string selection line SSL at its gate, and the transistor adjacent to the common source line CSL may be connected to the ground selection line GSL at its gate.

[0064] Cell transistors 2 including the stacked second data storage structure 116 and the gate pattern 140 may be respectively disposed on outer sidewalls of the channel 118. The cell transistor 2 may function as a second data storage unit.

[0065] Charges may be stored in the charge storage layer 112 by an electric field in a direction perpendicular to the outer sidewalls of the channel 118 contacting the second data storage structure 116 , and thus data may be written in the second data storage structure 116 .

[0066] For example, charges may be injected from the channel 118 into the charge storage layer 112 by Fowler-Nordheim (FN) tunneling, or charges stored in the charge storage layer 112 may be erased by FN tunneling. Charges may be stored in the charge storage layer 112 by trapping or floating. Therefore, the threshold voltage of the cell transistor 2 may be changed by the charges stored in the charge storage layer 112. Data may be distinguished by the threshold voltage of the cell transistor 2.

[0067] In an exemplary embodiment of the inventive concept, the cell transistor 2 may have one of a plurality of threshold voltages according to the charge stored in the charge storage layer 112. Therefore, 1 bit or a plurality of bits of data may be stored in the cell transistor 2 included in one memory cell. In other words, the threshold voltage of the second data storage structure 116 may be divided into a plurality of levels so that at least two bits of data may be stored in the second data storage structure 116.

[0068] The first data storage structure 120 may be formed on the inner sidewall of the trench 118. The first data storage structure 120 may serve as a first data storage unit 1.

[0069] The resistance of the first data storage structure 120 may be changed by an electric field in a direction parallel to the inner sidewall of the channel 118. Data may be distinguished by the resistance level of the first data storage structure 120.

[0070] In an exemplary embodiment of the present inventive concept, the first data storage structure 120 may have one of a plurality of resistance levels. Therefore, one bit of data or a plurality of bits of data may be stored in the first data storage structure 120 included in the one memory cell. In other words, the resistance of the first data storage structure 120 may be divided into the plurality of levels so that at least two bits of data may be stored in the first data storage structure 120.

[0071] Figure 4 An example of gate voltage-drain current according to the state in the above-described memory cell is shown.

[0072] Reference Figure 4 When the gate voltage Vg of the memory cell is lower than the lowest on-voltage of the cell transistor 2, the cell transistor 2 can be turned off, so the resistance level of the first data storage structure 120 can be distinguished. In the memory cell, the resistance of the first data storage structure 120 can be divided into multiple resistance levels.

[0073] The resistance level of the first data storage structure 120 can be distinguished by the drain current. Figure 4 As shown, the drain current Id may have any one of four states. Therefore, the resistance level of the first data storage structure 120 may be classified into four states.

[0074] When the gate voltage Vg is higher than the lowest on-voltage of the cell transistor 2 in the memory cell, the cell transistor 2 may be turned off or on according to the charge storage state of the cell transistor 2. In other words, the threshold voltage of the cell transistor 2 in the memory cell may be divided into a plurality of threshold voltage levels.

[0075] The threshold voltage of the cell transistor 2 can be distinguished by the voltage having a specific drain current value Iverify. Figure 4 As shown, the threshold voltage may have any one of four levels. Therefore, the level of the threshold voltage of the second data storage structure 116 may be divided into four levels.

[0076] As described above, the one storage unit may include two data storage units in which data is stored by different mechanisms. Therefore, more data can be stored in the one storage unit. In addition, the number of data states required for the amount of data stored in the one storage unit can be reduced.

[0077] Data Writing

[0078] Hereinafter, a method of storing (or writing) data in a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept may be described.

[0079] Figure 5 and Figure 6 is a circuit diagram illustrating a method of storing data in a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept.

[0080] Reference Figure 5 , a method of storing data in the first data storage structure 120 of the selected memory cell SC may be described. Figure 5 The conditions in are as follows:

[0081] Selected gate pattern: Apply cut-off voltage (Voff),

[0082] Unselected gate pattern: Apply pass voltage (Vpass),

[0083] Bit line of the selected memory cell SC: A write pulse (Vwrite1) for the first data storage structure 120 is applied.

[0084] When the pass voltage Vpass is applied to the unselected gate patterns to turn on all the unselected gate patterns, current may flow through the channels of the unselected cell transistors. At this time, current may hardly flow through the first data storage structure 120 of the unselected memory cells.

[0085] The pass voltage Vpass may be a voltage higher than a threshold voltage (eg, a maximum threshold voltage) in a cell transistor of a data programming state.

[0086] In addition, when the off voltage Voff is applied to the selected gate pattern, current may not flow through the selected cell transistor. The off voltage Voff may be a voltage lower than a threshold voltage (eg, a minimum threshold voltage) in the cell transistor in a data erase state.

[0087] Therefore, a write pulse may be applied only to the first data storage structure 120 of the selected memory cell SC through the bit line. Therefore, data may be written in the first data storage structure 120 of the selected memory cell SC.

[0088] In exemplary embodiments of the inventive concept, the resistance of the first data storage structure 120 may have one of at least two states or at least two levels according to a write pulse.

[0089] For example, the resistance of the first data storage structure 120 may have one of two states (eg, resistance state 0 or resistance state 1). Therefore, one bit of data may be stored in the first data storage structure 120 of the one memory cell.

[0090] Alternatively, the resistance of the first data storage structure 120 may have one of four states. In this case, the resistance of the first data storage structure 120 may include one of resistance state 1 (0, 0), resistance state 2 (0, 1), resistance state 3 (1, 0), and resistance state 4 (1, 1). Therefore, two bits of data may be stored in the first data storage structure 120 of the one memory cell.

[0091] As described above, the resistance of the first data storage structure 120 may have a plurality of states, and a plurality of bits of data may be stored in the first data storage structure 120 .

[0092] Reference Figure 6 , a method of programming (or writing) data in the second data storage structure 116 of the selected memory cell SC may be described.

[0093] Figure 6 The programming conditions in are as follows:

[0094] Selected gate pattern: Apply programming voltage (Vpgm),

[0095] Unselected gate pattern: Apply pass voltage (Vpass),

[0096] The bit line of the selected memory cell SC: 0 V (GND) is applied.

[0097] When a program voltage Vpgm is applied to the selected gate pattern, charges may be injected from the channel 118 into the charge storage layer 112 of the second data storage structure 116. Thus, the threshold voltage of the selected cell transistor may be changed, so that data may be written in the second data storage structure 116 of the selected memory cell SC.

[0098] A method of erasing data in the second data storage structure 116 of a memory cell may also be described.

[0099] Data erasure conditions are as follows:

[0100] Selected gate pattern: Apply 0V (GND),

[0101] Unselected gate pattern: Apply 0V (GND),

[0102] The bit line of the selected memory cell: floating,

[0103] Substrate (channel): Apply erase voltage (Vers).

[0104] When the erase voltage Vers is applied to the channel 118, the charges in the charge storage layer 112 may be discharged to the channel 118, and thus, the data may be erased. Thus, the threshold voltage of the selected cell transistor may be lowered.

[0105] In exemplary embodiments of the inventive concept, a threshold voltage of a selected cell transistor may have one of at least two states or at least two levels through a program or erase operation.

[0106] For example, the threshold voltage of the selected cell transistor may have one of two states (eg, threshold voltage state 0 or threshold voltage state 1). Thus, one bit of data may be stored in the second data storage structure 116 of the one memory cell.

[0107] For example, the threshold voltage of the selected cell transistor may have one of four states. In this case, the threshold voltage of the selected cell transistor may include one of threshold voltage state 1 (0, 0), threshold voltage state 2 (0, 1), threshold voltage state 3 (1, 0) and threshold voltage state 4 (1, 1). Therefore, two bits of data may be stored in the second data storage structure 116 of one memory cell.

[0108] Therefore, multiple bits of data may be stored in the second data storage structure 116 .

[0109] As described above, the memory cell can store data in each of the two data storage structures. In other words, the memory cell can have two data parameters for storing data. Therefore, the number of states required to store multiple bits of data in the one memory cell can be reduced.

[0110] Fig. 7A , Figure 7B , Fig. 8A and Figure 8B The number of states for storing a plurality of bits of data in a memory cell is respectively shown.

[0111] Fig. 7A and Fig. 8A 1 shows the number of states in which two bits of data and four bits of data are stored in a storage unit having two data parameters according to an exemplary embodiment of the inventive concept. In comparison, Figure 7B and Figure 8B The numbers of states in which two-bit data and four-bit data are respectively stored in one memory cell having one data parameter are shown.

[0112] Reference Fig. 7A, when one bit of data is stored in each of the first data storage structure 120 and the second data storage structure 116, two bits of data can be stored in one memory cell. In other words, one memory cell can store one of two resistance states (I) in the first data storage structure 120 and store one of two threshold voltage states (Vth) in the second data storage structure 116. In other words, one memory cell can be divided into four states by a combination of the states of the first data storage structure 120 and the second data storage structure 116, so that two bits of data can be stored in one memory cell.

[0113] On the other hand, refer to Figure 7B , when only one data storage structure is included in one memory cell, the data storage structure of the one memory cell may include four states to store two bits of data in the one memory cell.

[0114] Reference Fig. 8A , when two bits of data are stored in each of the first data storage structure 120 and the second data storage structure 116, four bits of data can be stored in the one memory cell. In other words, the one memory cell can store one of four resistance states (I) in the first data storage structure 120 and one of four threshold voltage states (Vth) in the second data storage structure 116. In other words, the data storage structure of the memory cell may include eight states. Therefore, data can be stored in each of the first data storage structure 120 and the second data storage structure 116, so that one memory cell can be divided into sixteen states by a combination of the states of the first data storage structure 120 and the second data storage structure 116. Therefore, four bits of data can be stored in one memory cell.

[0115] On the other hand, refer to Figure 8B , when only one data storage structure is included in one memory cell, the data storage structure of the one memory cell may include sixteen states to store four bits of data in the one memory cell.

[0116] In other words, when the one storage unit includes only one data storage structure, the one storage unit may need 2 n states to store n bits of data in the one memory cell.

[0117] On the other hand, when a storage unit includes two data storage structures, the storage unit may need two a +2 b (a+b=n) states are used to store n bits of data in the one memory cell.

[0118] As described above, data can be stored in each of the two data storage structures, and the data can be combined with each other. Therefore, the number of states required for a storage unit with multiple bits can be reduced. Therefore, the data stored in a storage unit can be easily distinguished.

[0119] On the other hand, in the general case of only one storage unit of one data storage structure, as the number of data bits stored in one storage unit increases, the number of states to be distinguished in the data storage structure can increase significantly. Therefore, each state may not be stored and read separately in the one storage unit.

[0120] However, in an exemplary embodiment of the present invention, as the number of data bits stored in a storage cell increases, the number of states required in the one storage cell can be significantly reduced compared to the case of a storage cell including a data storage structure. For example, according to an exemplary embodiment of the present invention, when six bits of data are stored in a storage cell, sixteen states may be required in the one storage cell. However, in the case of a storage cell including a data storage structure, 64 states may be required to store six bits of data in the storage cell. Therefore, according to an exemplary embodiment of the present invention, each state can be easily stored and read in a storage cell.

[0121] Data reading

[0122] Hereinafter, a method of reading data of a memory cell in a vertical semiconductor device according to an exemplary embodiment of the inventive concept may be described.

[0123] Figures 9 to 12 is a view for explaining a method of reading data of a memory cell in a vertical semiconductor device.

[0124] Reference Fig. 9 , a method of reading data of the first data storage structure 120 of the selected memory cell SC may be described. Fig. 9 The conditions are as follows:

[0125] Selected gate pattern: Apply cut-off voltage (Voff),

[0126] Unselected gate pattern: Apply pass voltage (Vpass),

[0127] The bit line of the selected memory cell SC: a first read voltage (Vread1) is applied.

[0128] When the pass voltage Vpass is applied to turn on all the unselected gate patterns, current may flow through the channels of the unselected cell transistors. At this time, current may hardly flow through the first data storage structure 120 of the unselected memory cells.

[0129] In addition, when the off voltage Voff is applied to the selected gate pattern, current may not flow through the selected cell transistor. Therefore, current may flow through the first data storage structure 120 depending on the resistance of the first data storage structure 120 of the selected memory cell SC.

[0130] Therefore, a current level may change as the resistance of the first data storage structure 120 changes. Therefore, data stored in the first data storage structure 120 of the selected memory cell SC may be read by comparing the current level with the verification current level.

[0131] In an exemplary embodiment of the inventive concept, when one bit of data is stored in the first data storage structure 120, two resistance states (e.g., resistance state 0 or resistance state 1) of the first data storage structure 120 may be distinguished by one verification current level. The one verification current level may be referred to as a first verification current level.

[0132] Fig.10 The distribution of the current level when two bits of data are stored in the first data storage structure 120 is shown.

[0133] Reference Fig.10 , when two bits of data are stored in the first data storage structure 120, one of four read current states may exist depending on the resistance of the first data storage structure 120. Therefore, the four resistance states of the first data storage structure 120, such as resistance state 1 (0, 0), resistance state 2 (0, 1), resistance state 3 (1, 0), and resistance state 4 (1, 1), may be distinguished by three verification current levels (in other words, Iref1, Iref2, and Iref3).

[0134] Reference Fig.11 , a method of reading data of the second data storage structure 116 of the selected memory cell SC may be described. Fig.11 The conditions are as follows:

[0135] Selected gate pattern: Apply read verification voltage (Vverify),

[0136] Unselected gate pattern: Apply pass voltage (Vpass),

[0137] The bit line of the selected memory cell SC: a second read voltage (Vread2) is applied.

[0138] When the pass voltage Vpass is applied to turn on all the unselected gate patterns, current may flow through the channels of the unselected cell transistors. At this time, current may hardly flow through the first data storage structure 120 of the unselected memory cells.

[0139] In addition, when the read verification voltage Vverify is applied to the selected gate pattern, the selected cell transistor can be turned on or off according to the data written in the selected cell transistor. Therefore, according to the threshold voltage of the selected cell transistor, current may or may not flow through the selected cell transistor.

[0140] Therefore, when the read verification voltage Vverify is applied to the selected gate pattern, the current level flowing through the selected cell transistor can be changed by turning on or off the selected transistor according to the data written into the second data storage structure 116. The threshold voltage of the selected cell transistor can be distinguished by the current level. Therefore, the data stored in the second data storage structure 116 can be read.

[0141] At this time, even if the selected transistor is turned off, current slightly flows through the first data storage structure 120 according to the resistance of the first data storage structure 120 of the selected memory cell SC. Therefore, the verification current value (e.g., Figure 4 Iverify) in the selected memory cell SC is set to a current value higher than the current flowing through the first data storage structure 120 having a low resistance state in the selected memory cell SC.

[0142] In an exemplary embodiment of the inventive concept, when one bit of data is stored in the second data storage structure 116, two threshold voltage states (eg, threshold voltage state 0 or threshold voltage state 1) of the second data storage structure 116 can be distinguished by applying a read verification voltage.

[0143] Fig.12 The distribution of threshold voltages when two bits of data are stored in the second data storage structure 116 is shown.

[0144] Reference Fig.12 , when two bits of data are stored in the second data storage structure 116, the second data storage structure 116 may have one of four threshold voltage states. In other words, the four threshold voltage states of the second data storage structure 116, such as threshold voltage state 1 (0, 0), threshold voltage state 2 (0, 1), threshold voltage state 3 (1, 0), and threshold voltage state 4 (1, 1), may be distinguished by applying three read verification voltages (e.g., Vverify1, Vverify2, and Vverify3).

[0145] As described above, a storage unit may include two data storage units in which data is stored by different mechanisms. The data stored in each data storage unit can be read separately. In addition, the number of data states required for the number of data stored in a storage unit can be reduced; therefore, the data can be correctly and easily read.

[0146] Data writing and reading order

[0147] Hereinafter, an example of an order for writing data in a memory cell may be described. However, the order for writing data in a memory cell may not be limited thereto.

[0148] In an exemplary embodiment of the present inventive concept, first, data may be written in the second data storage structure 116 including the charge storage layer 112. Thereafter, data may be written in the first data storage structure 120 including the variable resistance material.

[0149] In an exemplary embodiment of the present inventive concept, first, data may be written in the first data storage structure 120 including the variable resistance material. Thereafter, data may be written in the second data storage structure 116 including the charge storage layer 112.

[0150] In an exemplary embodiment of the inventive concept, data may be sequentially stored in the first data storage structure 120 and the second data storage structure 116 of the selected memory cell SC, respectively. For example, data may be written in the first data storage structure 120 including the variable resistance material of the selected memory cell SC, and then, the data may be written in the second data storage structure 116 including the charge storage layer 112 of the selected memory cell SC. For example, data may be written in the second data storage structure 116 of the selected memory cell SC, and then, the data may be written in the first data storage structure 120 of the selected memory cell SC.

[0151] Hereinafter, an example of an order for reading data stored in a storage unit may be described. However, the order for reading data stored in a storage unit may not be limited thereto.

[0152] In an exemplary embodiment of the present inventive concept, first, data of the second data storage structure 116 may be read. Thereafter, data of the first data storage structure 120 including the variable resistance material may be read.

[0153] In an exemplary embodiment of the present inventive concept, first, data of the first data storage structure 120 may be read. Thereafter, data of the second data storage structure 116 may be read.

[0154] In an exemplary embodiment of the present inventive concept, first, data of the first data storage structure 120 of the selected memory cell SC may be read. Thereafter, data of the second data storage structure 116 of the selected memory cell SC may be read. In this case, the verification current value (e.g., Figure 4 Iverify) in the selected memory cell SC is set to a current value higher than the current flowing through the first data storage structure 120 having a low resistance state in the selected memory cell SC.

[0155] However, the current flowing through the first data storage structure 120 may be abnormally high, in which case the current may be higher than the verification current Iverify (20, see Figure 4 ). If the current value flowing through the first data storage structure 120 is higher than the verification current Iverify, the verification current Iverify may be increased. In other words, the verification current Iverify may be reset to a value obtained by dividing the current flowing through the first data storage structure 120 by a fixed offset current ( Figure 4 Therefore, the reset verification current (Iverify1) can be higher than the original verification current Iverify.

[0156] Figures 13 to 16 are cross-sectional views illustrating stages of a method of fabricating a vertical semiconductor device according to an exemplary embodiment of the inventive concept.

[0157] Reference Fig.13 , the insulating layer 102 and the first sacrificial layer 104 may be alternately and repeatedly stacked on the substrate 100 to form a first mold layer. An upper surface of the first mold layer may be an upper surface of the insulating layer 102 .

[0158] In an exemplary embodiment of the present inventive concept, the insulating layer 102 may include an oxide such as silicon oxide. The first sacrificial layer 104 may include a nitride such as silicon nitride.

[0159] A plurality of channel holes 106 may be formed through the first mold layer to expose a surface of the substrate 100 .

[0160] In exemplary embodiments of the present inventive concepts, a semiconductor pattern 108 may be further formed on a bottom surface of the channel hole 106 , and the semiconductor pattern 108 may contact the substrate 100 .

[0161] A blocking layer 110, a charge storage layer 112, and a tunnel insulating layer 114 may be sequentially formed on an upper surface of the first mold layer, a sidewall of the channel hole 106, and an upper surface of the semiconductor pattern 108. Portions of the blocking layer 110, the charge storage layer 112, and the tunnel insulating layer 114 formed on the upper surface of the first mold layer and the upper surface of the semiconductor pattern 108 may be removed by an anisotropic etching process. Thus, the blocking layer 110, the charge storage layer 112, and the tunnel insulating layer 114 may be sequentially stacked on the sidewall of the channel hole 106. The blocking layer 110, the charge storage layer 112, and the tunnel insulating layer 114 may serve as a second data storage structure 116.

[0162] Reference Fig.14 A channel layer may be conformally formed on the tunnel insulating layer 114 , the semiconductor pattern 108 , and the first mold layer. A variable resistance layer may be formed on the channel layer. Thereafter, a filling insulating layer may be formed on the variable resistance layer to fill the channel hole 106 .

[0163] The filling insulating layer, the variable resistance layer, and the channel layer may be planarized until the upper surface of the first mold layer is exposed. The upper portion of the variable resistance layer and the upper portion of the filling insulating layer may be partially removed to form an upper recess that exposes the upper sidewall of the channel layer. An upper conductive pattern 124 may be formed to fill the upper recess.

[0164] Thus, a vertical structure 126 including the second data storage structure 116 , the trench 118 , the first data storage structure 120 , the filling insulation pattern 122 , and the upper conductive pattern 124 may be formed to fill the channel hole 106 .

[0165] The channel 118 may be formed on the tunnel insulating layer 114 and the semiconductor pattern 108 and may have a cylindrical shape. The channel 118 may be electrically connected to the substrate 100. The channel 118 may be disposed between the first data storage structure 120 and the second data storage structure 116. The channel 118 may include, for example, polysilicon.

[0166] The variable resistance layer formed on the channel 118 may include, for example, a cylindrical shape. The variable resistance layer may serve as a first data storage structure 120.

[0167] The filling insulating pattern 122 may be formed on the variable resistance layer and may fill most of the channel hole 106. The upper conductive pattern 124 may contact an upper portion of the channel 118. The upper conductive pattern 124 may include, for example, polysilicon.

[0168] Reference Fig.15, a first trench 130 passing through the first mold layer may be formed by an anisotropic etching process. The upper surface of the substrate 100 may be exposed by the first trench 130. The first trench 130 may extend in the second direction. A mold structure extending in the second direction may be formed by forming the first trench 130.

[0169] The first sacrificial layer 104 exposed by the sidewalls of the first trench 130 may be removed to form a first gap 132 between the insulating layers 102. A portion of the outer wall of the vertical structure 126 may be exposed through the first gap 132. In other words, a portion of the barrier layer 110 and the sidewalls of the semiconductor pattern 108 may be exposed through the first gap 132.

[0170] Reference Fig.16 , a gate electrode layer may be formed to fill at least the first gap 132 , and the gate electrode layer formed in the first trench 130 may be removed to form a gate pattern 140 in the first gap 132 .

[0171] In an exemplary embodiment of the present inventive concept, before forming the gate electrode layer, a second barrier layer may be further formed on the surface of the first gap 132 .

[0172] In an exemplary embodiment of the present inventive concept, the gate pattern 140 may include a barrier layer and a gate conductive layer sequentially stacked. The gate conductive layer may include a metal having a low resistivity such as tungsten, titanium, tantalum, and platinum, and the barrier layer may include a metal nitride such as tungsten nitride, titanium nitride, and tantalum nitride.

[0173] Thereafter, an insulating pattern 144 may be formed in the first trench 130 .

[0174] In exemplary embodiments of the present inventive concepts, insulating spacers may be formed on sidewalls of the first trench 130 , and a common source line may be formed in the first trench 130 to contact the substrate 100 .

[0175] By performing the above processes, a stack structure 142 including the insulating layers 102 and the gate patterns 140 which are alternately and repeatedly stacked may be formed on the substrate 100 .

[0176] Refer again Figure 1 , an upper insulating layer 150 may be formed on the stacked structure 142 and the insulating pattern 144. A bit line contact 152 may be formed through the upper insulating layer 150 and may be electrically connected to the upper conductive pattern 124. In addition, a bit line 154 extending in a third direction may be formed on the upper insulating layer 150 and the bit line contact 152. Thus, a bit line structure 156 including the bit line contact 152 and the bit line 154 may be formed.

[0177] As described above, a variable resistance layer is formed on the inner sidewall of the channel 118 ; therefore, a vertical semiconductor device having a memory cell including the first data storage structure 120 and the second data storage structure 116 may be manufactured.

[0178] A vertical semiconductor device according to an exemplary embodiment of the inventive concept may include two data storage cells in one memory cell. However, various modifications may be made to the structure of the memory cell and the shape of the memory cell.

[0179] Fig.17 is a cross-sectional view illustrating a vertical semiconductor device according to an exemplary embodiment of the inventive concept. Fig.18 is an enlarged cross-sectional view of a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept. Fig.19 is a circuit diagram of a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept.

[0180] Reference Figures 17 to 19 , the vertical semiconductor device may include a stack structure 142 a formed on a substrate 100 and a vertical structure 126 including a channel 118 and passing through the stack structure 142 a.

[0181] The stack structure 142 a may include insulating layers 102 and gate patterns 140 a that are alternately and repeatedly stacked.

[0182] The vertical structure 126 may include a second data storage structure 116, a channel 118, a first data storage structure 120a, and a filling insulating pattern 122 sequentially stacked on the gate pattern 140a in a direction parallel to the surface of the substrate 100. An upper conductive pattern 124 may be formed at an upper portion of the channel 118.

[0183] The first data storage structure 120a may face the gate pattern 140a and may have an isolated shape. For example, the first data storage structure 120a may protrude toward the gate pattern 140a along the third direction. The first data storage structures 120a included in the memory cells of the cell string may be spaced apart from each other in the first direction. In addition, the second data storage structure 116 included in the memory cells of the cell string may extend in the first direction, and the channel 118 may extend in the first direction.

[0184] In an exemplary embodiment of the present inventive concept, a recess (107, refer to FIG. 107 ) may be provided at a region from a sidewall of the channel hole 106 to a sidewall of the gate pattern 140a. Fig. 20 ). In other words, the recesses 107 may be opened through the sidewalls of the channel holes 106, and the recesses 107 may be repeatedly arranged to be spaced apart from each other in the first direction.

[0185] A vertical structure 126 may be formed in the channel hole 106 and the recess 107 .

[0186] In an exemplary embodiment of the present inventive concept, the second data storage structure 116 may be conformally formed on the sidewalls of the channel hole 106 and the surface of the recess 107. The channel 118 may be conformally formed on the surface of the channel hole 106 and in the recess 107. Therefore, the channel 118 may be electrically connected to the substrate 100.

[0187] The first data storage structures 120a may be formed in the recess 107, and may contact the channel 118. Thus, the first data storage structures 120a may be formed on the channel 118, and the first data storage structures 120a may be spaced apart from each other in the first direction.

[0188] In an exemplary embodiment of the present inventive concept, the gate pattern 140 formed on the sidewall of the semiconductor pattern 108 may have a shape similar to that of Figure 1 The shape shown is the same shape.

[0189] Each memory cell included in the cell string may have a Fig.19 See the circuit diagram shown. Fig.19 , first data storage structures (eg, variable resistance layers) of the memory cells may be physically spaced apart from each other. Fig.19 The electrical operation of the circuit diagram can be compared with Figure 3 The electrical operation of the circuit diagrams shown is essentially the same.

[0190] Therefore, it can be compared with the reference Figures 5 to 12 The vertical semiconductor device may store a plurality of bits of data in each of the first data storage structure 120a and the second data storage structure 116 of one memory cell.

[0191] Figure 20 to Figure 22 are cross-sectional views illustrating stages of a method of fabricating a vertical semiconductor device according to an exemplary embodiment of the inventive concept.

[0192] Reference Fig. 20 , an insulating layer 102 and a first sacrificial layer 104 may be alternately and repeatedly formed on a substrate 100 to form a first mold layer. A channel hole 106 may be formed through the first mold layer to expose a surface of the substrate 100. In an exemplary embodiment of the present inventive concept, a semiconductor pattern 108 may be formed on a bottom surface of the channel hole 106, and the semiconductor pattern 108 may contact the substrate 100.

[0193] Thereafter, a portion of the first sacrificial layer 104 exposed by the sidewall of the channel hole 106 may be etched to form a recess 107 .

[0194] Reference Fig.21 , a blocking layer 110, a charge storage layer 112, and an insulating layer 114 may be sequentially formed on an upper surface of the first mold layer, a sidewall of the channel hole 106, and an upper surface of the semiconductor pattern 108. The blocking layer 110, the charge storage layer 112, and the tunnel insulating layer 114 formed on the upper surface of the first mold layer and the upper surface of the semiconductor pattern 108 may be anisotropically etched. Therefore, the blocking layer 110, the charge storage layer 112, and the tunnel insulating layer 114 may be sequentially and conformally formed on the sidewall of the channel hole 106 and the surface of the recess 107. The blocking layer 110, the charge storage layer 112, and the tunnel insulating layer 114 may serve as a second data storage structure 116.

[0195] Reference Fig. 22 A channel layer may be conformally formed on the tunnel insulating layer 114 and the first mold layer. A variable resistance layer may be formed on the channel layer. The channel layer may not completely fill the recess 107. The variable resistance layer may completely fill the recess 107.

[0196] A portion of the variable resistance layer may be etched so that the variable resistance layer may remain only in the recess 107. Thus, a variable resistance pattern may be formed in the recess 107, and a plurality of variable resistance patterns may be spaced apart from each other in the first direction. Each variable resistance pattern may serve as a first data storage structure 120a.

[0197] Thereafter, a filling insulating layer may be formed on the first data storage structure 120a and the channel layer to fill the remaining portion of the channel hole 106. Thereafter, the filling insulating layer and the channel layer may be planarized until the upper surface of the first mold layer is exposed to form a filling insulating pattern 122 and the channel 118.

[0198] An upper portion of the filling insulating pattern 122 may be partially removed to form an upper recess exposing an upper sidewall of the trench 118 . An upper conductive pattern 124 may be formed to fill the upper recess. Thus, a vertical structure 126 may be formed in the trench hole 106 .

[0199] Subsequently, the reference can be performed in the same way Fig.15 , Fig.16 and Figure 1 Therefore, it is possible to manufacture Fig.17 A vertical semiconductor device is shown.

[0200] Fig.23 is a cross-sectional view illustrating a vertical semiconductor device according to an exemplary embodiment of the inventive concept. Fig.24is an enlarged cross-sectional view of a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept.

[0201] Reference Fig.23 and Fig.24 , the vertical semiconductor device may include a stack structure 142 formed on a substrate 100 and a vertical structure 126 a including a channel 118 and passing through the stack structure 142 .

[0202] The stack structure 142 may include insulating layers 102 and gate structures 141 that are alternately and repeatedly stacked. Thus, the gate structures 141 may be spaced apart from each other in the first direction.

[0203] The gate structure 141 may include a gate pattern 140 and a second data storage structure 116 surrounding a surface of the gate pattern 140. The second data storage structure 116 may include a blocking layer 110, a charge storage layer 112, and a tunnel insulating layer 114 sequentially stacked on a surface of the gate pattern 140.

[0204] The vertical structure 126 a may pass through the stack structure 142 and may have a pillar shape. The vertical structure 126 a may include a channel 118 , a first data storage structure 120 a , a filling insulation pattern 122 , and an upper conductive pattern 124 .

[0205] Channel hole 106 (see Fig. 20 ) may extend through the stacked structure 142 to the upper surface of the substrate 100. The recess 107 (see Fig. 20 ) may be disposed at a portion from the sidewall of the channel hole 106 to the sidewall of the gate pattern 140. In other words, the recess 107 may be opened through the sidewall of the channel hole 106, and a plurality of recesses 107 may be arranged in the first direction to be spaced apart from each other.

[0206] The vertical structure 126 a may be formed in the channel hole 106 and the recess 107 .

[0207] The channel 118 may be electrically connected to the substrate 100. The channel 118 may be conformally formed on the surface of the channel hole 106 and the surface of the recess 107, and may have a cylindrical shape. The diameter of the cylindrical shape may change as the distance from the substrate 100 changes.

[0208] A variable resistance pattern may be formed in each of the recesses 107, and may contact the channel 118. The variable resistance pattern may serve as a first data storage structure 120a.

[0209] The filling insulation pattern 122 may contact the first data storage structure 120 a and the channel 118 , and may fill most of the remaining portion of the channel hole 106 .

[0210] As described above, the variable resistance patterns in the memory cells may be physically spaced apart from each other. Fig.19 The circuit diagram shown is basically the same as the circuit diagram.

[0211] Hereinafter, a method of manufacturing the vertical type semiconductor device is briefly described.

[0212] First, you can execute and refer to Fig. 20 Subsequently, a channel 118 and a variable resistance pattern may be formed in the channel hole 106 and the recess 107. In addition, a filling insulation pattern 122 and an upper conductive pattern 124 may be formed in the channel hole 106, so that a vertical structure may be formed.

[0213] After that, you can execute and refer to Fig.15 The process shown is the same process to form the first trench 130 and the first gap 132 .

[0214] Then, refer to Fig.23 , a tunnel insulating layer 114, a charge storage layer 112, and a blocking layer 110 may be conformally formed in the first trench 130 and the first gap 132. A gate electrode layer may be formed on the blocking layer 110 to fill the first gap 132. Thereafter, the gate electrode layer formed in the first trench 130 may be selectively removed to form a gate pattern 140.

[0215] In exemplary embodiments of the present inventive concepts, the tunnel insulating layer 114 , the charge storage layer 112 , and the blocking layer 110 formed in the first trench 130 may be removed.

[0216] Thereafter, an insulating pattern 144 may be formed in the first trench 130 .

[0217] Thus, the stack structure 142 may be formed to include the insulating layers 102 and the gate structures 141 which are alternately and repeatedly stacked.

[0218] Subsequently, an upper insulating layer 150 and a bit line structure 156 are formed on the stack structure 142. Thus, Fig.23 A vertical semiconductor device is shown.

[0219] Fig.25 is a cross-sectional view illustrating a vertical semiconductor device according to an exemplary embodiment of the inventive concept. Fig.26 is an enlarged cross-sectional view of a memory cell of a vertical semiconductor device according to an exemplary embodiment of the inventive concept.

[0220] Reference Fig.25 and Fig.26, the vertical semiconductor device may include a stack structure 142 formed on a substrate 100 and a vertical structure 126 a including a channel 118 and passing through the stack structure 142 .

[0221] The stack structure 142 may include insulating layers 102 and gate structures 141 that are alternately and repeatedly stacked. Fig.23 and Fig.24 The stacking structure shown is essentially the same.

[0222] The channel hole 106 may extend through the stack structure 142 to the upper surface of the substrate 100 .

[0223] The vertical structure 126a may include the channel 118, the first data storage structure 120, the filling insulation pattern 122, and the upper conductive pattern 124. The vertical structure 126a may be formed in the channel hole 106.

[0224] The channel 118 may be electrically connected to the substrate 100. The channel 118 may have a cylindrical shape in the channel hole 106.

[0225] The first data storage structure 120 may be formed on the channel 118. Thus, the first data storage structure 120 may have a cylindrical shape. The first data storage structure 120 may be a variable resistance layer.

[0226] A filling insulation pattern 122 may be formed on the first data storage structure 120 to fill most of the remaining portions of the channel holes 106 .

[0227] As described above, the first data storage structures 120 of the memory cells in the cell string may be connected to each other in the first direction. Figure 3 The circuit diagram shown is basically the same as the circuit diagram.

[0228] Hereinafter, a method of manufacturing the vertical type semiconductor device is briefly described.

[0229] First, you can execute and refer to Fig.13 The same process as shown in the figure is used to form a channel hole 106 through the first mold layer to expose the surface of the substrate 100. After the channel hole 106 is formed, a channel 118 and a first data storage structure 120 may be conformally formed on the surface of the channel hole 106. A filling insulation pattern 122 and an upper conductive pattern 124 may be formed in the channel hole, so that a vertical structure 126a may be formed.

[0230] Afterwards, you can perform a reference Fig.15 The process is described to form the first trench 130 and the first gap 132 .

[0231] Reference Fig.25, the tunnel insulating layer 114, the charge storage layer 112, and the blocking layer 110 may be conformally formed in the first trench 130 and the first gap 132. A gate electrode layer may be formed on the blocking layer 110 to fill the first gap 132. Thereafter, the gate electrode layer formed in the first trench 130 may be selectively removed to form a gate pattern 140. In an exemplary embodiment of the present inventive concept, the tunnel insulating layer 114, the charge storage layer 112, and the blocking layer 110 formed in the first trench 130 may be removed.

[0232] Thereafter, an insulating pattern 144 may be formed in the first trench 130 .

[0233] Thus, the stack structure 142 may be formed to include the insulating layers 102 and the gate structures 141 which are alternately and repeatedly stacked.

[0234] Subsequently, an upper insulating layer 150 and a bit line structure 156 may be formed on the stack structure 142. Thus, an Fig.25 A vertical semiconductor device is shown.

[0235] Fig. 27 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Fig.28 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0236] Fig. 27 and Fig.28 Each of can be a planar semiconductor device.

[0237] Reference Fig. 27 , the semiconductor device may include an insulating layer 220 on the substrate to cover the upper surface of the substrate 100 .

[0238] The first data storage structure 222 may be formed on the insulating layer 220. The first data storage structure 222 may include a resistance switching material or a phase change material.

[0239] A channel 224 and a second data storage structure 232 may be formed on the first data storage structure 222. The second data storage structure 232 may include a blocking layer 226, a charge storage layer 228, and a tunnel insulating layer 230 sequentially stacked on the channel 224.

[0240] The gate pattern 240 may be formed on the second data storage structure 232 .

[0241] In an exemplary embodiment of the present inventive concept, the first data storage structure 222 may extend in the third direction. In an exemplary embodiment of the present inventive concept, the channel 224 may extend in the third direction. In an exemplary embodiment of the present inventive concept, the channel 224 may cover the insulating layer 220 and the first data storage structure 222.

[0242] In an exemplary embodiment of the present inventive concept, the second data storage structure 232 may extend in the third direction.

[0243] In an exemplary embodiment of the present inventive concept, Fig.28 As shown, the second data storage structure 232a may have an isolated shape. In other words, the second data storage structure 232a may include a blocking pattern 226a, a charge storage pattern 228a, and a tunnel insulating pattern 230a sequentially stacked on the channel 224.

[0244] The gate pattern 240 may extend in the second direction. A plurality of gate patterns 240 may be spaced apart in the third direction.

[0245] Fig. 27 The stacking of memory cells of the semiconductor device shown may be similar to that of the reference Figure 1 and the stacking of memory cells of the vertical semiconductor device shown in FIG. 2 .

[0246] Fig.29 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Fig.30 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0247] Fig.29 and Fig.30 Each of can be a planar semiconductor device.

[0248] Reference Fig.29 , the semiconductor device may include an insulating layer 220 on the substrate 100 to cover the substrate 100. The first data storage structure 222a, the channel 224, and the second data storage structure 232 may be formed on the insulating layer 220. In addition, the gate pattern 240 may be formed on the second data storage structure 232.

[0249] In exemplary embodiments of the inventive concepts, the first data storage structure 222 a may have an isolated pattern shape.

[0250] In an exemplary embodiment of the present inventive concept, the first data storage structure 222a may be formed in a recess included in the insulating layer 220. Therefore, an upper surface of the first data storage structure 222a and an upper surface of the insulating layer 220 may be coplanar with each other. In an exemplary embodiment of the present inventive concept, the first data storage structure 222a may be formed on a flat upper surface of the insulating layer 220. In this case, an upper surface of the first data storage structure 222a may protrude from an upper surface of the insulating layer 220.

[0251] In an exemplary embodiment of the present inventive concept, the channel 224 may extend in the third direction. In an exemplary embodiment of the present inventive concept, the channel 224 may cover the insulating layer 220 and the first data storage structure 222a.

[0252] In an exemplary embodiment of the present inventive concept, the second data storage structure 232 may extend in the third direction. Fig.30 As shown, the second data storage structure 232a may have an isolated shape. In other words, the second data storage structure 232a may include a blocking pattern 226a, a charge storage pattern 228a, and a tunnel insulating pattern 230a sequentially stacked on the channel 224.

[0253] The gate pattern 240 may extend in the second direction. The plurality of gate patterns 240 may be spaced apart in the third direction.

[0254] In the case of a planar semiconductor device, data may be stored in each of the first and second data storage structures of a memory cell, and the stored data may be individually read in the same manner as in a vertical semiconductor device.

[0255] Figures 27 to 30 Each semiconductor device shown can be used with reference to Figures 4 to 12 The write operation and the read operation are performed in substantially the same manner as described.

[0256] A semiconductor device according to an exemplary embodiment of the present invention may include two data storage structures in one memory cell, so that the amount of data stored in the one memory cell may be increased. In addition, the number of data states required for the amount of data stored in the one memory cell may be reduced. Furthermore, in the semiconductor device, the data stored in each of the first data storage structure and the second data storage structure in the one memory cell may be read separately.

[0257] While the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as set forth in the following claims.

[0258] This application claims the priority of Korean Patent Application No. 10-2019-0069038 filed on June 12, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A vertical semiconductor device, comprising: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the trench; and A gate pattern is provided on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction and extend in a second direction substantially parallel to the upper surface of the substrate.

2. The vertical semiconductor device according to claim 1, wherein: The first data storage structure includes a variable resistance material.

3. The vertical semiconductor device according to claim 1, wherein: The first data storage structure includes SrTiO3, BaTiO3, Pr 1-X Ca X MnO3, zirconium oxide, hafnium oxide, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, titanium oxide or tantalum oxide.

4. The vertical semiconductor device according to claim 1, wherein: The first data storage structure includes a GeSe material or a phase change material including germanium (Ge), antimony (Sb) and / or tellurium (Te).

5. The vertical semiconductor device according to claim 1, wherein: The second data storage structure includes a tunnel insulating layer, a charge storage layer and a blocking layer.

6. The vertical semiconductor device according to claim 5, wherein: The charge storage layer is a floating layer including silicon.

7. The vertical semiconductor device according to claim 5, wherein: The charge storage layer is a charge trapping layer including silicon nitride or metal nitride.

8. The vertical semiconductor device according to claim 1, wherein: The first data storage structure covers the first sidewall of the trench.

9. The vertical semiconductor device according to claim 1, wherein: A plurality of the first data storage structures are spaced apart from each other in the first direction, and the first data storage structures face each other in a horizontal direction with respect to the upper surface of the substrate.

10. The vertical semiconductor device according to claim 1, wherein: Data is stored in the first data storage structure and the second data storage structure respectively through electric fields in different directions.

11. The vertical semiconductor device according to claim 1, wherein: First data is stored in the first data storage structure by an electric field in a direction substantially parallel to the first sidewall of the channel, and second data is stored in the second data storage structure by an electric field in a direction substantially perpendicular to the first sidewall of the channel.

12. The vertical semiconductor device according to claim 1, wherein: The second data storage structure contacts a portion of a surface of the gate pattern.

13. The vertical semiconductor device according to claim 12, wherein: The second data storage structure surrounds the surface of the gate pattern.

14. A vertical semiconductor device comprising: Gate patterns stacked on a substrate, wherein the gate patterns are spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate; a channel passing through the gate pattern, wherein the channel is electrically connected to the substrate and has a cylindrical shape; a first data storage structure contacting a first sidewall of the trench; and A second data storage structure is on a second sidewall of the trench opposite the first sidewall, wherein the second data storage structure contacts the trench.

15. The vertical semiconductor device according to claim 14, wherein: The first data storage structure includes a variable resistance material.

16. The vertical semiconductor device according to claim 14, wherein: The second data storage structure includes a tunnel insulating layer, a charge storage layer and a blocking layer.

17. The vertical semiconductor device according to claim 14, wherein: First data is stored in the first data storage structure by an electric field in a direction substantially parallel to the first sidewall of the channel, and second data is stored in the second data storage structure by an electric field in a direction substantially perpendicular to the first sidewall of the channel.

18. A vertical semiconductor device comprising: a channel on a substrate; a first data storage structure formed on a first side of the channel; a second data storage structure formed on a second side of the channel opposite the first side; and A gate pattern is provided on the second data storage structure.

19. The vertical semiconductor device according to claim 18, wherein: The first data storage structure includes a variable resistance material.

20. The vertical semiconductor device according to claim 18, wherein: The second data storage structure includes a tunnel insulating layer, a charge storage layer and a blocking layer.

21. The vertical semiconductor device according to claim 18, wherein: First data is stored in the first data storage structure by an electric field in a first direction, and second data is stored in the second data storage structure by an electric field in a direction different from the first direction.

22. The vertical semiconductor device according to claim 18, wherein: The first data storage structure faces the gate pattern, and the second data storage structure faces the gate pattern.

23. A vertical semiconductor device comprising: a first gate pattern and a second gate pattern arranged in a vertical direction on a substrate, wherein an insulating layer is disposed between the first gate pattern and the second gate pattern; a channel layer disposed on the substrate; a first data storage element disposed on a first side of the channel layer; and A second data storage element is disposed on a second side of the channel layer, wherein the second data storage element is disposed between the second side of the channel layer and the first gate pattern.

24. The vertical semiconductor device according to claim 23, wherein: The channel layer directly contacts the first data storage element and the second data storage element.

25. The vertical semiconductor device of claim 23, wherein: The first data storage element and the second data storage element include different materials from each other.

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