Display Devices

Abstract

The present disclosure relates to a display device, comprising: a display panel, comprising a transmission area, a display area and an intermediate area, the intermediate area comprising at least one groove and positioned between the transmission area and the display area; an input sensing layer stacked on the display panel, wherein a metal layer overlapping with the at least one groove in a plan view is located in one of the display panel and the input sensing layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0072424 filed on June 18, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Aspects of one or more example embodiments are directed to a display panel including a first region located inside a display region and a display device including the display panel. Background Art

[0004] Recently, the applications of display devices have been diversified. In addition, as display devices have become thinner and lighter, the scope of use of display devices has expanded.

[0005] The area occupied by the display region of the display device has increased, and various functions that can be applied to or linked to the display device have been added to the display device. In order to increase the area occupied by the display region and add various functions, research has been conducted on display devices capable of arranging various components in the display region.

[0006] The above information disclosed in this background section is only for enhancement of background understanding and therefore, the information discussed in this background section does not necessarily constitute prior art. Summary of the invention

[0007] Aspects of one or more example embodiments include a display panel having a transmission area in which various components can be arranged within a display area and a display device including the display panel. However, one or more embodiments described herein are merely examples, and the scope of the present disclosure is not limited thereto.

[0008] According to one or more example embodiments, a display device includes: a display panel, including a transmission area, a display area and an intermediate area, the intermediate area including at least one groove and positioned between the transmission area and the display area; an input sensing layer stacked on the display panel, wherein a metal layer overlapping the at least one groove in a plan view is located in one of the display panel and the input sensing layer.

[0009] According to some example embodiments, in the display region, a thin film transistor including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode and connected to a display element and a storage capacitor including a lower electrode and an upper electrode facing each other, an insulating layer interposed between the lower electrode and the upper electrode, wherein the gate electrode serves as the lower electrode. The metal layer may include the same material as that contained in one of the gate electrode and the upper electrode, and may be arranged on the same layer on which one of the gate electrode and the upper electrode is arranged.

[0010] According to some example embodiments, the metal layer may be a continuous layer extending without disconnection.

[0011] According to some example embodiments, the metal layer may be a segmented layer having a gap of 3 μm or less in a plan view.

[0012] According to some example embodiments, the segmented layer may include a single segmented layer located on the same layer as the layer on which the gate electrode and one of the upper electrodes are arranged, or a multi-layer segmented layer, in which multiple layers are located on different layers so that multiple portions of one layer alternate with multiple portions of another layer, and the gaps are between the multiple portions of the one layer and the multiple portions of the other layer.

[0013] According to some example embodiments, the input sensing layer may include a lower sensing electrode and an upper sensing electrode facing each other, an insulating layer interposed between the lower sensing electrode and the upper sensing electrode, and the metal layer may include the same material as a material contained in one of the lower sensing electrode and the upper sensing electrode and may be arranged on the same layer on which one of the lower sensing electrode and the upper sensing electrode is arranged.

[0014] According to some example embodiments, the metal layer may be a continuous layer extending without disconnection.

[0015] According to some example embodiments, the metal layer may be a segmented layer having a gap of 3 μm or less in a plan view.

[0016] According to some example embodiments, the segmented layer may include a single segmented layer located on the same layer as the layer on which one of the lower sensing electrode and the upper sensing electrode is arranged, or a multi-layer segmented layer in which a plurality of layers are located on different layers such that a plurality of portions of one layer alternate with a plurality of portions of another layer, and the gap is between the plurality of portions of the one layer and the plurality of portions of the other layer.

[0017] According to some example embodiments, the display device may further include: a window covering the display panel and the input sensing layer from the outside; and an optical function layer interposed between the display panel and the window.

[0018] According to some example embodiments, the optical function layer may include an anti-reflection layer using polarization, and a black matrix for blocking light may not be positioned in a portion of the window corresponding to the middle area.

[0019] According to some example embodiments, the display area may include: a display element located on a substrate, in which a pixel electrode, an intermediate layer including an emission layer, and a relative electrode are stacked; and a multilayer film interposed between the substrate and the pixel electrode, in which an inorganic insulating layer, an organic insulating layer, and an inorganic layer are sequentially stacked, and the intermediate area includes an inorganic contact area, in which the inorganic layer and the inorganic insulating layer are in direct contact with each other through an opening, and the opening is included in the organic insulating layer and is adjacent to each of the at least one groove.

[0020] According to some example embodiments, the inorganic layer may be arranged not to overlap with each of the at least one groove in a plan view, and the metal layer may cover a portion of the middle region not covered by the inorganic layer in a plan view, the portion including each of the at least one groove.

[0021] According to some example embodiments, each of the at least one groove may include: a first hole passing through the inorganic layer; and a second hole or recess passing through the organic insulating layer.

[0022] According to some example embodiments, the multilayer film may further include a lower insulating layer located below the organic insulating layer, and each of the at least one groove may include: a first hole passing through the inorganic layer; a second hole passing through the organic insulating layer; and a third hole or recess passing through the lower insulating layer.

[0023] According to some example embodiments, the multilayer film may further include at least one upper insulating layer over the organic insulating layer, and the at least one upper insulating layer may include a hole overlapping each of the at least one groove.

[0024] According to some example embodiments, the at least one upper insulating layer may include an inorganic insulating layer and / or an organic insulating layer.

[0025] According to some example embodiments, the intermediate layer may include one or more organic material layers of a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer.

[0026] According to some example embodiments, the at least one groove may include a plurality of grooves spaced apart from each other, and the inorganic contact region may be interposed between the plurality of grooves.

[0027] According to some example embodiments, each of the at least one groove may have an undercut structure.

[0028] These and / or other aspects will become more apparent and easier to understand from the following description of example embodiments taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic perspective view of a display device according to some example embodiments.

[0030] Figure 2A and Figure 2B is a schematic cross-sectional view of a display device according to some example embodiments.

[0031] FIG. 3A to FIG. 3D is a schematic cross-sectional view of a display panel according to some example embodiments.

[0032] FIG. 4A to FIG. 4D is a schematic cross-sectional view of a display panel according to some example embodiments.

[0033] Figure 5A and Figure 5B is a schematic plan view of a display panel according to some example embodiments.

[0034] Figure 6 is a schematic equivalent circuit diagram of one pixel within a display panel according to some example embodiments.

[0035] Fig. 7A and Figure 7B is a plan view of a transmission region of a display panel according to some example embodiments.

[0036] Fig. 8A It is along Fig. 7A and Figure 7B A cross-sectional view taken along line VIII-VIII'.

[0037] Figure 8B yes Fig. 8A A cross-sectional view of a modifiable example of .

[0038] 9A to 9D It is used to describe manufacturing Fig. 8A A cross-sectional view of a method for displaying a panel.

[0039] FIG. 10A to FIG. 10B is a cross-sectional view of a method of manufacturing a display panel according to some example embodiments.

[0040] Fig.11A and Fig. 11B is a cross-sectional view of a method of manufacturing a display panel according to some example embodiments.

[0041] FIG. 12A to FIG. 12F is a cross-sectional view of a method of manufacturing a display panel according to some example embodiments.

[0042] Fig.13 is a schematic cross-sectional view of a middle area of ​​a display panel according to some example embodiments.

[0043] Fig.14A and Fig. 14B is a cross-sectional view of a modified example of a metal layer provided in a middle region of a display panel according to some example embodiments.

[0044] Fig.15 is a schematic cross-sectional view of a display device including a metal layer in an input sensing layer according to some example embodiments.

[0045] Fig.16 yes Fig.15 0 is a cross-sectional view of the layout of the upper sensing electrode and the lower sensing electrode of the input sensing layer shown in .

[0046] Fig.17A and Fig. 17B According to some example embodiments Fig.15 0 is a cross-sectional view of a modifiable example of a metal layer provided in an input sensing layer shown in FIG. DETAILED DESCRIPTION

[0047] Now, reference will be made in more detail to various aspects of some example embodiments shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, the example embodiments are described below with reference to the accompanying drawings only to explain various aspects of this specification. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. When a statement such as "at least one" precedes a column of elements, the entire column of elements is modified, without modifying the individual elements of the column.

[0048] It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, the layer, region or component may be directly or indirectly formed on the other layer, region or component. That is, for example, there may be intervening layers, regions or components.

[0049] For convenience of explanation, the sizes of elements in the drawings may be exaggerated. In other words, since the sizes and thicknesses of components in the drawings are arbitrarily shown for convenience of explanation, the following exemplary embodiments are not limited thereto.

[0050] When a specific example embodiment can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0051] In this specification, "A and / or B" means A or B, or A and B.

[0052] It will also be understood that when a layer, region, or component is referred to as being "connected" or "coupled" to another layer, region, or component, the layer, region, or component may be directly connected or coupled to the other layer, region, or component, or there may be intervening layers, regions, or components. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be directly electrically connected or coupled to the other layer, region, or component, or there may be intervening layers, regions, or components.

[0053] Figure 1 is a schematic perspective view of a display apparatus 1 according to some example embodiments.

[0054] Reference Figure 1 , the display device 1 includes a first area OA and a display area DA. The display area DA is a second area that at least partially surrounds the first area OA. The display device 1 can provide a specific image by using light emitted from a plurality of pixels arranged in the display area DA. Figure 1 FIG. 4 shows that a first area OA is arranged inside the display area DA, and the first area OA may be completely surrounded by the display area DA. The first area OA may be arranged with a Figure 2A and Figure 2B Describes the area of ​​the component.

[0055] The middle area MA may be arranged as a third area between the first area OA and the display area DA as the second area. The display area DA may be surrounded by the peripheral area PA as the fourth area. The middle area MA and the peripheral area PA may be non-display areas in which pixels are not arranged. The middle area MA may be completely surrounded by the display area DA, and the display area DA may be completely surrounded by the peripheral area PA.

[0056] Although an organic light emitting display is now shown and described as the display device 1, the display device 1 is not limited thereto. According to some example embodiments, a display device such as a quantum dot light emitting display may be used.

[0057] Despite Figure 1A single first area OA is included and the single first area OA is substantially circular, but the embodiment is not limited thereto. The number of the first areas OA may be two or more, and the shape of each first area OA may be circular, elliptical, polygonal, star-shaped, or diamond-shaped.

[0058] Figure 2A and Figure 2B is a schematic cross-sectional view of a display device 1 according to some example embodiments, and may correspond to a cross-sectional view taken along Figure 1 A cross section taken along line II-II'.

[0059] Reference Figure 2A , the display device 1 may include a display panel 10, an input sensing layer 40, and an optical functional layer 50. These layers may be covered by a window 60. The display device 1 may be any of various electronic devices such as a mobile phone, a notebook computer, and a smart watch.

[0060] The display panel 10 may display an image. The display panel 10 includes pixels arranged in a display area DA. Each pixel may include a display element and a pixel circuit connected to the display element. The display element may include an organic light emitting diode or a quantum dot organic light emitting diode, etc.

[0061] The input sensing layer 40 obtains coordinate information corresponding to an external input (e.g., a touch event). The input sensing layer 40 may include a sensing electrode (or a touch electrode) and a trace line connected to the sensing electrode. The input sensing layer 40 may be arranged on the display panel 10. The input sensing layer 40 may sense an external input according to a mutual capacitance method and / or a self-capacitance method.

[0062] The input sensing layer 40 may be directly formed on the display panel 10, or the input sensing layer 40 may be separately formed and then coupled to the display panel 10 through an adhesive layer such as an optically transparent adhesive. For example, the input sensing layer 40 may be formed sequentially after a process of forming the display panel 10. In this case, the input sensing layer 40 may be understood as a part of the display panel 10, and an adhesive layer may not be disposed between the input sensing layer 40 and the display panel 10. Figure 2A It is shown that the input sensing layer 40 is interposed between the display panel 10 and the optical functional layer 50. However, according to some example embodiments, the input sensing layer 40 may be located on the optical functional layer 50.

[0063] The optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident from the outside through the window 60 toward the display panel 10. The anti-reflection layer may include a phase retarder and a polarizer. The phase retarder may be a film type or a liquid coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be a film type or a liquid coating type. The film type polarizer may include a stretchable synthetic resin film, and the liquid coating type polarizer may include liquid crystals arranged in a predetermined arrangement. The phase retarder and the polarizer may also include protective films, respectively. The protective films of the phase retarder and the polarizer may be defined as the substrate layer of the anti-reflection layer.

[0064] According to some example embodiments, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged by taking into account the color of the light beam emitted by the pixel of the display panel 10. According to some example embodiments, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer arranged on different layers. The first reflected light and the second reflected light respectively reflected by the first reflective layer and the second reflective layer may destructively interfere with each other, and therefore, the reflectance of the external light may be reduced.

[0065] The optical function layer 50 may include a lens layer. The lens layer may improve emission efficiency or reduce color deviation of light emitted from the display panel 10. The lens layer may include a layer having a concave lens shape or a convex lens shape, and / or may include a plurality of layers having different refractive indices, respectively. The optical function layer 50 may include both an anti-reflection layer and a lens layer, or may include one of the anti-reflection layer and the lens layer.

[0066] According to some example embodiments, the optical function layer 50 may be formed successively after the process of forming the display panel 10 and / or the input sensing layer 40. In this case, an adhesive layer may not be disposed between the optical function layer 50 and the input sensing layer 40 and / or the display panel 10.

[0067] The display panel 10, the input sensing layer 40 and / or the optical function layer 50 may include an opening. Figure 2A , it is shown that the display panel 10, the input sensing layer 40 and the optical function layer 50 include a first opening 10H, a second opening 40H and a third opening 50H, respectively, and the first opening 10H, the second opening 40H and the third opening 50H overlap each other. The first opening 10H, the second opening 40H and the third opening 50H are positioned to correspond to the first area OA. According to some example embodiments, at least one of the display panel 10, the input sensing layer 40 and the optical function layer 50 may not include an opening. For example, one or two selected from the display panel 10, the input sensing layer 40 and the optical function layer 50 may not include an opening. Alternatively, as Figure 2BAs shown in , the display panel 10 , the input sensing layer 40 , and the optical function layer 50 may not include openings.

[0068] The first area OA may be a component area (eg, a sensor area, a camera area, or a speaker area, etc.) in which components 20 for adding various functions to the display device 1 are positioned. Figure 2A As shown in FIG. 1 , the assembly 20 may be positioned in the first opening 10H, the second opening 40H, and the third opening 50H. Alternatively, as shown in FIG. Figure 2B As shown in , the assembly 20 may be positioned below the display panel 10 .

[0069] Component 20 may include an electronic component. For example, component 20 may be an electronic component that uses light or sound. For example, the electronic component may include a sensor that outputs or / and receives light (such as an infrared sensor), a camera that receives light and takes an image, a sensor that outputs and senses light or sound to measure distance or identify fingerprints, a small lamp that outputs light, or a speaker that outputs sound. Electronic components using light can utilize light in various wavelength bands, such as visible light, infrared light, and ultraviolet light. According to some embodiments, the first area OA may be understood as a transmission area capable of transmitting light or / and sound output from component 20 to the outside or traveling from the outside toward component 20.

[0070] According to some example embodiments, when the display device 1 is used as a smart watch or a dashboard for a car, the component 20 may be a member such as a clock hand or a hand indicating predetermined information (e.g., vehicle speed, etc.). When the display device 1 includes a clock hand or a dashboard for a car, the component 20 may be exposed to the outside through the window 60, and the window 60 may include an opening corresponding to the first area OA.

[0071] As described above, the assembly 20 may include elements related to the functions of the display panel 10, or may include elements such as accessories that increase the aesthetics of the display panel 10. Figure 2A and Figure 2B It is not shown in the figure, but an optically transparent adhesive or the like may be positioned between the window 60 and the optical functional layer 50 .

[0072] FIG. 3A to FIG. 3D is a schematic cross-sectional view of a display panel 10 according to an embodiment.

[0073] Reference Figure 3A The display panel 10 includes a display layer 200 positioned on a substrate 100. The substrate 100 may include a glass material, or may include a polymer resin. The substrate 100 may have a multi-layer structure. For example, Figure 3AAs shown in the enlarged view of FIG. 1 , the substrate 100 may include a first base layer 101 , a first barrier layer 102 , a second base layer 103 , and a second barrier layer 104 .

[0074] Each of the first base layer 101 and the second base layer 103 may include a polymer resin. For example, the first base layer 101 and the second base layer 103 may include a copolymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), or cellulose acetate propionate (CAP). The aforementioned polymer resin may be transparent.

[0075] Each of the first barrier layer 102 and the second barrier layer 104 is a barrier layer that prevents penetration of external foreign matter, and thus may be a layer including an inorganic material (such as silicon nitride (SiN x , x>0) or silicon oxide (SiO x , x>0)) of a single layer or multiple layers.

[0076] The display layer 200 includes a plurality of pixels. The display layer 200 may include a display element layer 200A and a pixel circuit layer 200B. The display element layer 200A may include display elements arranged in pixels respectively, and the pixel circuit layer 200B may include an insulating layer and a pixel circuit arranged in each pixel. Each pixel circuit may include a thin film transistor and a storage capacitor, and each display element may include an organic light emitting diode OLED.

[0077] The display element of the display layer 200 may be covered by an encapsulation member such as a thin film encapsulation layer 300. The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. When the display panel 10 includes the substrate 100 including a polymer resin and the thin film encapsulation layer 300 including the inorganic encapsulation layer and the organic encapsulation layer, the flexibility of the display panel 10 may be improved.

[0078] The display panel 10 may include a first opening 10H that penetrates the display panel 10. The first opening 10H may be positioned in the first area OA. In this case, the first area OA may be a type of opening area. Figure 3A 2 shows that the substrate 100 and the thin film encapsulation layer 300 include through holes 100H and 300H, respectively, each corresponding to the first opening 10H of the display panel 10. The display layer 200 may include a through hole 200H corresponding to the first area OA.

[0079] According to some example embodiments, Figure 3BAs shown in , the substrate 100 may not include a through hole corresponding to the first area OA. The display layer 200 may include a through hole 200H corresponding to the first area OA. The thin film encapsulation layer 300 may not include a through hole corresponding to the first area OA. According to some example embodiments, as Figure 3C As shown in , the display layer 200 may not include the through hole 200H corresponding to the first area OA, and the display element layer 200A may not be positioned in the first area OA.

[0080] Despite FIG. 3A to FIG. 3C , the display element layer 200A is not arranged in the first area OA, but the present disclosure is not limited thereto. According to some example embodiments, Figure 3D As shown in , the auxiliary display element layer 200C may be positioned in the first area OA. The auxiliary display element layer 200C may include a display element having a different structure and / or operating in a different manner than the display element of the display element layer 200A.

[0081] According to some example embodiments, the display element layer 200A may include pixels, each pixel including an active organic light emitting diode, and the auxiliary display element layer 200C may include pixels, each pixel including a passive organic light emitting diode. When the auxiliary display element layer 200C includes a passive organic light emitting diode as a display element, there may be no elements constituting a pixel circuit under the corresponding passive organic light emitting diode. For example, a portion of the pixel circuit layer 200B located below the auxiliary display element layer 200C includes neither a transistor nor a storage capacitor.

[0082] According to some example embodiments, the auxiliary display element layer 200C may include a display element of the same type as the display element of the display element layer 200A (e.g., an active organic light emitting diode), but the pixel circuit located below the auxiliary display element layer 200C may have a different structure from the pixel circuit located below the display element layer 200A. For example, the pixel circuit located below the auxiliary display element layer 200C (e.g., a pixel circuit including a light shielding layer located between a substrate and a transistor) may include a different structure from the pixel circuit located below the display element layer 200A. Alternatively, the display element of the auxiliary display element layer 200C may be operated according to a control signal different from the control signal for the display element of the display element layer 200A. Components (e.g., infrared sensors) that do not require relatively high transmittance may be arranged in the first area OA in which the auxiliary display element layer 200C is arranged. In this case, the first area OA may be understood as both the component area and the auxiliary display area.

[0083] FIG. 4A to FIG. 4Dis a schematic cross-sectional view of a display panel 10' according to another embodiment. FIG. 3A to FIG. 3D Unlike the display panel 10 described above, which includes the thin film encapsulation layer 300, FIG. 4A to FIG. 4D The display panel 10 ′ may include an encapsulation substrate 300A and a sealant 340 .

[0084] like FIG. 4A to FIG. 4C As shown in FIG. 1 , at least one selected from the substrate 100, the display layer 200, and the encapsulation substrate 300A may include through holes 100H, 200H, and 300AH corresponding to the first area OA. The display element layer 200A may not be arranged in the first area OA, or as shown in FIG. Figure 4D As shown in FIG. 1 , the auxiliary display element layer 200C may be arranged in the first area OA. Figure 3D The auxiliary display element layer 200C described is the same.

[0085] Figure 5A and Figure 5B is a schematic plan view of a display panel 10 according to some example embodiments, and Figure 6 is an equivalent circuit diagram of one pixel of the display panel 10 according to the embodiment.

[0086] Reference Figure 5A , the display panel 10 may include a first area OA, a display area DA (which is a second area), a middle area MA (which is a third area), and a peripheral area PA (which is a fourth area). Figure 5A A diagram of a substrate 100 which may be understood as a display panel 10. For example, the substrate 100 may be understood as having a first area OA, a display area DA, a middle area MA, and a peripheral area PA.

[0087] The display panel 10 includes a plurality of pixels P arranged in a display area DA. Figure 6 As shown in , each pixel P may include a pixel circuit PC and an organic light emitting diode OLED as a display element connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Via the organic light emitting diode OLED, each pixel P may emit, for example, red light, green light, or blue light, or may emit red light, green light, blue light, or white light.

[0088] The second thin film transistor T2 as a switching thin film transistor may be connected to the scan line SL and the data line DL, and transmits a data voltage received via the data line DL to the first thin film transistor T1 based on a switching voltage received via the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage received from the second thin film transistor T2 and a first power supply voltage ELVDD supplied to the driving voltage line PL.

[0089] The first thin film transistor T1 as a driving thin film transistor can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a specific brightness through the driving current. The opposite electrode (e.g., cathode) of the organic light emitting diode OLED can receive the second power supply voltage ELVSS.

[0090] Despite Figure 6 , the pixel circuit PC includes two thin film transistors and one storage capacitor, but the present disclosure is not limited thereto. The number of thin film transistors and the number of storage capacitors may be changed according to the design of the pixel circuit PC. For example, in addition to the aforementioned two thin film transistors, the pixel circuit PC may also include four or more thin film transistors.

[0091] Return to reference Figure 5A , according to the plan view, the middle area MA may surround the opening area OA. The middle area MA is an area in which display elements such as organic light emitting diodes are not arranged. Signal lines configured to provide signals to pixels P arranged around the first area OA may pass through the middle area MA. In the peripheral area PA, a scan driver 1100 that provides a scan signal to each pixel P, a data driver 1200 that provides a data signal to each pixel P, and a main power line (not shown) for providing a first power supply voltage and a second power supply voltage may be arranged. Figure 5A In the embodiment, the data driver 1200 is positioned at one side of the substrate 100. However, according to some example embodiments, the data driver 1200 may be positioned on a flexible printed circuit board (FPCB) electrically connected to a pad arranged at one side of the display panel 10. Figure 5A In the embodiment, the first area OA is arranged on the upper left side of the display area DA. Figure 5B As shown in , the first area OA may be disposed at the center of an upper end of the display area DA.

[0092] Fig. 7A and Figure 7Bis a plan view of a portion of a display panel according to an embodiment.

[0093] Reference Fig. 7A , in the display area DA, the pixels P may be arranged around the first area OA. Some pixels P may be spaced apart from each other around the first area OA, and the first area OA may be defined between the pixels P. For example, in Fig. 7A and Figure 7B In a plan view of , the pixels P may be arranged up and down around the first area OA, and may also be arranged left and right around the first area OA.

[0094] A signal line adjacent to the first area OA among signal lines providing signals to the pixels P may bypass the first area OA. Fig. 7A In a plan view of , at least one of the data lines DL crossing the display area DA may extend in the y direction to provide data signals to pixels P arranged one above the other with the first area OA therebetween, and the at least one data line DL detours around an edge of the first area OA in the middle area MA. Fig. 7A In the plan view, at least one scan line SL among the scan lines SL crossing the display area DA may extend in the x direction to provide a scan signal to pixels P arranged left and right with the first area OA therebetween, and the at least one scan line SL bypasses an edge of the first area OA in the middle area MA.

[0095] The detouring portion (detouring portion or avoiding portion) SL-D of the scan line SL can be positioned on the same layer as the layer on which the extension portion SL-L crossing the display area DA is arranged, and can be formed integrally with the extension portion SL-L. The detouring portion DL-D1 of at least one data line DL can be arranged on a layer different from the layer on which the extension portion DL-L1 crossing the display area DA is arranged. The detouring portion DL-D1 of the data line DL can be connected to the extension portion DL-L1 through a contact hole. The detouring portion DL-D2 of at least one data line DL can be positioned on the same layer as the layer on which the extension portion DL-L2 is arranged, and can be formed integrally with the extension portion DL-L2.

[0096] One or more grooves G may be disposed between the first area OA and the area of ​​the middle area MA where the scan line SL and the data line DL bypass. In a plan view, each groove G may have a ring shape surrounding the first area OA. The grooves G may be spaced apart from each other.

[0097] like Figure 7BAs shown in , the left and right portions of the scan line SL having the first area OA therebetween may be cut off without avoiding the portion. In other words, in the case where the above-mentioned scan driver 1100 is arranged on each of the left and right sides of the display area DA, the pixel located on the left side of the display area DA may be connected to the scan driver 1100 located on the left side, and the pixel located on the right side of the display area DA may be connected to the scan driver 1100 located on the right side. In this case, the scan line SL does not need to be continuous while avoiding the first area OA.

[0098] Fig. 8A is a cross-sectional view of a display panel 10 - 1 according to some example embodiments, and may correspond to a cross-sectional view taken along Fig. 7A and Figure 7B A cross section taken along line VIII-VIII'. 9A to 9D Is manufacturing Fig. 8A 1 is a cross-sectional view of a process of a display panel 10 - 1 , and shows a middle area MA.

[0099] Reference Fig. 8A According to some example embodiments, the substrate 100 may include a glass material or a polymer resin. Figure 3A As shown in the enlarged view of , the substrate 100 may include a plurality of sub-layers.

[0100] A buffer layer 201 that prevents impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT may be disposed on the substrate 100. The buffer layer 201 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide, and may be a single layer or multiple layers including the inorganic insulating material.

[0101] The pixel circuit PC may be disposed on the buffer layer 201. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Fig. 8A The thin film transistor TFT may correspond to the above reference Figure 6 described driving thin film transistor. Although Fig. 8A Although not shown in the figure, the data line DL of the pixel circuit PC may be electrically connected to the switching thin film transistor included in the pixel circuit PC. According to the present embodiment, the thin film transistor TFT is a top gate type, in which the gate electrode GE is arranged on the semiconductor layer Act, and the gate insulating layer 203 is located between the gate electrode GE and the semiconductor layer Act. However, according to some example embodiments, the thin film transistor TFT may be a bottom gate type.

[0102] The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include, for example, amorphous silicon, an oxide semiconductor, or an organic semiconductor. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be formed as a multilayer or single layer including the foregoing materials.

[0103] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide. The gate insulating layer 203 may be a single layer or multiple layers including the aforementioned materials.

[0104] The source electrode SE and the drain electrode DE may be positioned on the same layer on which the data line DL is arranged, and may include the same material as that of the data line DL. The source electrode SE, the drain electrode DE, and the data line DL may include a highly conductive material. Each of the source electrode SE and the drain electrode DE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be a multilayer or a single layer including the foregoing materials. According to some example embodiments, each of the source electrode SE, the drain electrode DE, and the data line DL may be formed as a multilayer of Ti / Al / Ti.

[0105] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 overlapping each other, with the first interlayer insulating layer 205 located between the lower electrode CE1 and the upper electrode CE2. The storage capacitor Cst may overlap with the thin film transistor TFT. In this regard, Fig. 8A The case where the gate electrode GE of the thin film transistor TFT is the lower electrode CE1 of the storage capacitor Cst is shown. According to some example embodiments, the storage capacitor Cst may not overlap with the thin film transistor TFT. The storage capacitor Cst may be covered by the second interlayer insulating layer 207. The upper electrode CE2 of the storage capacitor Cst may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be formed as a multilayer or a single layer including the foregoing materials.

[0106] The first and second interlayer insulating layers 205 and 207 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide. Each of the first and second interlayer insulating layers 205 and 207 may be a single layer or multiple layers including the aforementioned materials.

[0107] The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst may be covered with the first organic insulating layer 209. An upper surface of the first organic insulating layer 209 may include a substantially flat surface.

[0108] The pixel circuit PC may be electrically connected to the pixel electrode 221. Fig. 8A As shown in , the contact metal layer CM may be arranged between the thin film transistor TFT and the pixel electrode 221. The contact metal layer CM may contact the thin film transistor TFT through a contact hole formed in the first organic insulating layer 209, and the pixel electrode 221 may contact the contact metal layer CM through a contact hole formed in the second organic insulating layer 211. The contact metal layer CM may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be formed as a multilayer or a single layer including the foregoing materials. According to some example embodiments, the contact metal layer CM may be formed as a multilayer of Ti / Al / Ti.

[0109] The first organic insulating layer 209 and the second organic insulating layer 211 may include an organic insulating material such as a commercially available polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an acrylic ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a blend thereof. According to some example embodiments, the first organic insulating layer 209 and the second organic insulating layer 211 may include polyimide.

[0110] The pixel electrode 221 may be located on the second organic insulating layer 211. The pixel electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). According to some example embodiments, the pixel electrode 221 may include a reflective layer including, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound of these materials. According to some example embodiments, the pixel electrode 221 may also include a reflective layer composed of ITO, IZO, ZnO or In above / below the reflective layer. 2 O 3 The film formed.

[0111] The pixel defining layer 215 may be located on the pixel electrode 221. The pixel defining layer 215 may include an opening through which the upper surface of the pixel electrode 221 is exposed, and the pixel defining layer 215 may cover the edge of the pixel electrode 221. The pixel defining layer 215 may include an organic insulating material. Alternatively, the pixel defining layer 215 may include an inorganic insulating material, such as silicon nitride (SiN x), silicon oxynitride (SiON) or silicon oxide (SiO x ). Alternatively, the pixel defining layer 215 may include an organic insulating material and an inorganic insulating material.

[0112] The intermediate layer 222 includes an emission layer 222b. The intermediate layer 222 may include a first functional layer 222a below the emission layer 222b and / or a second functional layer 222c above the emission layer 222b. The emission layer 222b may include a low molecular organic material or a high molecular organic material that emits light of a specific color.

[0113] The first functional layer 222a may be a single layer or multiple layers. For example, when the first functional layer 222a includes a polymer organic material, the first functional layer 222a is a hole transport layer (HTL) having a single layer structure, and may include poly (3,4-ethylenedioxythiophene) (PEDOT) and / or polyaniline (PANI). When the first functional layer 222a includes a low molecular weight material, the first functional layer 222a may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0114] The second functional layer 222c is optional. For example, when the first functional layer 222a and the emission layer 222b include a high molecular weight material, the second functional layer 222c may be formed. The second functional layer 222c may be a single layer or multiple layers. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0115] The emission layer 222b of the intermediate layer 222 may be arranged in each pixel in the display area DA. The emission layer 222b may be patterned to correspond to the pixel electrode 221. Unlike the emission layer 222b, the first functional layer 222a and / or the second functional layer 222c of the intermediate layer 222 may extend toward the middle area MA, so that the first functional layer 222a and / or the second functional layer 222c are positioned not only in the display area DA but also in the middle area MA.

[0116] The relative electrode 223 may include a conductive material having a low work function. For example, the relative electrode 223 may include a (semi) transparent layer, which includes, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or an alloy of these materials. Alternatively, the relative electrode 223 may also include a conductive material such as ITO, IZO, ZnO or In on a (semi) transparent layer including any of the above materials. 2 O 3The opposing electrode 223 may be disposed not only in the display area DA but also in the middle area MA. The first functional layer 222a, the second functional layer 222c, and the opposing electrode 223 may be formed via thermal deposition.

[0117] The capping layer 230 may be positioned on the opposite electrode 223. For example, the capping layer 230 may include LiF, and may be formed via thermal deposition. According to some embodiments, the capping layer 230 may be omitted.

[0118] The spacer 217 may be located on the pixel defining layer 215. The spacer 217 may include an organic insulating material such as polyimide. Alternatively, the spacer 217 may include an inorganic insulating material, or may include an inorganic insulating material and an organic insulating material.

[0119] The spacer 217 may include a material different from that used to form the pixel defining layer 215, or may include the same material as that used to form the pixel defining layer 215. According to some example embodiments, the pixel defining layer 215 and the spacer 217 may include polyimide. The pixel defining layer 215 and the spacer 217 may be simultaneously (or concurrently) formed during a mask process using a half-tone mask.

[0120] The organic light emitting diode OLED is covered with a thin film encapsulation layer 300. The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Fig.9D It is shown that the thin film encapsulation layer 300 includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first and second inorganic encapsulation layers 310 and 330. According to some example embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and a stacking order may be modified.

[0121] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be a single layer or multiple layers including the aforementioned materials. The organic encapsulation layer 320 may include a polymer material. Examples of polymer materials may include acrylic resins, epoxy resins, polyimides, and polyethylene. According to some example embodiments, the organic encapsulation layer 320 may include acrylate.

[0122] The thickness of the first inorganic encapsulation layer 310 and the thickness of the second inorganic encapsulation layer 330 may be different from each other. The thickness of the first inorganic encapsulation layer 310 may be greater than the thickness of the second inorganic encapsulation layer 330. Alternatively, the thickness of the second inorganic encapsulation layer 330 may be greater than the thickness of the first inorganic encapsulation layer 310, or the thickness of the first inorganic encapsulation layer 310 and the thickness of the second inorganic encapsulation layer 330 may be the same.

[0123] Reference Fig. 8A The middle area MA may include a first sub-middle area SMA1 relatively far from the first area OA and a second sub-middle area SMA2 relatively close to the first area OA. A line bypassing the first area OA and the groove G may be arranged in the middle area MA.

[0124] like Fig. 8A As shown in FIG. 1 , a line (eg, a data line DL) may be positioned in the first sub middle area SMA1 . Fig. 8A The data lines DL in the first sub-middle area SMA1 shown in FIG. Fig. 7A and Figure 7B Detour portions DL- D1 and DL- D2 of the data line DL are described. The first sub-middle area SMA1 may be understood as a line area or a detour area around which a line such as the data line DL is bypassed.

[0125] The data lines DL may be alternately arranged with each other, and an insulating layer may be located between the data lines DL. For example, the data lines DL may be alternately arranged, such as one data line DL among the adjacent data lines DL is arranged below the insulating layer (e.g., the first organic insulating layer 209 or the first interlayer insulating layer 205) and another data line DL among the adjacent data lines DL is arranged on the insulating layer (e.g., the first organic insulating layer 209 or the first interlayer insulating layer 205). When the data lines DL are alternately arranged with an insulating layer located between the data lines DL, the distance Δd (pitch) between the data lines may be reduced. Although Fig. 8A The data lines DL positioned in the first sub-middle area SMA1 are shown, but the above reference Fig. 7A and Figure 7B The described scan line SL (eg, a meandering portion of the scan line SL) may also be positioned in the first sub-middle area SMA1.

[0126] One or more grooves G may be arranged in the second sub-middle area SMA2. The organic material layer included in the middle layer 222 (e.g., the first functional layer 222a and / or the second functional layer 222c) may be disconnected (or separated) by the groove G. The second sub-middle area SMA2 may be understood as a disconnection area (or separation area) or a groove area of ​​the organic material layer.

[0127] The groove G may be formed in the multilayer film ML disposed between the substrate 100 and the pixel electrode 221. The multilayer film ML may include a first sublayer including an organic layer and a second sublayer including an inorganic layer. In this regard, Fig. 8A A multilayer film ML is shown including a first organic insulating layer 209 and an inorganic layer 210. The inorganic layer 210 may be positioned on the same layer (i.e., the first organic insulating layer) on which the contact metal layer CM is disposed, and may be formed during the same mask process as that for forming the contact metal layer CM.

[0128] The inorganic layer 210 may include the same material as that of the contact metal layer CM. For example, the inorganic layer 210 may include a metal as a material not including carbon, and may include three sub-layers, for example, Ti / Al / Ti.

[0129] Reference Fig. 8A and Fig.9A , the groove G of the multilayer film ML may be formed before the process of forming the intermediate layer 222. The groove G may have an undercut structure. The groove G may include a first hole 210h formed in the inorganic layer 210 and a groove or a second hole 209h formed in the first organic insulating layer 209. Fig.9A It is shown that the first hole 210h and the second hole 209h overlap each other to form a groove G. The bottom surface of the groove G may be positioned on a virtual surface between the top surface of the substrate 100 and the top surface of the first organic insulating layer 209. In this regard, Fig.9A , it is shown that the bottom surface of the groove G is positioned on the same virtual surface as the top surface of the second interlayer insulating layer 207 .

[0130] The end of the inorganic layer 210 defining the first hole 210h may be a so-called undercut structure that further protrudes toward the center of the groove G than the inner side surface of the first organic insulating layer 209 disposed below the inorganic layer 210. For example, the first width W1 of the first hole 210h may have a value less than the value of the second width W2 of the second hole 209h. Here, the second width W2 of the second hole 209h may be the width of a portion of the first organic insulating layer 209 just below the end of the inorganic layer 210 defining the first hole 210h. The end of the inorganic layer 210 protruding toward the center of the groove G and / or the first hole 210h may constitute a pair of eaves (or a pair of protruding tips, or tips PT). The protruding length d1 of each tip PT may be less than the depth h1 of the second hole 209h described below. For example, the protruding length d1 of each tip PT may be about 2 μm or less. According to some example embodiments, the protruding length d1 may be about 1 μm to about 1.5 μm.

[0131] As mentioned above, Fig.9AAs shown in , a first end portion of the inorganic layer 210 constituting the tip PT may be exposed, but the other end portion (eg, a second end portion 210 e located opposite to the tip PT) may be covered by the second organic insulating layer 211 .

[0132] The depth h1 of the second hole 209h may be the same as the thickness t1 of the first organic insulating layer 209. The depth h1 of the second hole 209h may correspond to the depth of the groove G. According to some example embodiments, the depth of the groove G may be about 1.5 μm or more. For example, the depth of the groove G may be about 2 μm or more.

[0133] The first organic insulating layer 209 may include an opening 209OD. The opening 209OD may be adjacent to the groove G and may be spaced apart from the groove G by a predetermined interval. Fig.9A As shown in FIG, the openings 209OD may be arranged at two opposite sides of the groove G. For example, around the groove G, one opening 209OD may be arranged at one side of the display area DA, and another opening 209OD may be arranged at one side of the first area OA.

[0134] The inorganic layer 210 may directly contact the second interlayer insulating layer 207 as an inorganic insulating layer located under the first organic insulating layer 209 through the opening 209OD, thereby forming an inorganic contact region ICR.

[0135] The inorganic layer 210 may directly contact the top surface of the second interlayer insulating layer 207 through the opening 209OD formed in the first organic insulating layer 209 , and the inorganic layer 210 and the second interlayer insulating layer 207 contacting each other may form the inorganic contact region ICR as described above.

[0136] The inorganic contact region ICR prevents penetration of moisture. In other words, a layer including an organic material among the layers located above the substrate 100 may serve as a path through which moisture advances. Fig. 8A As shown in , when the display panel 10-1 includes the first opening 10H corresponding to the first area OA, moisture may advance in a direction (x direction, hereinafter referred to as a lateral direction) parallel to the top surface of the substrate 100 through the first opening 10H. However, according to some example embodiments, since the middle area MA includes the inorganic contact area ICR, moisture may be blocked from advancing to the display area DA through the first organic insulating layer 209.

[0137] The partition wall PW may be disposed between the grooves G. The partition wall PW may include a plurality of sub-organic insulating layers stacked sequentially. Fig.9AAs shown in , the partition wall PW may have a structure in which a portion 209P of the first organic insulating layer 209, a portion 211P of the second organic insulating layer 211, a portion 215P of the pixel defining layer 215, and a portion 217P of the spacer 217 are stacked. According to some example embodiments, at least one of the portion 209P of the first organic insulating layer 209, the portion 211P of the second organic insulating layer 211, the portion 215P of the pixel defining layer 215, and the portion 217P of the spacer 217 may be omitted. In this case, the height from the substrate 100 to the top surface of the partition wall PW may be less than the height from the substrate 100 to the top surface of the spacer 217.

[0138] Reference Fig. 8A and Fig. 9B , the intermediate layer 222 may be formed after the groove G is formed. Each of the first functional layer 222a and / or the second functional layer 222c of the intermediate layer 222 may be integrally formed by using an open mask or the like, so that each of the first functional layer 222a and / or the second functional layer 222c is positioned in the display area DA and the intermediate area MA. In this case, the first functional layer 222a and / or the second functional layer 222c may be disconnected or separated by the groove G.

[0139] The layer including the organic material among the layers located above the substrate 100 may be used as a path through which moisture advances. Since the first functional layer 222a and / or the second functional layer 222c include an organic material, the first functional layer 222a and / or the second functional layer 222c may be used as a moisture transmission path. However, since the first functional layer 222a and / or the second functional layer 222c are disconnected or separated by the groove G, moisture may be prevented from advancing to the organic light emitting diode OLED through the first functional layer 222a and / or the second functional layer 222c.

[0140] Like the first functional layer 222a and / or the second functional layer 222c, the opposing electrode 223 formed via thermal deposition may be disconnected by the groove G. The capping layer 230 including, for example, LiF may also be disconnected by the groove G. According to some example embodiments, when the capping layer 230 includes an inorganic material such as silicon nitride, silicon oxynitride, and / or silicon oxide, such as Fig. 9C As shown in , the capping layer 230 may be continuously formed without being interrupted by the groove G. According to some example embodiments, the capping layer 230 may be omitted.

[0141] Reference Fig. 8A and Fig.9D , a thin film encapsulation layer 300 may be formed. The thin film encapsulation layer 300 may prevent the organic light emitting diode OLED from being damaged or deteriorated due to external impurities by covering the organic light emitting diode OLED of the display area DA.

[0142] The thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Compared with the first functional layer 222a, the second functional layer 222c and / or the opposite electrode 223, the first inorganic encapsulation layer 310 formed by chemical vapor deposition (CVD) or the like may have relatively excellent step coverage. Fig.9D As shown in , the first inorganic encapsulating layer 310 may be continuously formed. For example, the first inorganic encapsulating layer 310 may cover the entire inner surface of the groove G.

[0143] The organic encapsulation layer 320 may be formed by coating a monomer on the substrate 100 and hardening the monomer. Alternatively, the organic encapsulation layer 320 may be formed by coating a polymer. An end of the organic encapsulation layer 320 facing the first area OA may be adjacent to one side of the partition wall PW.

[0144] The second inorganic encapsulation layer 330 may be positioned on the organic encapsulation layer 320. The second inorganic encapsulation layer 330 may directly contact the first inorganic encapsulation layer 310 in a partial region of the middle region MA. Fig. 8A and Fig.9D As shown in FIG. 1 , the first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 may contact each other in a partial region of the middle area MA adjacent to the first area OA.

[0145] Despite 8A to 9D FIG. 1 shows that the display panel 10-1 includes a first opening 10H corresponding to the first area OA, but as shown in FIG. FIG. 3B to FIG. 3D As described above, the display panel 10 may not include the first opening 10H corresponding to the first area OA. The above features are also applicable to the later referenced FIG. 10A to FIG. 17B Description of the display panel.

[0146] Fig. 8A The cross section of the display panel 10-1 shown in FIG. 1 may be understood as a structure surrounding the first area OA. Fig. 7A and Figure 7B As shown in , when viewed in a direction perpendicular to the top surface of the substrate 100, Fig. 8A Each groove G may have an annular shape surrounding the first area OA. Similarly, when viewed in a direction perpendicular to the top surface of the substrate 100, the partition wall PW may also have an annular shape surrounding the first area OA. Similarly, when viewed in a direction perpendicular to the top surface of the substrate 100, Fig. 8A The elements shown in FIG. 1 (eg, the elements included in the middle area MA (eg, the inorganic layer 210, etc.)) may have a ring shape surrounding the first area OA. The above features may also be applied to the later referenced FIG. 10A to FIG. 17B Description of the display panel.

[0147] Return to reference Fig. 8A , in the middle area MA, the metal layer 216G1 is arranged under the groove G. The metal layer 216G1 covers the space where the inorganic layer 210 forming the inorganic contact region ICR is empty. In other words, the inorganic layer 210 is a metal layer such as a contact metal layer as described above, but there is no metal layer such as the inorganic layer 210 under the groove G. In addition, because the opposing electrode 223 as another metal layer is separated by the groove G, the metal layer is empty at the position overlapping with the groove G, and the metal layer 216G1 covers the position where the metal layer is empty. The metal layer 216G1 covers the vicinity of the groove as described above so as to prevent the inside of the display panel 10-1 from being seen from the outside.

[0148] In other words, because the optical function layer 50 that prevents reflection by using polarization is stacked on the display panel 10, when external light enters and is then reflected to the outside, the external light is blocked by the optical function layer 50, so that the inside of the display panel 10 is not visually recognized by the user's eyes. However, this is feasible when reflection occurs due to the regular phase difference of the metal layer. When the external light is reflected by a non-metallic layer such as polyimide, polarization cannot function properly due to the irregular phase difference, so the inside of the display panel 10 can be visually recognized by the user's eyes. In order to prevent this problem, a method of providing a black matrix in the area corresponding to the groove G of the window 60 to cover the reflected light can be considered. However, using this method requires space for arranging a dedicated black matrix, thus resulting in an increase in the dead space. However, as in the present embodiment, when the portion overlapping the groove G (i.e., the portion where the metal layer is empty) is covered by the metal layer 216G1 located below the groove G, the anti-reflection function of the optical function layer 50 can be used without providing a dedicated black matrix to fully prevent the visual recognition of the reflected light. Therefore, it is possible to prevent the middle area MA surrounding the first area OA as the transmission area from being visually recognized by the user.

[0149] According to the present embodiment, the metal layer 216G1 may include the same material as that included in the upper electrode CE2 of the storage capacitor Cst, and may be formed on the same layer as the layer on which the upper electrode CE2 of the storage capacitor Cst is formed. However, the position of the metal layer 216G1 is not limited thereto. From a plan view, as long as the metal layer 216G1 covers a position including the groove G where the metal layer is empty, the metal layer 216G1 may be formed on any other layer.

[0150] For example, Figure 8BAs shown in , a metal layer 216G2 may also be formed, the metal layer 216G2 including the same material as that included in the gate electrode GE of the thin film transistor TFT (i.e., the lower electrode CE1 of the storage capacitor Cst) and located on the same layer on which the gate electrode GE of the thin film transistor TFT (i.e., the lower electrode CE1 of the storage capacitor Cst) is formed. In addition, in this case, the metal layer 216G2 may effectively prevent the portion of the middle area MA not covered by the inorganic layer 210 (including the groove G) from being visually recognized by the user.

[0151] Furthermore, since the metal layers 216G1 and 216G2 are continuously arranged even under the partition wall PW, visual recognition of reflected light can be prevented even if a metal layer does not exist in the partition wall PW.

[0152] Fig. 10A and Fig. 10B is a cross-sectional view of a method of manufacturing the display panel 10 - 2 according to some example embodiments, and illustrates a middle area MA.

[0153] Reference Fig. 10A , a groove G is formed in the multilayer film ML, and the multilayer film ML may include three or more layers. For example, the multilayer film ML may include a first sublayer including an organic layer, a second sublayer positioned on the first sublayer and including an inorganic layer, and at least one lower insulating layer (or third sublayer) disposed below the organic layer, the at least one lower insulating layer including an inorganic insulating layer. According to some example embodiments, Fig. 10A As shown in FIG. 1 , the multilayer film ML may include a first organic insulating layer 209 , an inorganic layer 210 located on the first organic insulating layer 209 , and a second interlayer insulating layer 207 located under the first organic insulating layer 209 .

[0154] During the process of forming the groove G, a portion of at least one inorganic insulating layer disposed under the first organic insulating layer 209 may be etched. For example, while a portion of the second interlayer insulating layer 207 is being etched, a third hole 207h may be formed in the second interlayer insulating layer 207. According to some example embodiments, Fig. 10A A recess is formed in the second interlayer insulating layer 207 shown in FIG. 2 instead of a third hole 207 h penetrating the second interlayer insulating layer 207 .

[0155] Since each groove G is formed while removing a portion of at least one inorganic insulating layer disposed below the first organic insulating layer 209, the depth h2 of the groove G may be greater than the thickness t1 of the first organic insulating layer 209 (h2>t1) and less than the sum of the thickness t1 of the first organic insulating layer 209 and the thickness t2 of the at least one inorganic insulating layer (t1+t2>h2). The bottom surface of the groove G may be positioned on a dummy surface between the top surface of the substrate 100 and the top surface of the second interlayer insulating layer 207. The depth h2 of the groove G may be about 1.5 μm or more. For example, the depth h2 of the groove G may be about 2 μm or more, or about 2.5 μm or more, or about 3 μm or more, or about 3.5 μm or more.

[0156] The groove G may have an undercut shape, and the tip PT of the inorganic layer 210 may extend toward the center of the groove G and may constitute an eaves shape. A protruding length d1 of the tip PT may be equal to or less than about 2.0 μm, and may be, for example, about 1 μm to about 1.5 μm.

[0157] Next, if Fig. 10B As shown in , the intermediate layer 222, the opposite electrode 223, and the cover layer 230 may be sequentially formed over the substrate 100 having the groove G formed therein. According to some example embodiments, the first functional layer 222a, the second functional layer 222c, the opposite electrode 223, and the cover layer 230 may each be disconnected or separated by the groove G in the middle area MA. According to some example embodiments, the cover layer 230 may be omitted, or as shown in FIG. Fig. 9C As described above, the cover layer 230 may be continuously formed without being disconnected by the groove G.

[0158] The partition wall PW may be disposed between the grooves G, and the characteristics of other elements of the display panel 10-3 (eg, the end of the organic encapsulation layer 320 is adjacent to the side of the partition wall PW adjacent to the display area DA) are the same as those described above with reference to FIG. 8A to 9D The characteristics described are the same.

[0159] In addition, in the present embodiment, the metal layer 216G2 includes the same material as that included in the gate electrode GE of the thin film transistor TFT (i.e., the lower electrode CE1 of the storage capacitor Cst), and is formed on the same layer on which the gate electrode GE of the thin film transistor TFT (i.e., the lower electrode CE1 of the storage capacitor Cst) is formed. Similarly, the metal layer 216G2 can effectively prevent the portion of the middle area MA not covered by the inorganic layer 210 (including the groove G) from being visually recognized by the user.

[0160] Fig.11A and Fig. 11Bis a cross-sectional view of a method of manufacturing the display panel 10 - 3 according to some example embodiments, and illustrates a middle area MA.

[0161] Reference Fig.11A , a groove G may be formed in the multilayer film ML including the first organic insulating layer 209 and the inorganic layer 210. The first hole 210h formed in the inorganic layer 210 and the recess 209r formed in the first organic insulating layer 209 may constitute each groove G. The depth of the groove G (e.g., the depth h3 of the recess 209r) may be less than the thickness t1 of the first organic insulating layer 209. The depth h3 of the recess 209r may be about 1.5 μm or more, for example, about 2 μm or more.

[0162] like Fig.11A As shown in , when the depth h3 of the concave portion 209r is less than the thickness t1 of the first organic insulating layer 209, the bottom surface of the groove G may be positioned on a virtual surface between the top surface and the bottom surface of the first organic insulating layer 209. In this case, a portion of the first organic insulating layer 209 located below the bottom surface of the groove G may provide a path through which moisture may penetrate. However, according to some example embodiments, since the openings 209OD are respectively arranged at two opposite sides of the groove G, and the metal layer 210 and the inorganic insulating layer (e.g., the second interlayer insulating layer 207) are in direct contact with each other through the openings 209OD and thus constitute the inorganic contact region ICR, the above-mentioned moisture penetration may be prevented.

[0163] The groove G may have an undercut structure. The end of the inorganic layer 210 protruding toward the center of the groove G and / or the first hole 210h may constitute a pair of eaves (or a pair of protruding tips, or tips PT). The protruding length d1 of each tip PT may be about 1 μm to about 1.5 μm.

[0164] Reference Fig. 11B , the intermediate layer 222, the opposite electrode 223, and the cover layer 230 may be sequentially formed over the substrate 100 in which the groove G is formed. A portion of the intermediate layer 222 (e.g., the first functional layer 222a and / or the second functional layer 222c) may be disconnected or separated in the middle region MA by the groove G. Similarly, the opposite electrode 223 and the cover layer 230 may be disconnected or separated in the middle region MA. According to some example embodiments, the cover layer 230 may be omitted, or as described above with reference to Fig. 9C As described above, the cover layer 230 including the inorganic insulating layer may be continuously formed. Next, the thin film encapsulation layer 300 is formed.

[0165] The partition wall PW may be disposed between the grooves G, and an end portion of the organic encapsulation layer 320 is disposed adjacent to a side of the partition wall PW adjacent to the display area DA, and the display panel 10-3 includes elements such as the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 as described above with reference to 8A to 9D The description is the same.

[0166] In addition, in the present embodiment, the metal layer 216G1 includes the same material as that included in the upper electrode CE2 of the storage capacitor Cst, and is formed on the same layer on which the upper electrode CE2 of the storage capacitor Cst is formed. Similarly, the metal layer 216G1 can effectively prevent the portion of the middle area MA not covered by the inorganic layer 210 (including the groove G) from being visually recognized by the user.

[0167] FIG. 12A to FIG. 12F is a cross-sectional view of a method of manufacturing a display panel 10 - 4 according to another embodiment.

[0168] Reference Fig. 12A The multilayer film M may include a first sublayer as an organic layer, a second sublayer positioned on the first sublayer and comprising an inorganic layer, and at least one top insulating layer (or a fourth sublayer) positioned on the second sublayer, and the at least one top insulating layer may include an organic insulating layer, an inorganic insulating layer, or both an organic insulating layer and an inorganic insulating layer.

[0169] According to some example embodiments, Fig. 12A and Fig.12D As shown in FIG. 1 , the multilayer film ML may include a first organic insulating layer 209, an inorganic layer 210 located on the first organic insulating layer 209, and a second organic insulating layer 211 located on the inorganic layer 210. As described above, the inorganic layer 210 may be positioned on the same layer on which the contact metal layer CM is disposed, and may include the same material as that of the contact metal layer CM.

[0170] According to some example embodiments, Fig. 12B As shown in , at least one top insulating layer may include an inorganic insulating layer 212 and a second organic insulating layer 211. Therefore, the multilayer film ML may include a first organic insulating layer 209, an inorganic layer 210, an inorganic insulating layer 212, and a second organic insulating layer 211 stacked sequentially. According to some example embodiments, as Fig. 12C As shown in FIG. 2 , at least one top insulating layer may include an inorganic insulating layer 212. In this case, the multilayer film ML may include a first organic insulating layer 209, an inorganic layer 210, and an inorganic insulating layer 212 stacked sequentially. Hereinafter, a case where at least one top insulating layer includes a second organic insulating layer 211 will be described, and reference will be made later to FIG. 12C to FIG. 12FThe features and structures described are also applicable to the above referenced Fig. 12B and Fig. 12C The case of at least one top insulating layer is described.

[0171] The groove G may be formed by etching (eg, isotropic etching, etc.). Fig.12D As shown in , the first hole 210h of the inorganic layer 210, the second hole 209h of the first organic insulating layer 209, and the fifth hole 211h of the second organic insulating layer 211 overlapping each other may constitute each groove G. The characteristics of the protruding length d1 of each of the pair of tips PT extending toward the center of the groove G, the first width W1 of the first hole 210h of the inorganic layer 210, and the width of the portion of the groove G passing through the first organic insulating layer 209 (e.g., the second width W2) are the same as those described above. The side surface of the second organic insulating layer 211 defining the fifth hole 211h may not protrude further toward the center of the groove G than the pair of tips PT. In other words, the width W3 (hereinafter, referred to as the third width) of the bottom surface of the fifth hole 211h may be equal to or greater than the first width W1 of the first hole 210h of the inorganic layer 210.

[0172] Reference FIG. 12A to FIG. 12D , before the etching process for forming the groove G, the top insulating layer (eg, FIG. 12A to FIG. 12C The inorganic insulating layer 212 and / or the second organic insulating layer 211 shown in FIG. 2 may cover the end of the inorganic layer 210 corresponding to the tip PT (see FIG. 2 ). Fig.12D ). Therefore, the end portion of the inorganic layer 210 corresponding to the tip PT may be prevented from being damaged during a process of manufacturing the display panel 10 - 4 .

[0173] The partition wall PW may be adjacent to the groove G. For example, the partition wall PW may be positioned between adjacent grooves G. The partition wall PW may be formed while stacking the portion 211P of the second organic insulating layer 211, the portion 215P of the pixel defining layer 215, and the portion 217P of the spacer 217. A portion of the inorganic layer 210 positioned below the portion 211P of the second organic insulating layer 211 may also constitute the partition wall PW.

[0174] The first organic insulating layer 209 may include an opening 209OD. The inorganic layer 210 and the second interlayer insulating layer 207 located below the first organic insulating layer 209 may directly contact each other through the opening 209OD, thereby constituting an inorganic contact region ICR.

[0175] Reference Fig.12E, the intermediate layer 222, the opposite electrode 223, and the cover layer 230 may be sequentially formed over the substrate 100 in which the groove G is formed. The first functional layer 222a, the second functional layer 222c, the opposite electrode 223, and the cover layer 230 may each be disconnected or separated by the groove G in the middle area MA. According to some example embodiments, the cover layer 230 may be omitted, or as shown in FIG. Fig. 9C As described, the capping layer 230 may be continuously formed without being disconnected by the groove G.

[0176] Reference Fig.12F , forming a thin film encapsulation layer 300. For example, a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 may be sequentially formed. Because the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 have relatively excellent step coverage, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may cover the entire inner surface of the groove G. An end portion of the organic encapsulation layer 320 may be adjacent to one side surface of the partition wall PW.

[0177] In addition, in the present embodiment, the metal layer 216G1 includes the same material as that included in the upper electrode CE2 of the storage capacitor Cst, and is formed on the same layer on which the upper electrode CE2 of the storage capacitor Cst is formed. Similarly, the metal layer 216G1 can effectively prevent the portion of the middle area MA not covered by the inorganic contact region ICR (including the groove G) from being visually recognized by the user.

[0178] Fig.13 is a schematic cross-sectional view of a display panel 10 - 5 according to another embodiment.

[0179] Reference Fig.13 In the display panel 10-5, the characteristics of other elements except the groove G arranged in the middle area MA are similar to those of the reference Fig. 8A The characteristics of the display panel 10 - 1 described are substantially the same.

[0180] The display panel 10-5 may include three or more grooves G arranged in the middle area MA. The inorganic contact region ICR may be arranged between adjacent grooves G. The first functional layer 222a, the second functional layer 222c, the opposite electrode 223, and / or the cover layer 230 may each be disconnected by each groove G. Fig.13 The groove G and the inorganic contact region ICR have the same 8A to 9D The structure described above is substantially the same as the structure described above, but the present disclosure is not limited thereto. According to some example embodiments, the groove G, the partition wall PW and / or the inorganic contact region ICR may have the same structure as described above. FIG. 10A to FIG. 12FThe structures of the described embodiments are the same as the structures of the described embodiments or structures derived therefrom.

[0181] The display panel 10-5 may include a first opening 10H positioned in the first area OA. The first opening 10H may be formed by removing elements positioned in the first area OA using a scribing or cutting process. The scribing or cutting process may be performed along the first line SCL1, and Fig.13 The display panel 10 - 5 manufactured by performing a scribing or cutting process or the like along the first lines SCL1 is shown.

[0182] The first line SCL1 may pass through one groove G' among the grooves G. In this case, a stack including the first functional layer 222a, the second functional layer 222c, the opposite electrode 223, and / or the cover layer 230, each of which is disconnected by the groove G', may face the first opening 10H. According to some example embodiments, the first line SCL1 may be positioned between two adjacent grooves G among the grooves G. In this case, a side surface of the display panel defining the first opening 10H may be aligned with the first opening 10H. Fig. 8A The side surface of the display panel defining the first opening 10H is the same as shown in FIG. Fig. 8A As shown in , the structure positioned in the inorganic contact region ICR may face the first opening 10H.

[0183] In addition, in the present embodiment, the metal layer 216G1 includes the same material as that included in the upper electrode CE2 of the storage capacitor Cst, and is formed on the same layer on which the upper electrode CE2 of the storage capacitor Cst is formed. Similarly, the metal layer 216G1 can effectively prevent the portion of the middle area MA not covered by the inorganic layer 210 (including the groove G) from being visually recognized by the user.

[0184] The above-described embodiment shows a case where the metal layers 216G1 and 216G2 are continuous layers extending on one layer without being disconnected. Fig.14A and Fig. 14B As shown in FIG. 1 , metal layers 216G1 and 216G2 may be divided layers having gaps ga and gb therein. Fig.14A A single-layer structure is shown in which a divided metal layer 216G1 is located on one layer, and Fig. 14B A multi-layer structure is shown in which segmented metal layers 216G1 and 216G2 are located on different layers such that portions of segmented metal layer 216G1 alternate with portions of segmented metal layer 216G2 . Fig.14A The single-layer structure may include a split metal layer 216G2 located on the same layer as a layer on which a lower electrode is formed.

[0185] Because the split metal layers 216G1 and 216G2 are members for covering the portion of the display panel where the metal layer is empty, when such gaps ga and gb exist, the reflected light may be visually recognized by the user. However, when the gaps ga and gb are very small, the reflected light may not be recognized by the user's eyes. Generally, when the gaps ga and gb are 3 μm or less, the reflected light is not recognized by the user's eyes. Therefore, it is not necessary to make the metal layers 216G1 and 216G2 as continuous layers, and as Fig.14A and Fig. 14B As shown in , the metal layers 216G1 and 216G2 may be divided layers with gaps ga and gb as long as the reflected light is not recognized by the user's eyes.

[0186] Fig.15 is a schematic cross-sectional view of a display panel 10 - 6 according to another embodiment.

[0187] Reference Fig.15 , the display panel 10-6 may include a planarization layer 420 disposed over the thin film encapsulation layer 300 and positioned in the middle area MA. According to some example embodiments, the planarization layer 420 may be disposed only in the middle area MA.

[0188] The planarization layer 420 may include an organic insulating layer. The planarization layer 420 may include a polymer material. For example, the planarization layer 420 may include a silicon-based resin, an acrylic resin, an epoxy-based resin, polyimide, and polyethylene. According to some example embodiments, the planarization layer 420 may include a material different from that of the organic encapsulation layer 320.

[0189] The planarization layer 420 may cover at least one groove G located in the middle area MA. The planarization layer 420 may increase the flatness of the display panel 10-6 around the first area OA by covering the area in the middle area MA that is not covered by the organic encapsulation layer 320. Therefore, the input sensing layer 40 (see FIG. 1 ) on the display panel 10-6 may be prevented from being Figure 2A and Figure 2B ) and / or optical functional layer 50 (see Figure 2A and Figure 2B ). A portion of the planarization layer 420 may overlap the organic encapsulation layer 320. One end portion of the planarization layer 420 (eg, a first end portion 420e adjacent to the display area DA) may be positioned above the organic encapsulation layer 320.

[0190] The planarization layer 420 may be formed in the middle area MA by an exposure process and a development process, etc. During some processes (e.g., a cleaning process) in the process for forming the planarization layer 420, when external foreign matter (e.g., moisture) advances in the lateral direction of the display panel 10-6, the organic light emitting diode OLED in the display area DA may be damaged. However, according to an embodiment, since insulating layers (e.g., a first insulating layer 410 and a second insulating layer 430) are respectively arranged below and above the planarization layer 420, the above-mentioned problems and / or floating of adjacent layers due to moisture penetration may be prevented during and after the process of forming the planarization layer 420.

[0191] The first insulating layer 410 and the second insulating layer 430 may directly contact the bottom surface and the top surface of the planarization layer 420, respectively. The first insulating layer 410 and the second insulating layer 430 may each include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. Each of the first insulating layer 410 and the second insulating layer 430 may be a single layer or a multilayer including the aforementioned material.

[0192] The planarization layer 420 may have a step difference with respect to the layer below it. A portion of the planarization layer 420 including the first end portion 420e may have a step difference with respect to the top surface of the first insulating layer 410. During and / or after the process of manufacturing the display panel 10-6, in order to prevent the planarization layer 420 from being separated or floating from the layer below it due to the step difference, the cover layer 440 may be positioned above the first end portion 420e.

[0193] The cover layer 440 may include a metal. Each of the first insulating layer 410, the second insulating layer 430, and the third insulating layer 450 described below extends not only to the middle area MA but also to the display area DA. In contrast, the cover layer 440 may have a predetermined width and may cover the first end portion 420e of the planarization layer 420. The cover layer 440 located above the planarization layer 420 may extend toward the display area DA beyond the first end portion 420e of the planarization layer 420, but does not extend toward the display area DA.

[0194] The third insulating layer 450 may be positioned on the cover layer 440. The third insulating layer 450 may include an organic insulating material. For example, the organic insulating material of the third insulating layer 450 may include a photoresist (negative photoresist or positive photoresist) or a polymer-based organic material, and may extend toward the display area DA to cover the display area DA.

[0195] The portion located above the second insulating layer 430 may correspond to the input sensing layer 40. In other words, Fig.16As shown in FIG. 4 , the input sensing layer 40 includes a lower sensing electrode 216Y1 on the second insulating layer 430 and an upper sensing electrode 216Y2 between the second insulating layer 430 and the interlayer insulating layer 441 , and functions as a touch screen that senses a user's touch and transmits a signal to the display panel 10 .

[0196] According to the present embodiment, one of the lower sensing electrode 216Y1 and the upper sensing electrode 216Y2 is used as a metal layer covering the groove G. In other words, Fig.15 As shown in , one of the lower sensing electrode 216Y1 and the upper sensing electrode 216Y2 can prevent visual recognition of the inside of the display panel 10 by covering the groove G from above. Therefore, according to the above-described embodiment, the metal layers 216G1 and 216G2 are arranged below the groove G. According to the present embodiment, the lower sensing electrode 216Y1 and the upper sensing electrode 216Y2 serving as the metal layer are arranged above the groove G. In this case, because the lower sensing electrode 216Y1 and the upper sensing electrode 216Y2 cover the groove G to prevent visual recognition of the groove G, the inside of the display panel can be prevented from being visually recognized by the user.

[0197] In addition, the present embodiment shows a case where the lower sensing electrode 216Y1 and the upper sensing electrode 216Y2 (hereinafter, referred to as metal layers 216Y1 and 216Y2) are continuous layers extending on one layer without disconnection. Fig.17A and Fig. 17B As shown in FIG. 1 , the metal layers 216Y1 and 216Y2 may be divided layers having gaps ga and gb therebetween. Fig.17A A single-layer structure is shown in which the split metal layer 216Y1 or 216Y2 is located on one layer, and Fig. 17B A multi-layer structure is shown in which the segmented metal layers 216Y1 and 216Y2 are located on different layers such that the segmented metal layers 216Y1 alternate with the segmented metal layers 216Y2 .

[0198] Even when the gaps ga and gb of the divided metal layers 216Y1 and 216Y2 are 3 μm or less, the inside of the display panel is prevented from being visually recognized by the user. Therefore, it is not necessary to make the metal layers 216Y1 and 216Y2 as continuous layers, and as Fig.17A and Fig. 17B As shown in , the metal layers 216Y1 and 216Y2 may be divided layers with gaps ga and gb as long as the reflected light is not visible through the user's eyes.

[0199] The metal layers 216G1 , 216G2 , 216Y1 , and 216Y2 according to the above-described embodiments may be non-driving metal layers that are not used as wirings, or may be driving metal layers that are used as wirings.

[0200] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made herein without departing from the spirit and scope as defined by the present disclosure.

Claims

1. A display device, wherein: The display device comprises: a display panel comprising a transmission region, a display region, and an intermediate region, the intermediate region comprising at least one groove and being positioned between the transmission region and the display region; An input sensing layer, stacked on the display panel, wherein the metal layer overlapping the at least one groove in a plan view is located in one of the display panel and the input sensing layer, The metal layer is arranged below at least one groove in the middle area of ​​the display panel, and an insulating layer is interposed between the metal layer and the at least one groove; or, the metal layer is arranged above at least one groove in the middle area of ​​the display panel, and an insulating layer is interposed between the metal layer and the at least one groove.

2. The display device according to claim 1, wherein: A thin film transistor and a storage capacitor are included in the display region, the thin film transistor including a semiconductor layer, a gate electrode, a source electrode and a drain electrode and connected to a display element, and the storage capacitor includes a lower electrode and an upper electrode facing each other, an insulating layer is interposed between the lower electrode and the upper electrode, wherein the gate electrode serves as the lower electrode, and The metal layer includes the same material as a material contained in one of the gate electrode and the upper electrode, and is disposed on the same layer on which one of the gate electrode and the upper electrode is disposed.

3. The display device according to claim 2, wherein: The metal layer is a continuous layer extending without breaks.

4. The display device according to claim 2, wherein: The metal layer is a segmented layer having a gap of 3 μm or less in a plan view.

5. The display device according to claim 4, wherein: The segmented layer includes a single-layer segmented layer or a multi-layer segmented layer, wherein the single-layer segmented layer is located on the same layer as the layer on which the gate electrode and one of the upper electrodes are arranged, and in the multi-layer segmented layer, multiple layers are located on different layers so that multiple parts of one layer alternate with multiple parts of another layer, and the gap is between the multiple parts of the one layer and the multiple parts of the other layer.

6. The display device according to claim 1, wherein: The input sensing layer includes a lower sensing electrode and an upper sensing electrode facing each other, an insulating layer is interposed between the lower sensing electrode and the upper sensing electrode, and The metal layer includes the same material as a material included in one of the lower sensing electrode and the upper sensing electrode, and is disposed on the same layer on which one of the lower sensing electrode and the upper sensing electrode is disposed.

7. The display device according to claim 6, wherein: The metal layer is a continuous layer extending without breaks.

8. The display device according to claim 6, wherein: The metal layer is a segmented layer having a gap of 3 μm or less in a plan view.

9. The display device according to claim 8, wherein: The segmented layer includes a single segmented layer located on the same layer as the layer on which one of the lower sensing electrode and the upper sensing electrode is arranged, or a multi-layer segmented layer in which a plurality of layers are located on different layers such that a plurality of portions of one layer alternate with a plurality of portions of another layer, and the gap is between the plurality of portions of the one layer and the plurality of portions of the other layer.

10. The display device according to claim 1, wherein: The display device further includes: a window covering the display panel and the input sensing layer from the outside; and an optical function layer interposed between the display panel and the window.

11. The display device according to claim 10, wherein: The optical functional layer includes an anti-reflection layer using polarization, and A black matrix for blocking light is not positioned in a portion of the window corresponding to the middle area.

12. The display device according to claim 1, wherein: The display area includes: a display element located on a substrate, in which a pixel electrode, an intermediate layer including an emission layer, and a counter electrode are stacked; and a multilayer film interposed between the substrate and the pixel electrode, in which an inorganic insulating layer, an organic insulating layer, and an inorganic layer are sequentially stacked, and The intermediate region includes an inorganic contact region in which the inorganic layer and the inorganic insulating layer are in direct contact with each other through an opening included in the organic insulating layer and adjacent to the at least one groove.

13. The display device according to claim 12, wherein: The inorganic layer is arranged so as not to overlap each of the at least one groove in a plan view, and The metal layer covers a portion of the middle region not covered by the inorganic layer in a plan view, the portion including the at least one groove.

14. The display device according to claim 12, wherein: The at least one groove comprises: a first hole passing through the inorganic layer; and A second hole or recess passes through the organic insulating layer.

15. The display device according to claim 12, wherein: The multilayer film further includes a lower insulating layer located below the organic insulating layer, and The at least one groove comprises: a first hole passing through the inorganic layer; a second hole passing through the organic insulating layer; and A third hole or recess passes through the lower insulating layer.

16. The display device according to claim 12, wherein: The multi-layer film further includes at least one upper insulating layer located above the organic insulating layer, and the at least one upper insulating layer includes a hole overlapping the at least one groove.

17. The display device according to claim 16, wherein: The at least one upper insulating layer includes an inorganic insulating layer and / or an organic insulating layer.

18. The display device according to claim 12, wherein: The intermediate layer includes one or more organic material layers among a hole transport layer, a hole injection layer, an electron injection layer and an electron transport layer.

19. The display device according to claim 12, wherein: The at least one groove includes a plurality of grooves spaced apart from each other, and the inorganic contact region is interposed between the plurality of grooves.

20. The display device according to claim 1, wherein: The at least one groove has an undercut structure.

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