Integrated computing chip and method of making an integrated computing chip

Abstract

The application provides an integrated computing chip and a manufacturing method thereof. The integrated computing chip comprises a substrate, a silicon-based optical chip, a voltage driving chip, and a signal reading and processing chip. The silicon-based optical chip comprises an optical network operation unit and a photodetector array. The optical network operation unit comprises N*N silicon-based Mach-Zehnder interferometers, wherein N is a positive integer greater than or equal to 2, and is used for performing N-order matrix vector multiplication operation on input light and outputting an optical intensity signal. The photodetector array is connected with the optical network operation unit and is used for converting the optical intensity signal into an analog current signal. The voltage driving chip is electrically connected with a voltage control end of the optical network operation unit, is electrically connected with the substrate, and is used for outputting a driving voltage. The signal reading and processing chip is electrically connected with an output end of the photodetector array, is electrically connected with the substrate, and is used for processing the analog current signal. The integrated computing chip alleviates the problem of thermal crosstalk, and has high computing accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to an integrated computing chip and a manufacturing method of the integrated computing chip. BACKGROUND

[0002] Optical neural network chip opens up a new, multi-disciplinary field for the development of future artificial intelligence, and the academic and industrial communities have therefore carried out many more in-depth researches on this emerging field. However, at present, people mainly focus on the optical implementation of the linear operation and the nonlinear activation function part in artificial neural networks, such as using a silicon-based MZI (Mach-Zehnder interferometer) network structure or a micro-ring weight bank based on a wavelength division multiplexing system to implement matrix operation, and using a silicon-based tunable filter to implement nonlinear operation. However, the existing MZI network structure has a problem of thermal crosstalk, which affects the calculation accuracy.

[0003] The above information disclosed in the background section is only used to enhance the understanding of the background of the technology described herein, therefore, the background section can include some information that is not known to those skilled in the art as prior art in the country. SUMMARY

[0004] The main purpose of the present application is to provide an integrated computing chip and a manufacturing method of the integrated computing chip, so as to solve the problem of the existing MZI network structure affecting the calculation accuracy due to thermal crosstalk.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, an integrated computing chip is provided, comprising a substrate; a silicon-based optical chip comprising an optical network operation unit and a photodetector array, the optical network operation unit comprising N×N silicon-based Mach-Zehnder interferometers, N being a positive integer greater than or equal to 2, the optical network operation unit being configured to perform N-order matrix-vector multiplication operation on input light and output an optical intensity signal; the photodetector array being connected to the optical network operation unit and configured to convert the optical intensity signal into an analog current signal; a voltage driving chip, an output end of the voltage driving chip being electrically connected to a voltage control end of the optical network operation unit, the voltage driving chip being electrically connected to the substrate, the voltage driving chip being configured to output a driving voltage; a signal reading and processing chip, an input end of the signal reading and processing chip being electrically connected to an output end of the photodetector array, the signal reading and processing chip being electrically connected to the substrate, the signal reading and processing chip being configured to process the analog current signal.

[0006] Optionally, the voltage driving chip comprises: a digital-to-analog converter, configured to convert an externally input phase control signal into an analog signal; and an amplification circuit, one end of which is electrically connected to the digital-to-analog converter and the other end of which is electrically connected to the optical network operation unit, and the amplification circuit is configured to amplify the analog signal.

[0007] Optionally, the photodetector array comprises a plurality of arrayed photodetectors.

[0008] Optionally, the signal reading and processing chip comprises: a plurality of arrayed amplifiers, configured to convert the analog current signal into an analog voltage signal and amplify the analog voltage signal; a plurality of arrayed filters, each of which is electrically connected to one of the amplifiers, and the filters are configured to filter the amplified analog voltage signal; and a plurality of arrayed analog-to-digital converters, each of which is electrically connected to one of the filters, and the analog-to-digital converters are configured to convert the filtered analog voltage signal into a digital signal.

[0009] Optionally, the amplifiers are transimpedance amplifiers, and the filters are bandpass filters.

[0010] Optionally, the photodetectors are silicon-based waveguide super-high-speed photodetectors.

[0011] Optionally, the substrate is a ceramic substrate.

[0012] To achieve the above object, according to one aspect of the present application, a manufacturing method of an integrated computing chip is provided, comprising: connecting an optical network operation unit and a photodetector array to form a silicon-based optical chip; electrically connecting a voltage driving chip to the silicon-based optical chip; electrically connecting a signal reading and processing chip to the silicon-based optical chip; arranging the voltage driving chip on a substrate and electrically connecting the voltage driving chip to the substrate; and arranging the signal reading and processing chip on the substrate and electrically connecting the signal reading and processing chip to the substrate.

[0013] Optionally, electrically connecting the voltage driving chip to the silicon-based optical chip comprises: forming first alignment marks on the voltage driving chip and on the optical network operation unit, respectively; aligning the voltage driving chip and the optical network operation unit according to the first alignment marks; forming a plurality of first metal bumps on the voltage driving chip; and connecting the aligned voltage driving chip and the optical network operation unit through the plurality of first metal bumps.

[0014] Optionally, the signal reading and processing chip is electrically connected with the silicon-based optical chip, comprising: forming second alignment marks on the signal reading and processing chip and on the photodetector array respectively; aligning the signal reading and processing chip with the photodetector array according to the second alignment marks; forming a plurality of second metal bumps on the signal reading and processing chip; and connecting the aligned signal reading and processing chip with the photodetector array through the plurality of second metal bumps.

[0015] The integrated computing chip is electrically connected with the voltage control end of the optical network operation unit through the output end of the voltage driving chip, and the input end of the signal reading and processing chip is electrically connected with the output end of the photodetector array, so that the MZI optical phase of the silicon-based optical chip is electrically controlled by the voltage driving chip and the signal reading and processing chip through electromagnetic field, the crosstalk between the input end and the output end of the optical network operation unit is small, the isolation degree is high, the thermal crosstalk problem caused by the thermal control MZI is effectively alleviated, and the computing accuracy of the silicon-based optical chip is high. BRIEF DESCRIPTION OF DRAWINGS

[0016] The drawings constituting a part of the specification of the present application are used to provide further understanding of the present application, the illustrative embodiments of the present application and the description thereof are used to explain the present application, and do not constitute improper limitation on the present application. In the drawings:

[0017] Figure 1 A structural schematic diagram of an integrated computing chip according to an embodiment of the present application is shown;

[0018] Figure 2 A principle schematic diagram of an integrated computing chip according to an embodiment of the present application is shown;

[0019] Figure 3 A cross-sectional structural schematic diagram of an integrated computing chip according to an embodiment of the present application is shown;

[0020] Figure 4 A flowchart of a manufacturing method of an integrated computing chip according to an embodiment of the present application is shown; and

[0021] Figure 5 An integrated computing chip generated by a manufacturing method of an integrated computing chip according to an embodiment of the present application is shown.

[0022] Among the above drawings, the following reference signs are included:

[0023] 01, optical fiber unit; 101, optical network operation unit; 102, photodetector array; 103, voltage driving chip; 104, signal reading and processing chip; 105, substrate; 106, silicon-based optical chip; 201, photodetector; 202, amplifier; 203, filter; 204, analog-to-digital converter; 205, first metal bump; 206, second metal bump. DETAILED DESCRIPTION

[0024] It should be noted that the following detailed description is exemplary in nature and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0025] It is also important to note that the terms "including", "comprising", and / or "having" as used herein are specifically intended to be open-ended and also to mean including, comprising, and / or having other elements not specified. It should be noted that the use of the term "about" in describing the exemplary embodiments of the application is intended to mean that the amount or value in question is within the range of values considered to be about the value being described.

[0026] It will be understood that when an element (such as a layer, film, region, or substrate) is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In addition, it will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element, or intervening elements can also be present.

[0027] As introduced in the background section, the MZI network structure in the prior art has thermal crosstalk effect on calculation accuracy. In order to solve the above problem, the application provides an integrated computing chip and a manufacturing method of the integrated computing chip.

[0028] In a typical embodiment of the application, as shown in FIG. 1, the integrated computing chip comprises an optical fiber unit 01, an optical network operation unit 101, a photodetector array 102, a voltage driving chip 103, a signal reading and processing chip 104, a substrate 105, and a silicon-based optical chip 106. Figures 1 to 3As shown, an integrated computing chip is provided, comprising a substrate 105; a silicon-based optical chip 106, comprising an optical network operation unit 101 and a photodetector array 102, the optical network operation unit 101 comprising N×N silicon-based Mach-Zehnder interferometers, N being a positive integer greater than or equal to 2, the optical network operation unit 101 being configured to perform N-order matrix-vector multiplication operation on input light and output an optical intensity signal; the photodetector array 102 being connected to the optical network operation unit 101 and configured to convert the optical intensity signal into an analog current signal; a voltage driving chip 103, an output end of the voltage driving chip 103 being electrically connected to a voltage control end of the optical network operation unit 101, the voltage driving chip 103 being electrically connected to the substrate 105, the voltage driving chip 103 being configured to output a driving voltage; a signal reading and processing chip 104, an input end of the signal reading and processing chip 104 being electrically connected to an output end of the photodetector array 102, the signal reading and processing chip 104 being electrically connected to the substrate 105, the signal reading and processing chip 104 being configured to process the analog current signal.

[0029] The integrated computing chip described above is electrically connected between the output end of the voltage driving chip and the voltage control end of the optical network operation unit, and between the input end of the signal reading and processing chip and the output end of the photodetector array, the voltage driving chip and the signal reading and processing chip electrically control the MZI optical phase of the silicon-based optical chip through electromagnetic field, ensuring low crosstalk and high isolation between the input end and the output end of the optical network operation unit, effectively alleviating the thermal crosstalk problem caused by thermal control MZI, thereby ensuring high computing accuracy of the silicon-based optical chip.

[0030] Specifically, the silicon-based optical chip comprises 2N 2 modulation arms.

[0031] In actual application, as shown in Figure 3 and Figure 5 , the input light can enter the optical network operation unit through end-face coupling mode by an optical fiber unit 01. The optical fiber unit 01 comprises optical fibers and / or an optical fiber array which are not formed into an optical fiber array.

[0032] According to a specific embodiment of the present application, the voltage driving chip comprises: a digital-to-analog converter configured to convert an externally input phase control signal into an analog signal; and an amplification circuit electrically connected to one end of the digital-to-analog converter and electrically connected to the optical network operation unit, and configured to amplify the analog signal. The digital-to-analog converter is configured to convert the externally input phase control signal into the analog signal, and the amplification circuit is configured to amplify the analog signal, so that the driving voltage output after the externally input phase control signal is converted and amplified by the voltage driving chip can effectively perform phase control on the optical network operation unit, and the crosstalk problem of the silicon-based optical chip is further alleviated.

[0033] In actual application, the digital-to-analog converter is a multi-channel digital-to-analog converter, the externally input phase control signal outputs a multi-channel analog voltage signal through the digital-to-analog converter, and each channel can be independently dynamically configured, so that the output voltage of the voltage driving chip is continuously adjustable within 0 to 10 V, and effective phase control on the N*N MZI is further ensured. The amplification circuit can be an adjustment output stage circuit, and the amplification circuit can also be a vacuum tube amplification circuit, a transistor amplification circuit, an integrated amplification circuit, a voltage amplification circuit, a current amplification circuit or a power amplification circuit. Of course, the amplification circuit can also be other amplification circuits, and a person skilled in the art can select a suitable amplification circuit according to the need.

[0034] In a specific embodiment, the voltage driving chip is made of a high-voltage CMOS process. The high-voltage CMOS process is that, in the process of making a high-voltage deep well, an optical self-alignment mark is first formed on the surface of a substrate with deposited oxide by using a zero mask, and then the optical self-alignment mark is used as an alignment reference of a first mask to accurately copy a high-voltage well pattern on the first mask to photoresist. Of course, the voltage driving chip can also be made of other high-voltage CMOS processes, and a person skilled in the art can select a manufacturing process according to the actual need.

[0035] In another specific embodiment of the present application, as shown in Figure 2 The photodetector array comprises a plurality of arrayed photodetectors 201. The plurality of photodetectors 201 ensures that the light intensity signal after operation of the optical network operation unit is quickly converted into an analog current signal, so that the processing speed of the integrated computing chip is relatively fast.

[0036] According to another specific embodiment of the present application, as shown in Figure 2 and Figure 3As shown in the figure, the signal reading and processing chip 104 includes a plurality of arrayed amplifiers 202, which are used to convert the analog current signals into analog voltage signals and amplify them; a plurality of arrayed filters 203, which are electrically connected one by one with the amplifiers 202, and are used to filter the amplified analog voltage signals; and a plurality of arrayed analog-to-digital converters 204, which are electrically connected one by one with the filters 203, and are used to convert the filtered analog voltage signals into digital signals. By converting the analog current signals into analog voltage signals and amplifying them through the amplifiers, filtering the analog voltage signals through the filters, and converting the filtered analog voltage signals into digital signals through the analog-to-digital converters, the N-order matrix vector multiplication operation through the optical network operation unit is realized to obtain N-dimensional optical current signals, which are finally converted into N-dimensional digital signals and output. This effectively suppresses the noise signals, while ensuring that the output digital signals have small attenuation and good digital signal effect.

[0037] It should be noted that the amplifiers are transimpedance amplifiers, and the filters are bandpass filters. The transimpedance amplifiers have high bandwidth and can perform low-noise amplification on electrical signals to effectively alleviate the attenuation of the analog current signals in the conversion and transmission process, and suppress the amplification of noise signals. The bandpass filters allow waves of a specific frequency band to pass while shielding other frequency bands, further ensuring that the analog voltage signals converted and amplified through the transimpedance amplifiers have small noise. Of course, the amplifiers can also be transconductance amplifiers, high-gain operational amplifiers, or low-power operational amplifiers, and can also be other types of amplifiers; and the filters can also be low-pass filters, high-pass filters, or band-stop filters, and can also be other types of filters.

[0038] In a specific embodiment, the signal reading and processing chip is made of a low-voltage CMOS process. The low-voltage CMOS process includes forming a substrate region on a semiconductor substrate, making a shallow trench isolation on the semiconductor substrate, making a gate on the upper surface of the substrate region, disposing a photoresist on the upper surface of the semiconductor substrate to form a transmission region and a blocking region, the transmission region corresponding to the position of the low-voltage well, injecting first doping ions with low energy to form a surface superconducting layer in the substrate region, injecting second doping ions with a large angle to form a low-voltage semiconductor laser power halo in the substrate region, and injecting second doping ions with high energy to penetrate the gate and the shallow trench isolation in the substrate region to form the low-voltage well in the substrate region. Of course, the signal reading and processing chip can also be made of other low-voltage CMOS processes, and those skilled in the art can select the manufacturing process according to actual needs.

[0039] In order to ensure that the integration of the integrated computing chip is good and the photoelectric conversion speed is fast, in a specific embodiment, the photoelectric detector is a silicon-based waveguide super-speed photoelectric detector.

[0040] In actual application, the substrate is a ceramic substrate. The ceramic substrate has excellent electrical insulation performance, high thermal conductivity, excellent weldability and high adhesion strength, and has a large current carrying capacity.

[0041] In another typical embodiment of the present application, as shown in Figure 4 and Figure 5 A method for manufacturing an integrated computing chip is also provided, which comprises the following steps:

[0042] Step S101: connecting the optical network operation unit and the photoelectric detector array to form a silicon-based optical chip;

[0043] Step S102: electrically connecting the voltage driving chip with the silicon-based optical chip;

[0044] Step S103: electrically connecting the signal reading and processing chip with the silicon-based optical chip;

[0045] Step S104: disposing the voltage driving chip on the substrate and electrically connecting it with the substrate;

[0046] Step S105: disposing the signal reading and processing chip on the substrate and electrically connecting it with the substrate.

[0047] The method for manufacturing an integrated computing chip, by connecting the optical network operation unit and the photoelectric detector array to form the silicon-based optical chip, electrically connecting the voltage driving chip with the silicon-based optical chip, electrically connecting the signal reading and processing chip with the silicon-based optical chip, and disposing the voltage driving chip and the signal reading and processing chip on the substrate and electrically connecting them with the substrate, realizes the hybrid integration of the silicon-based optical chip, the voltage driving chip and the signal reading and processing chip. This manufacturing method is simple and easy to operate, has low cost and good stability, and can realize high-speed, low-power, low-latency, high-energy efficiency optical computing. At the same time, by electrically connecting the voltage driving chip with the silicon-based optical chip and the signal reading and processing chip with the silicon-based optical chip, and by the voltage driving chip and the signal reading and processing chip electrically controlling the MZI light phase of the silicon-based optical chip through electromagnetic field, the crosstalk between the input end and the output end of the optical network operation unit is small and the isolation degree is high, effectively alleviating the thermal crosstalk problem caused by thermal control MZI, thereby ensuring high calculation accuracy of the silicon-based optical chip.

[0048] In one embodiment of the present application, as shown in Figure 3 connecting the voltage driving chip and the silicon-based optical chip, comprising: forming first alignment marks on the voltage driving chip and the optical network operation unit respectively; aligning the voltage driving chip and the optical network operation unit according to the first alignment marks; forming a plurality of first metal bumps 205 on the voltage driving chip; and connecting the aligned voltage driving chip and the optical network operation unit through the plurality of first metal bumps 205. The plurality of first metal bumps achieve the electrical connection between the voltage driving chip and the optical network operation unit, which is simple in process and high in operability, and further ensures that the integrated computing chip integrated using the manufacturing method has high operation speed and high precision.

[0049] In actual application, a plurality of first metal bumps are formed on the voltage driving chip, the plurality of first metal bumps of the voltage driving chip are attached to the silicon-based optical chip through thermal compression and / or thermal acoustic process, the output electrode of the voltage driving chip is connected to the voltage control terminal pad of the optical network operation unit, and then solidification and filling are performed to achieve the electrical connection between the voltage driving chip and the optical network operation unit.

[0050] It should be noted that the voltage driving chip and the silicon-based optical chip are interconnected and integrated using heterogeneous integration technology.

[0051] In another embodiment of the present application, as shown in Figure 3 connecting the signal reading and processing chip and the silicon-based optical chip, comprising: forming second alignment marks on the signal reading and processing chip and the photodetector array respectively; aligning the signal reading and processing chip and the photodetector array according to the second alignment marks; forming a plurality of second metal bumps 206 on the signal reading and processing chip; and connecting the aligned signal reading and processing chip and the photodetector array through the plurality of second metal bumps 206. The plurality of second metal bumps achieve the electrical connection between the signal reading and processing chip and the photodetector array, which is simple in process and high in operability, and further ensures that the integrated computing chip integrated using the manufacturing method has high operation speed and high precision.

[0052] In the actual application process, a plurality of second metal bumps are formed on the signal reading and processing chip, the plurality of second metal bumps of the signal reading and processing chip are attached to the silicon-based optical chip through a hot pressing and / or a thermoacoustic process, the input electrode of the signal reading and processing chip is connected with the output pad of the photodetector array, and then solidification and filling are performed to realize the electrical connection between the signal reading and processing chip and the photodetector array.

[0053] It should be noted that the signal reading and processing chip and the silicon-based optical chip are interconnected and integrated by using heterogeneous integration technology.

[0054] In a specific embodiment, the voltage driving chip, the signal reading and processing chip, and the silicon-based optical chip are packaged by a ceramic package to form an integrated computing chip. The voltage driving chip is electrically connected with the ceramic substrate by wire bonding, and the signal reading and processing chip is electrically connected with the ceramic substrate by wire bonding.

[0055] From the above description, it can be seen that the embodiments of the present application achieve the following technical effects:

[0056] 1) The present application provides an integrated computing chip, the integrated computing chip is electrically connected with the voltage control end of the optical network operation unit through the output end of the voltage driving chip, and the input end of the signal reading and processing chip is electrically connected with the output end of the photodetector array, the voltage driving chip and the signal reading and processing chip electrically control the MZI optical phase of the silicon-based optical chip through electromagnetic field, which ensures that the crosstalk between the input end and the output end of the optical network operation unit is small and the isolation degree is high, effectively alleviates the thermal crosstalk problem caused by the thermal control MZI, and ensures that the calculation accuracy of the silicon-based optical chip is high.

[0057] 2) The application also provides a manufacturing method of the integrated computing chip, wherein the optical network operation unit and the photodetector array are connected to form the silicon-based optical chip, the voltage driving chip is electrically connected with the silicon-based optical chip, the signal reading and processing chip is electrically connected with the silicon-based optical chip, the voltage driving chip and the signal reading and processing chip are arranged on a substrate, and the voltage driving chip and the signal reading and processing chip are respectively electrically connected with the substrate, so that the hybrid integration of the silicon-based optical chip, the voltage driving chip and the signal reading and processing chip is realized. The manufacturing method is simple and easy to operate, has low cost and good stability, and can realize high-speed, low-power-consumption, low-latency, high-energy-efficiency optical computing. Meanwhile, the voltage driving chip is electrically connected with the silicon-based optical chip, the signal reading and processing chip is electrically connected with the silicon-based optical chip, the voltage driving chip and the signal reading and processing chip electrically control the MZI optical phase of the silicon-based optical chip through the electromagnetic field, so that the crosstalk between the input end and the output end of the optical network operation unit is small, the isolation degree is high, the thermal crosstalk problem caused by the thermal control MZI is effectively alleviated, and the calculation accuracy of the silicon-based optical chip is high.

[0058] The above only describes the preferred embodiments of the application and is not used to limit the application. The application can have various changes and modifications for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the application should be included in the protection scope of the application.

Claims

1. An integrated computing chip, comprising: The application relates to an integrated computing chip, which comprises the following parts: a substrate; A silicon-based optical chip comprises an optical network operation unit and a photodetector array, the optical network operation unit comprises N×N silicon-based Mach-Zehnder interferometers, N is a positive integer greater than or equal to 2, the optical network operation unit is used for N-order matrix vector multiplication operation on input light and outputs an optical intensity signal; the photodetector array is connected with the optical network operation unit and is used for converting the optical intensity signal into an analog current signal, and the silicon-based optical chip further comprises 2N 2 modulation arms. a voltage driving chip, the output end of the voltage driving chip being electrically connected with the voltage control end of the optical network operation unit, the voltage driving chip being electrically connected with the substrate, the voltage driving chip being used for outputting driving voltage, and the voltage driving chip being used for electrically controlling the silicon-based Mach-Zehnder interferometer in the silicon-based optical chip through an electromagnetic field; a signal reading and processing chip, the input end of the signal reading and processing chip being electrically connected with the output end of the photodetector array, the signal reading and processing chip being electrically connected with the substrate, and the signal reading and processing chip being used for processing the analog current signal. The voltage driving chip comprises the following parts: a digital-to-analog converter, the digital-to-analog converter being a multi-channel digital-to-analog converter, an externally input phase control signal being output as a multi-channel analog voltage signal through the digital-to-analog converter, and each channel being independently dynamically configured; an amplification circuit, one end of the amplification circuit being electrically connected with the digital-to-analog converter, the other end of the amplification circuit being electrically connected with the optical network operation unit, the amplification circuit being used for amplifying an analog signal, and the amplification circuit being used for guaranteeing that the driving voltage output after the phase control signal externally input is converted and amplified by the voltage driving chip can effectively perform phase control on the optical network operation unit; the photodetector array comprises a plurality of array-arranged photodetectors, the input light enters the optical network operation unit through an end face coupling mode of an optical fiber unit, and the optical fiber unit comprises optical fibers which do not form an optical fiber array and / or an optical fiber array.

2. The integrated computing chip of claim 1, wherein, The signal reading and processing chip comprises the following parts: a plurality of array-arranged amplifiers, the amplifiers being used for converting the analog current signal into an analog voltage signal and amplifying the analog voltage signal; a plurality of array-arranged filters, the filters being electrically connected with the amplifiers one by one, and the filters being used for filtering the amplified analog voltage signal; a plurality of array-arranged analog-to-digital converters, the analog-to-digital converters being electrically connected with the filters one by one, and the analog-to-digital converters being used for converting the filtered analog voltage signal into a digital signal.

3. The integrated computing chip of claim 2, wherein, The amplifiers are transimpedance amplifiers, and the filters are bandpass filters.

4. The integrated computing chip of claim 1, wherein, The photodetectors are super-high-speed photodetectors of silicon-based waveguides.

5. The integrated computing chip of claim 1, wherein, The substrate is a ceramic substrate.

6. A method of fabricating an integrated computing chip, comprising: The manufacturing method of the integrated computing chip is applied to the integrated computing chip in any one of claims 1 to 5, and the manufacturing method comprises the following steps: connecting the optical network operation unit and the photodetector array to form a silicon-based optical chip; electrically connecting the voltage driving chip with the silicon-based optical chip; electrically connecting the signal reading and processing chip with the silicon-based optical chip; arranging the voltage driving chip on the substrate and electrically connecting the voltage driving chip with the substrate; arranging the signal reading and processing chip on the substrate and electrically connecting the signal reading and processing chip with the substrate; electrically connecting the voltage driving chip with the silicon-based optical chip, which comprises the following steps: forming first alignment marks on the voltage driving chip and on the optical network operation unit respectively; aligning the voltage driving chip with the optical network operation unit according to the first alignment marks; forming a plurality of first metal bumps on the voltage driving chip; The voltage driving chip and the optical network operation unit are connected by a plurality of the first metal bumps.

7. The method of manufacturing according to claim 6, wherein, The signal reading and processing chip and the silicon-based optical chip are electrically connected, including: Second alignment marks are formed on the signal reading and processing chip and the photodetector array, respectively; The signal reading and processing chip and the photodetector array are aligned according to the second alignment marks; A plurality of second metal bumps are formed on the signal reading and processing chip; The signal reading and processing chip and the photodetector array are connected by a plurality of the second metal bumps.

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