A chip security simulation analysis method and device for preventing single time attack

Abstract

The present invention provides a chip security simulation analysis method and device for preventing single time attack, the device comprising: a key information storage unit for storing key signals and path information corresponding to the key signals; a simulation circuit unit for receiving test stimulus information for simulation testing; the test stimulus information includes the key signal; a key signal monitoring unit for monitoring the key signal according to the path information corresponding to the key signal, and recording the current timestamp information when the key signal changes; an operation time analysis unit for determining the change time zone corresponding to the key signal, and calculating the operation time value of the change time zone, and judging whether the operation time values ​​of each key signal are related, if so, recording each key signal with correlation and its corresponding operation time value. Through the above scheme, the security simulation test of the chip can be simulated, and the time attack analysis can be automatically completed.

Description

Technical Field

[0001] The present invention relates to the field of chip circuit design, and in particular to a chip security simulation analysis method and device for preventing single time attacks. Background Art

[0002] SSD data storage has gradually become the main storage medium for consumer device data storage and cloud storage. For SSD data storage, data error correction is of great significance, especially for personal key data and data related to government agencies. The SSD main control chip is the brain of the SSD storage device, and its security performance directly determines the final security performance of the SSD hard drive as a whole.

[0003] Side channel attacks are the main means of hacker attacks, and time attacks are the most commonly used in side channel attacks. Hackers infer the content of the chip operation by analyzing the running time information of the main control chip when it runs key information. At present, there are many algorithms and methods for defending against time attacks in technology, but they all need to wait until the chip is designed before detailed verification. Therefore, it is very meaningful to design a simulation platform that can quickly prevent time attacks. Summary of the invention

[0004] Therefore, it is necessary to provide a technical solution for chip security simulation analysis that can prevent single time attacks, so as to solve the problem that simulation defense against time attacks cannot be performed during the chip design process.

[0005] To achieve the above-mentioned object, the first aspect of the present invention provides a chip security simulation and analysis device for preventing a single time attack, the device comprising:

[0006] A key information storage unit, used to store key signals and path information corresponding to the key signals;

[0007] A simulation circuit unit, used for receiving test stimulus information to perform simulation testing; the test stimulus information includes the key signal;

[0008] A key signal monitoring unit, configured to monitor the key signal according to path information corresponding to the key signal, and record current timestamp information when the key signal changes;

[0009] The operation time analysis unit is used to determine the change time zone corresponding to the key signal, calculate the operation time value of the change time zone, and judge whether the operation time values ​​of each key signal are related. If they are related, each key signal with correlation and its corresponding operation time value are recorded; the change time zone corresponding to the key signal refers to the difference between the timestamp information of the current key signal change and the timestamp information of the last time the key signal changed.

[0010] Further, the key signal monitoring unit includes a marker insertion unit;

[0011] The marker insertion unit is used to set a marker signal, insert the marker signal into the path information corresponding to the key signal, and record the current timestamp information when the marker signal value changes; the value of the marker signal is equal to the value of the key signal in real time;

[0012] The operation time analysis unit is used to extract the marker signal and determine the change time zone corresponding to the key signal according to the timestamp information of each marker signal.

[0013] Furthermore, the device also includes:

[0014] A random number generating unit, used for generating random numbers;

[0015] The simulation stimulus generating unit is used to generate test stimulus information according to the random number generated by the random number generating unit, and transmit the test stimulus information to the simulation circuit unit.

[0016] Furthermore, the device also includes:

[0017] The drawing unit is used to generate corresponding charts according to the operation time values ​​of each key signal.

[0018] Furthermore, the changes in key signals include multiple different types of changes;

[0019] The operation time analysis unit is used to calculate the average operation time value of each same change type. When the difference between the average operation time value of a certain change type and the average operation time value of other change types is greater than a preset error, it is determined that the key signal has a correlation with the operation time value of the change type.

[0020] Further, the key information includes test key information; the device includes:

[0021] A key generating unit, used for generating the test key information;

[0022] A key recording unit, used for storing the test key information;

[0023] The operation time analysis unit is used to obtain the test key information and determine whether the operation time values ​​of each test key information are related.

[0024] Furthermore, the key generating unit comprises:

[0025] A source data storage unit, used to store encrypted source data, wherein the source data includes a source key and a hierarchical encryption and decryption algorithm;

[0026] A source data decryption unit is used to obtain the encrypted source data for decryption, obtain the decrypted source key and the decrypted hierarchical encryption and decryption algorithm, send the decrypted source key to the root key calculation unit, and store the decrypted hierarchical key encryption and decryption algorithm in the algorithm information storage unit;

[0027] A hierarchical information storage unit, used to store hierarchical key information and user identification information;

[0028] A root key operation unit, used to obtain the user identification information and the decrypted source key, and perform a hash operation on the user identification information according to the decrypted source key to obtain the root key information;

[0029] The hierarchical operation decryption unit is used to obtain the hierarchical key encryption and decryption algorithm, the hierarchical key information and the root key information, and use the hierarchical key encryption and decryption algorithm to apply the root key information to decrypt the hierarchical key information to obtain the test key information.

[0030] Furthermore, the hierarchical information storage unit is also used to store handshake request information and handshake response information;

[0031] The key generating unit comprises:

[0032] A handshake decryption operation circuit, used to decrypt the test key information itself using the test key information to obtain the handshake encryption key information;

[0033] A handshake encryption operation circuit, used for receiving the handshake request information, and encrypting the handshake request information using the handshake encryption key information to obtain handshake encryption information;

[0034] The handshake information verification circuit is used to obtain the handshake response information and the handshake encryption information, and determine whether the two match. If so, the verification passes and the test key information is stored in the key recording unit; otherwise, the verification fails and the test key information is not stored in the key recording unit.

[0035] The second aspect of the present invention further provides a chip security simulation analysis method for preventing a single time attack, the method is applied to the device, and the method comprises the following steps:

[0036] The key information storage unit stores the key signal and the path information corresponding to the key signal;

[0037] The simulation circuit unit receives the test stimulus information to perform simulation testing; the test stimulus information includes the key signal;

[0038] The key signal monitoring unit monitors the key signal according to the path information corresponding to the key signal, and records the current timestamp information when the key signal changes;

[0039] The operation time analysis unit determines the change time zone corresponding to the key signal, calculates the operation time value of the change time zone, and determines whether the operation time values ​​of each key signal are related. If they are related, each key signal with correlation and its corresponding operation time value are recorded; the change time zone corresponding to the key signal refers to the difference between the timestamp information of the current key signal change and the timestamp information of the last time the key signal changed.

[0040] Further, the key signal includes test key information, the test key information is generated by a key generation unit, and the key generation unit includes a source data storage unit, a source data decryption unit, a hierarchical information storage unit, a root key calculation unit, and a hierarchical calculation decryption unit;

[0041] The method comprises the following steps:

[0042] The source data storage unit stores encrypted source data, wherein the source data includes a source key and a hierarchical encryption and decryption algorithm;

[0043] The source data decryption unit obtains the encrypted source data for decryption, obtains the decrypted source key and the decrypted hierarchical encryption and decryption algorithm, sends the decrypted source key to the root key calculation unit, and stores the decrypted hierarchical key encryption and decryption algorithm in the algorithm information storage unit;

[0044] The hierarchical information storage unit stores hierarchical key information and user identification information;

[0045] The root key operation unit obtains the user identification information and the decrypted source key, and performs a hash operation on the user identification information according to the decrypted source key to obtain the root key information;

[0046] The hierarchical operation decryption unit obtains the hierarchical key encryption and decryption algorithm, the hierarchical key information and the root key information, and uses the hierarchical key encryption and decryption algorithm to apply the root key information to decrypt the hierarchical key information to obtain the test key information.

[0047] Different from the prior art, the chip security simulation analysis method and device for preventing single time attack described in the above technical solution include: a key information storage unit for storing key signals and path information corresponding to the key signals; a simulation circuit unit for receiving test stimulus information for simulation testing; the test stimulus information includes the key signal; a key signal monitoring unit for monitoring the key signal according to the path information corresponding to the key signal, and recording the current timestamp information when the key signal changes; an operation time analysis unit for determining the change time zone corresponding to the key signal, and calculating the operation time value of the change time zone, and judging whether the operation time values ​​of each key signal are related, and if so, recording each key signal with correlation and its corresponding operation time value. Through the above scheme, the chip security simulation test can be simulated in the chip design stage, and the time attack analysis can be automatically completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A schematic diagram of a chip security simulation and analysis device for preventing a single time attack according to an embodiment of the present invention;

[0049] Figure 2 A schematic diagram of a chip security simulation and analysis device for preventing a single time attack according to another embodiment of the present invention;

[0050] Figure 3 A schematic diagram of the structure of a key generation unit according to an embodiment of the present invention;

[0051] Figure 4 A schematic diagram of the structure of a key generating unit according to another embodiment of the present invention;

[0052] Figure 5 A flowchart of a chip security simulation analysis method for preventing a single time attack according to an embodiment of the present invention;

[0053] Figure 6 A flowchart of a chip security simulation analysis method for preventing a single time attack according to another embodiment of the present invention;

[0054] Figure 7 A schematic diagram of a chart drawn by a drawing unit according to an embodiment of the present invention.

[0055] Description of reference numerals:

[0056] 101. Key information storage unit;

[0057] 102. Simulation circuit unit;

[0058] 103, key signal monitoring unit; 201, mark insertion unit;

[0059] 104. Operation time analysis unit;

[0060] 105. Random number generating unit;

[0061] 106. Simulation stimulus generating unit;

[0062] 107. Drawing unit;

[0063] 108. A key generating unit;

[0064] 301. Source data storage unit;

[0065] 302. Source data decryption unit;

[0066] 303. Algorithm information storage unit;

[0067] 304. Hierarchical information storage unit;

[0068] 305. root key operation unit;

[0069] 306, hierarchical decryption operation unit; 3061, first-level decryption operation unit; 3062, second-level decryption operation unit; 3063, third-level decryption operation unit;

[0070] 307, handshake decryption operation circuit; 3071, first level handshake decryption operation circuit; 3072, second level handshake decryption operation circuit; 3073, third level handshake decryption operation circuit;

[0071] 308, handshake encryption operation circuit; 3081, first-level handshake encryption operation circuit; 3082, second-level handshake encryption operation circuit; 3083, third-level handshake encryption operation circuit;

[0072] 309, handshake information verification circuit;

[0073] 310. Key selection unit;

[0074] 311, algorithm selection unit; 3111, first-level algorithm selection unit; 3112, second-level algorithm selection unit; 3113, third-level algorithm selection unit;

[0075] 109. Key recording unit. DETAILED DESCRIPTION

[0076] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0077] like Figure 1 As shown, the first aspect of the present invention provides a chip security simulation and analysis device for preventing a single time attack, characterized in that the device comprises:

[0078] The key information storage unit 101 is used to store key signals and path information corresponding to the key signals. The key signal refers to the data to be monitored for security. For a computer, it is generally a string of machine codes consisting of "0" or "1", which can be key information or important security data. The path information refers to the set of executable paths of the key signal. By selecting appropriate test cases, the changes of the key signal can be detected in time, and then collected and analyzed.

[0079] In this embodiment, the key signals and the path information corresponding to the key signals can be obtained in the following manner: before the simulation test begins, an RTL test design is completed for the main control chip to be tested, and the circuit to be tested of the RTL design is used as an input file to start the simulation analysis platform, and the key signals in the RTL design and the path information corresponding to these signals are written into the key information storage unit.

[0080] The simulation circuit unit 102 is used to receive test stimulus information for simulation testing; the test stimulus information includes the key signal. The test stimulus information refers to a test case, which refers to a set of test inputs, execution conditions and expected results compiled for a specific goal, used to verify whether a specific software requirement is met. The simulation circuit unit 102 can be implemented by a simulation circuit tool, such as a VCS simulation tool and a modelsim simulation tool.

[0081] The key signal monitoring unit 103 is used to monitor the key signal according to the path information corresponding to the key signal, and record the current timestamp information when the key signal changes. When the key signal is executed according to the corresponding path information, if it changes (such as from "0" to "1"), the current timestamp information is recorded at this time. By screening the timestamp information of the key signal changes for analysis later, the correlation between the key signal in various types of changes can be analyzed, and then it can be determined whether the key signal is currently likely to be attacked.

[0082] The operation time analysis unit 104 is used to determine the change time zone corresponding to the key signal, calculate the operation time value of the change time zone, and determine whether the operation time values ​​of each key signal are related. If they are related, each key signal with correlation and its corresponding operation time value are recorded; the change time zone corresponding to the key signal refers to the difference between the timestamp information of the current key signal change and the timestamp information of the last time the key signal changed.

[0083] For example, when the operation time value of a certain change type of a key signal is significantly higher or lower than other change types, it can be determined that the key signal has a correlation with this change type, that is, the key signal has the possibility of being attacked during the simulation process, and then the operation time value of this change type will be uniformly recorded for further analysis by technical personnel.

[0084] Through the above solution, the security simulation test of the chip can be simulated in the early stage of chip design. Specifically, the performance of the main control chip is tested through various test cases, mainly including the time detection of key signal changes, so as to effectively warn hackers who use time attacks, greatly improving the analysis efficiency.

[0085] like Figure 2 As shown, the key signal monitoring unit 103 includes a marker inserting unit 201. The marker inserting unit 201 is used to set a marker signal, insert the marker signal into the path information corresponding to the key signal, and record the current timestamp information when the marker signal value changes; the value of the marker signal is equal to the value of the key signal in real time; the operation time analysis unit 104 is used to extract the marker signal, and determine the change time zone corresponding to the key signal according to the timestamp information of each marker signal.

[0086] In actual application, the key signal monitoring unit 103 will add a key signal monitoring component to the circuit simulation verification platform (i.e., the "simulation circuit unit" mentioned above) according to the current position of the key signal. For example, for the key signal a with path path_x, the monitoring component can be configured as:

[0087] wait(path_x.a==1'b1)$display_time;

[0088] In this way, the current simulation time can be printed when the key signal a in the path path_x is 1. Of course, the judgment condition in the path information can also be changed to (path_x.a == 0'b1)$display_time, which means that when the value of the key signal a is 0, the current simulation time is printed.

[0089] Then the marker insertion unit 201 is responsible for inserting time markers into the key signals, and the specific component configuration is as follows:

[0090] wait(path_x.a==1'b1)set flag_a=1'b1;

[0091] In this way, when the value of a of path path_x is 1, the identification signal a is set to 1, that is, the value of the identification signal is equal to the value of the key signal in real time. After all the test stimulus information is traversed, by searching and retrieving the values ​​of all identification signals, the change of the value of each key signal can be clearly known.

[0092] In some embodiments, the apparatus further comprises:

[0093] The random number generating unit 105 is used to generate a random number. Preferably, the random number generating unit generates a random number at regular intervals, and the generated random number is random, so that the stimulus generated by the simulation stimulus generating unit is also completely random.

[0094] The simulation stimulus generation unit 106 is used to generate test stimulus information according to the random number generated by the random number generation unit, and transmit the test stimulus information to the simulation circuit unit. As an influencing factor affecting the generation of the test stimulus information, the random number can ensure the randomness of the test stimulus information generation, thereby simulating the operation process of the main control chip under various application scenarios. In order to ensure that the test stimulus information can cover all possible situations as much as possible, in this embodiment, the number of random numbers generated by the random number generation unit 105 is also large enough (exceeding the preset number).

[0095] In some embodiments, the device further includes: a drawing unit 107, which is used to generate a corresponding chart according to the operation time value of each key signal. In this way, the tester can intuitively see whether the operation time of each key signal is related through the generated chart, and further analyze whether the current circuit is likely to be attacked by time when the operation time of each key signal is related, thereby effectively improving the test analysis efficiency.

[0096] For example, the key information is the test key information, which is an 8-bit value. The operation time value of the change time zone corresponding to each bit is shown in Table 1.

[0097] Key value 0 1 0 1 1 0 0 1 Time (ms) 3.9 8 3 8.5 7.8 3.2 2.5 9

[0098] Table 1 - Operation time value table of the change time zone corresponding to each bit

[0099] It can be seen from Table 1 that when the value of the bit of the key information is 1, such as the 2nd, 4th, 5th and 8th bits in Table 1, the corresponding operation time value is significantly higher than the operation time when the bit value is 0, that is, it can be determined that there is a correlation in the operation time when the key information changes to 1. The tester can further analyze the possibility of time attack on the current main control chip.

[0100] In order to enable testers to obtain simulation results more intuitively, Figure 7 As shown, according to each bit value of the key information and the corresponding operation time of these bits recorded in Table 1 during this simulation process, a broken line change graph is generated. Figure 7 The horizontal axis represents the key signal value (such as the key value of each bit of the key information), and the vertical axis represents the corresponding operation time value. Figure 7 It can be intuitively seen whether the change of the key value is linearly correlated with time. If there is a correlation, it means that the current chip under test is easy for hackers to discover patterns and crack security information during the calculation process. Testers can further optimize related designs to improve the overall security performance of the chip.

[0101] Preferably, the change of the key signal includes a plurality of different change types. The operation time analysis unit 104 is used to calculate the average value of the operation time values ​​of the same change type, and when the difference between the average value of the operation time value of a certain change type and the average value of the operation time value of other change types is greater than a preset error, it is determined that the key signal has a correlation with the operation time value of the change type.

[0102] For example, the preset error can be set to a ratio of 30% between the average value of the operation time value of a certain change type and the average value of the operation time value of other change types. Taking the data in Table 1 as an example, when the key value in Table 1 is 1, the operation time is around 8mS for many times, while the average value of other types of key values ​​is only 2.6mS. The ratio between the two is 307.6%, which is much larger than the preset error. Therefore, it can be determined that when the change type is 1 (from other values ​​to 1), the key signal has an obvious correlation in this change type. Of course, the preset error can be set according to actual needs, such as setting the difference between the operation time values ​​of two change types to be within 2ms, or the ratio between the two to be less than 50%, etc.

[0103] In some embodiments, the critical information includes test key information; the apparatus includes:

[0104] The key generating unit 108 is used to generate the test key information;

[0105] A key recording unit 109, used to store the test key information;

[0106] The operation time analysis unit 104 is used to obtain the test key information and determine whether the operation time values ​​of each test key information are related.

[0107] As a tool for data encryption and decryption, key information is a key link in chip security simulation. Therefore, in this embodiment, in addition to monitoring some key data, key information changes are also monitored to ensure that testers can promptly detect the possibility of time attacks on the key. The specific method is to monitor the operation time value of each test key information, and output prompt information when it is determined that the operation time value of a certain type of key information is related. The prompt information includes one or more of sound prompt information, image prompt information, light prompt information, and video prompt information.

[0108] In order to further improve the security of the key information used by the chip during the operation process, the present application designs a special key generation unit 108 to generate the key information required for the operation. Figure 3 As shown, the key generation unit 108 involved in this application includes:

[0109] The source data storage unit 301 is used to store the encrypted source data, and the source data includes a source key and a hierarchical encryption and decryption algorithm. In the present embodiment, the source data storage unit 301 is an OTP storage unit (i.e., a one-time programmable unit), which can effectively prevent the source data from being tampered with. In order to prevent hackers from directly obtaining the source data from the source data storage unit 301, the source data is first encrypted and then stored in the OTP storage unit in the present application, and the initial key used for encryption can be stored in other storage units to improve the security of the source data storage. The hierarchical encryption and decryption algorithm is the algorithm selected for subsequent data encryption and decryption, and can specifically include any one or more of the AES algorithm, the TDES algorithm, and the SM4 algorithm.

[0110] The source data decryption unit 302 is used to obtain the encrypted source data for decryption, obtain the decrypted source key and the decrypted hierarchical encryption and decryption algorithm, and send the decrypted source key to the root key operation unit, and store the decrypted hierarchical key encryption and decryption algorithm in the algorithm information storage unit 303.

[0111] The hierarchical information storage unit 304 is used to store hierarchical key information and user identification information.

[0112] The root key operation unit 305 is used to obtain the user identification information and the decrypted source key, and perform a hash operation on the user identification information according to the decrypted source key to obtain the root key information. Since the root key information is obtained by performing a hash operation on the user identification information by the decrypted source key, it can be ensured that the number of bits of the source key and the generated root key are consistent, and at the same time, it can be ensured that the chip uses different keys after receiving different user logins, further improving security. The user identification information is an ID to distinguish different users, for example, it can be a string of characters.

[0113] The hierarchical decryption operation unit 306 is used to obtain the hierarchical key encryption and decryption algorithm, the hierarchical key information and the root key information, and use the hierarchical key encryption and decryption algorithm to apply the root key information to decrypt the hierarchical key information to obtain the test key information. In this way, the decryption algorithm in the test key information generation process comes from the hierarchical key encryption and decryption algorithm in the algorithm information storage unit 303, and is screened by the algorithm selection unit 311. The object of decryption is the hierarchical key information, and the decryption key is the root key information. The three come from different units, thereby further improving the security of the generated test key information.

[0114] In order to prevent the test key information from being intercepted and tampered during the generation process, in this embodiment, the hierarchical information storage unit is also used to store handshake request information and handshake response information. The key generation unit 108 includes:

[0115] The handshake decryption operation circuit 307 is used to use the test key information to decrypt the test key information itself to obtain the handshake encryption key information. The test key information itself is easily intercepted or tampered with during the transmission process, but after the test key information is first decrypted by the test key information itself, the difficulty of the hacker's reverse cracking increases exponentially. Therefore, the present application first allows the test key information to decrypt the test key information itself before performing data verification to obtain the handshake encryption key information.

[0116] The handshake encryption operation circuit 308 is used to receive the handshake request information and encrypt the handshake request information using the handshake encryption key information to obtain the handshake encryption information. The handshake request information can be pre-stored in the handshake information storage unit 304. The handshake request information refers to the information to be verified, and the handshake encryption information can be obtained after being encrypted by the handshake encryption key information.

[0117] The handshake information verification circuit 309 is used to obtain the handshake response information and the handshake encryption information, and determine whether the two match. If so, the verification passes and the test key information is stored in the key recording unit; otherwise, the verification fails and the test key information is not stored in the key recording unit. The handshake response information refers to the verification standard information pre-stored in the handshake information storage unit 304 and obtained after the handshake request information is encrypted. By comparing the handshake response information and the handshake encryption information, it can be inferred whether the current test key information has been tampered with. If the two match, the test key information can be output.

[0118] like Figure 4As shown, in order to enable different users to use functions with different permissions when using the chip to be tested, in this embodiment, different levels of key information can be set for different users when using the chip to be tested, that is, the key generating unit can generate key information to be tested of the corresponding level according to the security level of the user. The higher the level, the higher the security of the key information to be tested.

[0119] Taking the key level as three security levels as an example, the device includes a key selection unit 310. The decryption operation unit includes a first-level decryption operation unit 3061, a second-level decryption operation unit 3062, and a third-level decryption operation unit 3063. The handshake decryption operation circuit includes a first-level handshake decryption operation circuit 3071, a second-level handshake decryption operation circuit 3072, and a third-level handshake decryption operation circuit 3073. The handshake encryption operation circuit includes a first-level handshake encryption operation circuit 3081, a second-level handshake encryption operation circuit 3082, and a third-level handshake encryption operation circuit 3083. The algorithm information storage unit 303 is provided with a plurality of encryption and decryption algorithms, including a first-level encryption and decryption algorithm, a second-level encryption and decryption algorithm, and a third-level encryption and decryption algorithm, and is selected in turn by a first-level algorithm selection unit 3111, a second-level algorithm selection unit 3112, and a third-level algorithm selection unit 3113. The hierarchical key information includes a first-level source key, a second-level source key, and a third-level source key.

[0120] Figure 4 The working principle of the key generating unit 108 is as follows: the key generating unit 108 obtains the current user level, and outputs a test key matching the user level to the key recording unit 109 through the key selecting unit 310. Assuming that there are three levels of user levels, the key selecting unit 310 selects the first-level key, the second-level key and the third-level key in turn for output. The security level of the third-level key is greater than that of the second-level key, and the security level of the second-level key is greater than that of the first-level key.

[0121] The generation process of the primary key is as follows:

[0122] The source data decryption unit 302 obtains the encrypted source key and hierarchical encryption and decryption algorithm in the source data storage unit 301, decrypts them, obtains the decrypted source key and hierarchical encryption and decryption algorithm, and sends the decrypted source key to the root key calculation unit 305, and stores the decrypted hierarchical key encryption and decryption algorithm in the algorithm information storage unit 303. The root key calculation unit obtains the user identification information and the decrypted source key, performs a hash operation on the user identification information according to the decrypted source key, and obtains the root key information.

[0123] Then the first-level decryption operation unit 3061 receives the first-level source key of the hierarchical information storage unit 304, and the first-level algorithm selection unit 3111 selects the first-level key encryption and decryption algorithm to the first-level decryption operation unit 3061, so that the first-level decryption operation unit 3061 uses the first-level key encryption and decryption algorithm to apply the root key information to decrypt the first-level source key to obtain the first-level key. If the security level of the current user is level one, the key selection unit 310 can select the first-level key to output.

[0124] Before output, in order to prevent the first-level key from being tampered with during transmission, the generated first-level key needs to be verified. Specifically, the first-level key itself is encrypted once by the first-level handshake decryption operation circuit 3071 using the first-level key to obtain the first-level handshake encryption key information. Then, the first-level handshake request data transmitted by the hierarchical information storage unit 304 is received by the first-level handshake encryption operation circuit 3081, and the first-level handshake request data is encrypted using the first-level handshake encryption key information to obtain the first-level handshake encryption information. Then, the first-level handshake response data transmitted by the hierarchical information storage unit 304 is received, and the first-level handshake response data is compared with the first-level handshake encryption information. If the two match, it means that the first-level key has not been tampered with, and it can be output through the key selection unit 310, otherwise a prompt message can be issued.

[0125] The process of generating the secondary key is as follows:

[0126] The generation process of the secondary key is similar to that of the primary key, except that the primary key is used as an input parameter for the generation of the secondary key (equivalent to the root key input when the primary key is generated). Specifically, the secondary decryption operation unit 3062 receives the second-layer source key of the hierarchical information storage unit 304, and the secondary algorithm selection unit 3112 selects the secondary key encryption and decryption algorithm to the secondary decryption operation unit 3062, so that the secondary decryption operation unit 3062 uses the secondary key encryption and decryption algorithm to apply the primary key to the second-layer source key to decrypt the second-layer source key to obtain the secondary key. If the current user's security level is level 2, the key selection unit 310 can select the secondary key to output.

[0127] Before output, in order to prevent the secondary key from being tampered with during transmission, the generated secondary key needs to be verified. Specifically, the secondary key itself is first encrypted once by the secondary handshake decryption operation circuit 3072 using the secondary key to obtain the secondary handshake encryption key information. Then, the second-layer handshake request data transmitted by the hierarchical information storage unit 304 is received by the secondary handshake encryption operation circuit 3082, and the second-layer handshake request data is encrypted using the secondary handshake encryption key information to obtain the second-layer handshake encryption information. Then, the second-layer handshake response data transmitted by the hierarchical information storage unit 304 is received, and the second-layer handshake response data is compared with the second-layer handshake encryption information. If the two match, it means that the secondary key has not been tampered with, and it can be output through the key selection unit 310, otherwise a prompt message can be issued.

[0128] The generation process of the three-level key is as follows:

[0129] The generation process of the third-level key is similar to that of the second-level key, except that the second-level key is used as an input parameter for the generation of the third-level key (equivalent to the first-level key input when the second-level key is generated). Specifically, the third-level decryption operation unit 3063 receives the third-level source key of the hierarchical information storage unit 304, and the third-level algorithm selection unit 3113 selects the third-level key encryption and decryption algorithm to the third-level decryption operation unit 3062, so that the third-level decryption operation unit 3063 uses the third-level key encryption and decryption algorithm to apply the second-level key to decrypt the third-level source key to obtain the third-level key. If the current user's security level is level three, the key selection unit 310 can select the third-level key for output.

[0130] Before output, in order to prevent the third-level key from being tampered with during transmission, the generated third-level key needs to be verified. Specifically, the third-level key itself is first encrypted once by the third-level handshake decryption operation circuit 3073 using the third-level key to obtain the third-level handshake encryption key information. Then, the third-level handshake request data transmitted by the hierarchical information storage unit 304 is received by the third-level handshake encryption operation circuit 3083, and the third-level handshake request data is encrypted using the third-level handshake encryption key information to obtain the third-level handshake encryption information. Then, the third-level handshake response data transmitted by the hierarchical information storage unit 304 is received, and the third-level handshake response data is compared with the third-level handshake encryption information. If the two match, it means that the third-level key has not been tampered with, and it can be output through the key selection unit 310, otherwise a prompt message can be issued.

[0131] Of course, in other embodiments, the number of user levels can also be other values, such as two security levels or more than four security levels. Correspondingly, the level of the test key information can also be other numbers, which can be set according to actual needs. When the level of the test key information is other numbers, the method of generating it can refer to Figure 4 The circuit application process shown will not be repeated here.

[0132] like Figure 5 As shown, the second aspect of the present application further provides a chip security simulation analysis method for preventing a single time attack, characterized in that the method is applied to the device as described in the first aspect of the present application, and the method comprises the following steps:

[0133] First, enter step S501, the key information storage unit stores the key signal and the path information corresponding to the key signal;

[0134] Then, the process proceeds to step S502, where the simulation circuit unit receives the test stimulus information to perform simulation testing; the test stimulus information includes the key signal;

[0135] Then, in step S503, the key signal monitoring unit monitors the key signal according to the path information corresponding to the key signal, and records the current timestamp information when the key signal changes;

[0136] Then enter step S504, the operation time analysis unit determines the change time zone corresponding to the key signal, calculates the operation time value of the change time zone, and determines whether the operation time values ​​of each key signal are related. If they are related, each key signal with correlation and its corresponding operation time value are recorded; the change time zone corresponding to the key signal refers to the difference between the timestamp information of the current key signal change and the timestamp information of the last time the key signal changed.

[0137] In some embodiments, the critical signal includes test key information, which is generated by a key generating unit, which includes a source data storage unit, a source data decryption unit, a hierarchical information storage unit, a root key operation unit and a hierarchical decryption operation unit.

[0138] like Figure 6 As shown, the method comprises the following steps:

[0139] First, enter step S601. The source data storage unit stores the encrypted source data, where the source data includes a source key and a hierarchical encryption and decryption algorithm.

[0140] Then, the source data decryption unit can enter step S602 to obtain the encrypted source data for decryption, obtain the decrypted source key and the decrypted hierarchical encryption and decryption algorithm, and send the decrypted source key to the root key operation unit, and store the decrypted hierarchical key encryption and decryption algorithm in the algorithm information storage unit.

[0141] In parallel with step S601 and step S602, step S603 may be entered in which the hierarchical information storage unit stores hierarchical key information and user identification information;

[0142] After step S602 and step S603, the process may proceed to step S604 where a root key operation unit obtains the user identification information and the decrypted source key, and performs a hash operation on the user identification information according to the decrypted source key to obtain the root key information.

[0143] After step S604, the hierarchical decryption operation unit may enter step S605 to obtain the hierarchical key encryption and decryption algorithm, the hierarchical key information and the root key information, and use the hierarchical key encryption and decryption algorithm to apply the root key information to decrypt the hierarchical key information to obtain the test key information.

[0144] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. A chip security simulation and analysis device for preventing single time attacks, characterized in that: The device comprises: A key information storage unit, used to store key signals and path information corresponding to the key signals; A simulation circuit unit, used for receiving test stimulus information to perform simulation testing; the test stimulus information includes the key signal; A key signal monitoring unit, configured to monitor the key signal according to path information corresponding to the key signal, and record current timestamp information when the key signal changes; The operation time analysis unit is used to determine the change time zone corresponding to the key signal, calculate the operation time value of the change time zone, and judge whether the operation time value of the key signal is relevant. If relevant, the relevant key signal and its corresponding operation time value are recorded; the change time zone corresponding to the key signal refers to the difference between the timestamp information of the current key signal change and the timestamp information of the last time the key signal changed.

2. The chip security simulation and analysis device for preventing a single time attack as claimed in claim 1, characterized in that: The key signal monitoring unit includes a marker insertion unit; The marker insertion unit is used to set a marker signal, insert the marker signal into the path information corresponding to the key signal, and record the current timestamp information when the marker signal value changes; The value of the marking signal is equal to the value of the key signal in real time; The operation time analysis unit is used to extract the marker signal and determine the change time zone corresponding to the key signal according to the timestamp information of each marker signal.

3. The chip security simulation and analysis device for preventing a single time attack as claimed in claim 1, characterized in that: The device also includes: A random number generating unit, used for generating random numbers; The simulation stimulus generating unit is used to generate test stimulus information according to the random number generated by the random number generating unit, and transmit the test stimulus information to the simulation circuit unit.

4. The chip security simulation and analysis device for preventing a single time attack as claimed in claim 1, characterized in that: The device also includes: The drawing unit is used to generate corresponding charts according to the operation time values ​​of the key signals.

5. The chip security simulation and analysis device for preventing a single time attack as claimed in claim 1, characterized in that: Changes in key signals include several different types of changes; The operation time analysis unit is used to calculate the average operation time value of each same change type. When the difference between the average operation time value of a certain change type and the average operation time value of other change types is greater than a preset error, it is determined that the key signal has a correlation with the operation time value of the change type.

6. The chip security simulation and analysis device for preventing a single time attack as claimed in claim 1, characterized in that: The key information includes test key information; the device includes: A key generating unit, used for generating the test key information; A key recording unit, used for storing the test key information; The operation time analysis unit is used to obtain the test key information and determine whether the operation time values ​​of each test key information are related.

7. The chip security simulation and analysis device for preventing a single time attack as claimed in claim 6, characterized in that: The key generating unit comprises: A source data storage unit, used to store encrypted source data, wherein the source data includes a source key and a hierarchical encryption and decryption algorithm; A source data decryption unit is used to obtain the encrypted source data for decryption, obtain a decrypted source key and a decrypted hierarchical encryption and decryption algorithm, send the decrypted source key to a root key calculation unit, and store the decrypted hierarchical encryption and decryption algorithm in an algorithm information storage unit; A hierarchical information storage unit, used to store hierarchical key information and user identification information; A root key operation unit, used to obtain the user identification information and the decrypted source key, and perform a hash operation on the user identification information according to the decrypted source key to obtain the root key information; The hierarchical operation decryption unit is used to obtain the hierarchical encryption and decryption algorithm, the hierarchical key information and the root key information, and use the hierarchical encryption and decryption algorithm to apply the root key information to decrypt the hierarchical key information to obtain the test key information.

8. The chip security simulation and analysis device for preventing a single time attack as claimed in claim 7, characterized in that: The hierarchical information storage unit is also used to store handshake request information and handshake response information; The key generating unit comprises: A handshake decryption operation circuit, used to decrypt the test key information itself using the test key information to obtain the handshake encryption key information; A handshake encryption operation circuit, used for receiving the handshake request information, and encrypting the handshake request information using the handshake encryption key information to obtain handshake encryption information; The handshake information verification circuit is used to obtain the handshake response information and the handshake encryption information, and determine whether the two match. If so, the verification passes and the test key information is stored in the key recording unit; otherwise, the verification fails and the test key information is not stored in the key recording unit.

9. A chip security simulation analysis method for preventing single time attack, characterized in that: The method is applied to the device as claimed in claim 1, and the method comprises the following steps: The key information storage unit stores the key signal and the path information corresponding to the key signal; The simulation circuit unit receives the test stimulus information to perform simulation testing; the test stimulus information includes the key signal; The key signal monitoring unit monitors the key signal according to the path information corresponding to the key signal, and records the current timestamp information when the key signal changes; The operation time analysis unit determines the change time zone corresponding to the key signal, calculates the operation time value of the change time zone, and determines whether the operation time value of the key signal is relevant. If relevant, the relevant key signal and its corresponding operation time value are recorded; the change time zone corresponding to the key signal refers to the difference between the timestamp information of the current key signal change and the timestamp information of the last time the key signal changed.

10. The chip security simulation analysis method for preventing a single time attack as claimed in claim 9, characterized in that: The key signal includes test key information, the test key information is generated by a key generation unit, the key generation unit includes a source data storage unit, a source data decryption unit, a hierarchical information storage unit, a root key calculation unit and a hierarchical calculation decryption unit; The method comprises the following steps: The source data storage unit stores encrypted source data, wherein the source data includes a source key and a hierarchical encryption and decryption algorithm; The source data decryption unit obtains the encrypted source data for decryption, obtains the decrypted source key and the decrypted hierarchical encryption and decryption algorithm, sends the decrypted source key to the root key calculation unit, and stores the decrypted hierarchical encryption and decryption algorithm in the algorithm information storage unit; The hierarchical information storage unit stores hierarchical key information and user identification information; The root key operation unit obtains the user identification information and the decrypted source key, and performs a hash operation on the user identification information according to the decrypted source key to obtain the root key information; The hierarchical operation decryption unit obtains the hierarchical encryption and decryption algorithm, the hierarchical key information and the root key information, and uses the hierarchical encryption and decryption algorithm to apply the root key information to decrypt the hierarchical key information to obtain the test key information.

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