Semiconductor Devices

Abstract

Embodiments of the present disclosure relate to semiconductor devices. Fins, control gate electrodes, and memory gate electrodes arranged along the Y direction, each of which is formed to extend along the Y direction to cross the fins, a plurality of first plugs electrically connected to a drain region formed in each fin, and a plurality of second plugs electrically connected to a source region formed in each fin. Here, the Nth plug of the plurality of first plugs arranged along the Y direction is coupled to each of the 2N‑1th and 2Nth fins along the Y direction. In addition, the Nth plug of the plurality of second plugs arranged along the Y direction is coupled to each of the 2Nth and 2N+1th fins along the Y direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2019-114431 filed on June 20, 2019 including its specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device, and more particularly, to a technology for a semiconductor device including a fin-type transistor. Background Art

[0004] It is known that a fin transistor is a transistor that has a high operating speed, can reduce leakage current and power consumption, and can be miniaturized. A fin field effect transistor (FINFET) is, for example, a semiconductor device having a sheet-like semiconductor layer pattern as a channel layer protruding from a substrate and having a gate electrode formed across the pattern.

[0005] EEPROM (Electrically Erasable Programmable Read-Only Memory) is widely used as a non-volatile memory device that can be electrically written and erased. The memory device represented by the currently widely used flash memory has a conductive floating gate electrode or a trap insulating film surrounded by an oxide film under the gate electrode of the MISFET. In addition, the charge accumulation state in the floating gate or the trap insulating film is used as storage information, and the storage state is read as the threshold of the transistor. The trap insulating film is an insulating film capable of storing charge, for example, a silicon nitride film or the like can be given. The threshold of the MISFET is shifted by injecting charge into the charge storage area and releasing the charge therefrom, so that it operates as a memory element. As a flash memory, there is a separate gate type unit using a MONOS (metal oxide-nitride oxide semiconductor) film.

[0006] The disclosed technologies are listed below.

[0007] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2017-45860.

[0008] Patent Document 1 discloses a MONOS memory cell made of FINFET. Summary of the invention

[0009] As semiconductor devices are miniaturized, when multiple fins are arranged in a transverse direction intersecting their extension direction, the distance between the fins arranged adjacent to each other becomes smaller. Therefore, a contact plug connected to the source region or drain region of the FINFET formed on each fin is formed so as to extend over two or more fins in the transverse direction. Therefore, the area required to form a memory cell of a 1-bit portion becomes larger. Therefore, the miniaturization of semiconductor devices becomes difficult.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0011] Typical embodiments among the embodiments disclosed in the present application will be briefly described below.

[0012] The semiconductor device according to the embodiment includes first to third fins, each fin protruding from the upper surface of the semiconductor substrate and each fin extending in a first direction. Each of the first to third fins is a part of the semiconductor substrate. In addition, the first to third fins are arranged in sequence along a second direction intersecting the first direction. The semiconductor device according to the present embodiment further includes a control gate electrode and a memory gate electrode, which are arranged adjacent to each other along the first direction. Each of the control gate electrode and the memory gate electrode extends along the second direction so as to cross the first to third fins. The semiconductor device according to the present embodiment further includes a source region and a drain region formed in each fin. The semiconductor device according to the present embodiment also includes a first plug connected to the drain region of each of the first fin and the second fin, and a second plug connected to the source region of each of the second fin and the third fin. In addition, the source region formed in the second fin, the drain region formed in the second fin, the control gate electrode on the second fin, and the memory gate electrode on the second fin constitute a memory cell.

[0013] According to the embodiments disclosed in the present application, the performance of a semiconductor device can be improved, in particular, the area per 1 bit of a fin-type MONOS memory can be reduced and the semiconductor device can be miniaturized. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a plan view of a semiconductor device according to an embodiment of the present application.

[0015] Figure 2 is a perspective view of a semiconductor device according to an embodiment of the present application.

[0016] Figure 3 is along Figure 1 Cross-sectional view along line AA and line BB.

[0017] Figure 4 is along Figure 1 Cross-sectional view along line CC.

[0018] Figure 5 is along Figure 1 Cross-sectional view along line DD.

[0019] Figure 6 is a plan view of a semiconductor device according to an embodiment of the present application.

[0020] Figure 7 is a plan view of a semiconductor device according to a modified example of the present application.

[0021] Figure 8 is an example table illustrating conditions for applying voltage to each portion of a selected memory cell during "write", "erase", and "read".

[0022] Fig. 9 is a plan view of a semiconductor device according to a comparative example studied by the present inventors. DETAILED DESCRIPTION

[0023] For the sake of convenience, in the following embodiments, the description is made by dividing them into a plurality of sections or embodiments, but unless otherwise explicitly stated, these sections or embodiments are not independent of each other, and one is related to a modified example, detail, supplementary description, etc. of part or all of another. In addition, in the following embodiments, except for the case where the number of elements is particularly specified or the case where the number of originals is obviously limited to a specific number in principle, the number of elements, etc. (including quantity, number, amount, range, etc.) is not limited to the number described, and may be equal to or greater than the above number, or may be equal to or less than the above number.

[0024] Furthermore, in the following embodiments, except for the cases clearly specified and the cases considered to be obviously necessary in principle, the constituent elements (including element steps, etc.) are not necessarily essential. Similarly, in the following embodiments, when the shapes, positional relationships, etc. of the components, etc. are mentioned, except for the cases clearly specified and the cases considered to be obvious in principle, the shapes, etc. are assumed to be substantially similar to or similar to the shapes, etc. The same applies to the above-mentioned numerical values ​​and ranges.

[0025] The embodiments will be described in detail below based on each of the accompanying drawings. In all the drawings used to illustrate the embodiments, components having the same function are represented by the same reference numerals, and their repeated descriptions are omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless it is particularly necessary. In addition, in the drawings used to illustrate the embodiments, shading may be applied to plan views, perspective views, etc. to make the configuration easy to understand.

[0026] In the following, reference will be made to Figures 1 to 6 The structure of the semiconductor device of this embodiment will be described. Figure 1is a plan view of the semiconductor device according to the present embodiment. Figure 2 is a perspective view of the semiconductor device according to the present embodiment. Figures 3 to 5 is a cross-sectional view of a semiconductor device according to this embodiment. Figure 1 In FIG, only the fin, gate electrode and plug are shown. Figure 2 In FIG. 1 , source and drain regions, an interlayer insulating film covering the memory cell, and a wiring layer on the interlayer insulating film are not shown. Figure 3 From the left, the Figure 1 The section along line AA and Figure 1 The cross section of line BB. Figure 4 is along Figure 1 Cross-sectional view along line CC. Figure 5 is along Figure 1 A cross-sectional view of line DD. Figure 6 In Figure 1, only the fins, gate electrodes, plugs, and some wires are shown. Figure 2 In the example, the description of the well is omitted. Figure 4 , the description of the source and drain regions is omitted.

[0027] Figure 1 to Figure 2 A memory cell area including a memory cell array is shown, which is formed by arranging a plurality of memory cells as non-volatile storage elements. The memory cell area is an area in which a non-volatile memory (electrically erasable programmable read-only memory) capable of electrically rewriting stored information is formed in a semiconductor chip through a write operation and an erase operation. In the memory cell area, each of a plurality of fins F1 to F4 and FD1 to FD4 extending in the X direction is arranged at equal intervals in the Y direction. Each of the X and Y directions is a direction along the upper surface of the semiconductor substrate SB, and the X direction intersects with the Y direction. For example, each of the fins F1 to F4 and FD1 to FD4 is a protruding portion of a cuboid selectively protruding from the upper surface of the semiconductor substrate SB, and has a sheet-like shape. Specifically, fins F1, FD1, F2, FD2, F3, FD3, F4, and FD4 are arranged in this order in the Y direction.

[0028] In a plan view, the direction in which each of the fins F1 to F4 and FD1 to FD4 extends is the longitudinal direction (long side direction, extension direction) of each fin, and the direction intersecting the longitudinal direction is the transverse direction (short side direction) of each fin. That is, the length of the fin is greater than the width of the fin. The fins F1 to F4 and FD1 to FD4 can have any shape as long as they are protruding parts with length, width and height. For example, it can have a zigzag layout in a plan view.

[0029] In a plan view, the lower end portions of the fins F1 to F4 and FD1 to FD4 are surrounded by a device isolation film EI covering the upper surface of the semiconductor substrate SB. That is, between the fins F1 to F4 and FD1 to FD4, the space between the fins arranged adjacent to each other in a plan view is filled with a device isolation film EI. Each of the fins F1 to F4 and FD1 to FD4 is a part of the semiconductor substrate SB and is an active region of the semiconductor substrate SB. However, the fins F1 to F4 are active regions for forming memory cells MC1 to MC8, respectively, and memory cells are not formed in the fins FD1 to FD4, respectively. That is, the fins FD1 to FD4 are dummy fins, i.e., pseudo fins, and a channel of a transistor is not formed in each of the fins FD1 to FD4.

[0030] Each of the fins F1 to F4 and FD1 to FD4 is a portion of the semiconductor substrate SB that is retained in a sheet-like shape between the grooves formed by etching back the upper surface of the semiconductor substrate SB. However, in the present application, the "upper surface of the semiconductor substrate" is defined as referring to the surface of the semiconductor substrate located between the fins arranged adjacent to each other in the memory cell array (memory cell area), in which a plurality of memory cells composed of fin-type field effect transistors (FINFETs) are formed. That is, when the "upper surface of the semiconductor substrate" is used herein, the upper surface does not refer to the upper surface of the fin, but refers to the bottom surface of the trench covered with a device isolation film around the fin.

[0031] A plurality of control gate electrodes CG and a plurality of memory gate electrodes MG extending in the Y direction are formed on the fins F1 to F4 and FD1 to FD4. The control gate electrode CG and the memory gate electrode MG are adjacent to each other via an insulating film C1, which is an oxide-nitride-oxide (Oxide Nitride Oxide) film including a charge storage portion. Here, the insulating film between the memory gate electrode MG and each of the fins F1 to F4 and FD1 to FD4 must be a film including a charge storage portion, for example, an ONO film. However, the insulating film between the control gate electrode CG and the memory gate electrode MG may be an insulating film composed of, for example, a silicon oxide film or a silicon nitride film. Therefore, the insulating film between the control gate electrode CG and the memory gate electrode MG does not need to be the same as the continuous insulating film formed directly below the memory gate electrode MG, and may be a stacked film or a single-layer film.

[0032] In each of the fins F1 to F4 and FD1 to FD4, a source region SR and a drain region DR as n-type semiconductor regions are formed from the surface of the fins F1 to F4 and FD1 to FD4 to the inside of the source region SR and the drain region DR, respectively. The source region SR and the drain region DR formed in one fin are arranged in a plan view in such a manner as to sandwich the control gate electrode CG and the memory gate electrode MG, with the drain region DR arranged on the control gate electrode CG side and the source region SR arranged on the memory gate electrode side. That is, in the X direction, the control gate electrode CG and the memory gate electrode MG adjacent to each other are located between the source region SR and the drain region DR.

[0033] Here, the paired semiconductor regions sandwiching the control gate electrode CG and the memory gate electrode MG in a plan view constitute a memory cell and can act as a source region or a drain region depending on the operation of the memory cell. Therefore, here, the semiconductor region (diffusion region) on the memory gate electrode MG side is defined as a source region, and the semiconductor region (diffusion region) on the control gate electrode CG side is defined as a drain region.

[0034] like Figure 1 As shown, a pair of control gate electrodes CG and memory gate electrodes MG adjacent to each other are arranged in a line-symmetrical manner along the X direction with respect to another pair of control gate electrodes CG and memory gate electrodes MG. That is, the memory gate electrode MG is not arranged between the control gate electrodes CG adjacent to each other, and a drain region DR is formed in each of the fins F1 to F4 and the fins FD1 to FD4 between the control gate electrodes CG. In addition, the control gate electrode CG is not arranged between the memory gate electrodes MG adjacent to each other, and a source region SR is formed in each of the fins F1 to F4 and the fins FD1 to FD4 between the memory gate electrodes MG.

[0035] One plug (drain contact plug, conductive connection portion) DC is electrically connected to the drain region DR of each of the fins F1, FD1, and F2. One plug DC is electrically connected to the drain region DR of each of the fins F3, FD3, and F4. That is, one plug DC is electrically connected to the drain region DR of each of the fins F1, FD1, and F2, and the plug DC overlaps the fins F1, FD1, and F2 in a plan view. Similarly, another plug DC is electrically connected to the drain region DR of each of the fins F3, FD3, and F4, and the other plug DC overlaps the fins F3, FD3, and F4 in a plan view.

[0036] On the other hand, these plugs DC are not connected to the drain region DR of each of the fins FD2 and FD4. That is, a plurality of plugs DC are spaced apart from each of the fins FD2 and FD4 in a plan view. In other words, each of the fins FD2 and FD4 is arranged between the plugs DC arranged in the Y direction in a plan view. Therefore, the fins FD2 and FD4 and the plugs DC are insulated from each other.

[0037] One plug SC is connected to the source region SR of each of the fin F1 and two fins (not shown). One plug SC is connected to the source region SR of each of the fins F2, FD2, and F3. One plug SC is connected to the source region SR of each of the fins F4, FD4, and fin FD4, and the source region SR of the fin FD4 and the fin are adjacent to each other. That is, one plug SC is electrically connected to the source region SR of each of the two fins of the fin F1 and the unshown region, and the plug SC overlaps the fin F1 and the two fins in a plan view. One plug SC is electrically connected to the source region SR of each of the fins F2, FD2, and F3, and the plug SC overlaps the fins F2, FD2, and F3 in a plan view. Similarly, another plug SC is electrically connected to the source region SR of each fin (not shown) adjacent to the fins F4, FD4, and fin FD4, and the plug SC overlaps the fins (not shown) adjacent to the fins F4, FD4, and fin FD4 in a plan view.

[0038] On the other hand, the plug SC and Figure 5 The source region SR of each of the fins FD1 and FD3 is shown to be unconnected. That is, a plurality of plugs SC are spaced apart from each of the fins FD1 and FD3 in a plan view. In other words, each of the fins FD1 and FD3 is arranged between the plugs SC arranged in the Y direction in a plan view. Therefore, the fins FD1 and FD3 and the plugs SC are insulated from each other.

[0039] In this way, multiple plugs DC and SC are arranged side by side along the Y direction. The plugs DC and plugs SC arranged along the X direction are arranged at positions moved half a circle along the Y direction. That is, the plugs DC and SC are arranged in a staggered manner. Therefore, among the multiple fins connected to one plug DC, one plug SC is connected to some fins, and another plug SC is connected to some of the other fins. Similarly, among the multiple fins connected to one plug SC, one plug SC is connected to some fins, and another plug SC is connected to some of the other fins. That is, each of the first fin connected to one end of the plug DC along the Y direction and the second fin connected to the other end of the plug DC along the Y direction is connected to a separate plug SC. Similarly, each of the second fin connected to one end of the plug SC along the Y direction and the third fin connected to the other end of the plug SC along the Y direction is connected to a separate plug DC.

[0040] Here, it is assumed that there are no fins FD1 to FD4 in which no channel is formed and which do not affect the operation of the semiconductor device. Figure 1 In the embodiment, each of the fins F1 to F4 including any one of the memory cells MC1 to MC8 can be regarded as the first fin, the second fin, the third fin, and the fourth fin arranged along the Y direction. At this time, the first plug DC of the plurality of plugs DC arranged along the Y direction is electrically connected to each of the first fin and the second fin. In addition, only focusing on Figure 1 The integrated plug SC shown, the first plug SC among the plurality of plugs SC arranged along the Y direction is electrically connected to each of the second fin and the third fin, and the second plug DC among the plurality of plugs DC arranged along the Y direction is electrically connected to each of the third fin and the fourth fin.

[0041] That is, the Nth plug DC arranged in the Y direction is coupled to the 2N-1th and 2Nth fins, and the Nth plug SC arranged in the Y direction is coupled to the 2Nth and 2N+1th fins. That is, the Nth plug DC of the plurality of plugs DC arranged in the Y direction is electrically connected to the drain region DR formed in each of the 2N-1th fin (protrusion) of the plurality of fins (protrusions) arranged in the Y direction and the 2Nth fin (protrusion) of the plurality of fins (protrusions). In addition, the Nth plug SC of the plurality of plugs SC arranged in the Y direction is electrically connected to the source region SR formed in each of the 2Nth fin (protrusion) of the plurality of fins (protrusions) arranged in the Y direction and the 2N+1th fin (protrusion) of the plurality of fins (protrusions).

[0042] Here, focusing on the presence of dummy fins FD1 to FD4, among the plugs DC arranged in the Y direction, the Nth plug DC is electrically connected to the fin FD1 between the 2N-1th fin F1 and the 2Nth fin F2 in the Y direction. In addition, the Nth plug SC among the plurality of plugs SC arranged in the Y direction is electrically connected to the fin FD2 between the 2Nth fin F2 and the 2N+1th fin F3 in the Y direction.

[0043] The memory cell MC1 is a nonvolatile memory element having a control gate electrode CG and a memory gate electrode MG, and a drain region DR and a source region SR formed in the fin F1. The memory cell MC2 is a nonvolatile memory element having a control gate electrode CG and a memory gate electrode MG, and a drain region DR and a source region SR formed in the fin F2. The memory cell MC3 is a nonvolatile memory element having a control gate electrode CG and a memory gate electrode MG, and a drain region DR and a source region SR formed in the fin F3. The memory cell MC4 is a nonvolatile memory element having a control gate electrode CG and a memory gate electrode MG, and a drain region DR and a source region SR formed in the fin F4. Hereinafter, the drain region DR and the source region SR constituting one memory cell may be referred to as a source / drain region.

[0044] Figure 1 Memory cells MC5 to MC8 are shown, each of which has a control gate electrode CG and a memory gate electrode MG different from the aforementioned control gate electrode CG and the aforementioned memory gate electrode MG. Memory cell MC5 includes a source / drain region formed in fin F1, memory cell MC6 includes a source / drain region formed in fin F2, memory cell MC7 includes a source / drain region formed in fin F3, and memory cell MC8 includes a source / drain region formed in fin F4. That is, memory cells MC1 and MC5 are formed on fin F1, memory cells MC2 and MC6 are formed on fin F2, memory cells MC3 and MC7 are formed on fin F3, and memory cells MC4 and MC8 are formed on fin F4.

[0045] The memory cells MC1 to MC4 and the memory cells MC5 to MC8 are symmetrical in the X direction with the line passing through the center of the plug SC in the X direction as an axis. That is, the memory cells MC1, MC5 share one source region SR with each other. This also applies to the memory cells MC2 and MC6, the memory cells MC3 and MC7, and the memory cells MC4 and MC8. In addition, other memory cells (not shown) arranged beside the memory cell MC1 in the X direction via the plug DC have a line-symmetrical configuration with respect to the memory cell MC1, and the above-mentioned memory cells and the memory cell MC1 share one drain region.

[0046] The memory cells MC1 to MC8 are connected to different combinations of plugs DC and SC. That is, only one memory cell is connected to a predetermined plug DC and a predetermined plug SC. Different potentials can be simultaneously supplied to the plugs DC arranged in the Y direction. In addition, different potentials (voltages) can be simultaneously supplied (applied) to the Nth plug SC of the plurality of plugs SC arranged in the Y direction and the N+1th plug SC of the plurality of plugs SC. That is, as Figure 6 As shown, the plurality of plugs SC arranged along the Y direction are alternately connected to different source lines. That is, the potential of the Nth plug SC among the plurality of plugs SC arranged along the Y direction and the potential of the N+1th plug SC among the plurality of plugs SC arranged along the Y direction can be controlled separately.

[0047] Therefore, any one memory cell can be selected from the memory cells MC1 to MC8, and a desired operation can be performed on it. That is, the operation of each of the memory cells MC1 to MC8 can be controlled separately. In other words, the operation of the memory cell MC1, which includes the source region SR and the drain region DR pair formed in the 2N-1th fin F1 among the multiple fins arranged along the Y direction (excluding the dummy fin), and the operation of the memory cell MC2, which includes the source region SR and the drain region DR pair formed in the 2Nth fin F2 among the multiple fins arranged along the Y direction, can be controlled separately. Therefore, the area required to form a 1-bit memory cell is determined by Figure 1 , and the region is within the range from the center of the plug SC to the middle of the plugs SC adjacent to each other in the Y direction.

[0048] The distance (width) of the region in the X direction is the distance between the center of each plug in the plugs DC and SC that clamp the control gate electrode CG and the memory gate electrode MG pair in the X direction. The distance (width, cell pitch) of the region in the Y direction is approximately 1.5 times the distance Ly. The distance Ly is the distance between the plugs DC that are adjacent to each other in the Y direction, and is also the distance between the plugs SC that are adjacent to each other in the Y direction. Here, since the plurality of fins arranged in the Y direction are arranged at equal intervals, the length of the plugs DC in the Y direction and the length of the plugs SC in the Y direction are determined by the distance between the plugs DC that are adjacent to each other in the Y direction, and the distance between the plugs SC that are adjacent to each other in the Y direction, respectively. Specifically, the length of each plug DC and SC in the Y direction is approximately twice the distance Ly. Therefore, as described above, the distance of the region in the Y direction is 1.5×Ly. That is, when a memory cell array is formed with the distance Ly of the width of the plugs DC or SC as a reference, the cell pitch in the Y direction is 1.5×Ly. In the case where dummy fins FD1 to FD4 are not formed (see Figure 7), as in the modified example of the present embodiment described later, this is also true. The cell size mentioned in this application is the size (area) of the region required to form a 1-bit memory cell, and the cell pitch mentioned in this application is the width of the region.

[0049] Although not described in the present embodiment, the semiconductor chip according to the present embodiment has a logic circuit region in addition to the memory cell region forming the memory cell array. The logic circuit region includes a plurality of fin-type MISFETs (metal insulator semiconductor field effect transistors, MIS-type field effect transistors) including logic circuits. In the logic circuit region, a plurality of fins forming the MISFETs are arranged at equal intervals along the transverse direction of each fin, for example, at the shortest distance that can be formed. In the memory cell region, dummy fins FD1 to FD4 are formed to match the arrangement of the fins in the logic circuit region, thereby achieving simplification of the semiconductor device manufacturing process and improvement of reliability. In addition, since dummy fins FD1 to FD4 are formed, the fins are densely formed. Therefore, defects such as local excessive depressions can be prevented from occurring.

[0050] In a region (memory cell array) where a plurality of memory cells are arranged in an array shape along the X direction and the Y direction, the structure of the memory cell of 1 bit surrounded by the dotted line is repeatedly arranged along the X direction and the Y direction. However, the memory cells adjacent to each other along the X direction or the Y direction have the same shape in a plan view. Figure 1 The layout is line-symmetrical with respect to each other, with one side of the rectangle formed by the dashed line as the axis.

[0051] Figure 3 A cross section including the control gate electrode CG, the memory gate electrode MG, the plugs DC and SC along the longitudinal direction of the fin F2 and a cross section including the memory gate electrode MG along the lateral direction of the fin F2 are shown in order from left to right. Figure 4 Cross sections including the plug SC along the lateral direction of the fins F2 to F4 and the fins FD1 to FD4 are respectively shown.

[0052] like Figures 2 to 5 , the control gate electrode CG and the memory gate electrode MG extend in the Y direction to cross multiple fins including the fin F2. It can be imagined that the upper surface of each control gate electrode CG and the memory gate electrode MG is covered with a silicide layer, but the silicide layer is not shown here. The silicide layer is composed of, for example, nickel silicide (NiSi). The fin F2 will be described below, but the other fins have the same structure as the fin F2. Although the memory cell MC2 will be mainly described below, the other memory cells have the same structure as the memory cell MC2.

[0053] The lower part of the side surface of the fin F2 is surrounded by the device isolation film EI formed on the upper surface of the semiconductor substrate SB. That is, the fins are separated from each other by the element isolation film EI. In the fin F2, a p-type well PW as a p-type semiconductor region is formed from the upper surface of the fin F2 to the lower part of the fin F2.

[0054] For example, the fin F2 is a protruding portion in the shape of a rectangular parallelepiped, protruding from the upper surface of the semiconductor substrate SB in a direction perpendicular to the upper surface. However, the fin F2 does not necessarily have to be a rectangular parallelepiped, and the corners of the rectangle in a cross-sectional view along the lateral direction may be rounded. In addition, the side surface of the fin F2 may be perpendicular to the upper surface of the semiconductor substrate SB, but may also have an inclination angle close to vertical. That is, the cross-sectional shape of the fin F2 is a rectangular parallelepiped or a trapezoid.

[0055] The control gate electrode CG is formed on the upper surface and side surface of the fin F2 via the gate insulating film GF, and the memory gate electrode MG is formed in the region adjacent to the control gate electrode CG via the insulating film C1 along the longitudinal direction (X direction) of the fin F2. The insulating film C1 is inserted between the control gate electrode CG and the memory gate electrode MG, and the control gate electrode CG and the memory gate electrode MG are electrically isolated by the insulating film C1. The insulating film C1 is inserted between the memory gate electrode MG and the upper surface of the fin F2. The insulating film C1 is continuously formed to cover the side and bottom surfaces of the memory gate electrode MG. Therefore, the insulating film C1 has an L-shaped cross-sectional shape. The control gate electrode CG and the memory gate electrode MG cover the upper surface and side surface of the fin F2.

[0056] The gate insulating film GF is a thermally oxidized film (silicon oxide film) formed by thermally oxidizing the upper surface and side surface of the fin F2 (the fin F2 is a protruding portion of the semiconductor substrate SB composed of silicon), and the thickness of the gate insulating film GF is, for example, 2 nm. The insulating film C1 includes a silicon oxide film X1 composed of an oxide film with a thickness of 4 nm formed by thermally oxidizing the upper surface and side surface of the fin F2, a silicon nitride film NF formed on the silicon oxide film X1, and a silicon oxide film X2 formed on the silicon nitride film NF. The silicon nitride film NF is the charge storage portion (charge storage layer, charge storage film layer) of the memory cell MC2. For example, the thickness of the silicon nitride film is 7 nm, and the thickness of the silicon oxide film X2 is 9 nm.

[0057] That is, the insulating film C1 has a stacked structure consisting of a silicon oxide film X1, a silicon nitride film NF, and a silicon oxide film X2 stacked in sequence from the upper surface side of the fin F2, and the side surface of the control gate electrode CG. The thickness of the insulating film C1 is, for example, 20 nm, and is greater than the thickness of the gate insulating film GF under the control gate electrode CG. The silicon oxide film X2 can be formed of a silicon oxynitride film.

[0058] Along the lateral direction (Y direction) of the fin F2, the control gate electrode CG extends along the upper surface of the fin F2, the side surface of the fin F2, and the upper surface of the device isolation film EI via the gate insulation film GF. Similarly, along the lateral direction of the fin F2, the memory gate electrode MG extends along the upper surface and side surface of the fin F2 and the upper surface of the device isolation film EI via the insulation film C1.

[0059] The side surface of the pattern including the control gate electrode CG, the memory gate electrode MG, the gate insulating film GF, and the insulating film C1 is covered with the sidewall spacer SW. The sidewall spacer SW has a stacked structure of a silicon nitride film and a silicon oxide film, for example.

[0060] A source region SR and a drain region DR are formed from the surface of the fin F2 to the inside of the fin F2 so as to sandwich the fin F2 directly below the pattern including the control gate electrode CG. The source region SR is composed of a diffusion region DS of an n+ type semiconductor region, and the drain region is composed of an extension region EX of an n- type semiconductor region and a diffusion region DD of an n+ type semiconductor region. The impurity concentration of the diffusion regions DD and DS is higher than that of the extension region EX, and the depth of the extension region EX is deeper than that of the diffusion regions DD and DS. The depth of the extension region EX may be shallower or deeper than that of the diffusion regions DD and DS, but in either case, the end portion of the extension region EX directly below the diffusion region DD is located on the fin F2 side, that is, on the channel region side. The extension region EX and the diffusion region DD are in contact with each other.

[0061] As described above, the short channel characteristics of the MISFET having the drain region DR can be improved by forming the drain region DR having the following structure, which includes the extension region EX having a low impurity concentration and the diffusion region DD having a high impurity concentration, that is, an LDD (Lightly Doped Drain) structure.

[0062] The interlayer insulating film IL1 is composed of, for example, a silicon oxide film formed on the fin F2 and the device isolation film EI.

[0063] A portion of the upper surface and side surface of the fin F2 in which the diffusion domain region DS constituting the source region SR is formed is continuously covered by an epitaxial layer (epitaxial growth layer, semiconductor layer) EPS. In addition, a portion of the upper surface and side surface of the fin F2 in which the diffusion region DD constituting the drain region DR is formed is continuously covered by an epitaxial layer (epitaxial growth layer, semiconductor layer) EPD. Similar to each of the multiple plugs DC and SC, each of the multiple epitaxial layers EPD and the multiple epitaxial layers EPS is arranged side by side along the Y direction. Each of the epitaxial layers EPD and EPS is an epitaxial layer formed by connecting semiconductor layers to each other, and the semiconductor layers grow from the surface of each fin by an epitaxial growth method, and grow from the fins arranged adjacent to each other along the Y direction.

[0064] That is, Figure 4 As shown, the epitaxial layer EPS is formed, for example, in contact with the fins F2, FD2 and F3, and another epitaxial layer EPS is in contact with the fins F4 and FD4, for example, but no epitaxial layer EPS is in contact with the fin FD3 between the fins F3 and F4. This is because after the interlayer insulating film IL1 is formed on the fin where the epitaxial layer is not formed, the upper surface of the interlayer insulating film IL1 is selectively etched back to expose the upper end of a portion of the epitaxial layer, and then the epitaxial layer EPS is formed using an epitaxial growth method. That is, since the fin FD3 is not exposed during the back etching process and the epitaxial layer EPS is formed when the fin FD3 is protected by the interlayer insulating film IL1, the fin FD3 is separated from the epitaxial layer EPS. The epitaxial layer EPD is also formed in the same manner as the epitaxial layer EPS. Therefore, each of the epitaxial layers EPS and EPD is formed inside the trench formed in the upper surface of the interlayer insulating film IL1. The interlayer insulating film IL2 is composed of, for example, a silicon oxide film of each of the epitaxial layers EPS and EPD embedded in the channel. The upper surface of each of the interlayer insulating films IL1 and IL2 is planarized on substantially the same plane.

[0065] Each of the epitaxial layers EPS and EPD is composed of, for example, SiP (silicon phosphide) or SiC (silicon carbide). Each of the epitaxial layers EPS and EPD is a semiconductor layer grown from the surface of each fin, and is integrated in the Y direction (see Figure 4 ) has a diamond shape in cross-section.

[0066] Each of the epitaxial layers EPS and EPD is a semiconductor layer into which n-type impurities such as P (phosphorus) or As (arsenic) are introduced. Furthermore, the epitaxial layer EPS constitutes a source region SR, and the epitaxial layer EPD constitutes a drain region DR.

[0067] The plug SC extending in the Y direction is connected to the upper surface of the epitaxial layer EPS. The plug DC extending in the Y direction is connected to the upper surface of the epitaxial layer EPD. However, a silicide layer (not shown) may be inserted between the plug SC and the epitaxial layer EPS, and between the plug DC and the epitaxial layer EPD. The silicide layer has the function of reducing the connection resistance between the plug DC or SC, which is a connection portion made of a metal film (for example, mainly containing tungsten (W)), and the epitaxial layer EPD or EPS composed of a semiconductor. The epitaxial layers EPD and EPS have the function of reducing the parasitic resistance between the fin and each of the plugs DC and SC. The epitaxial layer EPD has a similar Figure 4 However, in the plan view, the epitaxial EPS is formed on the same Figure 1 The plug SC is shown overlapping the position, and the epitaxial layer EPD is formed at the same Figure 1 The locations of the plug DC overlap are shown.

[0068] Therefore, although all epitaxial layers EPS are not connected to fin FD3, one epitaxial layer EPD is connected to fins F3 and F4 and fin FD3 on both sides of fin FD3 along the Y direction, and all epitaxial layers EPD are not connected to Figure 1 The fins FD2 and FD4 are shown. That is, of the two epitaxial layers EPD arranged along the Y direction, one epitaxial layer EPD is in contact with the fins F1, FD1 and F2, and the other epitaxial layer EPD is in contact with the fins F3, FD3 and F4.

[0069] In other words, the Nth epitaxial layer (semiconductor layer) EPD among the multiple epitaxial layers (semiconductor layers) EPD arranged along the Y direction contacts each of the following surfaces: the upper surface of the drain region DR formed in the 2N-1th fin (protrusion) of the multiple fins (protrusions) arranged along the Y direction and the 2Nth fin (protrusion) of the multiple fins (protrusions), and the side surfaces of the drain region DR formed in the 2N-1th fin (protrusion) of the multiple fins (protrusions) arranged along the Y direction and the 2Nth fin (protrusion) of the multiple fins (protrusions). In addition, the Nth epitaxial layer (semiconductor layer) EPS of the multiple epitaxial layers (semiconductor layers) EPS arranged along the Y direction contacts each of the following surfaces: the upper surface of the source region SR formed in the 2Nth fin (protrusion) of the multiple fins (protrusions) arranged along the Y direction and the 2N+1th fin (protrusion) of the multiple fins (protrusions), and the side surfaces of the source region SR formed in the 2Nth fin (protrusion) of the multiple fins (protrusions) arranged along the Y second direction and the 2N+1th fin (protrusion) of the multiple fins (protrusions).

[0070] The plug DC is electrically connected to the drain region (semiconductor region) DR formed in the fin via the epitaxial layer (semiconductor layer) EPD, and the plug SC is electrically connected to the source region (semiconductor region) SR formed in the fin via the epitaxial layer (semiconductor layer) EPS. Therefore, in a plan view, each of the plugs DC and SC does not need to overlap with all three fins arranged in the Y direction. Each of the plugs DC and SC is embedded in a contact hole opened in the interlayer insulating film IL2.

[0071] Figure 3The memory cell MC2 shown has a control gate electrode CG and a memory gate electrode MG, and a drain region DR and a source region SR formed in the fin F2 so as to sandwich the control gate electrode CG and the memory gate electrode MG. The control gate electrode CG, the drain region DR and the source region SR constitute a control transistor, the memory gate electrode MG, the drain region DR and the source region SR constitute a memory transistor, and the control transistor and the memory transistor constitute the memory cell MC2. That is, the control transistor and the memory transistor share a source / drain region.

[0072] Each of the control transistor and the memory transistor is a fin field effect transistor (FINFET) having a side surface and an upper surface of a fin F2 as a channel region. The distance between the drain region DR and the source region SR in the gate length direction (X direction) of each of the control gate electrode CG and the memory gate electrode MG corresponds to the channel length of the memory cell MC2. When the transistor including the memory cell MC2 is in an on state, a channel is formed on the upper surface and the side surface of the fin F2.

[0073] A plurality of wirings M1 are formed on the interlayer insulating film IL2 and are electrically connected to the drain region DR or source region SR of the memory cell MC2 via plugs DC or SC. Although not shown in the figure, a multilayer wiring layer in which a plurality of wirings and interlayer insulating films are stacked is formed on the wiring M1.

[0074] Figure 6 Source lines SL1 to SL4, bit lines BL1, and bit lines BL2 on fins F1 to F4 and FD0 to FD4 are shown, respectively. However, although lower wiring may be formed between plug DC and bit lines BL1 to BL2 or between plug SC and source lines SL1 to SL4, Figure 6 The lower wiring is not shown. Figure 6 Also shown are memory cells MC9 to MC16 having a line-symmetric layout with respect to memory cells MC1 to MC8 in the X direction. Figure 3 The interconnect M1 shown is arranged in Figure 6 The wiring M1 is shown below the source lines SL1 to SL4 and the bit lines BL1 to BL2. Note that the wiring M1 can constitute one of the bit lines and the source lines. The source lines SL1 to SL4 and the bit lines BL1 to BL2 are not formed at the same height, and one of the source lines and the bit lines is located above the other. Figure 6 , even in a portion where the bit lines BL1 , BL2 and other patterns overlap each other in a plan view, outlines of the bit lines BL1 , BL2 and other patterns are shown.

[0075] like Figure 6As shown, the bit lines BL1 and BL2 extend in the X direction and are aligned in the Y direction. The source lines SL1 to SL4 extend in the Y direction and are aligned with each other in the X direction. The bit line BL1 is electrically connected to the respective drain regions DR of the memory cells MC1, MC2, MC5, MC6, MC9, MC10, MC13, and MC14 through the plug DC. The bit line BL2 is electrically connected to the respective drain regions DR of the memory cells MC3, MC4, MC7, MC8, MC11, MC12, MC15, and MC16 through the plug DC. The source line SL1 is electrically connected to the source regions SR of the memory cells MC1, MC4, and MC5 and the SR of the memory cell MC8. The source line SL2 is electrically connected to the source regions SR of the memory cells MC2, MC3, and MC6 and the SR of the memory cell MC7. The source line SL3 is electrically connected to the source regions SR of the memory cells MC9, MC12, and MC13 and the SR of the memory cell MC16. The source line SL4 is electrically connected to the source regions SR of the memory cells MC10 , MC11 , and MC14 and the SR of the memory cell MC15 .

[0076] As described above, different source lines are alternately connected to the plugs SC arranged in the Y direction. Therefore, any one memory cell can be selected from the memory cells MC1 to MC16, and a desired operation can be performed on it. When each of the bit lines BL1 to BL2 extends just above the plug DC, the source lines SL1 to SL4 do not extend just above the plug SC, and the portions protruding from the source lines SL1 to SL4 in the X direction overlap with the plug SC in a plan view.

[0077] <Operation of Nonvolatile Memory>

[0078] Next, we will refer to Figure 8 An operation example of the nonvolatile memory is described.

[0079] Figure 8 is an example table showing conditions for applying voltage to each portion of a selected memory cell at the time of "writing", "erasing", and "reading". Figure 8 The table below describes the voltages applied to the Figure 3 The voltage Vmg of the memory gate electrode MG of the memory cell MC2 (selected memory cell) shown, the voltage Vs applied to the source region SR, the voltage Vcg applied to the control gate electrode CG, the voltage Vd applied to the drain region DR, and the voltage Vb applied to the p-type well PW. Note that Figure 8The contents shown in the table are appropriate examples of voltage application conditions, are not limited thereto, and can be variously changed as needed. In addition, in this embodiment, injecting electrons into the silicon nitride film NF as the charge storage portion of the memory transistor is defined as "writing", and injecting holes into the silicon nitride film NF is defined as "erasing".

[0080] As a writing system, a so-called SSI (Source Side Injection) method, that is, a writing method (hot electron injection writing method) in which writing is performed by hot electron injection injected from the source side can be used. Figure 8 The voltage shown in the "Write" column in is applied to each portion of the memory cell selected to perform writing, and electrons are injected into the silicon nitride film NF of the insulating film C1 of the selected memory cell to perform writing.

[0081] For example, in a write operation, 1.5V is applied to the drain region DR and 6V is applied to the source region SR. Therefore, current flows from the source region SR (on the memory gate electrode MG side) to the drain region DR (on the control gate electrode CG side). Carriers (electrons) flow from the drain region DR (on the control gate electrode CG side) to the source region SR (on the memory gate electrode MG side). That is, here, the semiconductor region (drain region DR) on the control gate electrode CG side serves as a source, and the semiconductor region (source region SR) on the memory gate electrode MG side serves as a drain.

[0082] At this time, hot electrons are generated in the channel region (between the source region and the drain region) located between the two gate electrodes (the memory gate electrode MG and the control gate electrode CG) in a plan view, and the hot electrons are injected into the silicon nitride film NF, which is the charge storage portion in the insulating film C1 below the gate electrode MG. The injected hot electrons are captured by the trap levels in the silicon nitride film NF of the insulating film C1, and therefore, the threshold voltage of the memory transistor is increased. That is, the memory transistor is in a write state.

[0083] As an erasing method, a so-called BTBT method, that is, an erasing method (hot hole injection erasing method) in which erasing is performed by hot hole injection by BTBT (band-to-band tunneling) can be used. That is, erasing is performed by injecting holes generated by BTBT (band-to-band tunneling) into the charge storage portion (silicon nitride film NF in the insulating film C1). For example, Figure 8The voltage shown in the "Erase" column in is applied to each part of the selected memory cell to be erased, holes are generated by the BTBT phenomenon, and are accelerated by the electric field to inject the holes into the silicon nitride film NF of the insulating film C1 of the selected memory cell, thereby reducing the threshold voltage of the memory transistor. That is, the memory transistor is in an erased state.

[0084] For example, when reading, Figure 8 The voltage shown in the "Read" column in is applied to each portion of the selected memory cell to be read. By setting the voltage Vmg applied to the memory gate electrode MG during reading to a value between the threshold voltage of the memory transistor in the write state and the threshold voltage of the memory transistor in the erase state, the write state and the erase state can be identified.

[0085] For example, in a read operation, 1.5V is applied to the drain region DR, and 0V is applied to the source region SR. Therefore, current flows from the drain region DR (on the control gate electrode CG side) to the source region SR (on the memory gate electrode MG side). Carriers (electrons) flow from the source region SR (on the memory gate electrode MG side) to the drain region DR (on the control gate electrode CG side). That is, in a write operation, the roles of the source and the drain are interchanged between the source region SR and the drain region DR.

[0086] <Influence of semiconductor devices>

[0087] Fig. 9 is a plan view of a semiconductor device of a comparative example studied by the present inventors. Figure 1 In the memory cell array of the present embodiment shown in FIG. 1 , one plug SC is connected to only two memory cells, and one plug SC is not connected to three or more memory cells. Figure 1 The floor plan shown is different. Fig. 9 In the planar layout of the memory cell array shown, one plug (source contact plug) SC1 connected to the source regions of the memory cells MC1 to MC4 extends in the Y direction, and three or more memory cells arranged in the Y direction are connected to each other.

[0088] like Fig. 9As shown, in the memory cell array, fins FD1, F1, F1, FD2, FD2, F2, F2, and FD3 are arranged in sequence along the Y direction. Each of the fins FD1, FD2, and FD3 has a source / drain region, but since the plug DC1 is not connected, a channel is not formed, and therefore a memory cell is not included. Each of the fins F1, F2, and F3 has a source / drain region, and plugs DC1 and SC1 are coupled to the source / drain region. Therefore, the source region SR and the drain region DR formed in each of the fins F1, F2, and F3 constitute a memory cell.

[0089] Here, the plug SC1 is connected to each of the two fins F1 connected to one plug DC1. That is, since it is impossible to apply different drain voltages or source voltages to the two fins F1 arranged adjacent to each other in the Y direction, the two fins F1 operate as one memory cell MC1. Therefore, the area required for forming a 1-bit memory cell in the memory cell array is determined by Fig. 9 The region surrounded by the dashed line is shown. The distance (width, cell pitch) of the region along the Y direction is, for example, the distance from the middle of two fins FD1 arranged adjacent to each other to the middle of two fins FD2 arranged adjacent to each other.

[0090] The plug DC1 of the comparative example has a distance Lx from one end along the Y direction to the other end along the Y direction. The distance Lx is the minimum length for forming the plug DC1, and when a plurality of fins are arranged at equal intervals along the Y direction with a minimum interval, the plug DC1 needs to overlap with two fins in a plan view. In the present example, the distance between the plugs DC1 arranged along the Y direction is the same distance Lx as the length of the plug DC1 along the Y direction. This is the same even if the dummy fins FD1, FD2, and FD3 are not formed, or only one fin is formed directly under the plug DC1. Therefore, the width required to form a 1-bit memory cell along the Y direction is 2×Lx. That is, in the comparative embodiment, since the memory cell array is formed with the distance Lx between the plugs DC1 as a reference, the cell pitch along the Y direction is 2×Lx. In Fig. 9 In the illustrated configuration, two dummy fins not connected to the plug DC1 among the dummy fins FD1 , FD2 , or FD3 are arranged side by side between the plugs DC1 that are adjacently arranged in the Y direction.

[0091] Here, in order to reduce the parasitic resistance between the fin and the plug DC1, an epitaxial layer (not shown) is grown on the fin so as to extend in the Y direction. Therefore, the distance between the plugs DC1 arranged adjacently in the Y direction needs to be wide. In the semiconductor device of the comparative example, since the length of the plug DC1 in the Y direction is formed to be the shortest, the distance between the plugs DC1 is the distance Lx, and one plug SC1 is connected to all the fins connected to each plug DC1 arranged in the Y direction. In this example, an individually controllable memory cell cannot be formed in each of the multiple fins connected to one plug DC1. On the other hand, even if only one fin is formed directly below the plug DC1, the cell size cannot be reduced. Therefore, in the comparative example, the problem of increasing the cell size occurs.

[0092] Therefore, in this embodiment, if Figure 1 As shown, a plurality of plugs DC periodically arranged along the Y direction and a plurality of plugs SC periodically arranged along the Y direction are formed, and the plugs SC are arranged at positions shifted by half a circle relative to the plugs DC along the Y direction. Here, for example, since different plugs SC are respectively connected to fins F1 and F2 connected to one plug DC1, the operation of the memory cell MC1 on the fin F1 and the operation of the memory cell MC2 on the fin F2 can be controlled respectively. Therefore, the cell size of a 1-bit memory cell can be reduced.

[0093] In particular, since the distance Lx of the comparative example (see Fig. 9 ) is, for example, 60 nm, and the distance Ly of this embodiment (see Figure 1 ) is, for example, 50 nm. In this embodiment, the cell pitch along the Y direction is 1.5×Ly. Compared with the comparative example in which the cell pitch along the Y direction is 2×Lx, the cell size can be reduced to 63%.

[0094] As described above, in the semiconductor device of the present embodiment, by reducing the cell size of the memory cell, the semiconductor device can be miniaturized and further integrated. Therefore, the performance of the semiconductor device can be improved.

[0095] <Modification example>

[0096] like Figure 7 As shown, dummy fins may not be formed. Figure 7 is a plan view showing the semiconductor device of this embodiment.

[0097] exist Figure 7 In the memory cell array shown, fins F1, F2, F3 and F4 are arranged in sequence along the Y direction. Figures 1 to 6 The structure is the same as described above, except that dummy fins FD1 to FD4 are not formed (see Figure 1 ).

[0098] Specifically, each of the plugs DC and SC is connected to only two fins. In addition, in a plan view, no fin is arranged between the plugs DC arranged adjacent to each other in the Y direction and the plugs SC arranged adjacent to each other in the Y direction.

[0099] Even if the dummy fin is not arranged as in the present modification example, Figures 1 to 6 In the same manner as in the semiconductor device, the cell size of a 1-bit memory cell is reduced, which can improve the performance of the semiconductor device.

[0100] Although the invention of the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned embodiments, and it is needless to say that various modifications can be made without departing from the gist thereof.

Claims

1. A semiconductor device, include: Semiconductor substrate; a plurality of first protruding portions, each of which protrudes from an upper surface of the semiconductor substrate and extends in a first direction along the upper surface of the semiconductor substrate, each of the plurality of first protruding portions being a part of the semiconductor substrate; a first gate electrode formed on an upper surface of each of the plurality of first protruding portions and a side surface of each of the plurality of first protruding portions via a first insulating film and extending in a second direction intersecting the first direction; a second gate electrode formed on the upper surface of each of the plurality of first protruding portions and the side surface of each of the plurality of first protruding portions via a second insulating film as a charge storage portion, and extending in the second direction, the second gate electrode being adjacent to one of the side surfaces of the first gate electrode via the insulating film; A first semiconductor region is formed in each of the plurality of first protruding portions in a form arranged adjacent to the first gate electrode in a plan view; a second semiconductor region formed in each of the plurality of first protruding portions in a form arranged adjacent to the second gate electrode in a plan view; a plurality of first plugs, respectively formed on the plurality of first protruding portions and arranged along the second direction; and a plurality of second plugs, respectively formed on the plurality of first protruding portions and arranged along the second direction, wherein the first gate electrode, the second gate electrode, the first semiconductor region and the second semiconductor region constitute a nonvolatile storage element, wherein an Nth plug of the plurality of first plugs arranged along the second direction is electrically connected to the first semiconductor region formed in each of the 2N-1th protrusion of the plurality of first protrusions arranged along the second direction and the 2Nth protrusion of the plurality of first protrusions, and The Nth plug of the plurality of second plugs arranged along the second direction is electrically connected to the second semiconductor region formed in each of the 2Nth protrusion of the plurality of first protrusions arranged along the second direction and the 2N+1th protrusion of the plurality of first protrusions.

2. The semiconductor device according to claim 1, further comprising: include: A plurality of first semiconductor layers are formed to be arranged along the second direction; as well as A plurality of second semiconductor layers are formed to be arranged along the second direction; The Nth semiconductor layer of the plurality of first semiconductor layers arranged along the second direction is in contact with each of the following surfaces: an upper surface of the first semiconductor region formed in each of the 2N-1th protrusion of the plurality of first protrusions arranged along the second direction and the 2Nth protrusion of the plurality of first protrusions; as well as a side surface of the first semiconductor region formed in each of the 2N-1th protrusion of the plurality of first protrusions arranged along the second direction and the 2Nth protrusion of the plurality of first protrusions, The Nth semiconductor layer of the plurality of second semiconductor layers arranged along the second direction is in contact with each of the following surfaces: an upper surface of the first semiconductor region formed in each of the 2Nth protruding portion of the plurality of first protruding portions arranged along the second direction and the 2N+1th protruding portion of the plurality of first protruding portions; as well as a side surface of the first semiconductor region formed in each of the 2Nth protrusion of the plurality of first protrusions arranged along the second direction and the 2N+1th protrusion of the plurality of first protrusions, wherein the plurality of first plugs are electrically connected to the first semiconductor regions formed in each of the plurality of first protruding portions via the plurality of first semiconductor layers, respectively; and The plurality of second plugs are electrically connected to the second semiconductor regions formed in each of the plurality of first protruding portions via the plurality of second semiconductor layers.

3. The semiconductor device according to claim 1, further comprising: include: a plurality of second protrusions, each of which protrudes from the upper surface of the semiconductor substrate and extends in the first direction, each of the plurality of second protrusions is a part of the semiconductor substrate, and each of the plurality of second protrusions is formed between two first protrusions of the plurality of first protrusions arranged along the second direction, the two first protrusions being arranged adjacent to each other wherein the Nth plug among the plurality of first plugs arranged along the second direction is electrically connected to the first second protruding portion among the plurality of second protruding portions, the Nth plug among the plurality of first plugs is located between the 2N-1th protruding portion among the plurality of first protruding portions and the 2Nth protruding portion among the plurality of first protruding portions, the 2N-1th protruding portion and the 2Nth protruding portion are arranged along the second direction, and The Nth plug among the multiple second plugs arranged along the second direction is electrically connected to the second protrusion among the multiple second protrusions, the Nth plug among the multiple second plugs is located between the 2Nth protrusion among the multiple first protrusions and the 2N+1th protrusion among the multiple first protrusions, and the 2Nth protrusion and the 2N+1th protrusion are arranged along the second direction.

4. The semiconductor device according to claim 3, in, In a plan view, the first second protrusion among the plurality of second protrusions electrically connected to the Nth plug among the plurality of first plugs is spaced apart from the plurality of second plugs, and Wherein, in a plan view, the second second protruding portion among the plurality of second protruding portions, which is electrically connected to the Nth plug of the plurality of second plugs, is separated from the plurality of first plugs.

5. The semiconductor device according to claim 1, wherein the plurality of first plugs arranged along the second direction are spaced apart from each other, and The plurality of second plugs arranged along the second direction are spaced apart from each other.

6. The semiconductor device according to claim 5, The potential of the Nth plug of the plurality of second plugs and the potential of the N+1th plug of the plurality of second plugs are individually controlled, and the Nth plug and the N+1th plug are arranged along the second direction.

7. The semiconductor device according to claim 1, The operation of the first nonvolatile storage element and the operation of the second nonvolatile storage element can be controlled separately from each other, the first nonvolatile storage element includes a pair of the first semiconductor region and the second semiconductor region formed in the 2N-1th protrusion among the multiple first protrusions arranged along the second direction, and the second nonvolatile storage element includes a pair of the first semiconductor region and the second semiconductor region formed in the 2Nth protrusion among the multiple first protrusions arranged along the second direction.

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