Display Devices

Abstract

A display device is disclosed, comprising: a substrate layer; a pixel circuit layer located on the substrate layer; and a display element layer located on the pixel circuit layer. The pixel circuit layer comprises a lens pattern located in a recess between the display element layer and the substrate layer, the display element layer comprises a light emitting element, and at least a portion of the light emitting element overlaps with the lens pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0073075 filed in the Korean Intellectual Property Office on June 19, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more exemplary embodiments of the present invention relate to a display device. Background Art

[0004] Recently, a technology for manufacturing ultra-small light-emitting elements using a material having an inorganic crystal structure with high reliability and a technology for manufacturing a light-emitting device using the light-emitting elements have been developed. For example, a technology for manufacturing a plurality of ultra-small light-emitting elements having a size as small as a nanometer level or a micrometer level and a technology for manufacturing various light-emitting devices including pixels using the ultra-small light-emitting elements have been developed.

[0005] The above information disclosed in this Background section is for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art. Summary of the invention

[0006] One or more exemplary embodiments of the present invention relate to a display device including a plurality of light-emitting elements, which can improve optical efficiency by a lens pattern unit (e.g., a lens pattern) located under the light-emitting elements in the display device. However, the present invention is not limited thereto, and a person of ordinary skill in the art can understand other aspects and features of the present invention from the exemplary embodiments described herein.

[0007] According to one or more exemplary embodiments, a display device includes: a substrate layer; a pixel circuit layer located on the substrate layer; and a display element layer located on the pixel circuit layer. The pixel circuit layer includes a lens pattern located at a recess between the display element layer and the substrate layer, the display element layer includes a light emitting element, and at least a portion of the light emitting element overlaps with the lens pattern.

[0008] In one or more exemplary embodiments, the display element layer may include a first electrode and a second electrode spaced apart from the first electrode, and the light emitting element may be located between the first electrode and the second electrode.

[0009] In one or more exemplary embodiments, the light emitting element may include a first semiconductor layer, an active layer surrounding at least a portion of the first semiconductor layer, and a second semiconductor layer of a different type from the first semiconductor layer and surrounding at least a portion of the active layer.

[0010] In one or more exemplary embodiments, the light emitting element may include a first end portion and a second end portion, the first end portion includes the active layer, and the second end portion does not include the active layer.

[0011] In one or more exemplary embodiments, the display element layer may include a first contact electrode on the first electrode and electrically connected to the first end portion, and a second contact electrode on the second electrode and electrically connected to the second end portion.

[0012] In one or more exemplary embodiments, the pixel circuit layer may include a plurality of transistors and an organic layer covering the plurality of transistors, the organic layer including a lens pattern.

[0013] In one or more exemplary embodiments, the display element layer may further include an insulating layer covering the first electrode, the second electrode, and the organic layer, and a refractive index of the insulating layer may be greater than a refractive index of the organic layer.

[0014] In one or more exemplary embodiments, the lens pattern may include an uneven pattern, and the uneven pattern may be configured to irregularly reflect incident light.

[0015] In one or more exemplary embodiments, the first electrode and the second electrode may not overlap with the lens pattern.

[0016] In one or more exemplary embodiments, a width of the lens pattern may be smaller than a length of the light emitting element.

[0017] In one or more exemplary embodiments, the lens patterns may correspond one-to-one to the light emitting elements.

[0018] In one or more exemplary embodiments, a width of the lens pattern may be greater than or equal to twice a length of the light emitting element.

[0019] According to one or more exemplary embodiments, a display device includes: a substrate layer; a pixel circuit layer located on the substrate layer; and a display element layer located on the pixel circuit layer. The pixel circuit layer includes a lens pattern including a plurality of cone-shaped portions, and the display element layer includes a light-emitting element, and at least a portion of the light-emitting element overlaps with the lens pattern.

[0020] In one or more exemplary embodiments, the display element layer may include a first electrode and a second electrode spaced apart from the first electrode, and the light emitting element may be located between the first electrode and the second electrode.

[0021] In one or more exemplary embodiments, the light emitting element may include a first semiconductor layer, an active layer surrounding at least a portion of the first semiconductor layer, and a second semiconductor layer of a different type from the first semiconductor layer and surrounding at least a portion of the active layer.

[0022] In one or more exemplary embodiments, the light emitting element may include a first end portion and a second end portion, the first end portion includes the active layer, and the second end portion does not include the active layer.

[0023] In one or more exemplary embodiments, the plurality of tapered portions may include a first tapered portion and a second tapered portion spaced apart from the first tapered portion, and a tapered angle of the first tapered portion may be different from a tapered angle of the second tapered portion.

[0024] In one or more exemplary embodiments, the pixel circuit layer may include a plurality of transistors and a metal layer on the plurality of transistors, the metal layer including the lens pattern and electrically connected to at least one of the plurality of transistors.

[0025] In one or more exemplary embodiments, the metal layer may include at least one of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof.

[0026] In one or more exemplary embodiments, a width of the lens pattern may be less than or equal to a length of the light emitting element.

[0027] Other aspects and features of the exemplary embodiments are described in more detail in the detailed description with reference to the accompanying drawings.

[0028] The display device according to the exemplary embodiment of the present invention may include a plurality of light emitting elements, and optical efficiency may be improved by forming a lens pattern under the light emitting elements.

[0029] In example embodiments, a lens pattern formed under a light emitting element may be formed together with (eg, in parallel or simultaneously with) one or more other structures without using a separate mask, thereby reducing processing costs and improving yield of a display device.

[0030] However, the aspects and features of the present invention are not limited thereto, and other aspects and features may be described in or understood from this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1A and Figure 1B are a perspective view and a cross-sectional view respectively showing a light emitting element according to an exemplary embodiment.

[0032] Figure 2A and Figure 2B are a perspective view and a cross-sectional view respectively showing a light emitting element according to another exemplary embodiment.

[0033] Figure 3 is a top plan view showing a display device according to an exemplary embodiment.

[0034] FIG. 4A to FIG. 4C is a circuit diagram illustrating a pixel according to various exemplary embodiments.

[0035] Figure 5 is a top view showing a pixel according to an exemplary embodiment.

[0036] Figure 6 is along Figure 5 A cross-sectional view taken along line AA'.

[0037] Fig. 7A According to an exemplary embodiment Figure 6 A local enlarged view of area Q.

[0038] Figure 7B According to another exemplary embodiment Figure 6 A local enlarged view of area Q.

[0039] Figure 8 is a cross-sectional view of a pixel according to another exemplary embodiment.

[0040] Fig. 9 yes Figure 8 A local enlarged view of area Q1.

[0041] Fig.10 is a top view of a pixel according to another exemplary embodiment.

[0042] Fig.11 is along Fig.10 A cross-sectional view taken along line BB'. DETAILED DESCRIPTION

[0043] Hereinafter, exemplary embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always represent the same elements. However, the present invention may be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that this disclosure will be thorough and complete, and the aspects and features of the present invention will be fully conveyed to those skilled in the art. Therefore, processes, elements, and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present invention may not be described. Unless otherwise noted, the same reference numerals always represent the same elements in the drawings and written descriptions, and therefore, their descriptions may not be repeated.

[0044] In the accompanying drawings, for clarity, the relative sizes of elements, layers and regions may be exaggerated and / or simplified. For ease of explanation, spatially relative terms such as "under ... ", "under ... ", "under ... ", "above ... ", "on " may be used herein to describe the relationship between an element (or elements) or feature (or features) and other elements (or elements) or features (or features) as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, spatially relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figure is flipped, the element described as "under" or "below" or "below" or "below" other elements or features will be oriented to "above" the other elements or features. Therefore, the exemplary terms "under ... " and "under ... " may include "above ... " and "below ... " two orientations. The device may be oriented in addition (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0045] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the spirit and scope of the present invention, the first element, first component, first region, first layer or first section described below may be named as the second element, second component, second region, second layer or second section.

[0046] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. Additionally, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0047] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "an" are also intended to include plural forms. It will also be understood that when the terms "comprises", "comprising", "includes" and "including", "has", "have" and "having" are used in this specification, the existence of the features, wholes, steps, operations, elements and / or components described are explained, but the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups is not excluded. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. When a statement such as "at least one of..." is placed after a list of elements, the entire list of elements is modified without modifying the individual elements of the list.

[0048] As used herein, the terms "substantially", "about" and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for inherent deviations in measurements or calculations that will be recognized by those of ordinary skill in the art. In addition, "may" when used in describing embodiments of the present invention means "one or more embodiments of the present invention". As used herein, the terms "use", "using" and "used" may be considered synonymous with the terms "utilize", "utilizing" and "utilized", respectively. In addition, the term "exemplary" is intended to mean an example or illustration.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of this specification and / or related art, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0050] Figure 1A and Figure 1B are a perspective view and a cross-sectional view respectively showing a light emitting element according to an exemplary embodiment. Figure 2A and Figure 2B are a perspective view and a cross-sectional view respectively showing a light emitting element according to another exemplary embodiment. Figure 1A and Figure 1B An example of a light emitting element LD having a core-shell structure is shown, and Figure 2A and Figure 2B An example of the light emitting element LD having a columnar rod-shaped structure is shown, but the kind and / or shape of the light emitting element LD according to the exemplary embodiment of the present invention is not limited thereto.

[0051] refer to Figure 1A and Figure 1B , the light emitting element LD according to the exemplary embodiment includes a first conductive semiconductor layer 11, a second conductive semiconductor layer 13, and an active layer 12 disposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. According to the exemplary embodiment, the first conductive semiconductor layer 11 may be disposed at a central region (e.g., in the middle or on) of the light emitting element LD, and the active layer 12 may be disposed on a surface of the first conductive semiconductor layer 11 to surround at least one region of the first conductive semiconductor layer 11. The second conductive semiconductor layer 13 may be disposed on a surface of the active layer 12 to surround at least one region of the active layer 12.

[0052] In some embodiments, the light emitting element LD may further include an electrode layer 14 and / or an insulating film INF surrounding at least one region of the second conductive semiconductor layer 13. For example, the light emitting element LD may include an electrode layer 14 disposed on the surface of the second conductive semiconductor layer 13 to surround a region of the second conductive semiconductor layer 13, and the insulating film INF may be disposed on the surface of the electrode layer 14 to surround at least one region of the electrode layer 14. In other words, the light emitting element LD according to the exemplary embodiment described above may be implemented with a core-shell structure including a first conductive semiconductor layer 11, an active layer 12, a second conductive semiconductor layer 13, an electrode layer 14, and an insulating film INF disposed in sequence from the middle of the light emitting element LD to the outside of the light emitting element LD. However, the present invention is not limited thereto, and in some embodiments, the electrode layer 14 and / or the insulating film INF may be omitted.

[0053] In an exemplary embodiment, the light emitting element LD may have a light emitting diode in one direction (eg, a first direction (eg, Figure 5 The light emitting element LD may have a polygonal cone shape extending in the direction of the light emitting element LD ("DR1" in the drawing) or in the extension direction). For example, at least one region of the light emitting element LD may have a hexagonal cone shape. However, the shape of the light emitting element LD is not limited thereto and may be variously changed.

[0054] When the extension direction (e.g., the first direction) of the light emitting element LD corresponds to the direction of the length LDL, the light emitting element LD may have one end (e.g., the first end) and the other end (e.g., the opposite end, the other end, or the second end) in the direction of the length LDL. According to an exemplary embodiment, one of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed at one end of the light emitting element LD, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed at the other end of the light emitting element LD.

[0055] In an exemplary embodiment of the present invention, the light emitting element LD may be an ultra-small light emitting diode having a core-shell structure and a polygonal columnar shape (e.g., a hexagonal cone-shaped shape with protruding ends). For example, the light emitting element LD may have a size as small as nanometer to micrometer. For example, the light emitting element LD may have a width and / or length LDL in the nanometer range or the micrometer range. However, the size and / or shape of the light emitting element LD may be changed differently according to the design specifications (or conditions) of various devices (e.g., such as display devices) using the light emitting element LD as a light source.

[0056] In an exemplary embodiment, the opposite end of the first conductive semiconductor layer 11 may have a protruding shape in the direction of the length LDL of the light emitting element LD. The protruding shapes of the opposite ends of the first conductive semiconductor layer 11 may be different from each other. For example, one end disposed at the upper side of the opposite end of the first conductive semiconductor layer 11 may have a conical shape that tapers toward the upper side to one vertex. The other end disposed at the lower side of the opposite end of the first conductive semiconductor layer 11 may have a polygonal columnar shape having a width (e.g., a predetermined width), but the present invention is not limited thereto. For example, in another exemplary embodiment of the present invention, the first conductive semiconductor layer 11 may have a polygonal shape that gradually narrows in width toward the lower side or has a step cross-section. However, the present invention is not limited thereto, and in other embodiments, the shapes of the opposite ends of the first conductive semiconductor layer 11 may be variously modified.

[0057] According to an exemplary embodiment, the first conductive semiconductor layer 11 may be disposed at the core (e.g., the middle or central region) of the light emitting element LD. In some embodiments, the light emitting element LD may be disposed in a shape corresponding to the shape of the first conductive semiconductor layer 11. For example, when the first conductive semiconductor layer 11 has a hexagonal cone shape, the light emitting element LD may have a hexagonal cone shape.

[0058] In some embodiments, the first conductive semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include at least one semiconductor material such as, for example, InAlGaN, GaN, AlGaN, InGaN, AlN and / or InN, and may include an n-type semiconductor layer doped with a first conductive dopant such as, for example, Si, Ge, Sn, etc. However, the present invention is not limited to the materials provided above, and the first conductive semiconductor layer 11 may be formed of various suitable materials.

[0059] The active layer 12 may be disposed and / or formed to surround the outer peripheral surface of the first conductive semiconductor layer 11 along the direction of the length LDL of the light emitting element LD. For example, the active layer 12 may be disposed and / or formed to surround a region (e.g., a remaining region) of the first conductive semiconductor layer 11 except for the other end at the lower end of the opposite ends of the first conductive semiconductor layer 11 disposed in the direction of the length LDL of the light emitting element LD.

[0060] The active layer 12 may be formed as a single quantum well structure or a multi-quantum well structure. In an exemplary embodiment, a cladding layer doped with a conductive dopant may be formed at an upper portion and / or a lower portion of the active layer 12. For example, the cladding layer may include an AlGaN layer and / or an InAlGaN layer (or may be formed of an AlGaN layer and / or an InAlGaN layer). According to an exemplary embodiment, materials such as AlGaN, AlInGaN, etc. may be used to form the active layer 12, and / or the active layer 12 may include various suitable materials.

[0061] When a voltage greater than or equal to the threshold voltage is applied to opposite ends of the light emitting element LD, the light emitting element LD emits light when electron-hole pairs are coupled in the active layer 12. Therefore, the emission of the light emitting element LD can be controlled so that the light emitting element LD can be used as a light source of various light emitting devices, such as a pixel of a display device, for example.

[0062] The second conductive semiconductor layer 13 may be provided and / or formed to surround the active layer 12 of the light emitting element LD. The second conductive semiconductor layer 13 may include a semiconductor layer different (e.g., a different type) from the semiconductor layer of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one semiconductor material such as, for example, InAlGaN, GaN, AlGaN, InGaN, AlN and / or InN, and may include a p-type semiconductor layer doped with a second conductive dopant such as, for example, Mg. However, the present invention is not limited thereto, and in other embodiments, the second conductive semiconductor layer 13 may be formed of various suitable materials.

[0063] In an exemplary embodiment, the light emitting element LD includes an electrode layer 14 surrounding at least one side of the second conductive semiconductor layer 13. The electrode layer 14 may be an ohmic contact electrode electrically connected to the second conductive semiconductor layer 13, but the present invention is not limited thereto. In some embodiments, the electrode layer 14 may include a metal or a metal oxide. For example, the electrode layer 14 may include (or be formed by) transparent electrode materials such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc., alone or in any suitable combination. In some embodiments, the electrode layer 14 may be transparent, substantially transparent or translucent. Therefore, the light generated from the light emitting element LD may be transmitted through the electrode layer 14 and may be emitted to the outside of the light emitting element LD.

[0064] The light emitting element LD may further include an insulating film INF disposed on a surface thereof. The insulating film INF may include a transparent insulating material. According to an exemplary embodiment, the insulating film INF may include a silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ) and / or titanium oxide (TiO 2 ), but the present invention is not limited thereto.

[0065] The insulating film INF may be provided to overlap (or cover) a portion of the outer peripheral surface of the first conductive semiconductor layer 11 and the outer peripheral surface of the electrode layer 14. In an exemplary embodiment, the insulating film INF may be formed to cover the entire outer peripheral surface of the electrode layer 14, and then the insulating film INF may be partially removed to expose a portion of the electrode layer 14 for contact with an electrode (e.g., a pixel (e.g., Figure 5 The first electrode (eg, Figure 5 "ELT1" in the figure is electrically connected.

[0066] The light emitting device including the light emitting element LD described above can be used in various devices using a light source. For example, the light emitting device can be used in various electronic devices using a light source, such as a display device or a lighting device, for example.

[0067] Figure 2A and Figure 2B Shows that with Figure 1A and Figure 1B The structure of the light emitting element LD shown in FIG. 1 is different from the structure of the light emitting element LD. For example, Figure 2A and Figure 2B The light emitting element LD is shown to have a columnar rod-shaped structure. That is, the type, structure, shape, etc. of the light emitting element LD according to the exemplary embodiment of the present invention may be variously modified. Figure 2A and Figure 2B In the exemplary embodiment shown in FIG. 1 , the same reference numerals are used for Figure 1A and Figure 1B Similar or identical constituent elements (eg, corresponding constituent elements) to the exemplary embodiments shown in FIG. 1 and FIG. 2 are similar to or identical to the exemplary embodiments shown in FIG. 1 and FIG. 3 (eg, corresponding constituent elements), and thus, repeated description thereof may be omitted.

[0068] refer to Figure 2A and Figure 2B , the light emitting element LD according to the exemplary embodiment of the present invention includes a first conductive semiconductor layer 11, a second conductive semiconductor layer 13, and an active layer 12 disposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. For example, the light emitting element LD may be formed of a stack in which the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13, and the electrode layer 14 are sequentially stacked.

[0069] One of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed at one end of the light emitting element LD, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed at the other end of the light emitting element LD. In addition, the light emitting element LD may include an electrode layer 14 disposed on one end of the second conductive semiconductor layer 13.

[0070] In some embodiments, the light emitting element LD may further include an insulating film INF disposed on a surface of the light emitting element LD. The insulating film INF may be formed on the surface of the light emitting element LD to surround the outer peripheral surface of the active layer 12, and may also surround a portion of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. The insulating film INF may expose opposite ends of the light emitting element LD having different polarities.

[0071] The light emitting element LD may include a rod-shaped light emitting diode having a rod shape. As used in this specification, "rod-shaped" or "rod-shaped" refers to a rod-shaped or bar-shaped shape that is longer in the length direction than in the width direction (e.g., having an aspect ratio greater than 1), such as a cylindrical shape or a polygonal columnar shape, and the shape of its cross section is not particularly limited. For example, in the cross section of the light emitting element LD, the length of the light emitting element LD may be greater than the width (e.g., diameter).

[0072] Figure 3 is a top plan view showing a display device according to an exemplary embodiment of the present invention. Figure 3A display device including a display panel PNL according to an exemplary embodiment is shown as a display device that can use a light emitting element LD (eg, Figures 1A to 2B For example, each pixel unit in the display panel PNL and each pixel PXL included in the pixel unit may include a plurality of light emitting elements LD.

[0073] For ease of explanation, Figure 3 The display area DA in FIG. 1 schematically shows the structure of the display panel PNL correspondingly. However, the display panel PNL according to the exemplary embodiment may further include at least one driving circuit unit (eg, at least one of a scan driver and a data driver) and / or a plurality of lines.

[0074] refer to Figure 3 According to an exemplary embodiment of the present invention, the display panel PNL may include a base layer BSL and a plurality of pixels PXL disposed on the base layer BSL. According to an exemplary embodiment, the pixel PXL may include a first color pixel, a second color pixel, and / or a third color pixel. Hereinafter, the term "pixel PXL" or "plurality of pixels PXL" used in this specification refers to at least one pixel among the first color pixel, the second color pixel, and the third color pixel, or is collectively referred to as two or more kinds of pixels.

[0075] In more detail, the display panel PNL and the base layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA excluding the display area DA. The pixels PXL may be disposed in the display area DA on the base layer BSL.

[0076] The base layer BSL may form a base member of the display panel PNL. According to an exemplary embodiment, the base layer BSL may be a hard substrate or film or a flexible substrate or film, and its material and properties are not particularly limited. For example, the base layer BSL may be a hard substrate formed of glass or tempered glass, a flexible substrate (or film) formed of a plastic or metal material or at least one insulating layer, and its material and properties are not particularly limited.

[0077] In some embodiments, the base layer BSL may be transparent, but the present invention is not limited thereto. For example, the base layer BSL may include a transparent, translucent, opaque, or reflective base member.

[0078] An area on the base layer BSL in which the pixels PXL are disposed is defined as a display area DA, and another area on the base layer BSL is defined as a non-display area NDA. For example, the base layer BSL may include a display area DA and a non-display area NDA, wherein the display area DA includes a plurality of pixel areas forming each pixel PXL, and the non-display area NDA is disposed adjacent to the display area DA (e.g., disposed around the periphery of the display area DA). Various lines and / or internal circuit units connected to the pixels PXL of the display area DA may be disposed in the non-display area NDA.

[0079] The plurality of pixels PXL may be dispersed at (e.g., in or above) the display area DA. For example, according to a stripe or pentile array structure, the plurality of pixels PXL may be regularly arranged at (e.g., in or above) the display area DA. However, the present invention is not limited thereto, and the pixels PXL may be arranged at (e.g., in or above) the display area DA in various suitable structures and / or arrangements.

[0080] According to an exemplary embodiment, two or more pixels PXL emitting light of different colors may be provided in the display area DA. For example, a first color pixel emitting a first color light, a second color pixel emitting a second color light, and a third color pixel emitting a third color light may be provided in the display area DA. At least one of the first color pixel, the second color pixel, and the third color pixel, which may be provided adjacent to each other, may form a pixel unit emitting light of various colors.

[0081] The color, type, and / or number of the pixels PXL constituting each pixel unit are not limited thereto. For example, the color of light emitted by each pixel PXL may be variously modified.

[0082] Each pixel PXL may include a control signal (eg, a scan signal and a data signal) and / or a power source (eg, a first power source (eg, FIG. 4A to FIG. 4C "VDD" in the figure) and a second power supply (e.g., FIG. 4A to FIG. 4C For example, each pixel PXL may include at least one ultra-small light emitting element LD having a size as small as nanometer to micrometer. For example, each pixel PXL may include a first pixel electrode and a second pixel electrode and / or a first power line (e.g., FIG. 4A to FIG. 4C ”PL1” in the figure) and a second power line (eg, FIG. 4A to FIG. 4C ” PL2 ” in FIG. 1 ) to form a plurality of ultra-small light-emitting elements LD connected in series and / or in parallel to form a light source or light source unit (eg, FIG. 4A to FIG. 4C ” in the .

[0083] In an exemplary embodiment, each pixel PXL may be formed of one or more active pixels. However, the type, structure and / or driving method of the pixel PXL applicable to the display device of the present invention are not limited thereto. For example, each pixel PXL may be formed of one or more pixels of a light-emitting display device having a passive or active structure of various suitable types.

[0084] FIG. 4A to FIG. 4C is a circuit diagram showing a pixel according to various exemplary embodiments. According to an exemplary embodiment, FIG. 4A to FIG. 4C Each pixel PXL shown in FIG. 1 may be a display panel PNL (eg, see Figure 3 ). In some embodiments, the first color pixel, the second color pixel, and the third color pixel may have structures that are the same or substantially the same (or similar) as each other.

[0085] refer to Figure 4A According to an exemplary embodiment of the present invention, the pixel PXL includes a light source unit (eg, light source) LSU for generating light having brightness corresponding to a data signal. In some embodiments, the pixel PXL may include a pixel circuit PXC for driving the light source unit LSU.

[0086] According to an exemplary embodiment, the light source unit LSU may include a plurality of light emitting elements LD electrically connected between a first power source VDD and a second power source VSS. In an exemplary embodiment, the light emitting elements LD may be connected in parallel to each other, but the present invention is not limited thereto. For example, in another exemplary embodiment, the plurality of light emitting elements LD may be connected in series and / or in parallel in a hybrid structure between the first power source VDD and the second power source VSS.

[0087] According to an exemplary embodiment, the first power supply VDD and the second power supply VSS may have different potentials so that the light emitting element LD can emit light. For example, the first power supply VDD may include (e.g., be set to) a high potential power supply, and the second power supply VSS may include (e.g., be set to) a low potential power supply. In some embodiments, for example, at least during the light emitting period of the pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS may be greater than or equal to the threshold voltage of the light emitting element LD.

[0088] although Figure 4A It is shown that the light emitting elements LD of the light source unit LSU of each pixel PXL are connected in parallel in the same direction (eg, in a forward direction) between the first power source VDD and the second power source VSS, but the present invention is not limited thereto.

[0089] According to an exemplary embodiment, one end of the light emitting element LD included in each light source unit LSU may be connected to the light source unit LSU through an electrode (eg, one electrode) (eg, a first electrode (eg, Figure 5 ”ELT1” in ) and / or the first contact electrode (e.g., Figure 5 The other end of the light emitting element LD can be connected to the pixel circuit PXC through another electrode of the light source unit LSU (for example, the second electrode of each pixel PXL (for example, Figure 5 ”ELT2” in ) and / or a second contact electrode (e.g., Figure 5 The “CNE2” in the figure) and the second power line PL2 are commonly connected to the second power source VSS.

[0090] Each light source unit LSU may emit light having brightness corresponding to a driving current supplied through a corresponding pixel circuit PXC. Thus, an image (eg, a predetermined image) may be displayed at (eg, in the middle or on) the display area DA.

[0091] The pixel circuit PXC may be connected to a scan line (e.g., an i-th scan line Si) and a data line (e.g., a j-th data line Dj) of a corresponding pixel PXL. For example, when the pixel PXL is disposed at an i-th (i is a natural number) row and a j-th (j is a natural number) column of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to an i-th scan line Si and a j-th data line Dj in the display area DA. According to an exemplary embodiment, the pixel circuit PXC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst.

[0092] The first transistor (or driving transistor) T1 is connected between the first power source VDD and the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 controls a driving current supplied to the light source unit LSU in response to a voltage of the first node N1.

[0093] The second transistor (or switching transistor) T2 is connected between the j-th data line Dj and the first node N1. The gate electrode of the second transistor T2 is connected to the i-th scan line Si. The second transistor T2 is turned on when a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the i-th scan line Si to electrically connect the j-th data line Dj to the first node N1.

[0094] During each frame period, a data signal of a corresponding frame is supplied to the j-th data line Dj, and the data signal is transmitted to the first node N1 via the second transistor T2. Therefore, a voltage corresponding to the data signal is charged to the storage capacitor Cst.

[0095] One electrode of the storage capacitor Cst is connected to the first power source VDD, and the other electrode of the storage capacitor Cst is connected to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to a data signal supplied to the first node N1 during each frame period.

[0096] Although the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are Figure 4A , but the present invention is not limited thereto. For example, in another exemplary embodiment, at least one of the first transistor T1 and the second transistor T2 may be modified to include an N-type transistor.

[0097] For example, Figure 4B As shown in , each of the first transistor T1 and the second transistor T2 may include an N-type transistor. In this case, the gate-on voltage of the scanning signal for writing the data signal supplied to the j-th data line Dj into the pixel PXL during each frame period may be a high-level voltage. Similarly, the voltage of the data signal for turning on the first transistor T1 may be a voltage having a voltage with a value similar to that of the gate-on voltage. Figure 4A The voltage of the waveform opposite to the voltage of the data signal used to turn on the first transistor T1 in the exemplary embodiment of the present invention. Figure 4B In an exemplary embodiment of the present invention, the larger the grayscale value to be represented, the higher the voltage level of the provided data signal.

[0098] In addition to modifying the connection positions of some circuit elements and the voltage levels of control signals (eg, scan signals and data signals) corresponding to the modified types of transistors (eg, T1 and T2), Figure 4B The configuration and operation of the pixel PXL shown in FIG. 1 are substantially similar to those of FIG. Figure 4A Therefore, the configuration and operation of the pixel PXL shown in FIG. Figure 4B Repeated description of the pixel PXL.

[0099] The structure of the pixel circuit PXC is not limited to Figure 4A and Figure 4B In other embodiments, the pixel circuit PXC may be formed by pixel circuits of various suitable structures and / or driving methods. For example, the pixel circuit PXC may have Figure 4C The structure shown in the exemplary embodiment of FIG.

[0100] refer to Figure 4C, in addition to being connected to the i-th scan line Si of the corresponding horizontal line (or row), the pixel circuit PXC may also be connected to at least one other scan line (or control line). For example, the pixel circuit PXC of the pixel PXL arranged in the i-th row of the display area DA may also be connected to the i-1-th scan line Si-1 and / or the i+1-th scan line Si+1. In some embodiments, in addition to the first power supply VDD and the second power supply VSS, the pixel circuit PXC may also be connected to a third power supply. For example, the pixel circuit PXC may also be connected to an initialization power supply Vint. According to an exemplary embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0101] The first transistor T1 is connected between the first power source VDD and the light source unit LSU. For example, one electrode (e.g., source electrode) of the first transistor T1 may be connected to the first power source VDD through the fifth transistor T5 and the first power line PL1, and the other electrode (e.g., drain electrode) of the first transistor T1 may be connected to one electrode of the light source unit LSU (e.g., first electrode of the corresponding pixel PXL) via the sixth transistor T6. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 controls the driving current provided to the light source unit LSU in response to the voltage of the first node N1.

[0102] The second transistor T2 is connected between the j-th data line Dj and one electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the corresponding scan line (for example, the i-th scan line Si). The second transistor T2 is turned on when a scan signal having a gate-on voltage is provided from the i-th scan line Si to electrically connect the j-th data line Dj to one electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal provided from the j-th data line Dj is transmitted to the first transistor T1.

[0103] The third transistor T3 is connected between the other electrode (e.g., drain electrode) of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the corresponding scan line (e.g., the i-th scan line Si). The third transistor T3 is turned on when a scan signal having a gate-on voltage is provided from the i-th scan line Si, thereby connecting (e.g., diode-connecting) the first transistor T1 in a diode form.

[0104] The fourth transistor T4 is connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the i-1th scan line Si-1. When the scan signal having the gate-on voltage is supplied to the i-1th scan line Si-1, the fourth transistor T4 is turned on to transmit the voltage of the initialization power supply Vint to the first node N1. According to an exemplary embodiment, the voltage of the initialization power supply Vint for initializing the gate voltage of the first transistor T1 may have a voltage level less than or equal to the lowest voltage level of the data signal.

[0105] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 is turned off when an emission control signal having a gate cut-off voltage (for example, a high level voltage) is provided to the i-th emission control line Ei, and is turned on in other cases.

[0106] The sixth transistor T6 is connected between the first transistor T1 and the light source unit LSU (or the second node N2). The gate electrode of the sixth transistor T6 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. The sixth transistor T6 is turned off when the emission control signal having the gate-off voltage is supplied to the i-th emission control line Ei, and is turned on in other cases.

[0107] The seventh transistor T7 is connected between one electrode of the light source unit LSU (e.g., the first electrode of the corresponding pixel PXL) (or the second node N2) and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to one of the scan lines of the next stage, for example, the i+1th scan line Si+1. The seventh transistor T7 is turned on when a scan signal having a gate-on voltage is supplied to the i+1th scan line Si+1 to supply the voltage of the initialization power supply Vint to one electrode of the light source unit LSU. Therefore, during each initialization period (during which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU), the voltage of one electrode of the light source unit LSU is initialized. However, the present invention is not limited thereto, and in other embodiments, various modifications may be made to the control signal for controlling the operation of the seventh transistor T7. For example, in another exemplary embodiment, the gate electrode of the seventh transistor T7 may be connected to a scan line of a corresponding horizontal line (e.g., a corresponding row), for example, the i-th scan line Si. In this case, the seventh transistor T7 is turned on when a scan signal having a gate-on voltage is supplied to the i-th scan line Si to supply the voltage of the initialization power source Vint to one electrode of the light source unit LSU.

[0108] The storage capacitor Cst is connected between the first power source VDD and the first node N1. The storage capacitor Cst stores a voltage corresponding to the data signal supplied to the first node N1 and the threshold voltage of the first transistor T1 during each frame period.

[0109] Although Figure 4C The transistors (eg, T1 to T7) included in the pixel circuit PXC are shown as P-type transistors, but the present invention is not limited thereto. For example, in another embodiment, at least one of the first to seventh transistors T1 to T7 may be modified to include an N-type transistor.

[0110] However, the present invention is not limited to FIG. 4A to FIG. 4C The structure of the pixel PXL is shown in the exemplary embodiment of FIG. 1 , and in other embodiments, each pixel PXL may have various suitable structures.

[0111] Figure 5 is a top view showing a pixel according to an exemplary embodiment. According to an exemplary embodiment, each pixel PXL may have FIG. 4A to FIG. 4C The structure of any one of the pixels PXL shown in FIG. 1 is the same or substantially the same as the structure of any one of the pixels PXL shown in FIG. 1 , but the present invention is not limited thereto.

[0112] For ease of explanation, Figure 5 FIG. 4 shows a structure of each pixel PXL relative to the light source unit LSU. However, the pixel PXL may further include a circuit element for controlling each light source unit LSU (for example, including FIG. 4A to FIG. 4C According to an exemplary embodiment, the circuit element may be disposed on a layer different from the layer of the light source unit LSU. For example, the circuit element may be disposed on a pixel circuit layer (eg, Figure 6 ” PCL” in the figure), wherein the pixel circuit layer is disposed on one side of the base layer BSL, and the light source unit LSU may be disposed on the display element layer (eg, Figure 6 The display element layer is arranged on the pixel circuit layer.

[0113] In some embodiments, Figure 5As shown in the exemplary embodiment of , each light source unit LSU is connected to a power line (e.g., a first power line PL1 and / or a second power line PL2), a circuit element (e.g., at least one circuit element included in the pixel circuit PXC) and / or a signal line (e.g., a scan line and / or a data line) through a first contact hole CH1 and a second contact hole CH2. In an exemplary embodiment of the present invention, at least one of the first electrode ELT1 and the second electrode ELT2 of each pixel PXL may be directly connected to a power line (e.g., a predetermined power line) and / or a signal line without passing through a contact hole, without an intermediate line, etc.

[0114] refer to Figure 5 , a pixel PXL according to an exemplary embodiment of the present invention may include a plurality of light emitting elements LD and an electrode included in each of the light source units LSU. For example, the pixel PXL may include a first electrode ELT1 and a second electrode ELT2, and the first electrode ELT1 and the second electrode ELT2 are disposed to be spaced apart from each other in each pixel region. A plurality of light emitting elements LD may be disposed between the first electrode ELT1 and the second electrode ELT2. A first contact electrode CNE1 and a second contact electrode CNE2 may be disposed on the first electrode ELT1 and the second electrode ELT2, respectively. Similar to the first electrode ELT1 and the second electrode ELT2, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed to be spaced apart from each other in each pixel region, so that the first end EP1 and the second end EP2 of the light emitting element LD may be connected to the first electrode ELT1 and the second electrode ELT2, respectively.

[0115] The first electrode ELT1 and the second electrode ELT2 may be arranged to be spaced apart from each other in a pixel region (e.g., an emission region EMA of a corresponding pixel PXL) that provides and / or forms each pixel PXL. According to an exemplary embodiment, each pixel region used in this specification may refer to a region in which a circuit element and / or a light source unit LSU included in the corresponding pixel PXL is arranged. The emission region EMA may refer to a region in which a light emitting element LD (e.g., an effective light source completely connected between the first electrode ELT1 and the second electrode ELT2) included in the light source unit LSU of each pixel PXL is arranged. In some embodiments, the first contact electrode CNE1 and the second contact electrode CNE2, the electrodes connected to the light emitting element LD (e.g., the first electrode ELT1 and the second electrode ELT2), and / or a portion thereof may be arranged in the emission region EMA. The emission region EMA may be surrounded by a light blocking and / or reflective dam structure (or a pixel defining layer) formed between the pixels PXL for defining each pixel region and the emission region EMA therein. For example, a dam structure surrounding the emission region EMA may be arranged around the emission region EMA.

[0116] The first electrode ELT1 and the second electrode ELT2 may be disposed to be spaced apart from each other. For example, the first electrode ELT1 and the second electrode ELT2 may be disposed parallel to each other at a certain distance (eg, a predetermined distance) at each emission area EMA (eg, middle or upper) in the first direction DR1.

[0117] In an exemplary embodiment, the first electrode ELT1 and the second electrode ELT2 may have a rod shape extending in one direction. For example, each of the first electrode ELT1 and the second electrode ELT2 may have a rod shape extending in a second direction DR2 that crosses (e.g., crosses orthogonally) the first direction DR1. However, the present invention is not limited thereto, and the shapes, arrangement directions, and / or mutual arrangement relationships of the first electrode ELT1 and the second electrode ELT2 may be variously changed.

[0118] In some embodiments, at least one of the first electrode ELT1 and the second electrode ELT2 may be disposed in each pixel region, and the number of the first electrode ELT1 and the second electrode ELT2 disposed in each pixel region is not particularly limited. For example, a plurality of first electrodes ELT1 extending in the second direction DR2 and arranged parallel to each other may be disposed in each pixel region.

[0119] In some embodiments, at least one second electrode ELT2 facing each first electrode ELT1 may be provided in each pixel region. For example, in each pixel region, one second electrode ELT2 may be provided between two first electrodes ELT1, or a plurality of second electrodes ELT2 corresponding to each of a plurality of first electrodes ELT1 may be provided.

[0120] According to an exemplary embodiment, the first electrode ELT1 may be connected to a circuit element (e.g., at least one transistor included in the pixel circuit PXC), a power line (e.g., a first power line PL1) and / or a signal line (e.g., a scan line, a data line, or a control line) through a first connection electrode CNT1 and / or a first contact hole CH1. In an exemplary embodiment, the first electrode ELT1 may be electrically connected to a circuit element (e.g., a predetermined circuit element) disposed below (e.g., below) the first electrode ELT1 through the first connection electrode CNT1 and the first contact hole CH1, and may be electrically connected to the first line through the circuit element. The first line may include a first power line PL1 for providing a first power supply VDD, but the present invention is not limited thereto. For example, in another exemplary embodiment, the first line may include a signal line to which a first drive signal (e.g., a scan signal, a data signal, or a control signal) is provided.

[0121] In another exemplary embodiment, the first electrode ELT1 may be directly connected to the power line (e.g., a predetermined power line) or the signal line without passing through the first connection electrode CNT1, the first contact hole CH1, and / or the circuit element. In this case, the first electrode ELT1 may be connected to the power line (e.g., a predetermined power line) or the signal line in whole or in part.

[0122] According to example embodiments, the first electrode ELT1 and the first connection electrode CNT1 may extend in different directions in each pixel region. For example, when the first connection electrode CNT1 extends in a first direction DR1, the first electrode ELT1 may extend in a second direction DR2 crossing the first direction DR1.

[0123] In an exemplary embodiment, the first electrode ELT1 and the first connection electrode CNT1 may be integrally connected to each other. For example, the first electrode ELT1 may be formed by branching at least one branch from the first connection electrode CNT1. When the first electrode ELT1 and the first connection electrode CNT1 are integrally connected to each other, the first connection electrode CNT1 may be considered as a part of the first electrode ELT1. However, the present invention is not limited thereto.

[0124] According to an exemplary embodiment, the second electrode ELT2 may be connected to a circuit element (e.g., at least one transistor included in the pixel circuit PXC), a power line (e.g., a second power line PL2) and / or a signal line (e.g., a scan line, a data line, or a control line) through the second connection electrode CNT2 and / or the second contact hole CH2. For example, the second electrode ELT2 may be electrically connected to a second power line PL2 disposed below (e.g., below) the second electrode ELT2 through the second connection electrode CNT2 and the second contact hole CH2. In another exemplary embodiment, the second electrode ELT2 may be directly connected to a power line (e.g., a predetermined power line) or a signal line without passing through the second connection electrode CNT2 and / or the second contact hole CH2. In this case, the second electrode ELT2 may be connected to the power line or the signal line as a whole or non-as a whole.

[0125] According to example embodiments, the second electrode ELT2 and the second connection electrode CNT2 may extend in different directions. For example, when the second connection electrode CNT2 extends in the first direction DR1, the second electrode ELT2 may extend in the second direction DR2 crossing the first direction DR1.

[0126] In an exemplary embodiment, the second electrode ELT2 and the second connection electrode CNT2 may be integrally connected to each other. For example, the second electrode ELT2 may be formed by branching at least one branch from the second connection electrode CNT2. When the second electrode ELT2 and the second connection electrode CNT2 are integrally connected to each other, the second connection electrode CNT2 may be considered as a part of the second electrode ELT2. However, the present invention is not limited thereto.

[0127] In the alignment step of the light emitting element LD, an alignment signal (e.g., a predetermined alignment signal) is applied between the first electrode ELT1 and the second electrode ELT2, so that an electric field can be formed between the first electrode ELT1 and the second electrode ELT2. As a result of the electric field, the light emitting element LD of each pixel area (e.g., the emission area EMA of each pixel PXL) can be aligned between the first electrode ELT1 and the second electrode ELT2.

[0128] A plurality of light emitting elements LD may be disposed between the first electrode ELT1 and the second electrode ELT2. Each of the light emitting elements LD may be electrically connected between the corresponding first electrode ELT1 and the second electrode ELT2.

[0129] Each of the light emitting elements LD may include a first end portion EP1 and a second end portion EP2, wherein the first end portion EP1 is disposed at one end (e.g., on) in the direction of the length LDL and is electrically connected to the first electrode ELT1, and the second end portion EP2 is disposed at the other end (e.g., the opposite end) in the direction of the length LDL (e.g., on) and is electrically connected to the second electrode ELT2. For example, each of the light emitting elements LD may be disposed laterally between the first electrode ELT1 and the second electrode ELT2 along the first direction DR1 at a region (e.g., in the middle or on) corresponding to the first electrode ELT1 and the second electrode ELT2 being disposed facing each other.

[0130] Although Figure 5 The light emitting elements LD are shown to be uniformly arranged in one direction (eg, the first direction DR1 ), but the present invention is not limited thereto. For example, at least one of the light emitting elements LD may be arranged between the first electrode ELT1 and the second electrode ELT2 in an oblique direction.

[0131] According to an exemplary embodiment, the light emitting element LD may be prepared in a solution (e.g., a predetermined solution) in a dispersed form, and may be provided to each pixel region (e.g., an emission region EMA of each pixel PXL) using an inkjet method or the like. For example, the light emitting element LD may be mixed with a volatile solvent and provided to each emission region EMA. In this case, when an alignment voltage (e.g., a predetermined alignment voltage) or an alignment signal is applied to the first electrode ELT1 and the second electrode ELT2, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, and the light emitting element LD is aligned between the first electrode ELT1 and the second electrode ELT2. After aligning the light emitting element LD, the solvent may be volatilized or removed to stably dispose the light emitting element LD between the first electrode ELT1 and the second electrode ELT2. In some embodiments, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed at opposite ends (e.g., on) of the light emitting element LD. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed at the first end EP1 and the second end EP2 of the light emitting element LD, respectively. Therefore, the light emitting element LD can be more stably connected between the first electrode ELT1 and the second electrode ELT2.

[0132] The first end EP1 of the light emitting element LD may be electrically connected to the first power source VDD via the first contact electrode CNE1, the first electrode ELT1, the pixel circuit PXC and / or the first power line PL1. The second end EP2 of the light emitting element LD may be electrically connected to the second power source VSS via the second contact electrode CNE2, the second electrode ELT2 and / or the second power line PL2. Therefore, at least one of the light emitting elements LD connected between the first electrode ELT1 and the second electrode ELT2 in the forward direction may emit light with a brightness corresponding to the driving current provided from the pixel circuit PXC and the like. Therefore, the pixel PXL emits light corresponding to the driving current.

[0133] The first end EP1 and the second end EP2 of at least one of the light emitting elements LD arranged between the first electrode ELT1 and the second electrode ELT2 of each pixel PXL may be electrically connected to the first electrode ELT1 and the second electrode ELT2, respectively. For example, the first end EP1 and the second end EP2 of at least one of the light emitting elements LD may be electrically connected to the first electrode ELT1 and the second electrode ELT2, respectively, through the first contact electrode CNE1 and the second contact electrode CNE2.

[0134] The first contact electrode CNE1 may be disposed on the first electrode ELT1 to overlap with the first electrode ELT1. The first contact electrode CNE1 may be electrically connected to each of the first electrodes ELT1 in at least one region. In addition, the second contact electrode CNE2 may be disposed on the second electrode ELT2 to overlap with the second electrode ELT2. The second contact electrode CNE2 may be electrically connected to the second electrode ELT2 in at least one region.

[0135] The pixel PXL may include a lens pattern unit (e.g., a lens pattern) LA having at least a portion overlapping each light emitting element LD. In some embodiments, the lens pattern unit LA may be formed to correspond to each light emitting element LD one by one, but the present invention is not limited thereto. For example, in other embodiments, a plurality of light emitting elements LD may correspond to one lens pattern unit (e.g., one lens pattern) LA.

[0136] The lens pattern unit LA may have a circular or elliptical shape in a plan view, but the present invention is not limited thereto. For example, in other embodiments, the lens pattern unit LA may have a triangular shape, a quadrilateral shape, or other polygonal shapes. In an exemplary embodiment, the lens pattern unit LA may have an elliptical shape, and the width in the first direction DR1 is greater than the width in the second direction DR2.

[0137] In an exemplary embodiment, the width (or diameter) D1 of the lens pattern unit LA may be smaller than the length LDL of the light emitting element LD, but the present invention is not limited thereto, and in another exemplary embodiment, the width D1 of the lens pattern unit LA may be greater than the length LDL of the light emitting element LD. For example, the width D1 of the lens pattern unit LA may be greater than or equal to twice the length LDL of the light emitting element LD.

[0138] The lens pattern unit LA may be disposed below (e.g., below) the light emitting element LD to reflect light emitted downward from the light emitting element LD upward. Therefore, in an exemplary embodiment, the lens pattern unit LA may improve the emission efficiency of a display device including the pixel PXL. According to an exemplary embodiment, the lens pattern unit LA may further include an uneven pattern (e.g., Figure 7B ”LAc” and “LAv” in FIG. 1 ). The uneven pattern of the lens pattern unit LA may reflect light irregularly incident on the lens pattern unit LA to the upper side. The viewing angle characteristics of a display device including the pixel PXL may be improved by the irregularly reflected light.

[0139] The lens pattern unit LA may be connected to a configuration of the pixel unit (eg, the second organic layer (eg, Figure 6 and Fig.11 "VIA2" in the Figure 8That is, a separate mask process for forming the lens pattern unit LA may not be used. Because the lens pattern unit LA may be formed via a parallel process, processing costs may be reduced and / or processing time may be shortened.

[0140] Figure 6 is along Figure 5 A cross-sectional view taken along the line A-A'. Figure 6 In an exemplary embodiment, one or more similar or identical or substantially identical constituent elements (e.g., corresponding constituent elements) as those in the exemplary embodiments described above are given the same reference marks, and thus, redundant descriptions thereof may be omitted.

[0141] refer to Figure 5 and Figure 6 According to an exemplary embodiment of the present invention, the pixel PXL includes a display element layer DPL disposed on one surface of the base layer BSL and including a plurality of light emitting elements LD. In addition, the pixel PXL may further include a pixel circuit layer PCL. For example, the pixel PXL may further include a pixel circuit layer PCL disposed between the base layer BSL and the display element layer DPL and including at least one circuit element electrically connected to the light emitting element LD.

[0142] According to an exemplary embodiment, the pixel circuit layer PCL may include at least one circuit element included in the pixel circuit PXC. For example, the pixel circuit layer PCL may include a plurality of transistors and storage capacitors (eg, FIG. 4A to FIG. 4C ”Cst” in the figure), and may also include at least one power line and / or signal line connected to the pixel circuit PXC and / or the light source unit LSU, etc.

[0143] The pixel circuit layer PCL may include a plurality of insulating layers disposed between each electrode and / or line. In an exemplary embodiment, the pixel circuit layer PCL may include a buffer layer BFL, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer ILD, a first organic layer VIA1, and a second organic layer VIA2 stacked (e.g., sequentially stacked) on one surface of the base layer BSL.

[0144] The buffer layer BFL may prevent or substantially prevent impurities from diffusing into each circuit element. The buffer layer BFL may be formed of a single layer, but the present invention is not limited thereto, and the buffer layer BFL may be formed of a plurality of layers to include at least two or more layers. When the buffer layer BFL is provided in a plurality of layers, each layer may be formed of the same or substantially the same material, or may be formed of different materials. However, the present invention is not limited thereto, and in another embodiment, the buffer layer BFL may be omitted.

[0145] Each transistor may include a semiconductor layer ACT, gate electrodes GT1 and GT2 , and transistor electrodes (eg, metal layers) SD11 , SD12 , and SD2 .

[0146] The semiconductor layer ACT may be disposed on the buffer layer BFL. For example, the semiconductor layer ACT may be disposed between the base layer BSL (eg, the base layer BSL on which the buffer layer BFL is formed) and the first gate insulating layer GI1. The semiconductor layer ACT may include a source region, a drain region, and a channel region disposed between the source region and the drain region.

[0147] According to example embodiments, the semiconductor layer ACT may include a semiconductor pattern including or formed of polycrystalline silicon, amorphous silicon, an oxide semiconductor, etc. In addition, a channel region of the semiconductor layer ACT may include a semiconductor pattern (e.g., an intrinsic semiconductor) not doped with impurities, and a source region and a drain region of the semiconductor layer ACT may each include a semiconductor pattern doped with impurities.

[0148] The first gate electrode GT1 may be disposed on the semiconductor layer ACT with the first gate insulating layer GI1 interposed therebetween. For example, the first gate electrode GT1 may be disposed between the first gate insulating layer GI1 and the second gate insulating layer GI2, and may overlap with at least one region of the semiconductor layer ACT. When the semiconductor layer ACT includes a plurality of channel regions, the first gate electrode GT1 disposed on the semiconductor layer ACT may be disposed in plurality to include at least one region overlapping each channel region.

[0149] The second gate electrode GT2 may be disposed on the first gate electrode GT1 with the second gate insulating layer GI2 interposed therebetween. For example, the second gate electrode GT2 may be disposed between the second gate insulating layer GI2 and the interlayer insulating layer ILD and may overlap at least one region of the first gate electrode GT1.

[0150] According to example embodiments, when a plurality of first gate electrodes GT1 are provided, the second gate electrode GT2 may be provided to overlap one of the first gate electrodes GT1 , and the second gate insulating layer GI2 may be provided to overlap all of the first gate electrodes GT1 .

[0151] The first metal layers SD11 and SD12 may be disposed on the semiconductor layer ACT and the gate electrodes GT1 and GT2, and at least one interlayer insulating layer ILD is interposed between the first metal layers SD11 and SD12 and the semiconductor layer ACT and the gate electrodes GT1 and GT2. For example, the first metal layers SD11 and SD12 may be disposed between the interlayer insulating layer ILD and the first organic layer VIA1.

[0152] The first metal layers SD11 and SD12 may be electrically connected to the semiconductor layer ACT or the gate electrodes GT1 and GT2. For example, one of the first metal layers SD11 and SD12 may be connected to the semiconductor layer ACT through a contact hole CT11 passing through the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD. The other first metal layer SD12 of the first metal layers SD11 and SD12 may also be connected to the second gate electrode GT2 through a contact hole CT12 passing through the interlayer insulating layer ILD.

[0153] The first organic layer VIA1 may be disposed on the first metal layers SD11 and SD12. The first organic layer VIA1 may include, for example, an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer (or be formed of an inorganic layer). However, the present invention is not limited thereto, and the first organic layer VIA1 may include, for example, an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. (or be formed of an organic layer).

[0154] The second metal layer SD2 may be disposed on the semiconductor layer ACT, the gate electrodes GT1 and GT2, and the first metal layers SD11 and SD12, and the first organic layer VIA1 is interposed between the second metal layer SD2 and the semiconductor layer ACT, the gate electrodes GT1 and GT2, and the first metal layers SD11 and SD12. For example, the second metal layer SD2 may be disposed between the first organic layer VIA1 and the second organic layer VIA2. The second metal layer SD2 may be electrically connected to the semiconductor layer ACT, the gate electrodes GT1 and GT2, and / or the first metal layers SD11 and SD12. For example, the second metal layer SD2 may be connected to the first metal layer SD11 through a contact hole CT2 passing through the first organic layer VIA1. The second metal layer SD2 may be disposed (e.g., completely disposed) on the first organic layer VIA1, and may then be patterned to be electrically connected to other layers.

[0155] The first metal layers SD11 and SD12 and the second metal layer SD2 may include at least one metal, such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti) and / or alloys thereof, but the present invention is not limited thereto.

[0156] The second organic layer VIA2 may be disposed on the second metal layer SD2. The second organic layer VIA2 may include, for example, an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer (or be formed of an inorganic layer). However, the second organic layer VIA2 is not limited thereto, and the second organic layer VIA2 may include, for example, an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. (or be formed of an organic layer).

[0157] The second organic layer VIA2 disposed on the second metal layer SD2 may include a lens pattern unit (e.g., lens pattern) LA. The lens pattern unit LA may be formed to include at least a portion overlapping the light emitting element LD. The width D1 of the lens pattern unit LA may be the same or substantially the same (e.g., equal) as the distance between the first electrode ELT1 and the second electrode ELT2, but the present invention is not limited thereto. For example, in other embodiments, the width D1 may be greater than or less than the distance between the first electrode ELT1 and the second electrode ELT2.

[0158] As described above, the lens pattern unit LA may be disposed below (e.g., below) the light emitting element LD to reflect light emitted downward from the light emitting element LD (e.g., toward the base layer BSL relative to the light emitting element LD) upward. Therefore, in some embodiments, the lens pattern unit LA may improve the emission efficiency of the display device.

[0159] In an exemplary embodiment, the lens pattern unit LA may be formed in parallel (e.g., simultaneously) with the formation of the second organic layer VIA2. For example, when the second organic layer VIA2 is formed by using a half-tone mask or a slit (e.g., a slit pattern) having a pitch (e.g., a predetermined pitch), the lens pattern unit LA may be formed in parallel (e.g., simultaneously). In another exemplary embodiment, the lens pattern unit LA may be formed by a separate process after the second organic layer VIA2 is formed. For example, the lens pattern unit LA may be formed by an etching process after the second organic layer VIA2 is formed.

[0160] The lens pattern unit LA may be a recessed pattern recessed toward the base layer BSL relative to the upper surface of the second organic layer VIA2. That is, the thickness of the second organic layer VIA2 may be thinner (e.g., thinnest) at the middle (or central portion) of the lens pattern unit LA and may be thicker toward the edge of the lens pattern unit LA.

[0161] Reference Fig. 7A and Figure 7B The light emitting element LD and the lens pattern unit LA of the second organic layer VIA2 are described in more detail.

[0162] Fig. 7A According to an exemplary embodiment Figure 6 A partial magnified view of area Q. Figure 7B According to another exemplary embodiment Figure 6 A partial magnified view of area Q.

[0163] refer to Figure 6 , Fig. 7A and Figure 7B The second organic layer VIA2 may include a lens pattern unit (eg, a lens pattern) LA, and a light emitting element LD may be disposed on the lens pattern unit LA.

[0164] As described above, the light emitting element LD may include the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13, the electrode layer 14, and the insulating film INF on (eg, covering) these layers.

[0165] The first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may include different kinds of semiconductor layers (or be formed of different types of semiconductor layers). For example, the first conductive semiconductor layer 11 may include an N-type semiconductor material, and the second conductive semiconductor layer 13 may include a P-type semiconductor material. The active layer 12 may be interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. The electrode layer 14 may be provided to surround the second conductive semiconductor layer 13. The insulating film INF may be provided to cover the electrode layer 14, and may be provided to cover the outer surface (e.g., the protruding outer surface) of the first conductive semiconductor layer 11.

[0166] The light emitting element LD may include a first opening 14 a and a second opening 11 a to be electrically connected to the first contact electrode CNE1 and the second contact electrode CNE2 , respectively.

[0167] The first opening 14a may be formed at (eg, in or on) the insulating film INF, and at least a portion of the electrode layer 14 may be exposed through the first opening 14a. The electrode layer 14 may contact the first contact electrode CNE1 through the first opening 14a.

[0168] The second opening 11a may be formed at (eg, in or on) the insulating film INF, and at least a portion of the first conductive semiconductor layer 11 may be exposed through the second opening 11a. The first conductive semiconductor layer 11 may contact the second contact electrode CNE2 through the second opening 11a.

[0169] After the light emitting element LD is disposed on the first insulating layer INS1 , the first opening 14 a and the second opening 11 a may be formed through an etching process.

[0170] When a voltage is applied to the light emitting element LD through the first contact electrode CNE1 and the second contact electrode CNE2, electron-hole pairs are coupled in the active layer 12, and the light emitting element LD emits light. Light L1, L2, and L3 emitted from the light emitting element LD may be emitted toward an external direction relative to the active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. However, one end of the first conductive semiconductor layer 11 that does not overlap with the active layer 12 and the second conductive semiconductor layer 13 may be an area where light is not emitted. Because of the difference in viewing angles of the display device, the user may notice the area where light is not emitted.

[0171] The light L1, L2, and L3 emitted from the light emitting element LD may include light (or light portions) L1 and L2 emitted upward relative to the light emitting element LD and light (or light portion) L3 emitted downward relative to the light emitting element LD. The light portions L1 and L2 emitted upward may be emitted to the outside to be recognized (or observed) by a user, but the light portion L3 emitted downward may not be emitted to the outside, so that it may not be recognized (or observed) by the user.

[0172] The second organic layer VIA2 and the first insulating layer INS1 disposed under the light emitting element LD may have different refractive indices from each other. For example, the refractive index of the second organic layer VIA2 may be lower (or smaller) than the refractive index of the first insulating layer INS1. Because the first insulating layer INS1 and the second organic layer VIA2 may have different refractive indices from each other, a contact surface between the first insulating layer INS1 and the second organic layer VIA2 may form an optical interface.

[0173] At least a portion of the light L3 transmitted from the first insulating layer INS1 toward the second organic layer VIA2 may be reflected at the optical interface between the first insulating layer INS1 and the second organic layer VIA2. The reflected light L4 may be emitted (e.g., reflected) upward and may be observed by a user. Therefore, when the lens pattern unit LA is formed at (e.g., on) the second organic layer VIA2, the emission efficiency of the display device may be improved.

[0174] In some embodiments, the lens pattern unit LA can control the reflection direction of the reflected light L4. The reflection direction of the reflected light L4 can be changed according to (e.g., depending on) the shape of the lens pattern unit LA. For example, when the lens pattern unit LA is formed so that the reflected light L4 is guided toward one end of the first conductive semiconductor layer 11 (e.g., an area that does not emit light), the area that does not emit light of the light emitting element LD can be covered (e.g., the area that does not emit light of the light emitting element LD can transmit the reflected light L4), thereby improving the viewing angle characteristics of the display device.

[0175] In an exemplary embodiment, the surface of the lens pattern unit LA may be formed as a substantially smooth surface to improve the cohesion of the reflected light L4 and improve the light extraction efficiency. However, the surface of the lens pattern unit LA is not limited thereto. For example, in another exemplary embodiment, as shown in FIG. Figure 7B As shown in , a surface of the lens pattern unit LA' may include uneven patterns LAc and LAv. Figure 7B yes Fig. 7A An exemplary embodiment that is a modification of the exemplary embodiment shown in .

[0176] The uneven patterns LAc and LAv may be formed along the surface of the lens pattern unit LA'. The uneven patterns LAc and LAv may reflect light in various directions (e.g., random directions) by irregularly reflecting incident light. In other words, the uneven patterns LAc and LAv may improve the viewing angle characteristics of the display device by dispersing the amount of light (e.g., light parts) in various directions (e.g., all directions) and by reducing the difference in the amount of light according to the viewing angle.

[0177] In more detail, in an exemplary embodiment, the uneven patterns LAc and LAv may include a plurality of concave patterns LAc and a plurality of convex patterns LAv. The concave patterns LAc and the convex patterns LAv may be alternately arranged. In an exemplary embodiment, the widths of the concave patterns LAc and the convex patterns LAv may be the same or substantially the same as each other, but the present invention is not limited thereto, and in other embodiments, the widths of the concave patterns LAc and the convex patterns LAv may be different from each other. In an exemplary embodiment, the widths of each of the concave patterns LAc may be the same or substantially the same as each other, but the present invention is not limited thereto, and in other embodiments, the widths of each of the concave patterns LAc may be different from each other as needed or desired.

[0178] The uneven patterns LAc and LAv may be formed entirely at the lens pattern unit LA' (e.g., in the middle or on the top), or may be formed at a specific area (e.g., in the middle or on the top), and / or may not be formed at a specific area (e.g., in the middle or on the top) to control the direction of the reflected light L4. For example, the uneven patterns LAc and LAv may not be formed at the middle (or central portion) of the lens pattern unit LA', and the uneven patterns LAc and LAv may be formed at the periphery (e.g., only at the periphery) of the lens pattern unit LA'.

[0179] according to Figure 7B The structure of the exemplary embodiment shown in FIG. 1 may be applied to all suitable structures of one or more of the exemplary embodiments described below.

[0180] Refer to Figure 1 again. Figure 5 and Figure 6, the display element layer DPL may include a light source unit LSU included in each of the pixels PXL. For example, the display element layer DPL may include at least one pair of first electrodes ELT1 and second electrodes ELT2, and a plurality of light emitting elements LD may be disposed between the first electrodes ELT1 and the second electrodes ELT2. In some embodiments, the display element layer DPL may further include at least one conductive layer and / or insulating layer.

[0181] In an exemplary embodiment, the display element layer DPL may include first and second electrodes ELT1 and ELT2, a first insulating layer INS1, a light emitting element LD, a second insulating layer INS2, first and second contact electrodes CNE1 and CNE2, and a third insulating layer INS3 disposed (e.g., sequentially disposed) and / or formed on the base layer BSL and / or the pixel circuit layer PCL.

[0182] Each of the first electrode ELT1 and the second electrode ELT2 may include at least one conductive material. For example, each of the first electrode ELT1 and the second electrode ELT2 may include (or be formed of): at least one metal, such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti) and / or alloys thereof; conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and / or indium tin zinc oxide (ITZO); and / or conductive polymers, such as PEDOT. However, the present invention is not limited thereto.

[0183] The first insulating layer INS1 may be disposed on the first electrode ELT1 and the second electrode ELT2. For example, the first insulating layer INS1 may be formed on the first electrode ELT1 and the second electrode ELT2 (e.g., completely formed on the first electrode ELT1 and the second electrode ELT2). In addition, the first insulating layer INS1 may cover the lens pattern unit LA of the second organic layer VIA2. For example, the first insulating layer INS1 may alleviate (e.g., fill) the step caused by the lens pattern unit LA at (e.g., in or on) the second organic layer VIA2. The upper surface of the first insulating layer INS1 may be substantially flattened (e.g., flattened or substantially flattened) to provide a space (e.g., an area) for arranging the light emitting element LD. However, the present invention is not limited thereto. For example, in another exemplary embodiment, the first insulating layer INS1 may be formed along the surface of the second organic layer VIA2. In this case, the upper surface of the first insulating layer INS1 may have a step and may include a concave pattern similar to the concave pattern of the second organic layer VIA2.

[0184] As described above, in some embodiments, the first insulating layer INS1 may be formed to cover (e.g., completely cover) the first and second electrodes ELT1 and ELT2 and the second organic layer VIA2. After the light emitting element LD is disposed and aligned on the first insulating layer INS1, the first insulating layer INS1 may be partially opened to expose the first and second electrodes ELT1 and ELT2 in at least one region.

[0185] In each of the emission regions EMA formed with the first insulating layer INS1, a plurality of light emitting elements LD may be provided and aligned. For example, a plurality of light emitting elements LD may be provided to each emission region EMA using an inkjet method, and the light emitting elements LD may be aligned between the first electrode ELT1 and the second electrode ELT2 by an alignment voltage (e.g., a predetermined alignment voltage or an alignment signal) applied to the first electrode ELT1 and the second electrode ELT2.

[0186] The second insulating layer INS2 may be disposed on the light emitting element LD aligned between the first electrode ELT1 and the second electrode ELT2, and may expose the first end EP1 and the second end EP2 of the light emitting element LD. For example, the second insulating layer INS2 may be partially disposed on a portion of the light emitting element LD that does not cover the first end EP1 and the second end EP2 of the light emitting element LD. The second insulating layer INS2 may be formed in each emission area EMA in an independent pattern, but the present invention is not limited thereto.

[0187] After the alignment of the light emitting element LD is completed, the second insulating layer INS2 is formed on the light emitting element LD so that the light emitting element LD can be prevented or substantially prevented from deviating from the aligned position. In some embodiments, when there is a space between the first insulating layer INS1 and the light emitting element LD before the second insulating layer INS2 is formed, the space can be filled during the process of forming the second insulating layer INS2. Therefore, the light emitting element LD can be supported more stably.

[0188] In some embodiments, during the process of forming the second insulating layer INS2, first and second openings (eg, Fig. 7A 14a and 11a).

[0189] In an exemplary embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the second insulating layer INS2 and may be disposed on the same or substantially the same layer as each other. In this case, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed in the same or substantially the same process using the same or substantially the same conductive material, but the present invention is not limited thereto.

[0190] In another exemplary embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on different layers from each other. In this case, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed using conductive materials that are the same or substantially the same as each other or different from each other in different processes. When the first contact electrode CNE1 and the second contact electrode CNE2 are disposed on different layers, at least one insulating layer may be further formed on any contact electrode on a lower layer of the first contact electrode CNE1 and the second contact electrode CNE2.

[0191] The first contact electrode CNE1 and the second contact electrode CNE2 may be electrically connected to the first end portion EP1 and the second end portion EP2 of the light emitting element LD. In addition, the first contact electrode CNE1 and the second contact electrode CNE2 may be electrically connected to the first electrode ELT1 and the second electrode ELT2 by passing through the first insulating layer INS1 and the second insulating layer INS2 in the above-mentioned at least one region. Therefore, the first end portion EP1 and the second end portion EP2 of the light emitting element LD may be electrically connected to the first electrode ELT1 and the second electrode ELT2. However, in another exemplary embodiment, when the first contact electrode CNE1 and the second contact electrode CNE2 are directly connected to the separated power line and / or signal line, the first contact electrode CNE1 and the second contact electrode CNE2 may not be directly connected to and / or electrically connected to the first electrode ELT1 and the second electrode ELT2.

[0192] However, the present invention is not limited thereto, and the connection structure between the first and second contact electrodes CNE1 and CNE2 and the first and second electrodes ELT1 and ELT2 may be variously modified.

[0193] The third insulating layer INS3 may be disposed on the first contact electrode CNE1 and the second contact electrode CNE2. For example, the third insulating layer INS3 may be disposed on one surface of the base layer BSL, at (or on) which the light emitting element LD and the first contact electrode CNE1 and the second contact electrode CNE2 are formed, and the third insulating layer INS3 may cover the light emitting element LD and the first contact electrode CNE1 and the second contact electrode CNE2. The third insulating layer INS3 may include at least one inorganic and / or organic layer.

[0194] In an exemplary embodiment, the third insulating layer INS3 may include a thin film encapsulation layer having a multi-layer structure, but the present invention is not limited thereto. According to one or more exemplary embodiments, at least one overcoat layer and / or an encapsulation substrate may be further disposed on the third insulating layer INS3.

[0195] According to an exemplary embodiment, each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include a single layer or a plurality of layers (or be formed of a single layer or a plurality of layers), and may include at least one inorganic insulating material and / or an organic insulating material. For example, each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include various kinds of organic or inorganic insulating materials, for example, silicon nitride (SiN x ), but the material included in each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 is not limited thereto. In addition, the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include different insulating materials, or at least some of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include the same or substantially the same insulating material.

[0196] As described above, the lens pattern unit LA may be formed below (e.g., below) each light emitting element LD. The lens pattern unit LA may reflect light emitted from the light emitting element LD toward the lens pattern unit LA upward to improve the emission efficiency of the display device, and may adjust the direction of the reflected light L4 to improve the viewing angle characteristics of the display device. The structure and shape of the lens pattern unit LA are not limited to one or more exemplary embodiments described herein, and various modifications may be made.

[0197] In the following, reference will be made to Figures 8 to 11 One or more other exemplary embodiments of a display device are described. In the following exemplary embodiments, constituent elements that are the same or substantially the same as constituent elements of the previously described exemplary embodiments will be denoted by the same or substantially the same reference numerals, and therefore, redundant descriptions thereof may be omitted or simplified, and the differences therebetween will be mainly described in more detail.

[0198] Figure 8 is a cross-sectional view of a pixel according to another exemplary embodiment. Fig. 9 yes Figure 8 A partial enlarged view of area Q1. Figure 8 and Fig. 9 The exemplary embodiment of is different from one or more of the exemplary embodiments described above. For example, in Figure 8 and Fig. 9 In the exemplary embodiment of FIG. 1 , the lens pattern unit LA1 is formed in the second metal layer SD2 instead of the second organic layer VIA2 , and other structures may be the same or substantially the same as one or more exemplary embodiments described above.

[0199] refer to Figure 8 and Fig. 9, the second metal layer SD2 may include a lens pattern unit LA1. The lens pattern unit LA1 may be disposed below (e.g., below) the light emitting element LD to include at least a portion overlapping the light emitting element LD. The lens pattern unit LA1 may be formed to correspond to each light emitting element LD one by one, but the present invention is not limited thereto. For example, in other embodiments, a plurality of light emitting elements LD may correspond to one lens pattern unit LA1.

[0200] The shape of the lens pattern unit LA1 in a plan view may be Figure 5 The lens pattern units LA shown in FIG. 1 are the same or similar (eg, substantially the same). For example, the lens pattern unit LA1 may have a circular or elliptical shape in a plan view.

[0201] In an exemplary embodiment, the width D2 of the lens pattern unit LA1 may be smaller than the length LDL of the light emitting element LD, but in another exemplary embodiment, the width D2 of the lens pattern unit LA1 may be greater than the length LDL of the light emitting element LD.

[0202] The lens pattern unit LA1 may be disposed under (eg, below) the light emitting element LD to reflect light emitted downward from the light emitting element LD upward. That is, the lens pattern unit LA1 may improve emission efficiency of a display device including the pixel PXL1.

[0203] When the second metal layer SD2 is formed, the lens pattern unit LA1 may be formed in parallel (eg, simultaneously). For example, the lens pattern unit LA1 may be formed by disposing (eg, completely disposing) the second metal layer SD2 on the first organic layer VIA1 and patterning the second metal layer SD2.

[0204] The lens pattern unit LA1 may include a plurality of cone portions TP1, TP2, and TP3. The plurality of cone portions TP1, TP2, and TP3 may include a first cone portion TP1, a second cone portion TP2, and a third cone portion TP3. The second cone portion TP2 may be adjacent to (e.g., surround) the first cone portion TP1, and the third cone portion TP3 may be adjacent to (e.g., surround) the second cone portion TP2.

[0205] Each of the tapered portions TP1 , TP2 , and TP3 may be disposed to be spaced apart from each other, but the present invention is not limited thereto, and in other embodiments, at least a portion of the tapered portions TP1 , TP2 , and TP3 may contact each other.

[0206] Each of the tapered portions TP1, TP2, and TP3 may have a different taper angle. The taper angle is defined as an acute angle between an axis and a side surface. For example, the taper angle of the first tapered portion TP1 may be the largest, the taper angle of the second tapered portion TP2 may be smaller, and the taper angle of the third tapered portion TP3 may be the smallest. However, the present invention is not limited thereto, and the taper angles of the tapered portions TP1, TP2, and TP3 may be variously modified as needed or desired.

[0207] At least some of the light L3 emitted downward from the light emitting element LD may be transmitted through the second organic layer VIA2 toward the second metal layer SD2. According to an exemplary embodiment, the second metal layer SD2 may include a highly reflective metal material. The light L3 transmitted toward the second metal layer SD2 may be reflected at the surface of each of the tapered portions TP1, TP2, and TP3.

[0208] As described above, each of the tapered portions TP1, TP2, and TP3 may have a different tapered angle, so that light incident on the lens pattern unit LA1 of the second metal layer SD2 may be reflected in different directions. Reflected light L4 reflected by one or more of the tapered portions TP1, TP2, and TP3 may be emitted to the outside. The emission efficiency and viewing angle characteristics of the display device may be improved by the light emitted to the outside.

[0209] According to reference Figure 8 and Fig. 9 The structure of the described exemplary embodiment can be applied to one or more of the exemplary embodiments described above and one or more of the exemplary embodiments described below. Figures 5 to 7B According to one or more exemplary embodiments, the second organic layer VIA2 may include the lens pattern unit LA, and the second metal layer SD2 may include the lens pattern unit LA1.

[0210] Fig.10 is a top view of a pixel according to another exemplary embodiment. Fig.11 is along Fig.10 A cross-sectional view taken along line BB'. Fig.10 and Fig.11 The exemplary embodiment of is different from one or more of the exemplary embodiments described above. For example, in Fig.10 and Fig.11 In the exemplary embodiment, the lens pattern unit LA2 is formed to have a larger width (eg, a larger width than the lens pattern unit LA and the lens pattern unit LA1), and does not correspond one-to-one with the light emitting element LD, and Fig.10 and Fig.11 Other structures of the exemplary embodiments of the present invention may be the same or similar (eg, substantially the same) to one or more exemplary embodiments described above.

[0211] refer to Fig.10 and Fig.11 , the second organic layer VIA2 may include a lens pattern unit LA2. The lens pattern unit LA2 may have a circular or elliptical shape in a plan view, but the present invention is not limited thereto.

[0212] The lens pattern unit LA2 may be disposed under (eg, below) the light emitting element LD, and may overlap with the plurality of light emitting elements LD. Fig.10 The exemplary embodiment shows that the lens pattern unit LA2 may overlap with six light emitting elements LD, but the present invention is not limited thereto, and in other embodiments, the lens pattern unit LA2 may overlap with less than or more than six light emitting elements LD.

[0213] The width D3 of the lens pattern unit LA2 may be greater than the length LDL of the light emitting element LD. For example, the width D3 of the lens pattern unit LA2 may be greater than or equal to twice the length LDL of the light emitting element LD.

[0214] The lens pattern unit LA2 may reflect light emitted downward from the light emitting element LD upward. The lens pattern unit LA2 may reflect (or emit) more light upward, and may improve emission efficiency and viewing angle characteristics of a display device including the pixel PXL2.

[0215] because Fig.10 and Fig.11 Other configurations (eg, layers and components) shown in the reference Figures 5 to 7B The lens pattern units LA described in one or more exemplary embodiments are the same or similar (eg, substantially the same), and thus a redundant description thereof may be omitted.

[0216] Although one or more exemplary embodiments of the present invention are described with reference to the accompanying drawings, it should be understood that the embodiments described herein should be considered in a descriptive sense only, rather than for limiting purposes. Therefore, those of ordinary skill in the art to which the present invention belongs will understand that various aspects and features of the present invention may be modified without departing from the spirit and scope of the present invention as defined by the attached claims and their equivalents.

Claims

1. Display equipment, including: basal layer; A pixel circuit layer, located on the base layer; as well as A display element layer is located on the pixel circuit layer. The pixel circuit layer includes a lens pattern located in a recess between the display element layer and the base layer. The display element layer includes a light emitting element, and at least a portion of the light emitting element overlaps with the lens pattern. wherein the lens pattern reflects incident light, The light emitting element comprises a first semiconductor layer, an active layer and a second semiconductor layer, wherein the active layer surrounds at least a portion of the first semiconductor layer, the type of the second semiconductor layer is different from that of the first semiconductor layer and the second semiconductor layer surrounds at least a portion of the active layer, and Wherein, in a plan view, at least a portion of the first semiconductor layer does not overlap with the lens pattern.

2. The display device according to claim 1, wherein: The display element layer includes a first electrode and a second electrode spaced apart from the first electrode, and the light emitting element is located between the first electrode and the second electrode.

3. The display device according to claim 2, wherein: The light emitting element includes a first end portion and a second end portion, the first end portion includes the active layer, and the second end portion does not include the active layer.

4. The display device according to claim 3, wherein: The display element layer includes a first contact electrode and a second contact electrode, wherein the first contact electrode is located on the first electrode and electrically connected to the first end portion, and the second contact electrode is located on the second electrode and electrically connected to the second end portion.

5. The display device according to claim 2, wherein: The pixel circuit layer includes a plurality of transistors and an organic layer covering the plurality of transistors, and the organic layer includes the lens pattern.

6. The display device according to claim 5, wherein: The display element layer further includes an insulating layer covering the first electrode, the second electrode and the organic layer, and Wherein, the refractive index of the insulating layer is greater than the refractive index of the organic layer.

7. The display device according to claim 5, wherein: The lens pattern includes an uneven pattern, and Wherein, the non-uniform pattern is configured to irregularly reflect incident light.

8. The display device according to claim 2, wherein: The first electrode and the second electrode do not overlap the lens pattern.

9. The display device according to claim 8, wherein: The width of the lens pattern is smaller than the length of the light emitting element.

10. The display device according to claim 9, wherein: The lens patterns correspond to the light emitting elements one by one.

11. The display device according to claim 2, wherein: The width of the lens pattern is greater than or equal to twice the length of the light emitting element.

12. Display equipment, including: basal layer; A pixel circuit layer, located on the base layer; as well as A display element layer is located on the pixel circuit layer. The pixel circuit layer includes a lens pattern, and the lens pattern includes a plurality of cone-shaped portions. The display element layer includes a light emitting element, and at least a portion of the light emitting element overlaps with the lens pattern. wherein the lens pattern reflects incident light, The light emitting element comprises a first semiconductor layer, an active layer and a second semiconductor layer, wherein the active layer surrounds at least a portion of the first semiconductor layer, the type of the second semiconductor layer is different from that of the first semiconductor layer and the second semiconductor layer surrounds at least a portion of the active layer, and Wherein, in a plan view, at least a portion of the first semiconductor layer does not overlap with the lens pattern.

13. The display device according to claim 12, wherein: The display element layer includes a first electrode and a second electrode spaced apart from the first electrode, and the light emitting element is located between the first electrode and the second electrode.

14. The display device according to claim 13, wherein: The light emitting element includes a first end portion and a second end portion, the first end portion includes the active layer, and the second end portion does not include the active layer.

15. The display device according to claim 13, wherein: The plurality of tapered portions include a first tapered portion and a second tapered portion spaced apart from the first tapered portion, and Wherein, a taper angle of the first taper portion is different from a taper angle of the second taper portion.

16. The display device according to claim 15, wherein: The pixel circuit layer includes a plurality of transistors and a metal layer located on the plurality of transistors, the metal layer including the lens pattern and electrically connected to at least one of the plurality of transistors.

17. The display device according to claim 16, wherein: The metal layer includes at least one of silver, magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, chromium, titanium and alloys thereof.

18. The display device according to claim 17, wherein: The width of the lens pattern is less than or equal to the length of the light emitting element.

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