A memristor-based amplifier with adjustable gain and phase

Abstract

The present invention discloses a gain and phase adjustable amplifier based on a memristor, which utilizes the electrical characteristics of the memristor and is combined with a negative resistance source-coupled differential pair circuit, and the gain and phase of the amplifier are changed by setting the resistance value of the memristor through pulse programming. A current mirror with high output impedance is used in the architecture to bypass the DC component of the memristor, so that the static operating voltage at both ends of the memristor is less than the threshold voltage of the memristor, which significantly saves the integrated circuit layout area compared to the traditional bypass capacitor method. By connecting a negative resistance generating circuit in series with the memristor, the memristor as a positive resistor can be adjusted through pulse programming to obtain an adjustable resistance value within a certain positive and negative resistance range, and the positive and negative adjustable resistor can be used as the load of the source-coupled differential pair circuit to achieve both the gain and the phase of the amplifier.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a memristor-based gain and phase adjustable amplifier. Background Art

[0002] Memristor is the fourth basic circuit element besides resistor, capacitor and inductor, which represents the mathematical relationship between charge and magnetic flux. In recent years, with the continuous advancement of nanostructure characterization technology and in-depth research on the performance of memristors, the preparation and application of memristors have made certain progress, and the integration and comprehensive application of memristors in the electronic field have become possible. Since memristors have resistance memory function, their resistance changes with the change of their charge, and the size of the resistance can change reversibly with the direction or polarity of the charge. Therefore, this feature can be used to design many novel application circuits in analog integrated circuits.

[0003] Operational amplifiers are the most basic application circuits in automation technology and electronic information technology. Especially in instrumentation amplifier circuits and communication circuits, more precise control of amplifier gain is required to ensure signal stability. However, traditional gain and phase control amplifiers have the disadvantages of complex circuits, inability to control the amplification phase, and inability to achieve gain pulse programming. Summary of the invention

[0004] The present invention aims to solve the problem that the circuit of the traditional gain and phase control amplifier is relatively complex and it is difficult to realize the pulse programming control of gain and phase, and provides a gain and phase adjustable amplifier based on a memristor.

[0005] To solve the above problems, the present invention is achieved through the following technical solutions:

[0006] A gain and phase adjustable amplifier based on a memristor comprises a source-coupled differential pair circuit, a negative resistance generating circuit, memristors MR1-MR2 and current mirrors CM1-CM4; the negative electrode of the memristor MR1, the output end of the current mirror CM3 and the output end M of the negative resistance generating circuit are connected; the negative electrode of the memristor MR2, the output end of the current mirror CM4 and the output end N of the negative resistance generating circuit are connected; the positive electrode of the memristor MR1, the output end of the current mirror CM1 and the in-phase output end P of the source-coupled differential pair circuit are connected; the positive electrode of the memristor MR2, the output end of the current mirror CM2 and the inverting output end Q of the source-coupled differential pair circuit are connected; the source-coupled differential pair circuit is connected to an input differential signal V ip and V in Connected.

[0007] The above memristor-based gain and phase adjustable amplifier further comprises switches S1-S5; the two ends of switch S1 are respectively connected to the pulse programming input signal V proand the output terminal N of the negative resistance generating circuit; the two ends of the switch S2 are respectively connected to the two output terminals M and N of the negative resistance generating circuit; the two ends of the switch S3 are respectively connected to the reset input signal V res The two ends of switch S4 are respectively connected to the in-phase output terminal P and the inverting output terminal Q of the source-coupled differential pair circuit; the two ends of switch S5 are respectively connected to the inverting output terminal Q of the source-coupled differential pair circuit and the ground V ss .

[0008] The above memristor-based gain and phase adjustable amplifier further includes a load resistor R L ; Load resistance R L The two ends are respectively connected to the in-phase output terminal P of the source-coupled differential pair circuit and the inverting output terminal Q of the source-coupled differential pair circuit.

[0009] In the above scheme, the output source current or sink current of the current mirror CM1, the current mirror CM2, the current mirror CM3 and the current mirror CM4 is equal to the single-side static current of the source-coupled differential pair circuit.

[0010] In the above scheme, current mirrors CM1 and CM2 are both PMOS current mirrors; current mirrors CM3 and CM4 are both NMOS current mirrors.

[0011] In the above scheme, the structures of current mirrors CM1 and CM2 are exactly the same. Among them: current mirror CM1 is composed of PMOS tube M1, PMOS tube M2, PMOS tube M3 and resistor R1; the source of PMOS tube M1 and the source of PMOS tube M2 are connected to the power supply V at the same time. dd The drain of the PMOS tube M1 is connected to the source of the PMOS tube M3; the gate of the PMOS tube M1, the gate and drain of the PMOS tube M2, the gate of the PMOS tube M3 and one end of the resistor R1 are connected; the other end of the resistor R1 is grounded V ss The drain of PMOS tube M3 forms the output end of current mirror CM1. Current mirror CM2 is composed of PMOS tube M4, PMOS tube M5, PMOS tube M6 and resistor R2. The source of PMOS tube M4 and the source of PMOS tube M5 are connected to the power supply V at the same time. dd The drain of the PMOS tube M4 is connected to the source of the PMOS tube M6; the gate of the PMOS tube M4, the gate and drain of the PMOS tube M5, the gate of the PMOS tube M6 and one end of the resistor R2 are connected; the other end of the resistor R2 is grounded V ss ; The drain of the PMOS tube M6 forms the output end of the current mirror CM2.

[0012] In the above scheme, the structures of current mirrors CM3 and CM4 are exactly the same. Among them: current mirror CM3 is composed of NMOS tube M7, NMOS tube M8, NMOS tube M9 and resistor R3; one end of resistor R3 is connected to power supply V ddThe other end of the resistor R3, the gate of the NMOS tube M7, the gate of the NMOS tube M8, and the gate and drain of the NMOS tube M9 are connected; the source of the NMOS tube M7 and the drain of the NMOS tube M8 are connected; the source of the NMOS tube M8 and the source of the NMOS tube M9 are grounded at the same time V ss The drain of NMOS tube M7 forms the output end of current mirror CM3. Current mirror CM4 is composed of NMOS tube M 10 、NMOS tube M 11 、NMOS tube M 12 and resistor R4; one end of resistor R4 is connected to power supply V dd ; The other end of resistor R4, NMOS tube M 10 The gate of NMOS tube M 11 The gate of the NMOS tube M 12 The gate and drain of NMOS tube M are connected; 10 The source and NMOS tube M 11 The drain of NMOS tube M 11 The source and NMOS tube M 12 The source of V ss ; NMOS tube M 10 The drain of forms the output terminal of current mirror CM4.

[0013] In the above scheme, the negative resistance generating circuit is composed of a PMOS tube M 13 And PMOS tube M 14 Composition: PMOS tube M 13 The source and PMOS tube M 14 The source of dd ; PMOS tube M 13 The drain and PMOS tube M 14 After the gate of the PMOS tube is connected, an output terminal M of the negative resistance generating circuit is formed; 14 The drain and PMOS tube M 13 After being connected to the gate of , another output terminal N of the negative resistance generating circuit is formed.

[0014] In the above scheme, the source coupling differential pair circuit is composed of NMOS tube M 15 、NMOS tube M 16 and NMOS tube M 17 Composition: NMOS tube M 15 The gate is connected to the input differential signal V ip ; NMOS tube M 16 The gate is connected to the input differential signal V in ; NMOS tube M 15 The drain of the NMOS tube M forms the in-phase output terminal P of the source-coupled differential pair circuit; 16The drain of the NMOS tube M forms the inverting output terminal Q of the source-coupled differential pair circuit; 15 The source of NMOS tube M 16 The source and NMOS tube M 17 The drain of NMOS tube M 17 The drain of NMOS tube M is connected to the input bias voltage V2; 17 The source of the grounded V ss .

[0015] The present invention utilizes the electrical characteristics of a memristor and combines it with a negative resistance source-coupled differential pair circuit, and changes the gain and phase of the amplifier by setting the resistance of the memristor through pulse programming. A current mirror with high output impedance is used in the architecture to bypass the DC component of the memristor, so that the static operating voltage at both ends of the memristor is less than the threshold voltage of the memristor, which significantly saves the integrated circuit layout area compared to the traditional bypass capacitor method. By connecting a negative resistance generating circuit in series with the memristor, the memristor as a positive resistor can be adjusted through pulse programming to obtain an adjustable resistance value within a certain positive and negative resistance range, and using this positive and negative adjustable resistor as the load of the source-coupled differential pair circuit can achieve both the gain and phase of the amplifier.

[0016] Compared with the prior art, the present invention has the following characteristics:

[0017] 1. Connect the negative resistance generating circuit in series with the memristor. By adjusting the memristor as a positive resistance, an adjustable resistance value within the positive and negative resistance range can be obtained. Using this positive and negative adjustable resistance as the load of the source-coupled differential pair can obtain the same-phase or anti-phase amplification of the amplifier.

[0018] 2. The DC component of the memristor is bypassed by a current mirror with high output impedance, which significantly saves layout area compared to the traditional bypass capacitor method.

[0019] 3. Pulse programming control of amplifier gain and phase can be achieved by pulse programming of the resistance value of the memristor. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The schematic diagram of a memristor-based gain and phase adjustable amplifier.

[0021] Figure 2 The figure is a circuit diagram for realizing a gain and phase adjustable amplifier based on a memristor.

[0022] Figure 3 The memristor resistance and gain curve of the memristor-based gain and phase adjustable amplifier.

[0023] Figure 4The memristor resistance and phase curve of the memristor-based gain and phase adjustable amplifier. DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific examples.

[0025] Figure 1 The schematic diagram of a gain and phase adjustable amplifier based on a memristor omits the memristor programming circuit and load. It is composed of a source-coupled differential pair circuit, a negative resistance generating circuit, memristors MR1-MR2, PMOS current mirrors CM1-CM2, and NMOS current mirrors CM3-CM4. The input differential signals Vip and Vin are respectively connected to the in-phase input terminal and the inverting input terminal of the source-coupled differential pair circuit. The output of the current mirror CM1 is connected to the positive electrode of the memristor MR1 and then connected to the in-phase output terminal P of the source-coupled differential pair circuit. The output of the current mirror CM2 is connected to the positive electrode of the memristor MR2 and then connected to the inverting output terminal Q of the source-coupled differential pair circuit. The output of the current mirror CM3 is connected to the negative electrode of the memristor MR1 and then connected to an output terminal M of the negative resistance generating circuit. The output of the current mirror CM4 is connected to the negative electrode of the memristor MR2 and then connected to another output terminal N of the negative resistance generating circuit of the source-coupled differential pair circuit. The source-coupled differential pair circuit is connected to the input differential signal V ip and V in Connected.

[0026] The structure of the memristor-based gain and phase adjustable amplifier is highly symmetrical. The PMOS current mirror CM1 is exactly the same as the PMOS current mirror CM2, and the NMOS current mirror CM3 is exactly the same as the NMOS current mirror CM4. When the memristor-based gain and phase adjustable amplifier is working normally, the pull current or sink current output by the current mirror CM1, the current mirror CM2, the current mirror CM3 and the current mirror CM4 must be equal to the single-sided static current of the source-coupled differential pair circuit, so that the static operating current flowing through the memristor MR1 and the memristor MR2 is zero, ensuring that the resistance of the memristor will not be affected by the static bias current of other MOS tubes when the memristor-based gain and phase adjustable amplifier is working normally.

[0027] If current mirrors CM1, CM2, CM3 and CM4 are high output impedance current mirrors, then current mirrors CM1, CM2, CM3 and CM4 in the AC path of the memristor-based gain and phase adjustable amplifier can be regarded as open circuits. At this time, the series connection of the negative resistance generating circuit and the memristor serves as the load resistance of the source-coupled differential pair circuit. Therefore, when the width-to-length ratio of all MOS tubes and the static operating current are fixed, the gain and phase of the memristor-based gain and phase adjustable amplifier depend on the absolute value and positive and negative of the resistance value after the series connection of the negative resistance generating circuit and the memristor.

[0028] Figure 2 for Figure 1 The figure shows the implementation circuit diagram of the gain and phase adjustable amplifier based on memristor.

[0029] PMOS tubes M1, M2, M3 and resistor R1 together form a Wilson current mirror, namely current mirror CM1. After the source of PMOS tube M1 is connected to the source of PMOS tube M2, the power supply end of current mirror CM1 is formed and connected to the power supply V dd The drain of PMOS tube M1 is connected to the source of PMOS tube M3. The gate of PMOS tube M1, the gate and drain of PMOS tube M2, the gate of PMOS tube M3 and one end of resistor R1 are connected. The other end of resistor R1 forms the ground end of current mirror CM1 and is grounded to V ss The drain of the PMOS tube M3 forms the output end of the current mirror CM1 and is connected to the in-phase output end P of the source-coupled differential pair circuit.

[0030] PMOS tubes M4, M5, M6 and resistor R2 together form a Wilson current mirror, namely current mirror CM2. The source of PMOS tube M4 and the source of PMOS tube M5 are connected to form the power supply end of current mirror CM2, and are connected to power supply V dd The drain of the PMOS tube M4 is connected to the source of the PMOS tube M6. The gate of the PMOS tube M4, the gate and drain of the PMOS tube M5, and the gate of the PMOS tube M6 are connected to one end of the resistor R2. The other end of the resistor R2 forms the ground end of the current mirror CM2 and is grounded to V ss The drain of the PMOS tube M6 forms the output end of the current mirror CM2 and is connected to the inverting output end Q of the source-coupled differential pair circuit.

[0031] NMOS tubes M7, M8, M9 and resistor R3 together form a Wilson current mirror, namely current mirror CM3. One end of resistor R3 forms the power supply end of current mirror CM3 and is connected to power supply V ddThe other end of the resistor R3, the gate of the NMOS tube M7, the gate of the NMOS tube M8, and the gate and drain of the NMOS tube M9 are connected. The source of the NMOS tube M7 is connected to the drain of the NMOS tube M8. The source of the NMOS tube M8 is connected to the source of the NMOS tube M9 to form the ground end of the current mirror CM3 and to the ground V ss The drain of the NMOS tube M7 forms the output end of the current mirror CM3 and is connected to an output end M of the negative resistance generating circuit.

[0032] NMOS tube M 10 、NMOS tube M 11 、NMOS tube M 12 Together with resistor R4, it forms a Wilson current mirror, namely current mirror CM4. One end of resistor R4 forms the power supply end of current mirror CM4 and is connected to power supply V dd The other end of resistor R4 and NMOS tube M 10 The gate of NMOS tube M 11 The gate of the NMOS tube M 12 The gate and drain of NMOS tube are connected. 10 The source and NMOS tube M 11 The drain of NMOS tube M 11 The source and NMOS tube M 12 After the source of is connected, the ground terminal of the current mirror CM4 is formed and grounded V ss . NMOS tube M 10 The drain of forms the output end of the current mirror CM4 and is connected to another output end N of the negative resistance generating circuit.

[0033] The above current mirrors CM1, CM2, CM3 and CM4 all use Wilson current mirrors, which have the advantage of providing a larger output impedance. To ensure the symmetry of the circuit, R1 = R2 and R3 = R4 are taken. The output source current or sink current of the current mirrors CM1, CM2, CM3 and CM4 are equal.

[0034] PMOS tube M 13 And PMOS tube M 14 The negative resistance generating circuit is formed by using a structure in which the gate and the drain are cross-connected. 13 The source and PMOS tube M 14 After being connected to the source of the negative resistance generating circuit, the power supply end is formed and connected to the power supply V dd . PMOS tube M 13 The drain and PMOS tube M 14 After the gate of the PMOS tube is connected, an output terminal M of the negative resistance generating circuit is formed. 14 The drain and PMOS tube M13 After the gate of the PMOS tube is connected, another output terminal N of the negative resistance generating circuit is formed. The characteristic of this circuit structure is that 13 The drain terminal and the PMOS tube M 14 The input impedance seen between the drain terminals is a negative value, and the resistance of the negative resistor depends on the PMOS tube M 13 And PMOS tube M 14 To ensure the symmetry of the circuit, the PMOS tube M 13 And PMOS tube M 14 Use the same aspect ratio.

[0035] NMOS tube M 15 、NMOS tube M 16 and NMOS tube M 17 The source-coupled differential pair circuit is formed. 15 The gate is connected to the input differential signal V ip . NMOS tube M 16 The gate is connected to the input differential signal V in . NMOS tube M 15 The drain of the NMOS tube M forms the in-phase output terminal P of the source-coupled differential pair circuit. 16 The drain of the NMOS tube M forms the inverting output terminal Q of the source-coupled differential pair circuit. 15 The source of NMOS tube M 16 The source and NMOS tube M 17 The drain of NMOS tube M 17 The drain of NMOS tube M is connected to the input bias voltage V2. 17 The source of the source coupler forms the ground terminal of the differential pair circuit and is grounded to V ss . NMOS tube M 15 and NMOS tube M 16 The width-to-length ratio is equal and plays an amplifying role, while the NMOS tube M 17 is the tail current mirror of the source-coupled differential pair circuit, and the NMOS tube M 17 The gate bias voltage V2 should make the output current of the tail current mirror twice the output sink current or source current of the above-mentioned single Wilson current mirror.

[0036] The negative electrode of the memristor MR1 and the output end of the current mirror CM3 are connected at the output end M of the negative resistance generating circuit. The negative electrode of the memristor MR2 and the output end of the current mirror CM4 are connected at the output end N of the negative resistance generating circuit. The positive electrode of the memristor MR1, the output end of the current mirror CM1 and the load resistor R L One end of is connected to the in-phase output terminal P of the source-coupled differential pair circuit. The positive electrode of the memristor MR2, the output terminal of the current mirror CM2 and the load resistor R LThe other end is connected to the inverting output terminal Q of the source coupling differential pair circuit.

[0037] The two ends of switch S1 are connected to the pulse programming input signal V pro The two ends of switch S2 are connected to the two output ends M and N of the negative resistance generating circuit respectively. The two ends of switch S3 are connected to the reset input signal V res The two ends of switch S4 are respectively connected to the in-phase output terminal P and the inverting output terminal Q of the source-coupled differential pair circuit. The two ends of switch S5 are respectively connected to the inverting output terminal Q of the source-coupled differential pair circuit and the ground V ss The function of switches S1-S5 is to control the initialization reset and pulse programming of the resistance value of memristor MR1 and memristor MR2. Pulse programming input signal V pro and reset input signal V res Of course, the memristor-based gain and phase adjustable amplifier of the present invention can also use other switch control schemes, such as increasing or decreasing the number of switches. The above switch control scheme is only a more simplified preferred scheme.

[0038] The negative resistance generating circuit and the memristor are connected in series and serve as the load of the source-coupled differential pair circuit. The high potential point of each memristor is connected to the ground V through a current mirror that outputs the pull current. ss , and the low potential point is connected to the power supply V through the current mirror of the output sink current dd Each current mirror has a large output impedance, so that the current mirror can be regarded as an open circuit in the AC path, and the sink current or source current output by each current mirror is equal to the unilateral current of the source-coupled differential pair circuit, which can make the static operating current flowing through the memristor almost zero. The phase of the amplifier gain depends on the resistance value of the negative resistance generating circuit and the memristor in series. When the resistance value of the memristor is greater than or less than the AC input impedance of the negative resistance generating circuit, the phase of the amplifier gain is opposite.

[0039] The working principle of the present invention is:

[0040] In order to ensure the circuit symmetry of the memristor-based gain and phase adjustable amplifier, the resistance values ​​of memristors MR1 ​​and MR2 must be equal, so the resistance pulse programming and resistance initialization of memristors MR1 ​​and MR2 need to be performed simultaneously. The memristor-based gain and phase adjustable amplifier has three operating modes, namely, amplifier gain and phase programming mode, amplifier gain and phase initialization mode, and normal operating mode.

[0041] In the amplifier gain and phase initialization mode, switches S2, S3, S4, and S5 are all closed, and switch S1 is open, resetting the input signal V res The resistance values ​​of the memristor MR1 and the memristor MR2 are reset to the maximum resistance values ​​of the memristors.

[0042] In the amplifier gain and phase programming mode, switches S1, S2, S4, and S5 are all in the closed state, and switch S3 is open. At this time, the pulse programming input signal V pro After passing through the parallel connection of memristor MR1 and memristor MR2, it flows into V ss According to the polarity of the pulse, the resistance of the memristor MR1 and the memristor MR2 can be increased or decreased at the same time, thereby realizing the pulse programming control of the resistance of the memristor.

[0043] In normal working mode, switches S1, S2, S3, S4 and S5 are all disconnected. At this time, the differential input signal is transmitted from the NMOS transistor M 15 And MOS tube M 16 When the memristor-based gain and phase adjustable amplifier is in normal operating mode, it is assumed that the NMOS tube M 15 and NMOS tube M 16 The transconductance of PMOS tube M is gm1. 13 And PMOS tube M 14 The transconductance of both memristors MR1 ​​and MR2 is gm2; and it is assumed that the resistance of the memristor MR1 and memristor MR2 after pulse programming is M, and other parasitic effects are not considered. The gain of the memristor-based gain and phase adjustable amplifier when unloaded is A V for:

[0044]

[0045] From the above theoretical analysis results, it can be seen that when the resistance M of the memristor MR1 and the memristor MR2 is greater than 1 / gm2, the amplifier is in-phase amplification; when the resistance M of the memristor MR1 and the memristor MR2 is less than 1 / gm2, the amplifier is in-phase amplification. Figure 3 and Figure 4 They are the memristor resistance value M vs. gain curve and the memristor resistance value M vs. phase curve of the memristor-based gain and phase adjustable amplifier, and both curves are Figure 2 The simulation results of the circuit in SPICE. The value of 1 / gm2 set in the simulation is approximately equal to 25 kilo-ohms. The minimum and maximum values ​​of the memristor are 20 ohms and 100 kilo-ohms respectively. Figure 3As shown in the figure, the ordinate of the figure is the gain of the gain and phase adjustable amplifier based on the memristor, and the abscissa is the resistance M of the memristor MR1 and the memristor MR2. It can be concluded that the gain of the gain and phase adjustable amplifier based on the memristor first decreases and then increases. When the resistance M is approximately equal to 25 kiloohms, the gain A of the gain and phase adjustable amplifier based on the memristor v Approaches 0. Figure 4 As shown in the figure, the ordinate is the phase of the gain and phase adjustable amplifier based on the memristor, and the abscissa is the phase of the gain and phase adjustable amplifier based on the memristor. Figure 3 The same can be seen from this figure that when the resistance M of memristors MR1 ​​and MR2 increases from 20 ohms to 100 kiloohms, the phase of the gain and phase adjustable amplifier based on the memristor changes suddenly from -180° to 0° when the resistance M is approximately equal to 25 kiloohms. It can be seen from this that Figure 3 and Figure 4 The simulation results are basically consistent with the above theoretical analysis.

[0046] The present invention utilizes the electrical characteristics of a memristor and combines it with a negative resistance source-coupled differential pair, and changes the gain and phase of the amplifier by programming the memristor to set the resistance value. First, a current mirror is used to bypass the DC component of the memristor, so that the static operating voltage at both ends of the memristor is less than the threshold voltage of the memristor. The memristor is connected in series with a negative resistance generating circuit, and a suitable width-to-length ratio and a static operating voltage are set for the CMOS transistor in the negative resistance generating circuit, so that when the resistance value of the memristor changes between a maximum value and a minimum value, the sum of the resistance values ​​of the memristor resistance and the negative resistance generating circuit can change between a reasonable positive and negative value. Then, the whole after the memristor and the negative resistance generating circuit are connected in series is used as the load of the source-coupled differential pair, so that an adjustable positive and negative gain can be obtained by changing the resistance value of the memristor. The present invention uses a memristor to solve the defects of the traditional gain control amplifier that cannot control the amplification phase and cannot perform pulse programming on the gain, and uses a current mirror to bypass the DC component of the memristor, which can significantly save the chip layout area compared to the traditional bypass capacitor. The gain and phase adjustable amplifier based on memristor can be applied in the field of analog integrated circuits.

[0047] It should be noted that although the embodiments of the present invention described above are illustrative, they are not intended to limit the present invention, and therefore the present invention is not limited to the above specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. A memristor-based gain and phase adjustable amplifier, characterized in that: It includes a source coupling differential pair circuit, a negative resistance generating circuit, memristors MR1-MR2 and current mirrors CM1-CM4; The negative electrode of the memristor MR1, the output end of the current mirror CM3 and the output end M of the negative resistance generating circuit are connected; the negative electrode of the memristor MR2, the output end of the current mirror CM4 and the output end N of the negative resistance generating circuit are connected; the positive electrode of the memristor MR1, the output end of the current mirror CM1 and the in-phase output end P of the source-coupled differential pair circuit are connected; the positive electrode of the memristor MR2, the output end of the current mirror CM2 and the inverting output end Q of the source-coupled differential pair circuit are connected; the source-coupled differential pair circuit is connected to the input differential signal V ip and V in Connected.

2. The memristor-based gain and phase adjustable amplifier according to claim 1, characterized in that: Further comprising switches S1-S5; The two ends of switch S1 are connected to the pulse programming input signal V pro and the output terminal N of the negative resistance generating circuit; the two ends of the switch S2 are respectively connected to the two output terminals M and N of the negative resistance generating circuit; the two ends of the switch S3 are respectively connected to the reset input signal V res The two ends of switch S4 are respectively connected to the in-phase output terminal P and the inverting output terminal Q of the source-coupled differential pair circuit; the two ends of switch S5 are respectively connected to the inverting output terminal Q of the source-coupled differential pair circuit and the ground V ss .

3. The memristor-based gain and phase adjustable amplifier according to claim 1, characterized in that: It further includes a load resistor R L ; Load resistance R L The two ends are respectively connected to the in-phase output terminal P of the source-coupled differential pair circuit and the inverting output terminal Q of the source-coupled differential pair circuit.

4. The memristor-based gain and phase adjustable amplifier according to claim 1, characterized in that: The output source current or sink current of the current mirror CM1, the current mirror CM2, the current mirror CM3 and the current mirror CM4 is equal to the single-side static current of the source-coupled differential pair circuit.

5. The memristor-based gain and phase adjustable amplifier according to claim 1, characterized in that: Current mirrors CM1 and CM2 are both PMOS current mirrors; current mirrors CM3 and CM4 are both NMOS current mirrors.

6. A memristor-based gain and phase adjustable amplifier according to claim 1 or 5, characterized in that: The structures of current mirrors CM1 and CM2 are exactly the same, where: The current mirror CM1 is composed of PMOS tube M1, PMOS tube M2, PMOS tube M3 and resistor R1; the source of PMOS tube M1 and the source of PMOS tube M2 are connected to the power supply V at the same time. dd The drain of the PMOS tube M1 is connected to the source of the PMOS tube M3; the gate of the PMOS tube M1, the gate and drain of the PMOS tube M2, the gate of the PMOS tube M3 and one end of the resistor R1 are connected; the other end of the resistor R1 is grounded V ss ; The drain of the PMOS tube M3 forms the output end of the current mirror CM1; The current mirror CM2 is composed of PMOS tube M4, PMOS tube M5, PMOS tube M6 and resistor R2; the source of PMOS tube M4 and the source of PMOS tube M5 are connected to the power supply V at the same time. dd The drain of the PMOS tube M4 is connected to the source of the PMOS tube M6; the gate of the PMOS tube M4, the gate and drain of the PMOS tube M5, the gate of the PMOS tube M6 and one end of the resistor R2 are connected; the other end of the resistor R2 is grounded V ss ; The drain of the PMOS tube M6 forms the output end of the current mirror CM2.

7. The memristor-based gain and phase adjustable amplifier according to claim 1 or 5, characterized in that: The structures of current mirrors CM3 and CM4 are exactly the same, where: The current mirror CM3 is composed of NMOS tubes M7, M8, M9 and resistor R3; one end of resistor R3 is connected to the power supply V dd The other end of the resistor R3, the gate of the NMOS tube M7, the gate of the NMOS tube M8, and the gate and drain of the NMOS tube M9 are connected; the source of the NMOS tube M7 and the drain of the NMOS tube M8 are connected; the source of the NMOS tube M8 and the source of the NMOS tube M9 are grounded at the same time V ss ; The drain of NMOS tube M7 forms the output end of current mirror CM3; The current mirror CM4 is composed of NMOS tube M 10 、NMOS tube M 11 、NMOS tube M 12 and resistor R4; one end of resistor R4 is connected to power supply V dd ; The other end of resistor R4, NMOS tube M 10 The gate of NMOS tube M 11 The gate of the NMOS tube M 12 The gate and drain of NMOS tube M are connected; 10 The source and NMOS tube M 11 The drain of NMOS tube M 11 The source and NMOS tube M 12 The source of V ss ; NMOS tube M 10 The drain of forms the output terminal of current mirror CM4.

8. The memristor-based gain and phase adjustable amplifier according to claim 1, characterized in that: The negative resistance generating circuit is composed of PMOS tube M 13 And PMOS tube M 14 Composition: PMOS tube M 13 The source and PMOS tube M 14 The source of dd ; PMOS tube M 13 The drain and PMOS tube M 14 After the gate of the PMOS tube is connected, an output terminal M of the negative resistance generating circuit is formed; 14 The drain and PMOS tube M 13 After being connected to the gate of , another output terminal N of the negative resistance generating circuit is formed.

9. The memristor-based gain and phase adjustable amplifier according to claim 1, characterized in that: The source coupling differential pair circuit is composed of NMOS tube M 15 、NMOS tube M 16 and NMOS tube M 17 Composition: NMOS tube M 15 The gate is connected to the input differential signal V ip ; NMOS tube M 16 The gate is connected to the input differential signal V in ; NMOS tube M 15 The drain of the NMOS tube M forms the in-phase output terminal P of the source-coupled differential pair circuit; 16 The drain of the NMOS tube M forms the inverting output terminal Q of the source-coupled differential pair circuit; 15 The source of NMOS tube M 16 The source and NMOS tube M 17 The drain of NMOS tube M 17 The drain of NMOS tube M is connected to the input bias voltage V2; 17 The source of the grounded V ss .

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