Synchronous rectification control circuit and voltage converter

Abstract

Disclosed are a synchronous rectification control circuit and a voltage converter. The voltage converter includes the synchronous rectification control circuit. The synchronous rectification control circuit provides a synchronous rectifier tube preparatory conduction signal and a synchronous rectifier tube conduction control signal. The two signals act together on the conduction control of the synchronous rectifier tube. The synchronous rectifier tube conduction control signal prohibits the conduction of the synchronous rectifier tube during the parasitic oscillation time, thereby avoiding the misconduction of the synchronous rectifier tube during the parasitic oscillation time, improving the synchronous rectification effect, and improving the power supply efficiency of the voltage converter.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a synchronous rectification control circuit and a voltage converter. Background Art

[0002] Flyback voltage converter (power converter) such as Figure 1 As shown, it includes a primary circuit and a secondary circuit, the primary circuit and the secondary circuit are isolated by a transformer T, the primary circuit includes a primary switch Q in the electrical loop, and the energy can be transferred to the secondary circuit through the switching action of the primary switch Q, and the secondary circuit includes an output capacitor C0 connected in series with the secondary side of the transformer T and a synchronous rectifier SR arranged between the secondary side of the transformer T and the output capacitor C0, and the two ends of the output capacitor are connected to the load. Among them, in order to improve the efficiency of the power supply, the synchronous rectifier of the secondary side usually adopts a synchronous rectifier with a lower resistance than a diode or a body diode and a low loss in the synchronous conduction state, and a high-efficiency rectification function is achieved by timely controlling the conduction and shutdown of the synchronous rectifier.

[0003] Among them, for the voltage-controlled synchronous rectifier, the turn-on time point of the synchronous rectifier is generally determined by detecting the drain-source voltage Vds of the synchronous rectifier SR, such as Figure 2 As shown, when it is detected that Vds is less than the second threshold voltage Vth2, it is considered that the body diode of the synchronous rectifier has been turned on, and the synchronous rectifier can be controlled to be turned on.

[0004] In the prior art, when the circuit operates in the DCM (Discontinuous Conduction Mode) mode, the circuit will generate parasitic oscillations, and the parasitic oscillations may also cause the body diode of the synchronous rectifier SR to turn on, thereby misleadingly turning on the synchronous rectifier SR under the parasitic oscillation. Figure 2 As shown, in the prior art, the PWM (Pulse Width Modulation) signal corresponds to controlling the conduction of the synchronous rectifier SR, and a Blank signal is set after the PWM signal. The Blank signal corresponds to the parasitic oscillation time, and controls the synchronous rectifier SR to maintain the shutdown to prevent the synchronous rectifier SR from being mis-conducted. However, if the power supply needs to be compatible with CCM (Continuous Conduction Mode), QR (quasi-resonant) mode and DCM operation, the blank time of the Blank signal will prevent the normal conduction of the synchronous rectifier SR in the QR and CCM working modes, thereby reducing the power supply efficiency. Summary of the invention

[0005] In view of the above problems, an object of the present invention is to provide a synchronous rectification control circuit and a voltage converter, so as to improve the synchronous rectification effect and improve the power supply efficiency.

[0006] According to one aspect of the present invention, a synchronous rectification control circuit is provided, comprising a synchronous rectifier tube drain-source voltage access terminal and a synchronous rectifier tube gate control signal output terminal, characterized in that it comprises:

[0007] A synchronous rectifier pre-conduction signal generating circuit, comprising an input terminal connected to the synchronous rectifier drain-source voltage access terminal, a third reference signal input terminal and a synchronous rectifier pre-conduction signal output terminal;

[0008] A first comparator, comprising an input terminal connected to the drain-source voltage access terminal of the synchronous rectifier, a first reference signal input terminal and a first comparison signal output terminal;

[0009] A logic circuit, comprising a first input terminal connected to the first comparison signal output terminal, a second input terminal and a synchronous rectifier conduction control signal output terminal;

[0010] A second comparator comprises an input terminal connected to the drain-source voltage access terminal of the synchronous rectifier, a second reference signal input terminal and a second comparison signal output terminal;

[0011] A delay invalidation circuit, comprising an input terminal and an output terminal connected to the first comparison signal;

[0012] A first logic gate circuit comprises a first input terminal connected to the output terminal of the delay invalidation circuit, a second input terminal connected to the second comparison signal output terminal, and an output terminal connected to the reset terminal of the second trigger;

[0013] The second logic gate circuit includes a first input terminal connected to the synchronous rectifier preparatory conduction signal output terminal, a second input terminal connected to the synchronous rectifier conduction control signal output terminal, and an output terminal connected to the synchronous rectifier gate control signal output terminal.

[0014] The first reference signal level is greater than the third reference signal level, and the third reference signal level is greater than the second reference signal level.

[0015] Optionally, the logic circuit includes:

[0016] a pulse generator, comprising an input terminal and an output terminal connected to the first comparison signal output terminal;

[0017] A second trigger, wherein the set end of the second trigger is connected to the output end of the pulse generator, the output end of the second trigger is connected to the second input end of the second logic gate circuit, and the output end of the second trigger is the synchronous rectifier conduction control signal output end.

[0018] Optionally, the synchronous rectifier tube preparatory conduction signal generating circuit includes:

[0019] A third comparator comprises a non-inverting input terminal connected to the drain-source voltage access terminal of the synchronous rectifier, an inverting input terminal connected to the third reference signal input terminal, and a third comparison signal output terminal;

[0020] The first trigger is a reset dominant trigger, the reset end of the first trigger is connected to the third comparison signal output end, the set end is connected to the first comparison signal output end, and the output end is the synchronous rectifier tube preparatory conduction signal output end.

[0021] Optionally, the delay invalidation circuit includes:

[0022] A capacitor including a first terminal connected to the positive output terminal of the current source and a second terminal connected to ground;

[0023] a switch connected in parallel to both ends of the capacitor, the switch comprising a switch control end connected to the first comparison signal output end;

[0024] The fourth comparator comprises an input terminal connected to the first terminal of the capacitor, a fourth reference signal input terminal and an output terminal, and the output terminal of the fourth comparator is the output terminal of the delay invalidation circuit.

[0025] Optionally, the delay invalidation circuit further includes an inverter, and the inverter is connected in series between the first comparison signal output terminal and the switch control terminal;

[0026] The switch is an NMOS tube, and the gate of the NMOS tube is the switch control terminal.

[0027] Optionally, the fourth reference signal input terminal is connected to a fourth reference signal output terminal of an external fourth reference signal configuration circuit.

[0028] According to another aspect of the present invention, there is provided a voltage converter, characterized in that it comprises:

[0029] A transformer, comprising a primary circuit and a secondary circuit, wherein the secondary circuit comprises a synchronous rectifier tube;

[0030] According to the synchronous rectification control circuit provided by the present invention, the synchronous rectifier gate control signal output terminal is connected to the gate of the synchronous rectifier.

[0031] The synchronous rectification control circuit provided by the present invention provides a synchronous rectifier preparatory conduction signal and a synchronous rectifier conduction control signal, wherein the delay invalidation circuit, the second comparator and the first logic gate circuit judge the reduction speed of the synchronous rectifier drain-source level according to the relationship between the time for the synchronous rectifier drain-source voltage to decrease to the second reference signal level and the delay time, and then judge the conduction reason of the body diode of the synchronous rectifier, provide a synchronous rectifier conduction permission detection signal, and then provide a synchronous rectifier conduction control signal through the logic circuit, and control the conduction of the synchronous rectifier through the second logic gate circuit and the synchronous rectifier preparatory conduction signal, so as to effectively detect the conduction reason of the synchronous rectifier and prohibit the synchronous rectifier from mis-conduction within the parasitic oscillation time.

[0032] The voltage converter provided by the present invention includes the synchronous rectification control circuit provided by the present invention, and the synchronous rectification control circuit controls the conduction and shutdown of the synchronous rectifier tube of the secondary circuit of the voltage converter, which can avoid the misconduction of the synchronous rectifier tube when the secondary circuit of the voltage converter is in the parasitic oscillation time, thereby improving the power supply efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0034] Figure 1 A schematic diagram of the structure of a flyback voltage converter according to the prior art is shown;

[0035] Figure 2 A control signal timing diagram of a synchronous rectifier tube according to the prior art is shown;

[0036] Figure 3 A schematic structural diagram of a synchronous rectification control circuit according to an embodiment of the present invention is shown;

[0037] Figure 4 shows a working timing diagram of a pulse generator according to an embodiment of the present invention;

[0038] Figure 5 FIG. 4 shows a timing diagram of a synchronous rectification control circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0040] The term "connection" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conductive medium such as a conductor, wherein the electrical conductive medium may contain parasitic inductance or parasitic capacitance, or a connection through an intermediate circuit or component described in the embodiments in the specification; an indirect connection may also include a connection through other active or passive devices on the basis of achieving the same or similar functions, such as a connection through a circuit or component such as a signal amplification circuit.

[0041] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0042] Figure 3 A structural schematic diagram of a synchronous rectification control circuit according to an embodiment of the present invention is shown.

[0043] like Figure 3 As shown, the synchronous rectification control circuit 100 of the embodiment of the present invention includes a first comparator COMP1, a second comparator COMP2, a third comparator COMP3, a fourth comparator COMP4, a first trigger T1, a second trigger T2, a pulse generator 101, a first logic gate circuit 102, a second logic gate circuit 103, an inverter 104, a capacitor C1, a switch S1 and a current source I1, as well as an external reference value configuration circuit 105, a resistor Rcf and a synchronous rectifier drain-source voltage access terminal (not shown in the figure) for providing a synchronous rectifier drain-source voltage Vds. Among them, the first trigger T1 and the second trigger T2 can be reset dominant triggers, that is, when the reset terminal is 0 and invalid, its output state can be set by the set terminal.

[0044] The inverting input terminal of the first comparator COMP1 is connected to the synchronous rectifier drain-source voltage access terminal to receive the synchronous rectifier drain-source voltage Vds, the non-inverting input terminal receives the first reference signal Vth1, and the output terminal outputs the first comparison signal CU1.

[0045] The inverting input terminal of the second comparator COMP2 is connected to the synchronous rectifier drain-source voltage access terminal to receive the synchronous rectifier drain-source voltage Vds, the non-inverting input terminal receives the second reference signal Vth2, and the output terminal outputs the second comparison signal CU2.

[0046] The non-inverting input terminal of the third comparator COMP3 is connected to the drain-source voltage access terminal of the synchronous rectifier, receives the drain-source voltage Vds of the synchronous rectifier, the inverting input terminal receives the third reference signal Vth3, the output terminal is connected to the set terminal S of the first trigger, and provides the first reset signal T1R (third comparison signal).

[0047] Among them, Vth1>0>Vth3>Vth2.

[0048] The set terminal S of the first trigger T1 is connected to the output terminal of the first comparator COMP1, the reset terminal R is connected to the output terminal of the third comparator COMP3, and the output terminal Q provides a first control signal T1U (a synchronous rectifier preparatory conduction signal, the validity of which is a necessary condition for the conduction of the synchronous rectifier).

[0049] The input end of the pulse generator 101 is connected to the output end of the first comparator COMP1, and the output end is connected to the set end S of the second flip-flop T2. When the first comparison signal CU1 is valid, a narrow pulse is output to set and initialize the output state of the second flip-flop T2.

[0050] The reset terminal R of the second trigger T2 receives the second reset signal T2R, and the output terminal Q outputs the second control signal T2U (a synchronous rectifier conduction control signal, which corresponds to the shutdown of the synchronous rectifier when valid. In the present embodiment, the synchronous rectifier conduction control signal mainly controls the conduction and shutdown of the synchronous rectifier, that is, when the synchronous rectifier conduction control signal is valid, the synchronous rectifier is in the shutdown state regardless of whether the synchronous rectifier preparatory conduction signal is valid).

[0051] The first trigger T1 and the third comparator COMP3 constitute a synchronous rectifier pre-conduction signal generating circuit, which outputs a synchronous rectifier pre-conduction signal, which corresponds to a signal of a conventional synchronous rectifier control circuit for controlling the conduction of the synchronous rectifier, and which may mislead the synchronous rectifier during the parasitic oscillation time. The synchronous rectifier control circuit 100 of the embodiment of the present invention also provides a synchronous rectifier conduction control signal, limits the synchronous rectifier pre-conduction signal, and prohibits the conduction of the synchronous rectifier during the parasitic oscillation time.

[0052] In this embodiment, a logic circuit is formed by the second trigger T2 and the pulse generator 101. The first input terminal of the logic circuit is connected to the output terminal of the first comparator COMP1, the second input terminal is connected to the output terminal of the first logic gate circuit 102, and the output terminal provides a synchronous rectifier conduction control signal.

[0053] The input end of the inverter 104 is connected to the output end of the first comparator COMP1 to receive the first comparison signal CU1, and the output end is connected to the switch control end of the switch S1 to control the on and off of the switch S1. In this embodiment, the switch S1 can be selected as an NMOS (N-Metal-Oxide-Semiconductor) tube, which has a fast switch response speed.

[0054] The first end of the capacitor C1 is connected to the positive output end of the current source I1, and the second end is grounded. The switch S1 is connected in parallel to both ends of the capacitor C1. By controlling the on and off of the switch S1, the charging and discharging of the capacitor C1 is controlled, and a ramp voltage Vramp is provided at the first end of the capacitor C1.

[0055] The first end of the capacitor C1 is connected to the inverting input of the fourth comparator COMP4. The non-inverting input of the fourth comparator COMP4 is connected to the reference value configuration circuit 105 to receive the fourth reference signal Vth_conf. The output of the fourth comparator COMP4 provides a fourth comparison signal CU4.

[0056] Among them, one end of the external reference value configuration circuit 105 provides a fourth reference signal Vth_conf, and the other end is grounded through a resistor Rcf. Its internal circuit may include a variable resistor, which is connected in series with the resistor Rcf between a voltage source and the ground. The fourth reference signal Vth_conf is provided at its intermediate node, and the level value of the fourth reference signal Vth_conf can be adjusted. By comparing with the ramp voltage Vramp, the effective time node of the fourth comparison signal CU4 can be changed, and the delay time of the delay invalidation circuit (the output signal is invalid to 0 after the delay time) composed of the switch S1, the capacitor C1, the current source I1, the inverter 104 and the fourth comparator COMP4 can be changed.

[0057] The output ends of the fourth comparator COMP4 and the second comparator COMP2 are respectively connected to the first input end and the second input end of the first logic gate circuit 102 (first AND logic gate circuit), and the output end of the first logic gate circuit 102 is connected to the reset end R of the second flip-flop T2, providing a second reset signal T2R (i.e., a synchronous rectifier conduction permission detection signal). In this embodiment, the first logic gate circuit 102 is an AND gate, and when the fourth comparison signal CU4 and the second comparison signal CU2 are both 1, the second reset signal T2R is valid, and the second control signal T2U provided by the output end of the second flip-flop T2 is a high level 1. In this article, a high level can be represented as 1 (valid), and a low level can be represented as 0 (invalid).

[0058] The output terminal Q of the first trigger T1 is connected to the first input terminal of the second logic gate circuit 103 (the second AND logic gate circuit), the output terminal Q of the second trigger T2 is inverted and connected to the second input terminal (the inverting input terminal, the input signal is inverted and performs AND logic with the input signal of the first input terminal) of the second logic gate circuit 103, the output terminal of the second logic gate circuit 103 is connected to the gate of the synchronous rectifier SR, and the synchronous rectifier gate control signal SR Gate is provided. In this embodiment, the second logic gate circuit 103 is an AND gate. When the first control signal T1U is 1 and the second control signal T2U is 0, the synchronous rectifier gate control signal SR Gate is 1, and the synchronous rectifier SR is turned on.

[0059] Figure 4 FIG. 4 shows a working timing diagram of a pulse generator according to an embodiment of the present invention.

[0060] like Figure 4 As shown, the pulse generator 101 of the embodiment of the present invention outputs a narrow pulse at the rising edge of its input signal, wherein the width of the narrow pulse is smaller than the delay time.

[0061] Figure 5 FIG. 4 shows a timing diagram of a synchronous rectification control circuit according to an embodiment of the present invention.

[0062] like Figure 5 As shown, t1 to t3 is the first time, during which the body diode of the synchronous rectifier is normally turned on, and Vds is reduced from Vth1 to Vth2; t8 to t11 is the second time, during which the body diode of the synchronous rectifier is turned on due to parasitic oscillation, and Vds is reduced from Vth1 to Vth2; the time from t1 to t4 is the same as the time from t8 to t10, which is the delay time.

[0063] During the time from t2 to t6 and from t9 to t13, Vds is less than Vth3, and the T1R signal is invalid and is 0. During the other time periods, the T1R signal is valid and is 1. During the time from t1 to t7 and from t8 to t13, Vds is less than Vth1, and the CU1 signal is valid and is 1. The first trigger T1 can be a reset dominant trigger. When the T1R signal is invalid and CU1 is valid, the first control signal T1U at the output end is valid and is 1, that is, the first control signal T1U is valid and is 1 during the time from t2 to t6 and from t9 to t13, and can control the synchronous rectifier to be turned on.

[0064] At time t1, the rising edge of the CU1 signal changes to 1, the pulse generator 101 outputs a narrow pulse, the output terminal of the second trigger T2 is set to 1, and the second control signal T2U is 1; the capacitor C1 starts to charge, and at time t4, the capacitor C1 is charged so that the ramp voltage Vramp provided by the first terminal reaches the level value of the fourth reference signal Vth_conf, and the CU4 signal changes from 1 to 0; Vds drops to Vth2 at time t3, the CU2 signal changes to 1 at time t3, and is 1 from time t3 to t5. Time t3 is before time t4, so that from time t3 to t4, the first input of the first logic gate circuit is The input terminal and the second input terminal are 1 at the same time, and the T2R signal is 1 during the time from t3 to t4, and the output terminal of the second trigger T2 can be reset to 0, that is, during the time from t3 to t4, the second control signal T2U is reset to 0, and this state is maintained until t8 when the CU1 signal generates a rising edge, the T2S signal is valid, and the second control signal T2U is set to 1 again. The second control signal T2U is inverted and connected to the two input terminals of the second logic gate circuit with the first control signal T1U, so that the two input terminals of the second logic gate circuit are simultaneously valid during the time from t3 to t6, and the output is the synchronous rectifier gate control signal SR Gate that is valid as 1, which controls the synchronous rectifier to be turned on during the time from t3 to t6.

[0065] At time t7 , the CU1 signal changes to 0, the switch S1 is turned on, the first end of the capacitor C1 is grounded through the turned-on switch S1 , the ramp voltage Vramp changes to 0, and the CU4 signal changes to 1.

[0066] At time t8, Vds is in a parasitic oscillation state and Vds decreases to Vth1, CU1 becomes 1, the pulse generator outputs a narrow pulse, the switch S1 is disconnected, the capacitor C1 starts to charge, the Vramp voltage starts to rise, and the T2S signal is briefly set to 1, and the second control signal T2U at the output end of the second trigger T2 is set to 1.

[0067] After the delay time, at t10, Vramp rises to the level of the fourth reference signal Vth_conf, CU4 becomes 0, this is the parasitic oscillation time, Vds decreases slowly from Vth1 to Vth2, that is, at t10, Vds has not yet decreased to Vth2, CU2 signal is 0, to t11, Vds decreases to Vth2, CU2 is 1, to t12, Vds rises to Vth2, CU2 becomes 0, that is, CU4 signal t7 to t 10, and CU2 is 1 during the subsequent t11 ​​to t12 time, CU2 and CU4 are not 1 at the same time, so that the T2R signal is 0 during the time from t7 to t13, and the second control signal T2U is not reset to 0 during the time from t7 to t13, but maintained at 1, so that the inverted signal of the second control signal T2U is 0 during the time from t7 to t13, and is not 1 at the same time as the first control signal T1U during the time from t9 to t13, and the synchronous rectifier gate control signal SR Gate is not 1 during the time from t9 to t13, and maintains the disconnected state, thereby avoiding the misleading turn-on of the synchronous rectifier during the parasitic oscillation time.

[0068] The synchronous rectification control circuit of the embodiment of the present invention provides a first control signal T1U, which corresponds to the turn-on time of a conventional synchronous rectifier when the first control signal T1U is valid; provides a second control signal T2U, which corresponds to the turn-off of the synchronous rectifier when the second control signal T2U is valid; the inverted signals of the first control signal T1U and the second control signal T2U are connected to the two input ends of the AND gate, and when the first control signal T1U is valid and the second control signal T2U is invalid, a high-level synchronous rectifier gate control signal SR Gate is output to turn on the synchronous rectifier; and a delay time is set, and the delay time starts when Vds decreases to Vth1 and ends when Vramp increases to the level of the fourth reference signal Vth_conf. Among them, when the delay starts, the second control signal T2U is initialized to 1 (valid). If Vds decreases to Vth2 within the delay time, it is judged that the body diode of the synchronous rectifier is normally turned on. When Vds decreases to Vth2, the first control signal T1U is reset to 0 (invalid), and the synchronous rectifier is turned on. If Vds does not decrease to Vth2 within the delay time, it is judged that the body diode of the synchronous rectifier is turned on by parasitic oscillation. When the delay time starts, the second control signal T2U is initialized to 1. Before the delay time ends, the second control signal T2U is not reset and maintained at 1. The delay start time is between Vds decreasing to Vth3, that is, before the effective time of the first control signal T1U during the parasitic oscillation time, which can avoid the misconduction of the synchronous rectifier during the parasitic oscillation time.

[0069] Among them, during the delay time, when the fourth comparison signal CU4 is 1 and Vds is less than Vth2, the second comparison signal CU2 is 1, and the fourth comparison signal CU4 and the second comparison signal CU2 are subjected to AND logic through the first logic gate circuit 102 to obtain the second reset signal T2R. When Vds decreases to Vth2 during the delay time, the second reset signal T2R is valid, and the second control signal T2U is reset to 0. When Vds decreases to Vth2 after the delay time, the second reset signal T2R continues to be invalid to 0, and the second control signal T2U maintains the initial valid 1, thereby providing the second control signal T2U. That is, the second control signal is first set to 1 during the delay time, and then the detection of the cause of the conduction of the body diode of the synchronous rectifier tube is completed during the delay time, and it is determined whether to reset the second control signal to 0 according to the detection result.

[0070] The synchronous rectification control circuit of the present invention detects the time when the synchronous rectifier tube decreases from the first reference signal to the second reference signal, sets the delay time as the threshold time when the synchronous rectifier tube decreases from the first reference signal to the second reference signal, provides a narrow pulse to initialize the second control signal to 1 when the drain-source voltage of the synchronous rectifier tube decreases to the first reference signal, and when the drain-source voltage of the synchronous rectifier tube is less than the second reference signal, the second comparison signal is 1, and within the delay time, the fourth comparison signal is 1, and the second comparison signal and the fourth comparison signal are executed with logic to provide a second reset signal, and when the effective time of the second comparison signal and the fourth comparison signal have an intersection, the body diode of the corresponding synchronous rectifier tube is normally turned on, so that the second control signal is invalid, and within the invalid time of the second control signal, the synchronous rectifier tube can be turned on within the effective time of the first control signal; when the effective time of the second comparison signal and the fourth comparison signal has no intersection, the body diode of the corresponding synchronous rectifier tube is turned on due to parasitic oscillation, so that the second control signal remains valid, and the synchronous rectifier tube remains turned off within the time when the first control signal is valid and the second control signal is valid, thereby avoiding the mis-conduction of the synchronous rectifier tube within the parasitic oscillation time.

[0071] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "in-phase" and "inverted" in the above-mentioned logic controls can be interchanged or changed with each other, and the same function or purpose as the above-mentioned embodiment can be achieved by adjusting the subsequent logic controls.

[0072] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A synchronous rectification control circuit, comprising a synchronous rectifier drain-source voltage access terminal and a synchronous rectifier gate control signal output terminal, characterized in that: include: A synchronous rectifier pre-conduction signal generating circuit, comprising an input terminal connected to the synchronous rectifier drain-source voltage access terminal, a third reference signal input terminal and a synchronous rectifier pre-conduction signal output terminal; A first comparator, comprising an input terminal connected to the drain-source voltage access terminal of the synchronous rectifier, a first reference signal input terminal and a first comparison signal output terminal; A logic circuit, comprising a first input terminal connected to the first comparison signal output terminal, a second input terminal and a synchronous rectifier conduction control signal output terminal; A second comparator comprises an input terminal connected to the drain-source voltage access terminal of the synchronous rectifier, a second reference signal input terminal and a second comparison signal output terminal; A delay invalidation circuit, comprising an input terminal and an output terminal connected to the first comparison signal; A first logic gate circuit, comprising a first input terminal connected to the output terminal of the delay invalidation circuit, a second input terminal connected to the second comparison signal output terminal, and a synchronous rectifier tube conduction permission detection signal output terminal, wherein the synchronous rectifier tube conduction permission detection signal output terminal is connected to the second input terminal of the logic circuit; A second logic gate circuit comprises a first input terminal connected to the synchronous rectifier preparatory conduction signal output terminal, a second input terminal connected to the synchronous rectifier conduction control signal output terminal, and an output terminal connected to the synchronous rectifier gate control signal output terminal; The first reference signal level is greater than the third reference signal level, and the third reference signal level is greater than the second reference signal level. The synchronous rectifier preparatory conduction signal generating circuit comprises a third comparator and a first trigger, wherein the third comparator comprises a non-inverting input terminal connected to the synchronous rectifier drain-source voltage access terminal, an inverting input terminal connected to the third reference signal input terminal, and a third comparison signal output terminal, wherein the first trigger is a reset dominant trigger, wherein the reset terminal of the first trigger is connected to the third comparison signal output terminal, the set terminal is connected to the first comparison signal output terminal, and the output terminal is the synchronous rectifier preparatory conduction signal output terminal, The logic circuit includes a pulse generator and a second trigger, wherein the pulse generator includes an input terminal and an output terminal connected to the first comparison signal output terminal, a set terminal of the second trigger is connected to the output terminal of the pulse generator, a reset terminal of the second trigger is connected to the synchronous rectifier conduction permission detection signal output terminal, an output terminal of the second trigger is inverted and connected to the second input terminal of the second logic gate circuit, and an output terminal of the second trigger is a synchronous rectifier conduction control signal output terminal. The delay invalidation circuit includes a capacitor, a switch and a fourth comparator. The capacitor includes a first end connected to the positive output end of the current source and a second end connected to the ground. The switch is connected in parallel with the two ends of the capacitor. The switch includes a switch control end connected to the first comparison signal output end. The fourth comparator includes an input end connected to the first end of the capacitor, a fourth reference signal input end and an output end. The output end of the fourth comparator is the output end of the delay invalidation circuit.

2. The synchronous rectification control circuit according to claim 1, characterized in that: The delay invalidation circuit further includes an inverter, which is connected in series between the first comparison signal output terminal and the switch control terminal; The switch is an NMOS tube, and the gate of the NMOS tube is the switch control terminal.

3. The synchronous rectification control circuit according to claim 1, characterized in that: The fourth reference signal input terminal is connected to a fourth reference signal output terminal of an external fourth reference signal configuration circuit.

4. A voltage converter, characterized in that: include: A transformer, comprising a primary circuit and a secondary circuit, wherein the secondary circuit comprises a synchronous rectifier tube; According to the synchronous rectification control circuit according to any one of claims 1 to 3, the synchronous rectifier gate control signal output terminal is connected to the gate of the synchronous rectifier.

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