Interface circuit and interface circuit system

Abstract

The present application provides an interface circuit and an interface circuit system, the interface circuit comprising: a high-frequency blocker for blocking high-frequency signals; a low-frequency blocker for blocking low-frequency signals; a signal switcher, the input end of the signal switcher is connected to a physical port, the first output end of the signal switcher is connected to the high-frequency blocker, and the second output end of the signal switcher is connected to the low-frequency blocker. By arranging the signal switcher, the high-frequency blocker and the low-frequency blocker in the interface circuit, the low-frequency signal and the high-frequency signal are output from the low-frequency signal output end and the high-frequency signal output end respectively, so that the low-frequency signal and the high-frequency signal can share a physical port input interface circuit, thereby reducing the volume of the interface circuit.

Description

Technical Field

[0001] The present application relates to the field of signal processing, and in particular, to an interface circuit and an interface circuit system. Background Art

[0002] CVBS and SDI signals are often used in the field of video communication. CVBS is a widely used traditional image data transmission standard that transmits data in an analog waveform. The frequency range of CVBS is relatively low, and the signal frequency range is within 6MHz. SDI is a digital component serial interface. According to different rates, it can be divided into: standard definition SD-SDI, high definition standard HD-SDI and 3G-SDI, with corresponding rates of 270Mb / s, 1.485Gb / s and 2.97Gb / s respectively.

[0003] In the field of video communication, since the frequency ranges of CVBS signals and SDI signals are different, in order to ensure the receiving sensitivity of the signals, the physical ports of the two are set independently. The two independent physical ports will cause the interface circuit to be larger in size, which will cause the device equipped with the interface circuit to be larger in size, which is not conducive to the miniaturization of the device. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide an interface circuit and an interface circuit system to reduce the size of the interface circuit.

[0005] In a first aspect, an embodiment of the present application provides an interface circuit, comprising: a high-frequency blocker for blocking high-frequency signals; a low-frequency blocker for blocking low-frequency signals; a signal switcher, wherein an input end of the signal switcher is connected to a physical port, a first output end of the signal switcher is connected to the high-frequency blocker, and a second output end of the signal switcher is connected to the low-frequency blocker; the signal switcher is used to output the low-frequency signal from the first output end to the high-frequency blocker when a low-frequency signal is input to the input end, so that the low-frequency signal is output from the low-frequency output end of the interface circuit; and when a high-frequency signal is input to the input end, the high-frequency signal is output from the second output end to the low-frequency blocker, so that the high-frequency signal is output from the high-frequency output end of the interface circuit.

[0006] By setting a signal switch, a high-frequency blocker and a low-frequency blocker in the interface circuit, the low-frequency signal and the high-frequency signal are output from the low-frequency signal output terminal and the high-frequency signal output terminal respectively, so that the low-frequency signal and the high-frequency signal can share a physical port input interface circuit, thereby reducing the volume of the interface circuit.

[0007] In an optional implementation, the interface circuit further includes: a controller; the controller is connected to the control end of the signal switch.

[0008] In an optional embodiment, the control end of the signal switch includes: a first control end and a second control end; the controller includes a first control circuit and a second control circuit, the first control circuit is connected to the first control end, and the second control circuit is connected to the second control end.

[0009] In an optional embodiment, the first control circuit includes: a first control signal input terminal, a first voltage input terminal, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a first transistor and a second transistor; the first voltage input terminal is connected to the base of the first transistor via the first resistor, one end of the third resistor is connected between the first resistor and the base of the first transistor, and the other end is grounded; the first voltage input terminal is connected to the collector of the first transistor via the second resistor, and the second resistor is also connected to the collector of the second transistor; the emitter of the first transistor is connected to the fourth resistor and then grounded; the first capacitor is connected between the collector and the emitter of the second transistor, and the emitter of the second transistor is grounded; the first control signal input terminal is connected to the base of the second transistor via the fifth resistor.

[0010] In an optional embodiment, the second control circuit includes: a second control signal input terminal, a second voltage input terminal, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a second capacitor, a third transistor and a fourth transistor; the second voltage input terminal is connected to the base of the third transistor via the sixth resistor, one end of the eighth resistor is connected between the sixth resistor and the base of the third transistor, and the other end is grounded; the second voltage input terminal is connected to the collector of the third transistor via the seventh resistor, and the seventh resistor is also connected to the collector of the fourth transistor; the emitter of the third transistor is connected to the ninth resistor and then grounded; the second capacitor is connected between the collector and the emitter of the fourth transistor, and the emitter of the fourth transistor is grounded; the second control signal input terminal is connected to the base of the fourth transistor via the tenth resistor.

[0011] In an optional implementation, the high-frequency signal is one of an SDI signal, an H-SDI signal or a 3G-SDI signal; and the low-frequency signal is a CVBS signal.

[0012] In an optional implementation, the high-frequency blocker is an inductor, and the inductance value of the inductor is greater than 2.7uH.

[0013] In an optional implementation, the low-frequency blocker is a capacitor, and the capacitance value of the capacitor is less than 10PF.

[0014] In an optional implementation, the lowest signal passing frequency of the signal switch is 0 Hz, and the highest signal passing frequency is greater than 3 GHZ.

[0015] In a second aspect, an embodiment of the present application provides an interface circuit system, which includes: a high-frequency signal processing circuit, a low-frequency signal processing circuit, and an interface circuit as described in any of the foregoing embodiments; the high-frequency signal processing circuit is connected to the high-frequency output end of the interface circuit, and the low-frequency signal processing circuit is connected to the low-frequency output end of the interface circuit.

[0016] In an optional implementation, the high-frequency signal processing circuit is an SDI transmitting circuit or an SDI receiving circuit, and the low-frequency signal processing circuit is a CVBS transmitting circuit or a CVBS receiving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A structural block diagram of an interface circuit provided in an embodiment of the present application;

[0019] Figure 2 A circuit diagram of an interface circuit provided in an embodiment of the present application;

[0020] Figure 3 A structural block diagram of an interface circuit system provided in an embodiment of the present application.

[0021] Icon: 100 -interface circuit; 101 -signal switch; 102 -high frequency blocker; 103 -low frequency blocker; 104 -physical port; 105 -controller; 300 -interface circuit system; 301 -high frequency signal processing circuit; 302 -low frequency signal processing circuit. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0023] CVBS and SDI signals are often used in the field of video communication. CVBS is a widely used traditional image data transmission standard that transmits data in an analog waveform. The frequency range of CVBS is relatively low, and the signal frequency range is within 6MHz. SDI is a digital component serial interface. According to different rates, it can be divided into: standard definition SD-SDI, high definition standard HD-SDI and 3G-SDI, with corresponding rates of 270Mb / s, 1.485Gb / s and 2.97Gb / s respectively.

[0024] In the field of video communication, since the frequency ranges of CVBS signals and SDI signals are different, in order to ensure the receiving sensitivity of the signals, the physical ports of the two are set independently. Two independent physical ports will make the device bulky and is not conducive to the miniaturization of the device.

[0025] Based on this, an embodiment of the present application provides an interface circuit and an interface circuit system to solve the above problems.

[0026] See also Figure 1 , Figure 1 This is a structural block diagram of an interface circuit provided in an embodiment of the present application. The interface circuit 100 may include: a signal switch 101, a high-frequency blocker 102, and a low-frequency blocker 103.

[0027] Specifically, the input end of the signal switch 101 is connected to a physical port 104, the first output end of the signal switch 101 is connected to the high-frequency blocker 102, and the second output end of the signal switch 101 is connected to the low-frequency blocker 103. One end of the high-frequency blocker 102 is connected to the first output end of the signal switch 101, and the other end serves as the low-frequency output end of the interface circuit 100; one end of the low-frequency blocker 103 is connected to the second output end of the signal switch 101, and the other end serves as the high-frequency output end of the interface circuit 100.

[0028] The external signal is input into the interface circuit 100 through the physical port 104. When a low-frequency signal is input into the input end of the signal switch 101, the low-frequency signal is output from the first output end to the high-frequency blocker 102, so that the low-frequency signal is output from the low-frequency output end of the interface circuit 100; when a high-frequency signal is input into the input end, the high-frequency signal is output from the second output end to the low-frequency blocker 103, so that the high-frequency signal is output from the high-frequency output end of the interface circuit 100.

[0029] The signal switch 101 may be a single pole double throw switch (SPDT), a microwave switch, HMC284MS8G, HMC194MS8, etc., and this application does not impose any limitation on this.

[0030] Optionally, the high-frequency signal may be one of an SDI signal, an H-SDI signal or a 3G-SDI signal; and the low-frequency signal may be a CVBS signal. The two signals share a physical port 104 and are both input into the interface circuit 100 from the physical port 104 .

[0031] It should be noted that after the external signal is input into the interface circuit 100 through the physical port 104, if the external signal is a low-frequency signal, the signal switch 101 outputs the low-frequency signal from the first output terminal. Since the high-frequency blocker 102 only blocks high-frequency signals and does not process low-frequency signals. Therefore, the low-frequency signal passes through the high-frequency blocker 102 and is output from the low-frequency output terminal of the interface circuit 100. Considering that the isolation of the signal switch 101 is limited, a part of the low-frequency signal will be output from the second output terminal to the next stage circuit. A low-frequency blocker 103 is set at the second output terminal, and the low-frequency signal cannot pass through the low-frequency blocker 103, thereby making it impossible for the low-frequency signal to be output from the second output terminal to the next stage circuit. Similarly, when the external signal is a high-frequency signal, a part of the high-frequency signal will be output from the first output terminal, and a high-frequency blocker 102 is set at the first output terminal, and the high-frequency signal cannot pass through the high-frequency blocker 102, thereby making it impossible for the high-frequency signal to be output from the first output terminal to the next stage circuit.

[0032] By setting a signal switch, a high-frequency blocker and a low-frequency blocker in the interface circuit, the low-frequency signal and the high-frequency signal are output from the low-frequency signal output terminal and the high-frequency signal output terminal respectively, so that the low-frequency signal and the high-frequency signal can share a physical port input interface circuit, thereby reducing the volume of the interface circuit.

[0033] Optionally, in order to achieve good high-frequency blocking performance, the high-frequency blocker 102 may be an inductor, and the inductance of the inductor is greater than 2.7 uH.

[0034] Optionally, in order to achieve good low-frequency blocking performance, the low-frequency blocker 103 may be a capacitor, and the capacitance value of the capacitor is less than 10PF.

[0035] Optionally, in order to improve the applicability of the interface circuit 100 , the lowest signal passing frequency of the signal switch 101 is 0 Hz, and the highest signal passing frequency is greater than 3 GHz.

[0036] Optionally, the high-frequency signal may be one of an SDI signal, an H-SDI signal or a 3G-SDI signal; and the low-frequency signal may be a CVBS signal.

[0037] Optionally, the interface circuit 100 may further include a controller 105, which is connected to the control end of the signal switch 101. According to the input signal frequency, the controller 105 outputs a control signal to the control end of the signal switch 101 to control the signal switch 101 to output a high-frequency signal from the high-frequency output end and a low-frequency signal from the low-frequency output end.

[0038] The interface circuit 100 will be described in detail below with reference to a specific example.

[0039] See also Figure 2 , Figure 2 A circuit diagram of an interface circuit provided in an embodiment of the present application.

[0040] For example, in the embodiment of the present application, the signal switch 101 included in the interface circuit 100 is described as a chip of the HMC284MS8G model. It can be understood that the model of the signal switch 101 here is only an example, and the present application is not limited thereto.

[0041] like Figure 2 As shown, pin No. 3 (RFC) of the signal switch 101 is the input end of the signal switch 101 , which is connected to the physical port 104 , and the external signal is input into the signal switch 101 from pin No. 3 .

[0042] Pin 5 (RF1) of the signal switch 101 is a low frequency output terminal, connected to the inductor L1. The inductor L1 is a high frequency blocker 102. Pin 8 (RF2) of the signal switch 101 is a high frequency output terminal, connected to the capacitor C3. The capacitor C3 is a low frequency blocker 103.

[0043] Optionally, in order to achieve good high-frequency blocking performance, the inductance value of the inductor L1 is greater than 2.7uH. In order to achieve good low-frequency blocking performance, the capacitance value of the capacitor C1 is less than 10PF.

[0044] Pin 6 (GND1), pin 7 (GND2), and pin 9 (GND3) of the signal switch 101 are all grounded.

[0045] The control end of the signal switch 101 consists of a first control end and a second control end, wherein pin 1 (A) is the first control end and pin 2 (B) is the second control end.

[0046] The controller 105 includes a first control circuit and a second control circuit. The first control circuit is connected to the first control terminal, and the second control circuit is connected to the second control terminal.

[0047] Optionally, the first control circuit includes: a first control signal input terminal SWITCH_A, a first voltage input terminal POWER_IN, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a first transistor VT1, and a second transistor VT2.

[0048] The first voltage input terminal is connected to the base of the first transistor VT1 via a first resistor R1 with a resistance of 10KΩ, one end of a third resistor R3 with a resistance of 1KΩ is connected between the first resistor R1 and the base of the first transistor VT1, and the other end is grounded. The first voltage input terminal is connected to the collector of the first transistor VT1 via a second resistor R2 with a resistance of 1.5KΩ, and the second resistor R2 is also connected to the collector of the second transistor VT2. The emitter of the first transistor VT1 is connected to the fourth resistor R4 with a resistance of 120Ω and then grounded. The first capacitor C1 with a capacitance of 0.1uF is connected between the collector and emitter of the second transistor VT2, and the emitter of the second transistor VT2 is grounded. The first control signal input terminal is connected to the base of the second transistor VT2 via a fifth resistor R5 with a resistance of 4.7KΩ.

[0049] The fifth resistor R5 is a current limiting resistor to prevent the current input to the base of the second transistor VT2 from being too large. The first capacitor C1 is used to de-jitter (de-burr) the control signal input from the first control signal input terminal to the second transistor VT2. The first transistor VT1 and the second transistor VT2 are NPN transistors.

[0050] Optionally, the second control circuit includes: a second control signal input terminal SWITCH_B, a second voltage input terminal POWER_IN, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a second capacitor C2, a third transistor VT3, and a fourth transistor VT4.

[0051] The second voltage input terminal is connected to the base of the third triode VT3 via the sixth resistor R6 with a resistance of 10KΩ, one end of the eighth resistor R8 with a resistance of 1KΩ is connected between the sixth resistor R6 and the base of the third triode VT3, and the other end is grounded. The second voltage input terminal is connected to the collector of the third triode VT3 via the seventh resistor R7 with a resistance of 1.5KΩ, and the seventh resistor R7 is also connected to the collector of the fourth triode VT4. The emitter of the third triode VT3 is connected to the ninth resistor R9 with a resistance of 120Ω and then grounded. The second capacitor C2 with a capacitance of 0.1uF is connected between the collector and emitter of the fourth triode VT4, and the emitter of the fourth triode VT4 is grounded. The second control signal input terminal is connected to the base of the fourth triode VT4 via the tenth resistor R10 with a resistance of 4.7KΩ.

[0052] The tenth resistor R10 is a current limiting resistor to prevent the current input to the base of the fourth transistor VT4 from being too large. The second capacitor C2 is used to de-jitter (de-burr) the control signal input from the second control signal input terminal to the fourth transistor VT4. The third transistor VT3 and the fourth transistor VT4 are NPN transistors.

[0053] The two control terminals of the signal switch 101 require two voltages of 0V (low level) and 5V (high level) as control levels. When the external signal is a low-frequency signal, the first control circuit and the second control circuit of the controller 105 send control signals to the first control terminal and the second control terminal of the signal switch 101 respectively, so that the level of the No. 1 pin (A) of the signal switch 101 is a low level and the level of the No. 2 pin (B) of the signal switch 101 is a high level. At this time, the input terminal of the signal switch 101 is connected to the first output terminal and disconnected from the second output terminal, and the low-frequency signal is output from the first output terminal. When the external signal is a high-frequency signal, the first control circuit and the second control circuit of the controller 105 send control signals to the first control terminal and the second control terminal of the signal switch 101 respectively, so that the level of the No. 1 pin (A) of the signal switch 101 is a high level and the level of the No. 2 pin (B) of the signal switch 101 is a low level. At this time, the input end of the signal switch 101 is disconnected from the first output end and connected to the second output end, and the high-frequency signal is output from the second output end.

[0054] The low level voltage output by the commonly used single-chip microcomputer is 0V, and the high level voltage is 3.3V, which cannot meet the requirements of the control end of the signal switch 101. Therefore, it is necessary to convert the high level voltage 3.3V output by the single-chip microcomputer into 5V through the action of the first control circuit and the second control circuit to meet the requirements of the control end of the signal switch 101.

[0055] Taking the first control circuit as an example, when POWER_IN provides an input voltage of 5V, the voltage across the third resistor R3 is about 0.45V, which is less than the conduction voltage of the first transistor VT1, so VT1 is turned off, that is, VT1 is disconnected. In this case, when SWICH_A is at a high level (3.3V), VT2 is turned on and is in a saturated state. Since the collector and emitter voltages of VT2 are very small after VT2 reaches the saturated state and the emitter of VT2 is grounded, the level of pin 1 (A) of the signal switch 101 is 0V. When SWICH_A is at a low level (0V), VT2 is turned off, and pin 1 (A) of the signal switch 101 is pulled up to POWE_IN through R2. At this time, the level of pin 1 (A) is 5V.

[0056] When POWER_IN provides an input voltage of 12V, when SWICH_A is at a high level (3.3V), VT2 is turned on and is in a saturated state. Since the collector and emitter voltages of VT2 are very small after VT2 reaches a saturated state and the emitter of VT2 is grounded, the level of pin 1 (A) of the signal switch 101 is 0V. When SWICH_A is at a low level (0V), VT2 is cut off, that is, VT2 is disconnected. R1 and R3 divide the voltage of POWER_IN, and the voltage across R3 is greater than 0.7V, so VT1 is turned on. Due to the limitation of R1, VT1 is in a linear region. According to the characteristics of the transistor, it can be calculated that the collector of VT1 is 5V. At this time, the level of pin 1 (A) of the signal switch 101 is 5V.

[0057] For different input voltages, by controlling SWICH_A to output a high level or a low level, the control of pin 1 (A) of the signal switch 101 is realized. It can be understood that the structures of the first control circuit and the second control circuit are exactly the same. Therefore, the process of controlling SWICH_B to output a high level or a low level to realize the control of pin 2 (B) of the signal switch 101 is consistent with the above process, and is not repeated here to make the specification concise.

[0058] It should be noted that, in this embodiment, the specific values ​​of capacitors C1-C3 and resistors R1-R10 are not limited to the values ​​in this example, and the specific voltage values ​​of the input voltage of the first control circuit, the input voltage power supply of the first control circuit, and the control terminal level of the signal switch are not limited to the voltage values ​​used in the above examples. The specific selection of components such as signal switchers and transistors is not limited to the models used in the above examples. For example, the signal switcher can use HMC194MS8, etc., and the field effect transistor can use PNP transistors, etc., which should not be regarded as a limitation on this application.

[0059] Based on the same inventive concept, an interface circuit system is also provided in the embodiment of the present application. Figure 3 , Figure 3 This is a structural block diagram of an interface circuit system provided in an embodiment of the present application, wherein the interface circuit system 300 includes a high-frequency signal processing circuit 301, a low-frequency signal processing circuit 302, and the above-mentioned interface circuit 100. The high-frequency signal processing circuit 301 is connected to the high-frequency output terminal of the interface circuit 100, and the low-frequency signal processing circuit 302 is connected to the low-frequency output terminal of the interface circuit 100.

[0060] Optionally, when the high frequency signal is an SDI signal, the high frequency signal processing circuit may be an SDI transmitting circuit or an SDI receiving circuit. When the low frequency signal is a CVBS signal, the low frequency signal processing circuit may be a CVBS transmitting circuit or a CVBS receiving circuit.

[0061] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0062] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0063] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An interface circuit, characterized in that: include: High frequency blocker, used to block high frequency signals; Low frequency blocker, used to block low frequency signals; A signal switch, wherein an input end of the signal switch is connected to a physical port, a first output end of the signal switch is connected to the high-frequency blocker, and a second output end of the signal switch is connected to the low-frequency blocker; The signal switch is used for, when a low-frequency signal is input to the input end, outputting the low-frequency signal from the first output end to the high-frequency blocker, so that the low-frequency signal is output from the low-frequency output end of the interface circuit; when a high-frequency signal is input to the input end, outputting the high-frequency signal from the second output end to the low-frequency blocker, so that the high-frequency signal is output from the high-frequency output end of the interface circuit; The interface circuit further comprises: a controller; the controller is connected to the control end of the signal switch; Wherein, the control end of the signal switch includes: a first control end and a second control end; The controller comprises a first control circuit and a second control circuit, the first control circuit is connected to the first control terminal, and the second control circuit is connected to the second control terminal; Wherein, the first control circuit includes: a first control signal input terminal, a first voltage input terminal, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a first transistor and a second transistor; The first voltage input terminal is connected to the base of the first transistor via the first resistor, one end of the third resistor is connected between the first resistor and the base of the first transistor, and the other end is grounded; The first voltage input terminal is connected to the collector of the first transistor via the second resistor, and the second resistor is also connected to the collector of the second transistor; The emitter of the first transistor is connected to the fourth resistor and then grounded; The first capacitor is connected between the collector and the emitter of the second transistor, and the emitter of the second transistor is grounded; The first control signal input terminal is connected to the base of the second transistor via the fifth resistor; Wherein, the second control circuit includes: a second control signal input terminal, a second voltage input terminal, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a second capacitor, a third transistor and a fourth transistor; The second voltage input terminal is connected to the base of the third transistor via the sixth resistor, one end of the eighth resistor is connected between the sixth resistor and the base of the third transistor, and the other end is grounded; The second voltage input terminal is connected to the collector of the third transistor via the seventh resistor, and the seventh resistor is also connected to the collector of the fourth transistor; The emitter of the third triode is connected to the ninth resistor and then grounded; The second capacitor is connected between the collector and the emitter of the fourth transistor, and the emitter of the fourth transistor is grounded; The second control signal input terminal is connected to the base of the fourth transistor via the tenth resistor; Among them, the fifth resistor is used to prevent the current input into the base of the second transistor from being too large, and the first capacitor is used to deburr the control signal input from the first control signal input terminal to the second transistor; the tenth resistor is used to prevent the current input into the base of the fourth transistor from being too large, and the second capacitor is used to deburr the control signal input from the second control signal input terminal to the fourth transistor.

2. The interface circuit according to claim 1, characterized in that: The high-frequency signal is one of an SDI signal, an H-SDI signal or a 3G-SDI signal; and the low-frequency signal is a CVBS signal.

3. The interface circuit according to claim 1, characterized in that: The high-frequency blocker is an inductor, and the inductance value of the inductor is greater than 2.7uH; the low-frequency blocker is a capacitor, and the capacitance value of the capacitor is less than 10PF.

4. The interface circuit according to claim 1, characterized in that: The lowest signal passing frequency of the signal switch is 0 Hz, and the highest signal passing frequency is greater than 3 GHz.

5. An interface circuit system, characterized in that: The interface circuit system comprises: a high-frequency signal processing circuit, a low-frequency signal processing circuit and an interface circuit as claimed in any one of claims 1 to 4; The high-frequency signal processing circuit is connected to the high-frequency output end of the interface circuit, and the low-frequency signal processing circuit is connected to the low-frequency output end of the interface circuit.

6. The interface circuit system according to claim 5, characterized in that: The high-frequency signal processing circuit is an SDI transmitting circuit or an SDI receiving circuit, and the low-frequency signal processing circuit is a CVBS transmitting circuit or a CVBS receiving circuit.

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