Wafer, method for manufacturing the same, and semiconductor device

Abstract

The present disclosure relates to a wafer, a manufacturing method thereof, and a semiconductor device. The method for manufacturing the wafer includes: providing a wafer body, on which a saw street for dicing is provided; forming through-silicon vias for dicing in the saw street, and filling the through-silicon vias for dicing with a protective material to form a dicing line. By providing through-silicon vias filled with a protective material in the saw street, when the wafer is diced, the through-silicon vias for dicing are diced to prevent the dicing stress from damaging the die area. The through-silicon vias can effectively reduce the width of the saw street, which is beneficial to the miniaturization of the saw street and improves the effective utilization rate of the wafer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a wafer, a method for manufacturing the same, and a semiconductor device. Background Art

[0002] With the development and progress of technology, the integration degree of integrated circuit chips is getting higher and higher. Single-layer chips can no longer meet the usage requirements, and the application of multi-layer stacked chips is becoming more and more widespread. Stacked chips are obtained by cutting multi-layer stacked wafers.

[0003] The multi-layer stacked wafer includes a chip area and a cutting area. When cutting the cutting area, the chip area may be damaged due to the influence of cutting stress and the like. In order to ensure that the chip area is not damaged during cutting, a relatively large area of the cutting area is usually set. However, an overly large cutting area reduces the effective utilization rate of the wafer, thereby increasing the chip cost.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present disclosure is to provide a wafer, a method for manufacturing the same, and a semiconductor device, so as to at least to some extent overcome the problem of low effective utilization rate of the wafer caused by the relatively large area of the cutting area in the related art.

[0006] According to a first aspect of the present disclosure, there is provided a method for manufacturing a wafer, the method for manufacturing the wafer comprising:

[0007] Providing a wafer body, on which a scribe line for cutting is provided;

[0008] Forming a through-silicon via for cutting in the scribe line, and filling the through-silicon via for cutting with a protective material to form a cutting line.

[0009] According to an embodiment of the present disclosure, the forming a through-silicon via for cutting in the scribe line includes:

[0010] Forming a blind hole on the scribe line on a first surface of the wafer body;

[0011] Filling the blind hole with a protective material;

[0012] Thinning a second surface of the wafer body until the blind hole is exposed, the second surface being opposite to the first surface.

[0013] According to an embodiment of the present disclosure, the forming a through-silicon via for cutting in the scribe line includes:

[0014] Form a first through-silicon via (TSV) in the scribe line on the first wafer body;

[0015] Fill the first through-silicon via with a protective material;

[0016] Form a second through-silicon via at a position corresponding to the scribe line and the first through-silicon via on the second wafer body, and stack the first wafer body and the second wafer body;

[0017] Fill the second through-silicon via with the protective material.

[0018] According to an embodiment of the present disclosure, the through-silicon via includes continuously distributed through-silicon vias or discretely distributed through-silicon vias.

[0019] According to an embodiment of the present disclosure, multiple rows of through-silicon vias are formed in the scribe line.

[0020] According to an embodiment of the present disclosure, the width of the through-silicon via is 2 μm - 50 μm, and the depth of the through-silicon via is 15 μm - 150 μm.

[0021] According to an embodiment of the present disclosure, the protective material includes one or more of copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide, and tetraethyl orthosilicate.

[0022] According to an embodiment of the present disclosure, air gap holes are provided in the through-silicon via.

[0023] According to a second aspect of the present disclosure, there is provided a wafer, which includes:

[0024] A wafer body, on which a scribe line for cutting is provided;

[0025] Through-silicon vias, provided in the scribe line, and filled with a protective material.

[0026] According to an embodiment of the present disclosure, the through-silicon vias are formed in the scribe line and extend along the extension direction of the scribe line.

[0027] According to an embodiment of the present disclosure, the through-silicon via includes continuously distributed through-silicon vias or discretely distributed through-silicon vias.

[0028] According to an embodiment of the present disclosure, the scribe line forms multiple rows of through-silicon vias.

[0029] According to an embodiment of the present disclosure, the width of the through-silicon via is 2 μm - 50 μm, and the depth of the through-silicon via is 15 μm - 150 μm.

[0030] According to an embodiment of the present disclosure, the protective material includes one or more of copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide, and tetraethyl orthosilicate.

[0031] According to an embodiment of the present disclosure, an air gap hole is provided in the cut through-silicon via.

[0032] According to a third aspect of the present disclosure, a semiconductor device is provided, which includes multiple wafers as described above, and the multiple wafers are stacked.

[0033] The wafer manufacturing method provided by the present disclosure, by providing a cut through-silicon via filled with a protective material in the dicing street, when dicing the wafer, cutting the cut through-silicon via can prevent the cutting stress from damaging the die area. Through the cut through-silicon via, the width of the dicing street can be effectively reduced, which is beneficial to the miniaturization of the dicing street and improves the effective utilization rate of the wafer.

[0034] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0036] Figure 1 It is a flowchart of the first wafer manufacturing method provided for an exemplary embodiment of the present disclosure.

[0037] Figure 2 It is a flowchart of the second wafer manufacturing method provided for an exemplary embodiment of the present disclosure.

[0038] Figure 3 It is a flowchart of the third wafer manufacturing method provided for an exemplary embodiment of the present disclosure.

[0039] Figure 4 It is a top view schematic diagram of a wafer provided for an exemplary embodiment of the present disclosure.

[0040] Figure 5 It is a cross-sectional view schematic diagram of a wafer provided for an exemplary embodiment of the present disclosure.

[0041] Figures 6 to 9 It is a process diagram of forming a cut through-silicon via provided for an exemplary embodiment of the present disclosure.

[0042] Figures 10 to 11 Another process diagram for forming through - silicon vias by cutting provided for the exemplary embodiments of the present disclosure.

[0043] Figure 12 A schematic diagram of the distribution of through - silicon vias cut provided for the exemplary embodiments of the present disclosure.

[0044] Figure 13 A schematic diagram of cutting through - silicon vias provided for the exemplary embodiments of the present disclosure.

[0045] Figure 14 Another schematic diagram of the distribution of through - silicon vias cut provided for the exemplary embodiments of the present disclosure.

[0046] In the figure:

[0047] 100, wafer body; 110, die; 120, saw street; 200, through - silicon via cut; 210, blind hole; 230, first through - silicon via cut; 240, second through - silicon via cut; 250, air - gap hole; 20, protective material layer; 300, first wafer body; 400, second wafer body. Detailed implementation manners

[0048] Now, the exemplary embodiments will be described more comprehensively with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that this invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and thus their detailed descriptions will be omitted.

[0049] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the accompanying drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0050] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open - ended inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0051] In this exemplary embodiment, a wafer manufacturing method is first provided. As Figure 1 shown, the wafer manufacturing method may include the following steps:

[0052] Step S110: Provide a wafer body 100, on which a dicing street 120 for dicing is provided;

[0053] Step S120: Form a through-silicon via for dicing 200 in the dicing street 120, and the through-silicon via is filled with a protective material.

[0054] In the wafer manufacturing method provided by the embodiments of the present disclosure, by providing the through-silicon via for dicing 200 filled with a protective material in the dicing street 120, pre-dicing of the wafer is performed. When the wafer is diced, it is possible to prevent the dicing stress from damaging the die area 110. Through the through-silicon via for dicing 200, the width of the dicing street 120 can be effectively reduced, which is beneficial to the miniaturization of the dicing street 120 and improves the effective utilization rate of the wafer.

[0055] In step S110, the wafer body 100 may be divided into a dicing street 120 and a die area 110. When dicing, the dicing blade acts on the dicing street 120, and the die area 110 is reserved. The wafer body 100 may include a silicon substrate such as a silicon epitaxial wafer or silicon-on-insulator, or may be a substrate of other semiconductor materials such as GaN. Moreover, the substrate may be an intrinsic semiconductor substrate, or an N-type doped or P-type doped semiconductor substrate, and the embodiments of the present disclosure do not limit this. A dielectric layer may be provided on the substrate, and the material of the dielectric layer may be one or more of silicon oxide, silicon nitride, or silicon oxynitride. In specific implementation, the dielectric layer may be formed by methods such as chemical vapor deposition or atomic layer deposition. It can be understood that the dielectric layer may be a single insulating material layer, or may be a stack of multiple identical or different insulating material layers.

[0056] In a feasible implementation manner provided by the embodiments of the present disclosure, as Figure 2 shown, step S120 may include:

[0057] Step S210: Form a blind hole 210 in the dicing street 120 part of the first surface of the wafer body 100;

[0058] Step S220: Fill the blind hole 210 with a protective material;

[0059] Step S230: Thin the second surface of the wafer body 100 until the blind hole 210 is exposed, and the second surface and the first surface are opposite to each other.

[0060] In step S210, as Figure 6As shown in the figure, blind holes 210 are formed on the first surface of the wafer body 100 in the scribe lane 120. Among them, the blind holes 210 can be formed by dry etching, wet etching, laser etching or a combination of dry and wet etching. For example, dry etching can be reactive ion etching or inductively coupled plasma etching, and wet etching can be etching with hydrofluoric acid solution, buffered hydrofluoric acid etching solution, potassium hydroxide solution, or TMAH solution. The blind holes 210 are located in the scribe lane 120, and the cross-section of the blind holes 210 can be rectangular or trapezoidal.

[0061] It should be noted that the position of the blind holes 210 can be defined by photoresist. A photoresist is coated on the first surface of the wafer body 100, and exposure is performed through a corresponding mask plate to transfer the pattern of the mask plate to the photoresist layer; through development, the area where the silicon vias 200 are to be opened is exposed on the photoresist layer; and the blind holes 210 are formed by etching.

[0062] In step S220, as Figure 7 shown, a protective material can be filled in the blind holes 210. The protective material can be one or more of conductive materials such as copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, and titanium nitride. At this time, an insulating layer can be formed on the walls of the blind holes 210 and the first surface of the wafer body 100 before filling the protective material. For example, the insulating layer can be formed by chemical vapor deposition, physical vapor deposition, or thermal growth. The above conductive materials are filled in the blind holes 210, for example, the above conductive materials are filled in the blind holes 210 by electroplating. First, a seed layer is deposited on the insulating layer, and a metal protective layer is electroplated and filled on the seed layer. During the electroplating process, a metal layer will be formed on the first surface of the wafer body 100, and this metal layer needs to be removed, for example, by etching or chemical mechanical polishing.

[0063] When the filling material is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide, and tetraethyl orthosilicate, etc., the protective material can be filled by chemical vapor deposition, physical vapor deposition, or thermal growth. At the same time, as Figure 7 shown, a protective material layer 20 will be formed on the first surface of the wafer body 100. As Figure 8 shown, at this time, the protective material layer 20 can be removed or not removed according to actual needs. Further, air gap holes 250 can be provided between the protective materials filled in the blind holes 210.

[0064] In step S230, as Figure 9As shown, the second surface of the wafer body 100 is thinned until the blind hole 210 is exposed. The second surface of the wafer body 100 can be thinned by etching or chemical mechanical polishing. Here, the second surface of the wafer body 100 is opposite to the first surface. For example, if the first surface of the wafer body 100 is the back surface of the wafer body 100, then the second surface is the front surface of the wafer body 100.

[0065] In a feasible implementation manner provided by the embodiments of the present disclosure, as Figure 3 shown, step S120 may include:

[0066] Step S310, forming a first cut-through silicon via 230 in the scribe line 120 on the first wafer body 300;

[0067] Step S320, filling a protective material in the first cut-through silicon via 230;

[0068] Step S330, forming a second cut-through silicon via 240 at a position corresponding to the scribe line 120 and the first cut-through silicon via 230 on the second wafer body 400. The first wafer body 300 and the second wafer body 400 are stacked;

[0069] Step S340, filling the protective material in the second cut-through silicon via 240.

[0070] In step S310, as Figure 10 shown, a first cut-through silicon via 230 can be formed in the scribe line 120 on the first wafer body 300. In the case of multi-layer wafer stacking, by first forming blind holes 210 on each layer of the wafer body, filling them, then thinning the wafer body 100, and then bonding the multi-layer wafers, the process is complex. Therefore, a double-layer stacking structure can be formed first, and then cut-through silicon vias 230 are formed on each layer of the wafer body 100 respectively, which can simplify the manufacturing process and improve production efficiency. For example, the stacking structure includes a first wafer body 300 and a second wafer body 400 stacked. A first cut-through silicon via 230 can be formed on the surface of the first wafer body 300 to expose the second wafer 400, and the first cut-through silicon via 230 is filled; then a second cut-through silicon via 240 is formed at a position corresponding to the surface of the second wafer body 400 and the first cut-through silicon via 230 to expose the first cut-through silicon via 230, and the second cut-through silicon via 240 is filled, omitting the thinning step and simplifying the manufacturing process.

[0071] Among them, the first through-silicon via 230 can be formed by dry etching, wet etching, laser etching or a combination of dry and wet etching. For example, the dry etching can be reactive ion etching or inductively coupled plasma etching, and the wet etching can be etching with a hydrofluoric acid solution, a buffered hydrofluoric acid etching solution, a potassium hydroxide solution, or a TMAH solution. The first through-silicon via 230 is located in the scribe line 120, and the cross-section of the first through-silicon via 230 can be rectangular or trapezoidal.

[0072] It should be noted that the position of the first through-silicon via 230 can be defined by a photoresist. A photoresist is coated on the surface of the first wafer body 300 and exposed through a corresponding mask plate to transfer the pattern of the mask plate to the photoresist layer; through development, the area where the through-silicon via 200 is to be opened is exposed on the photoresist layer; the first through-silicon via 230 is formed by etching.

[0073] In step S320, a protective material can be filled in the first through-silicon via 230. The protective material can be one or more of conductive materials such as copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, and titanium nitride. At this time, an insulating layer can be formed on the wall of the first through-silicon via 230 and the surface of the wafer body 100 before filling the protective material. For example, the insulating layer can be formed by chemical vapor deposition, physical vapor deposition, or thermal growth. The above-mentioned conductive material is filled in the first through-silicon via 230, for example, the above-mentioned conductive material is filled in the first through-silicon via 230 by electroplating. First, a seed layer is deposited on the insulating layer, and a metal protection layer is electroplated and filled on the seed layer. During the electroplating process, a metal layer will be formed on the surface of the wafer body 100, and this metal layer needs to be removed, for example, by etching or chemical mechanical polishing.

[0074] When the filling material is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide, and tetraethyl orthosilicate, etc., the protective material can be filled by chemical vapor deposition, physical vapor deposition, or thermal growth. At the same time, a protective material layer 20 will be formed on the surface of the first wafer body 300. At this time, the protective material layer 20 can be removed or not removed according to actual needs. Further, as Figure 13 shown, air gap holes 250 can be provided between the protective materials filled in the first through-silicon via 230.

[0075] In step S330, as Figure 11As shown, the second through-silicon via 240 can be formed at the position corresponding to the dicing lane 120 and the first through-silicon via 230 on the second wafer body 400. Among them, the second through-silicon via 240 can be formed by dry etching, wet etching, laser etching, or a combination of dry and wet etching. For example, dry etching can be reactive ion etching or inductively coupled plasma etching, and wet etching can be potassium hydroxide solution etching. The second through-silicon via 240 is located in the dicing lane 120, and the cross-section of the second through-silicon via 240 can be rectangular or trapezoidal.

[0076] It should be noted that the position of the second through-silicon via 240 can be defined by photoresist. A photoresist is coated on the surface of the second wafer body 400, exposed through a corresponding mask plate, and the pattern of the mask plate is transferred to the photoresist layer; through development, the area where the through-silicon via 200 is to be opened is exposed on the photoresist layer; and the second through-silicon via 240 is formed by etching.

[0077] In step S340, the protective material is filled in the second through-silicon via 240. The protective material can be one or more of conductive materials such as copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, and titanium nitride. At this time, an insulating layer can be formed on the wall of the second through-silicon via 240 and the surface of the wafer body 100 first when filling the protective material. For example, the insulating layer can be formed by chemical vapor deposition, physical vapor deposition, or thermal growth. The above conductive material is filled in the second through-silicon via 240, for example, the above conductive material is filled in the second through-silicon via 240 by electroplating. First, a seed layer is deposited on the insulating layer, and a metal protective layer is electroplated and filled on the seed layer. During electroplating, a metal layer will be formed on the surface of the wafer body 100, and this metal layer needs to be removed, for example, by etching or chemical mechanical polishing.

[0078] When the filling material is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide, and tetraethyl orthosilicate, etc., the protective material can be filled by chemical vapor deposition, physical vapor deposition, or thermal growth. At the same time, a protective material layer 20 will be formed on the surface of the second wafer body 400, and at this time, the protective material layer 20 can be removed or not removed according to actual needs. Further, air gap holes 250 can be provided between the protective materials filled in the second through-silicon via 240.

[0079] For the structure of more-layer wafer stacking, on the basis of the double-layer stacking structure where the first through-silicon via 230 and the second through-silicon via 240 have been formed, each additional layer of wafer can be fabricated by the method of stacking first and then forming through-silicon vias, which can simplify the manufacturing process and improve production efficiency.

[0080] Such as Figure 12As shown, cutting through-silicon vias 200 are formed along the extending direction of the dicing lane 120. The cutting through-silicon vias 200 include continuously distributed through-silicon vias or discretely distributed through-silicon vias. Multiple rows of cutting through-silicon vias 200 are formed in the dicing lane 120. The width L of the cutting through-silicon vias 200 is 2 μm - 20 μm, and the depth S of the cutting through-silicon vias 200 is 15 μm - 150 μm. When the dicing lane 120 has multiple rows of cutting through-silicon vias 200, the width of the entire through-silicon via region is 2 μm - 20 μm. The width of the cutting through-silicon vias 200 refers to the distance between two sidewalls of the cutting through-silicon vias 200 parallel to the dicing lane 120.

[0081] Among them, as Figure 14 shown, multiple rows of cutting through-silicon vias 200 can be arranged in the dicing lane 120, and the multiple rows of cutting through-silicon vias 200 can be arranged in parallel in the dicing lane 120. The multiple rows of cutting through-silicon vias 200 form multiple cutting lines, and the cutting stress is further relieved through the multiple cutting lines.

[0082] The wafer manufacturing method provided by the embodiments of the present disclosure prevents the cutting stress from damaging the die area 110 during wafer dicing by arranging cutting through-silicon vias 200 filled with a protective material in the dicing lane 120. The width of the dicing lane 120 can be effectively reduced through the cutting through-silicon vias 200, which is beneficial to the miniaturization of the dicing lane 120 and improves the effective utilization rate of the wafer.

[0083] In this exemplary embodiment, a wafer is further provided, as Figure 4 shown. The wafer includes a wafer body 100 and cutting through-silicon vias 200. A dicing lane 120 for dicing is arranged on the wafer body 100; the cutting through-silicon vias 200 are arranged in the dicing lane 120, and the cutting through-silicon vias 200 are filled with a protective material.

[0084] The wafer provided by the embodiments of the present disclosure prevents the cutting stress from damaging the die area 110 during wafer dicing by arranging cutting through-silicon vias 200 filled with a protective material in the dicing lane 120. The width of the dicing lane 120 can be effectively reduced through the cutting through-silicon vias 200, which is beneficial to the miniaturization of the dicing lane 120 and improves the effective utilization rate of the wafer.

[0085] The wafer body 100 can be divided into a dicing street 120 and a die area 110. During dicing, a dicing blade acts on the dicing street 120, and the die area 110 is reserved. The wafer body 100 can include a silicon substrate such as a silicon epitaxial wafer or silicon-on-insulator, or can be a substrate of other semiconductor materials such as GaN. Moreover, the substrate can be an intrinsic semiconductor substrate, or an N-type doped or P-type doped semiconductor substrate, which is not limited in the embodiments of the present disclosure. A dielectric layer can be provided on the substrate, and the material of the dielectric layer can be one or more of silicon oxide, silicon nitride, or silicon oxynitride. In specific implementation, the dielectric layer can be formed by methods such as chemical vapor deposition or atomic layer deposition. It can be understood that the dielectric layer can be a single insulating material layer, or can be a stack of multiple identical or different insulating material layers.

[0086] A through-silicon via for dicing 200 is formed in the extending direction of the dicing street 120. The through-silicon via for dicing 200 includes continuously distributed through-silicon vias or discretely distributed through-silicon vias. Multiple rows of through-silicon vias for dicing 200 are formed in the dicing street 120. The width L of the through-silicon via for dicing 200 is 2 micrometers to 20 micrometers, and the depth S of the through-silicon via for dicing 200 is 15 micrometers to 150 micrometers. When the dicing street 120 has multiple rows of through-silicon vias for dicing 200, the width of the entire through-silicon via area is 2 micrometers to 20 micrometers. The width of the through-silicon via for dicing 200 refers to the distance between two sidewalls of the through-silicon via for dicing 200 that are parallel to the dicing street 120.

[0087] It should be noted that the cross-sectional shape of the through-silicon via for dicing can be a rectangle as shown in Figure 12 or can be in shapes such as a crosshatch, a circle, an ellipse, or a polygon, etc., which is not specifically limited in the embodiments of the present disclosure.

[0088] The protective material can include one or more of copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide, and tetraethyl orthosilicate. Further, an air gap hole 250 is provided in the through-silicon via for dicing 200.

[0089] When the protective material is one or more of conductive materials such as copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, and titanium nitride, at this time, the through-silicon via for dicing 200 can include an insulating layer and a protective material layer, and the insulating layer is located between the through-hole on the wafer body 100 and the protective material. When filling the protective material, an insulating layer can be first formed on the through-hole wall and the first surface of the wafer body 100. For example, the insulating layer can be formed by chemical vapor deposition, physical vapor deposition, or thermal growth. The above conductive materials are filled into the through-hole, for example, the above conductive materials are filled into the through-hole by electroplating. First, a seed layer is deposited on the insulating layer, and a metal protective layer is electroplated and filled on the seed layer.

[0090] When the filling material is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide, and tetraethyl orthosilicate, etc., the protective material can be filled by chemical vapor deposition, physical vapor deposition, or thermal growth. At the same time, a protective material layer 20 will be formed on the first surface of the wafer body 100. At this time, the protective material layer 20 can be removed or not removed according to actual needs. Further, an air gap hole 250 can be provided between the protective materials filled in the blind hole 210.

[0091] For the wafer provided by the embodiment of the present disclosure, by providing the cut-through silicon vias 200 filled with the protective material in the scribe line 120, when the wafer is cut, it can prevent the cutting stress from damaging the die area 110. Through the cut-through silicon vias 200, the width of the scribe line 120 can be effectively reduced, which is beneficial to the miniaturization of the scribe line 120 and improves the effective utilization rate of the wafer.

[0092] In this exemplary embodiment, a semiconductor device is further provided, as Figure 5 shown. The semiconductor device includes multiple layers of the above-mentioned wafers, and the multiple layers of wafers are stacked. The cut-through silicon vias 200 are provided in the scribe line 120 of each layer of wafer, and the positions of the cut-through silicon vias 200 of the multiple layers of wafers correspond. After the multiple layers of wafers are stacked, the projections of the cut-through silicon vias 200 on any wafer coincide. The wafers are cut along the cut-through silicon vias 200 to obtain multiple stacked dies.

[0093] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily think of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include the common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A wafer manufacturing method, characterized in that, the wafer manufacturing method includes: providing a first wafer body and a second wafer body arranged in a stacked manner, and scribe lines for cutting are respectively arranged on the surfaces of the first wafer body and the second wafer body; forming through-silicon vias for cutting in the scribe lines, and a protective material is filled in the through-silicon vias for cutting to form cutting lines, including: forming a first through-silicon via for cutting in the scribe line on the surface of the first wafer body, and the first through-silicon via for cutting exposes the second wafer body; filling the protective material in the first through-silicon via for cutting; forming a second through-silicon via for cutting at a position corresponding to the first through-silicon via for cutting on the surface of the second wafer body, and the second through-silicon via for cutting exposes the first through-silicon via for cutting; filling the protective material in the second through-silicon via for cutting.

2. The wafer manufacturing method according to claim 1, characterized in that, the through-silicon vias for cutting include continuously distributed through-silicon vias or discretely distributed through-silicon vias.

3. The wafer manufacturing method according to claim 1, characterized in that, multiple rows of through-silicon vias for cutting are formed in the scribe lines.

4. The wafer manufacturing method according to claim 1, characterized in that, the width of the through-silicon vias for cutting is 2 μm - 50 μm, and the depth of the through-silicon vias for cutting is 15 μm - 150 μm.

5. The wafer manufacturing method according to claim 1, characterized in that, the protective material includes one or more of copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide, and tetraethyl orthosilicate.

6. The wafer manufacturing method according to claim 1, characterized in that, air gap holes are provided in the through-silicon vias for cutting.

7. A semiconductor device, characterized in that, it includes multiple wafers formed by the wafer manufacturing method according to any one of claims 1 - 6, and the multiple wafers are arranged in a stacked manner.

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