Semiconductor device, method for manufacturing the same, and static random access memory device

Abstract

The present disclosure describes apparatuses and methods for eliminating the need for a read assist circuit. In one embodiment, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed under either the source region or the drain region. A first nanosheet is formed (i) horizontally between the source region and the drain region; and (ii) vertically above the buried insulator layer. The buried insulator layer reduces current flowing through the first nanosheet.

Description

Technical Field

[0001] The technology described in this disclosure relates generally to electronic systems, and more particularly to increasing the read margin of electronic devices using partially buried insulator (BI) nano-sheet devices. Background Art

[0002] Metal oxide semiconductor field effect transistor (MOSFET) is a semiconductor device commonly used in both digital and analog circuits, including static random access memory (SRAM) devices. Metal oxide semiconductor field effect transistors are commonly used to switch and amplify electronic signals within electronic devices. A typical metal oxide semiconductor field effect transistor includes a source, a drain, and a gate electrode. The gate electrode is energized so that current flows from the source through a channel region to the drain. The gate electrode is characterized by a channel length and width. As electronic devices become smaller and smaller, the size of the channel length of the metal oxide semiconductor field effect transistor is reduced. However, because it is more difficult to control the channel region, such a reduction in channel length reduces transistor performance.

[0003] FinFET is a three-dimensional (3D) multi-gate metal oxide semiconductor field effect transistor that provides more control over the channel area. With the FinFET design, a thin silicon fin is used as a channel, and the thin silicon fin is wrapped by a gate electrode. It is this 3-dimensional structure that facilitates more control over the channel area. However, the reduction in gate length can lead to short channel effects such as current leakage, surface scattering, velocity saturation, impact ionization, threshold voltage variations, and / or hot carrier effects. Summary of the invention

[0004] Some embodiments of the present disclosure provide a semiconductor device comprising: a source region and a drain region, a buried insulator (BI) layer, and a first nanosheet. The source region and the drain region are formed above a substrate. The buried insulator layer is formed below only one of the source region or the drain region and above the substrate. The first nanosheet is formed (i) between the source region and the drain region in a horizontal direction, and (ii) above the buried insulator layer in a vertical direction.

[0005] Other embodiments of the present disclosure provide a static random access memory device, comprising: a plurality of static random access memory bit cells and a bit line. Each static random access memory bit cell comprises: a portion of a buried insulator layer, and a plurality of nanosheet layers. A portion of the buried insulator layer is formed below only a first source / drain region. The plurality of nanosheet layers separate the first source / drain region from the second source / drain region. The bit line couples the plurality of static random access memory bit cells together, and the bit line is electrically coupled to the portion of the buried insulator layer.

[0006] Other embodiments of the present disclosure provide a method for manufacturing a semiconductor device, comprising: forming a first nanosheet above a substrate; depositing a first gate electrode layer above the first nanosheet; forming a buried insulator layer above the substrate; and forming only one of a source region or a drain region above the buried insulator layer, wherein the first nanosheet is located (i) between the source region or the drain region in a horizontal direction, and (ii) above the buried insulator layer in a vertical direction.

[0007] Some other embodiments of the present disclosure provide a semiconductor device including a first transistor. The first transistor is higher than a substrate and includes: a first source / drain region, a layer between the source / drain region and the substrate and made of a dielectric material, and a second source / drain region. The second source / drain region contacts the substrate.

[0008] Other embodiments of the present disclosure provide a memory device comprising: a plurality of bit cells and a first bit line. Each bit cell comprises: a first transistor and a first bit line. The first transistor is higher than a substrate and has a first source / drain region, a first layer, and a second source / drain region. The first layer is between the first source / drain region and the substrate and is made of a material different from the substrate. The second source / drain region contacts the substrate. The first bit line is coupled to the first source / drain region of the first transistor.

[0009] Other embodiments of the present disclosure provide a method of using a semiconductor device, comprising: generating a first current flowing through a first transistor of a bit cell, the bit cell having a first source / drain region connected to a bit line of the bit cell; and generating a second current greater than the first current, the second current flowing through a second transistor of the bit cell connected to a second source / drain region of the first transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various aspects of the present disclosure can be described in detail below and in conjunction with the accompanying Figure 1Please read together for the best understanding. It is worth noting that, according to the standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0011] Figure 1 is a top view of an exemplary portion of a static random access memory device according to various embodiments of the present disclosure;

[0012] Figure 2 According to various embodiments of the present disclosure, Figure 1 A schematic illustration of an exemplary static random access memory bit cell;

[0013] Figure 3 is a cross-sectional view of an exemplary nanosheet transistor that may be used in an exemplary static random access memory bit cell according to various embodiments of the present disclosure;

[0014] Figure 4 is a cross-sectional view of another exemplary nanosheet transistor that may be used in an exemplary static random access memory bit cell according to various embodiments of the present disclosure;

[0015] Figure 5 is a top view of an exemplary portion of a static random access memory device according to various embodiments of the present disclosure;

[0016] Figure 6 is an exemplary SRAM device having an array of multiple SRAM bit cells according to various embodiments of the present disclosure;

[0017] Figure 7 According to various embodiments of the present disclosure, Figure 6 A cross-sectional view of an exemplary static random access memory device;

[0018] Figure 8 is a flow chart of an exemplary method of forming a static random access memory device having a partially buried insulator layer and nanosheets according to various embodiments of the present disclosure.

[0019]

Explanation of symbols

[0020] 100: Static random access memory device

[0021] 110: Static random access memory bit cell

[0022] 120:Buried insulator layer

[0023] 130: Gate

[0024] 140: Gate

[0025] 210: Transistor

[0026] 215: Storage Node

[0027] 220: Transistor

[0028] 230: Transistor

[0029] 235: Storage Node

[0030] 240: Transistor

[0031] 250: Transistor

[0032] 260: Transistor

[0033] 300:Nanosheet transistor

[0034] 310:Substrate

[0035] 320:Buried insulator layer

[0036] 330: Source region

[0037] 340: Drain region

[0038] 350: Gate

[0039] 360: Contact

[0040] 370: Dielectric Materials

[0041] 380:Nanosheet

[0042] 385: Current Path

[0043] 390: Gate electrode

[0044] 400:Nanosheet transistor

[0045] 420:Buried insulator layer

[0046] 430: Source region

[0047] 500: Static random access memory device

[0048] 520:Buried insulator layer

[0049] 550: Gate

[0050] 555: Gate

[0051] 600: Static random access memory device

[0052] 602: Bit unit

[0053] 604: Bit unit

[0054] 606: Bit unit

[0055] 608: Bit unit

[0056] 610: Bit unit

[0057] 612: Bit unit

[0058] 614:Bit unit

[0059] 616: Bit unit

[0060] 620:Buried insulator layer

[0061] 622:Buried insulator layer

[0062] 650: Bit line

[0063] 730: Source / drain region

[0064] 800: Flowchart

[0065] 810: Steps

[0066] 820: Steps

[0067] 830: Steps

[0068] 840: Steps

[0069] BI:Buried Insulator

[0070] BIT:bit

[0071] BL: Bit Line

[0072] BLB: Bit Line

[0073] EPI: Epitaxy

[0074] I PD :Current

[0075] I PG :Current

[0076] Lbi: Length

[0077] Lp: Length

[0078] Sp: interval

[0079] VDD: supply voltage

[0080] VSS: Supply voltage

[0081] Wbi: Width

[0082] WL: Word line

[0083] Ws: Width Detailed implementation manners

[0084] The subsequent disclosures provide many different implementation manners or embodiments to implement different features of the provided subject matter. The following describes specific embodiments of components and configurations to simplify the present disclosure. Of course, these are only embodiments and are not intended to limit. For example, in the subsequent description, forming a first feature above or on a second feature may include an implementation manner in which the first and second features are formed in direct contact, and may also include an implementation manner in which additional features may be formed between the first and second features, so the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for the sake of simplicity and clarity and does not imply a relationship between the various implementation manners and / or configurations discussed.

[0085] In a fin field-effect transistor device, a reduction in the gate length makes a metal-oxide-semiconductor field-effect transistor susceptible to many short-channel effects, such as current leakage, surface scattering, velocity saturation, impact ionization, threshold voltage variation, and / or hot carrier effects. A nanosheet device can provide an alternative, which in some embodiments can have stronger gate controllability than a fin field-effect transistor. Generally, both fin field-effect transistors and nanosheet field-effect transistors use read / write assist circuits, such as sense amplifiers, negative voltage bias circuits, and / or selective precharge circuits, to improve read performance. The devices and methods described herein include eliminating the need for read assist circuits through the use of partially buried insulator nanosheet devices.

[0086] SRAM devices are computer memory devices that are made of transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), and / or nano-sheet field effect transistors. An array of multiple SRAM bit cells can be combined with various control circuits to form an SRAM macro. In an SRAM macro, due to the use of FinFETs and / or nano-sheet field effect transistors, additional read and / or write assist circuits may be required because these devices are sensitive to current. Read margin is a metric used to evaluate the read performance of an SRAM bit cell. Read margin can be characterized by a β-ratio, which is the ratio between multiple currents flowing through some transistors of an SRAM bit cell. The higher the β-ratio, the better the SRAM bit cell performs a read operation. When the β ratio is a low value, additional circuits can be used together with the SRAM bit cell to improve the read performance of the SRAM bit cell. More specifically, the read assist circuit can increase the read performance. The additional circuit in turn means more space that may or may not be feasible within the device. In some embodiments, the device described herein includes a SRAM bit cell having a portion of multiple nanosheets, and the portion of multiple nanosheets enables the SRAM bit cell to become a read assist-free SRAM. Such a device includes a buried insulator layer and a nanosheet, the buried insulator layer is below the source region or drain region of the SRAM bit cell, and the nanosheet separates the source region and the drain region from each other. In other words, the SRAM bit cell described in some embodiments uses a buried insulator layer to increase the β ratio, eliminating the need for a read assist circuit and saving space within the device.

[0087] Figure 1 FIG. 1 is a top view of an exemplary portion of a SRAM device 100 according to various embodiments of the present disclosure. As shown, the portion of the SRAM device 100 includes a SRAM bit cell 110. When the current I PG When flowing across the gate 130, the current I PG will decrease, making the current I PG is less than the current I flowing through the gate 140 PD. This reduction occurs in part because the buried insulator layer 120 is made of a dielectric material. This makeup reduces the number of ions within the device due to the lack of fully doped source / drain regions. Dielectric materials are insulating materials that inhibit the flow of current. In other words, the flow of current through the dielectric material is minimized. The beta ratio of a static random access memory bit cell can be expressed by the following equation:

[0088]

[0089] Among them, I PG is the current through the transistor coupled to the bit line of the SRAM bit cell, and I PD is the current through the other transistor of the SRAM bit cell inverter, both of which are Figure 2 Because the buried insulator layer 120 makes I PG Lower, so I PG The value is less than I PD A larger number divided by a smaller number results in a larger number for the beta ratio of the SRAM bit cell 110. With a large beta ratio, the read performance of the SRAM bit cell 110 is good, and no additional circuitry is required to assist the read performance.

[0090] Figure 2 According to various embodiments of the present disclosure, Figure 1Schematic depiction of an exemplary SRAM bit cell 110. The SRAM bit cell 110 is a six transistor (6T) SRAM having N-type metal oxide semiconductor (NMOS) transistors 210, 220, 230, 240, and P-type metal oxide semiconductor (PMOS) transistors 250, 260. When powered, the SRAM bit cell 110 stores a single bit of information. The transistors 210, 240 couple a pair of data lines (e.g., bit lines BL / BLB) to storage nodes 215, 235, respectively. The supply voltage VDD provides a positive voltage (e.g., 0.6 to 3.0V) to the PMOS transistors 250, 260. The second supply voltage VSS can be set to ground or a negative voltage. N-type metal oxide semiconductor transistors 220, 230 are coupled to a second supply voltage and to each other via storage nodes 215, 235, depending on the state of the SRAM bit cell 110. The SRAM bit cell 110 is a latch that will retain its data state indefinitely as long as the power provided is sufficient to operate the components within the SRAM bit cell 110. P-type metal oxide semiconductor transistor 250 and N-type metal oxide semiconductor transistor 220 together form a complementary metal oxide semiconductor (CMOS) inverter. P-type metal oxide semiconductor transistor 260 and N-type metal oxide semiconductor transistor 230 together form another complementary metal oxide semiconductor inverter. The two complementary metal oxide semiconductor inverters are cross-coupled together and operate to continuously enhance the charge stored on the storage nodes 215, 235. The two storage nodes 215, 235 are inverted with each other. When storage node 215 is at logic "1" (typically a high voltage), storage node 235 is at logic "0" (typically a low voltage) at the same time, and vice versa. When SRAM bit cell 110 is written, a complementary write data signal is placed on bit line BL / BLB. A positive control signal on word line WL is coupled to the gates of both NMOS transistors 210, 240. NMOS transistors 220, 230 and PMOS transistors 250, 260 are sized so that the data on bit line BL / BLB can overwrite the stored data and thus write to SRAM bit cell 110.

[0091] When voltage is applied to the bit lines BL / BLB, the SRAM bit cell 110 is read. Once voltage is applied to the bit lines BL / BLB, voltage is applied to the word line WL. One of the bit lines BL / BLB will be pulled down by the bit cell operation. This pull down is facilitated by electrical coupling of the bit lines BL / BLB to the buried insulator layer 120, as in Figure 7 The contents are described in more detail in I PG is defined as the current flowing through the N-type metal oxide semiconductor transistor 210. PD is defined as the current flowing through the NMOS transistor 220. Since the current I PG Flowing through transistor 210, current I PG The buried insulator layer 120 is electrically impacted and reduces the amperage. PD Greater than current I PG Because of this, the β ratio of equation (1) is large, which means that no additional read assist circuitry is required.

[0092] Figure 3 is a cross-sectional view of an exemplary nanosheet transistor 300 that may be used in an exemplary static random access memory bit cell according to various embodiments of the present disclosure. The nanosheet transistor 300 includes a substrate 310, a buried insulator layer 320, a source region 330, a drain region 340, a gate 350, a contact 360, a dielectric material 370, a nanosheet 380, and a gate electrode 390. Figure 3 In the embodiment illustrated in FIG. 3 , a buried insulator layer 320 may be formed below the source region 330. When the nanosheet transistor 300 is operating, a drive current flows between the source region 330 and the drain region 340. The presence of the buried insulator layer 320 reduces this drive current, resulting in a decrease in I PG The low current value, I PG The low current value in turn increases the β ratio, as previously shown in Figure 1 to Figure 2 As a result, nanosheet transistor 300 does not need to be used in conjunction with any read assist circuitry.

[0093] The substrate 310 may be made of any number of suitable semiconductor materials, such as Si, P, Ge, Ga, SiGe, and / or InAs, or any combination thereof. The buried insulator layer 320 may be made of any number of suitable dielectric materials, such as Si 3 N 4 、SiO 2 、Al 2 O 3 , HfO 2 、2 O 5 , and / or TiO 2 , or any combination thereof. The source region 330 and the drain region 340 are epitaxially grown doped regions. As is known in the art, such regions are interchangeable. The nanosheets 380 and gate electrodes 390 can be alternately stacked on top of each other, located (i) vertically between the top surface of the buried insulator layer 320 and the bottom surface of the dielectric material 370, and (ii) horizontally between the source region 330 and the drain region 340. The nanosheet acts as a channel between the source region 330 and the drain region 340. The drive current of the nanosheet transistor 300 flows through the nanosheet 380 along the current path 385. The nanosheet 380 can be made of any number of suitable semiconductor materials, such as Si, P, Ge, Ga, SiGe, and / or InAs, or any combination thereof. The gate electrode 390 is a gate dielectric (in Figure 3 Although not shown, the gate dielectric surrounds the nanosheet 380 and is located between the nanosheet 380 and the gate electrode 390. The gate dielectric can be made of any number of suitable dielectric materials, such as Si. 3 N 4 、SiO 2 、Al 2 O 3 , HfO 2 、 2 O 5 , and / or TiO 2 , or any combination thereof. The gate electrode 390 may be made of any number of suitable conductive materials, such as Cu, W, CO, Ru, or any combination thereof. The gate 350 may be made of any number of suitable conductive materials, such as Cu, W, CO, Ru, or any combination thereof. Similarly, the contact 360 may be made of any number of suitable conductive materials, such as Cu, W, CO, Ru, or any combination thereof.

[0094] Figure 4 is a cross-sectional view of another exemplary nanosheet transistor 400 that may be used in an exemplary static random access memory bit cell according to various embodiments of the present disclosure. Figure 4 In the embodiment illustrated in FIG. 4 , the buried insulator layer 420 is formed under the drain region 340 , but not under the source region 430 .

[0095] Figure 5is a top view of an exemplary portion of a static random access memory device 500 according to various embodiments of the present disclosure. Polysilicon (poly) or gate 550 has an associated length Lp. The spacing or interval Sp from the polysilicon or gate 550 to another gate 555 is less than a large value of the polysilicon length Lp (e.g., ~20 times Lp) and greater than or equal to at least twice the polysilicon length (e.g., ~2 times Lp). In other words, the relationship between the polysilicon length Lp and the polysilicon interval Sp can be expressed as:

[0096] 20LP>sP≥2Lp (2)

[0097] The polysilicon or gate 550 has a depth Dp (not shown) that is less than an amount (e.g., 50 times Lp) of the polysilicon length Lp, but greater than a different amount (e.g., 5 times Lp) of the polysilicon length Lp. In other words, the relationship between the polysilicon depth and the polysilicon length can be expressed as:

[0098] 50LP>DP>5Lp (3)

[0099] The buried insulator layer 520 has a length Lbi that is greater than or equal to the polysilicon spacing Sp between the plurality of gates. In other words, the relationship between the length of the buried insulator layer 520 and the polysilicon spacing Sp can be expressed as:

[0100] Lbi≥Sp (4)

[0101] The buried insulator layer 520 is formed above the substrate and has a depth Dbi (not shown) that is less than an amount of the polysilicon length Lp (e.g., ˜30 times Lp), but greater than about half of the polysilicon depth Dp (e.g., 0.5 times Dp). In other words, the relationship between the depth Dbi of the buried insulator layer 520, the polysilicon length Lp, and the polysilicon depth Dp can be expressed as:

[0102] 30Lp>Dbi>0.5Dp (5)

[0103] The nanosheet 380 has a sheet width Ws that is less than or equal to a magnitude of the polysilicon length Lp (e.g., 10 times Lp) and greater than or equal to about half of the polysilicon length Lp (e.g., 0.5 times Lp). In other words, the relationship between the sheet width Ws and the polysilicon length Lp can be expressed as:

[0104] 10Lp≥Ws≥0.5Lp (6)

[0105] The buried insulator layer 520 has a width Wbi that is greater than or equal to the sheet width Ws of the nanosheet 380. In other words, the relationship between the width Wbi of the buried insulator layer 520 and the sheet width Ws can be expressed as:

[0106] Wbi≥Ws (7)

[0107] Figure 6 6 is an exemplary SRAM device 600 having an array of multiple SRAM bit cells 602, 604, 606, 608, 610, 612, 614, 616 according to various embodiments of the present disclosure. As shown, at least two buried insulator layers span each bit cell. For example, bit cell 602 includes a portion of buried insulator layer 620 and a portion of buried insulator layer 622. In other words, each buried insulator layer 620, 622 spans multiple bit cells.

[0108] Figure 7 According to various embodiments of the present disclosure Figure 6 6. A cross-sectional view of an exemplary static random access memory device 600 with a bit line 650 as the axis. The bit line 650 couples the bit cells 610, 612, 614, and 616 together. The bit line 650 is also electrically coupled to each buried insulator layer within each bit cell. For example, the bit line 650 is electrically coupled to the buried insulator layer 620 of the bit cell 616 via the source / drain region 730. Through this electrical coupling, the current I PD become lower, as in Figure 1 to Figure 2 Described in .

[0109] Figure 8 FIG. 8 is a flow chart 800 of an exemplary method for forming a static random access memory device having a partially buried insulator layer and a plurality of nanosheets according to various embodiments of the present disclosure. The method can be applied to a variety of underlying structures. However, for ease of understanding, the following is combined with Figure 3 to Figure 4 and Figure 8A description is given. The first nanosheet 380 is formed above the substrate 310. The first nanosheet 380 may be formed epitaxially above the substrate 310 (step 810). A gate electrode 390 (gate electrode layer) is formed above the first nanosheet 380. The gate electrode 390 (gate electrode layer) is deposited using chemical vapor deposition (CVD) which includes low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes (step 820). The buried insulator layer 320 is formed above the substrate 310 (step 830). Source and drain regions are formed above the substrate 310 and the buried insulator layer 320 (step 840). The first nanosheet 380 is (i) horizontally positioned between the source and drain regions, and (ii) vertically above the buried insulator layer 320.

[0110] Although six-transistor (6T) static random access memory (SRAM) bit cell is described in these figures, those skilled in the art can understand that any type of bit cell can be implemented using the teachings herein. These bit cells can include, but are not limited to, seven-transistor (7T), eight-transistor (8T), nine-transistor (9T), and / or ten-transistor (10T) bit cells.

[0111] The use of various circuits and configurations as described herein can provide many advantages. For example, the embedded buried insulator layer under the source / drain regions, along with the use of multiple nanosheets, reduces the current flowing through the first transistor of the SRAM bit cell. The reduction in current increases the beta ratio (β ratio) of the SRAM bit cell that includes the ratio of this current flow. Such an improvement represents that the read performance of this SRAM bit cell is high and no additional read assist circuit is required. Eliminating the need for any read assist circuit saves space within the device that can be used for other circuits and / or can reduce the overall size of the device.

[0112] In one embodiment, a semiconductor device includes a source region and a drain region which are formed above a substrate. A buried insulator layer is formed under either the source region or the drain region. A first nanosheet is formed (i) horizontally between the source region and the drain region; and (ii) vertically above the buried insulator layer. The current flowing through the buried insulator layer increases the beta ratio that includes the ratio of this current flow.

[0113] In another embodiment, a static random access memory includes a plurality of static random access memory bit cells. Each static random access memory bit cell has a portion of a buried insulator layer formed under a first source / drain region and a plurality of nanosheet layers that separate the first source / drain region from a second source / drain region. A bit line couples the plurality of static random access memory bit cells together. The bit line is electrically coupled to this portion of the buried insulator layer.

[0114] In yet another embodiment, a method includes forming a first nanosheet above a substrate. Depositing a first gate electrode layer above the first nanosheet. Forming a buried insulator layer above the substrate. Forming a source region and a drain region above the buried insulator layer and the substrate. The buried insulator layer is located (i) horizontally between the source region and the drain region; and (ii) vertically above the buried insulator layer.

[0115] Some embodiments of the present disclosure provide a semiconductor device, comprising: a source region and a drain region, a buried insulator (BI) layer, and a first nanosheet. The source region and the drain region are formed above a substrate. The buried insulator layer is formed under either the source region or the drain region and above the substrate. The first nanosheet is formed (i) horizontally between the source region and the drain region, and (ii) vertically above the buried insulator layer.

[0116] In some embodiments, the semiconductor device further comprises: a gate, an insulator layer, and a second nanosheet. The gate is formed around the first nanosheet. The insulator layer is formed vertically above the first nanosheet, and the insulator layer separates the first nanosheet and the second nanosheet. The second nanosheet is formed above the insulator layer, wherein the gate is formed above the second nanosheet.

[0117] In some embodiments, in the semiconductor device, the semiconductor device is not coupled to a read assist circuit.

[0118] In some embodiments, in the semiconductor device, each of the first nanosheet and the second nanosheet comprises a semiconductor material having at least one of Si, P, Ge, Ga, SiGe, or InAs.

[0119] In some embodiments, in the semiconductor device, the buried insulator layer comprises a dielectric material having Si 3 N 4 、SiO 2 、Al 2 O 3 、HfO 2 、Ta 2 O 5, or TiO 2 At least one of the following.

[0120] In some embodiments, in a semiconductor device, the depth of the buried insulator layer is between approximately (i) 30 times the length of a gate and (ii) 0.5 times the depth of this gate.

[0121] In some embodiments, in a semiconductor device, the width of the buried insulator layer is greater than or equal to the width of the first nanosheet.

[0122] In some embodiments, in a semiconductor device, the width of the first nanosheet is between approximately (i) 10 times the length of a gate and (ii) 0.5 times this length of this gate.

[0123] In some embodiments, in a semiconductor device, the length of the buried insulator layer is greater than or equal to a spacing between a gate and a gate of another semiconductor device.

[0124] Some embodiments of the present disclosure provide a static random access memory (SRAM) device, comprising: a plurality of static random access memory bit cells, and a bit line. Each static random access memory bit cell comprises: a portion of a buried insulator (BI) layer, and a plurality of nanosheet layers. This portion of the buried insulator layer is formed under a first source / drain region. The plurality of nanosheet layers separate the first source / drain region from a second source / drain region. The bit line couples these plurality of static random access memory bit cells together, and the bit line is electrically coupled to this portion of the buried insulator layer.

[0125] In some embodiments, in a static random access memory device, none of these plurality of bit cells is coupled to a read assist circuit.

[0126] In some embodiments, in a static random access memory device, each of these plurality of nanosheets comprises a semiconductor material having at least one of Si, P, Ge, Ga, SiGe, or InAs.

[0127] In some embodiments, in a static random access memory device, the buried insulator layer comprises a dielectric material having Si 3 N 4 , SiO 2 , Al 2 O 3 , HfO 2 , Ta 2 O 5 , or TiO 2 At least one of the following.

[0128] In some embodiments, in a static random access memory device, the plurality of nanosheets are separated from each other by a plurality of insulating layers.

[0129] In some embodiments, in a static random access memory device, the plurality of nanosheets are positioned above this portion of the buried insulator layer in a vertical direction.

[0130] In some embodiments, in a static random access memory device, each static random access memory bit cell in the static random access memory bit cells includes a first transistor coupled to a second transistor, and a first current passes through the first transistor, wherein the first current is less than a second current passing through the second transistor.

[0131] Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including: forming a first nanosheet above a substrate; depositing a first gate electrode layer above the first nanosheet; forming a buried insulator (BI) layer above the substrate; and forming source and drain regions above the buried insulator layer and the substrate, wherein the buried insulator layer is located (i) between the source region and the drain region in a horizontal direction, and (ii) above the buried insulator layer in a vertical direction.

[0132] In some embodiments, the method of manufacturing a semiconductor device further includes: forming a gate above the first nanosheet; forming an insulator layer above the first nanosheet in a vertical direction, the insulator separating the first nanosheet from a second nanosheet; and forming a second nanosheet above the insulator layer, wherein the gate is formed above the second nanosheet.

[0133] In some embodiments, in the method of manufacturing a semiconductor device, each of the first nanosheet and the second nanosheet is formed using a semiconductor material having at least one of Si, P, Ge, Ga, SiGe, or InAs.

[0134] In some embodiments, in the method of manufacturing a semiconductor device, the buried insulator layer is formed using a dielectric material having Si 3 N 4 、SiO 2 、Al 2 O 3 、HfO 2 、Ta 2 O 5 、or TiO 2 and having at least one of the following.

[0135] The foregoing outlines several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or attain the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, comprising: a source region and a drain region formed above a substrate; a buried insulator layer formed beneath only one of the source region or the drain region and buried in the substrate, wherein a bottom of the buried insulator layer is lower than a topmost surface of the substrate; and a first nanosheet formed (i) horizontally between the source region and the drain region, and (ii) vertically above the buried insulator layer.

2. The semiconductor device according to claim 1, characterized in that, further comprising: a gate formed around the first nanosheet; an insulator layer formed vertically above the first nanosheet, the insulator layer separating the first nanosheet and a second nanosheet; and the second nanosheet formed above the insulator layer, wherein the gate is formed above the second nanosheet.

3. The semiconductor device according to claim 1, characterized in that, the semiconductor device is not coupled to a read assist circuit.

4. The semiconductor device according to claim 2, characterized in that, each of the first nanosheet and the second nanosheet comprises a semiconductor material having at least one of Si, P, Ge, Ga, SiGe, or InAs.

5. The semiconductor device according to claim 1, characterized in that, The buried insulator layer includes a dielectric material having Si 3 N 4 、SiO 2 、Al 2 O 3 、HfO 2 、Ta 2 O 5 、or TiO 2 and at least one of them.

6. The semiconductor device according to claim 1, characterized in that, a depth of the buried insulator layer is between (i) 30 times a length of a gate and (ii) 0.5 times a depth of the gate.

7. The semiconductor device according to claim 1, characterized in that, a width of the buried insulator layer is greater than or equal to a width of the first nanosheet.

8. The semiconductor device according to claim 7, characterized in that, the width of the first nanosheet is between (i) 10 times a length of a gate and (ii) 0.5 times the length of the gate.

9. The semiconductor device according to claim 1, characterized in that, a length of the buried insulator layer is greater than or equal to a spacing between a gate and a gate of another semiconductor device.

10. A static random access memory device, characterized in that, comprising: a plurality of static random access memory bit cells, each static random access memory bit cell comprising: a portion of a buried insulator layer, wherein a bottom of the buried insulator layer is lower than a topmost surface of a substrate, and the portion of the buried insulator layer is formed only beneath a first source / drain region; and a plurality of nanosheet layers separating the first source / drain region from a second source / drain region; and a bit line coupling the plurality of static random access memory bit cells together, the bit line being electrically coupled to the portion of the buried insulator layer.

11. The static random access memory device according to claim 10, characterized in that, none of the plurality of bit cells is coupled to a read assist circuit.

12. The static random access memory device according to claim 10, characterized in that, Each of the plurality of nanosheets includes a semiconductor material having at least one of Si, P, Ge, Ga, SiGe, or InAs.

13. The static random access memory device according to claim 10, wherein, The buried insulator layer includes a dielectric material having Si 3 N 4 、SiO 2 、Al 2 O 3 、HfO 2 、Ta 2 O 5 、or TiO 2 and at least one of the following.

14. The static random access memory device according to claim 10, wherein, The plurality of nanosheets are separated from each other by a plurality of insulating layers.

15. The static random access memory device according to claim 10, wherein, The plurality of nanosheets are located above the portion of the buried insulator layer in the vertical direction.

16. The static random access memory device according to claim 10, wherein, Each static random access memory bit cell in the static random access memory bit cells includes a first transistor coupled to a second transistor, and a first current passes through the first transistor, wherein the first current is less than a second current passing through the second transistor.

17. A method of manufacturing a semiconductor device, wherein, comprising: Forming a first nanosheet above a substrate; Depositing a first gate electrode layer above the first nanosheet; Forming a buried insulator layer buried in the substrate, wherein a bottom of the buried insulator layer is lower than a topmost surface of the substrate; and Forming a source region and a drain region, the buried insulator layer being located under only one of the source region and the drain region, wherein the first nanosheet is located (i) between the source region and the drain region in the horizontal direction, and (ii) above the buried insulator layer in the vertical direction.

18. The method of manufacturing a semiconductor device according to claim 17, wherein, further comprising: Forming a gate above the first nanosheet; Forming an insulator layer above the first nanosheet in the vertical direction, the insulator separating the first nanosheet from a second nanosheet; and Forming the second nanosheet above the insulator layer, wherein the gate is formed above the second nanosheet.

19. The method of manufacturing a semiconductor device according to claim 18, wherein, Each of the first nanosheet and the second nanosheet is formed using a semiconductor material having at least one of Si, P, Ge, Ga, SiGe, or InAs.

20. The method of manufacturing a semiconductor device according to claim 17, wherein, The buried insulator layer is formed using a dielectric material having Si 3 N 4 , SiO 2 , Al 2 O 3 , HfO 2 , Ta 2 O 5 , or TiO 2 and at least one of the above.

21. A semiconductor device, wherein, comprising: A first transistor, above a substrate and including: A first source / drain region; A layer between the first source / drain region and the substrate and made of a dielectric material, the layer being buried in the substrate; A second source / drain region, contacting the substrate; and A channel region, between the first source / drain region and the second source / drain region in the horizontal direction, wherein the channel region contacts the substrate.

22. The semiconductor device according to claim 21, wherein, The channel region is above the topmost surface of the substrate.

23. The semiconductor device according to claim 21, It is characterized in that it further includes a gate electrode on the top surface of the channel region.

24. The semiconductor device according to claim 21, it is characterized in that the channel region includes a plurality of nanosheets.

25. The semiconductor device according to claim 24, it is characterized in that each of the nanosheets has a nanosheet width, and the layer has a width equal to or greater than the nanosheet width.

26. The semiconductor device according to claim 21, it is characterized in that the first transistor includes a gate, and the layer has a depth greater than half of the depth of the gate.

27. The semiconductor device according to claim 21, it is characterized in that it further includes a second transistor adjacent to the first transistor, wherein the layer has a length equal to or greater than a space between a gate of the first transistor and a gate of the second transistor.

28. A memory device, it is characterized in that it includes: a plurality of bit cells, each bit cell including: a first transistor above a substrate and having a first source / drain region, a first layer between the first source / drain region and the substrate and made of a dielectric material different from the substrate, the first layer being buried in the substrate, a second source / drain region contacting the substrate; and a channel region horizontally between the first source / drain region and the second source / drain region, wherein the channel region contacts the substrate; and a first bit line coupled to the first source / drain region of the first transistor.

29. The memory device according to claim 28, it is characterized in that the channel region is above a top surface of the substrate.

30. The memory device according to claim 28, it is characterized in that it further includes a gate electrode on the top surface of the channel region.

31. The memory device according to claim 28, it is characterized in that it further includes an inverter connected to the second source / drain region of the first transistor.

32. The memory device according to claim 28, it is characterized in that each bit cell further includes: a second transistor above the substrate and having: a first source / drain region, a second layer between the first source / drain region and the substrate and made of a different material from the substrate, and a second source / drain region contacting the substrate; and a second bit line coupled to the first source / drain region of the second transistor.

33. The memory device according to claim 32, it is characterized in that it further includes an inverter connected to the second source / drain region of the second transistor.

34. The memory device according to claim 32, it is characterized in that each of the first transistor and the second transistor has a gate connected to a word line.

35. A method of using a semiconductor device, it is characterized in that it includes: generating a first current flowing through a first transistor of a bit cell, the first transistor having a first source / drain region connected to a bit line of the bit cell; and A second current greater than the first current is generated, and the second current flows through a second transistor of the bit cell, and the second transistor is connected to a second source / drain region of the first transistor.

36. The method of using a semiconductor device according to claim 35, wherein, it further includes performing a read operation on the bit cell without a read assist circuit.

37. The method of using a semiconductor device according to claim 35, wherein, the second transistor is further connected to a third transistor, and the second transistor and the third transistor form an inverter.

38. The method of using a semiconductor device according to claim 35, wherein, the first transistor has a gate which is connected to a word line.

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