Analog-to-digital converter decision control
By introducing a CDAC control circuit into the SAR ADC, the trigger setup time delay is eliminated, the decision feedback timing is optimized, the problem of long CDAC decision feedback time is solved, and faster and more accurate conversion is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TEXAS INSTRUMENTS INC
- Filing Date
- 2020-06-22
- Publication Date
- 2026-06-12
AI Technical Summary
The decision feedback time of existing successive approximation register (SAR) analog-to-digital converters (ADCs) with capacitive digital-to-analog converters (CDACs) is relatively long, which affects the conversion time and accuracy.
By introducing a CDAC control circuit into the SAR ADC, the setup time delay of the trigger in the trigger is eliminated, the time for the digital circuit controlling the CDAC to generate control signals is reduced, and the decision feedback timing is optimized.
It effectively reduced the time spent on each decision, improved the conversion speed and accuracy, and reduced the total conversion time.
Smart Images
Figure CN112152629B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of this application relate to decision control of analog-to-digital converters. Background Technology
[0002] Various analog-to-digital converters (ADCs) and conversion techniques are used to convert electrical signals from the analog domain to the digital domain. Typically, the ADC process involves sampling the analog signal and comparing the sampled analog signal to a threshold. The binary result is recorded based on the comparison. The process of comparing samples to the threshold can be repeated multiple times, with each successive comparison using a different threshold and a residual sample. The number of iterations typically affects the noise level of any result and the resolution of the final digital signal.
[0003] A successive approximation register (SAR) converter is an example of an analog-to-digital converter (ADC). A SAR ADC performs a binary search for the digital value that best corresponds to the voltage of the analog signal. In a SAR ADC, the voltage input is compared to half the voltage reference. If the voltage input is greater than half the voltage reference, a logic '1' is stored in the register. Alternatively, if the voltage input is less than half the voltage reference, a logic '0' is stored in the register. Next, if the previous comparison indicates that the voltage input is greater than half the voltage reference, the voltage input is compared to three-quarters of the voltage reference. Again, if the comparison indicates a greater condition, a logic '1' is stored in the register. Conversely, if the comparison indicates a less condition, a logic '0' is stored in the register. Alternatively, if the previous comparison indicates that the voltage input is less than half the voltage reference, the voltage input is compared to one-quarter of the voltage reference. Again, if the comparison indicates a greater condition, a logic '1' is stored in the register. Conversely, if the comparison indicates a less condition, a logic '0' is stored in the register. This process continues for lower-order multiples of the voltage reference. It is understandable that the above process can provide high-resolution ADC results in a relatively short time. In particular, only a single iteration can be used to produce each bit of resolution. For example, only 10 iterations are needed for 10-bit resolution, and only 20 iterations are needed for 20-bit resolution. Summary of the Invention
[0004] This document discloses a circuit for reducing the time required to provide decision feedback to a capacitive digital-to-analog converter (CDAC) of a successive approximation register (SAR) analog-to-digital converter (ADC) and reducing the ADC's conversion time. In one example, the ADC includes a CDAC, a comparator, and SAR control circuitry. The comparator is coupled to the output of the CDAC. The SAR control circuitry is coupled to the output of the comparator and the input of the CDAC. The SAR control circuitry includes a flip-flop. The flip-flop includes a clock input terminal, a data input terminal, an enable input terminal, and an output. The clock input terminal is coupled to the output of the comparator. The data input terminal is coupled to a constant voltage source. The enable input terminal is coupled to SAR state circuitry. The output is coupled to the CDAC.
[0005] In another example, the CDAC circuit includes a CDAC and control circuitry. The CDAC includes multiple capacitors and multiple switches. Switches are coupled to the capacitors. Control circuitry is coupled to the CDAC. Control circuitry includes flip-flops. Flip-flops include a clock input terminal, a data input terminal, an enable input terminal, and an output. The clock input terminal is coupled to the comparator's output. The data input terminal is coupled to a constant voltage source. The enable input terminal is coupled to the CDAC state circuitry. The output is coupled to the first of the switches.
[0006] In another example, a method includes comparing the outputs of a first CDAC and a second CDAC via a comparator circuit. The method further includes using a signal generated at the output of the comparator circuit as a clock signal to time a constant value in a flip-flop. The method further includes routing an output signal generated by the flip-flop to the CDAC, wherein the output signal controls the switching of a reference voltage to a capacitor in the CDAC. Attached Figure Description
[0007] To describe the various examples in detail, reference will now be made to the accompanying drawings, in which:
[0008] Figure 1 A block diagram of an example of a successive approximation register (SAR) analog-to-digital converter (ADC) according to this disclosure is shown;
[0009] Figure 2 Explanation is shown Figure 1 Timing diagram of an example of comparator operation in a SAR ADC;
[0010] Figure 3 A schematic level diagram of a portion of an example capacitive digital-to-analog converter (CDAC) suitable for SAR ADC according to this disclosure is shown;
[0011] Figure 4 A schematic level diagram of an example CDAC control circuit for reducing decision time according to this disclosure is shown;
[0012] Figure 5 Explanation is shown Figure 4 A timing diagram illustrating an example of the operation of the CDAC control circuit;
[0013] Figure 6 A schematic level diagram of a CDAC control circuit, another example of reducing decision time according to this disclosure, is shown; and
[0014] Figure 7 and 8 A flowchart of an example method for controlling a CDAC according to this disclosure is shown. Detailed Implementation
[0015] Certain terms are used throughout the specification and claims to refer to specific system components. As those skilled in the art will understand, different parties may refer to components by different names. This document is not intended to distinguish components with different names rather than different functions. In this disclosure and claims, the terms "including" and "comprising" are used in an open-ended manner and should therefore be interpreted as meaning "including, but not limited to, (including)...". Furthermore, the term "coupled" is intended to indicate an indirect or direct wired or wireless connection. Thus, if a first device is "coupled" to a second device, the connection may be a direct connection or an indirect connection via other devices and connections. The expression "based on" is intended to mean "at least partially based on". Thus, if X is based on Y, then X can be a function of Y and any number of other factors.
[0016] Some successive approximation register (SAR) analog-to-digital converters (ADCs) contain a capacitive digital-to-analog converter (DAC) to generate an analog signal, which is compared as part of a binary search of the ADC's digital output value. During the conversion, the switching of the reference voltage to the CDAC is controlled by digital circuitry. The output of the digital circuitry is a function of the comparison result from the CDAC output. Therefore, in a SAR ADC, the time from one bit decision to the next (and the overall conversion rate) is limited by the time required for the digital circuitry to change the control signal supplied to the reference voltage switch of the CDAC.
[0017] The CDAC control circuit disclosed herein reduces the time required for the digital circuitry controlling the CDAC to generate the control signal for the next CDAC bit comparison. The implementation of the control circuit improves decision feedback timing by eliminating the flip-flop setup time delay in the flip-flop of the control circuitry that stores the control signal for the next bit. For example, if the implementation of the control circuit eliminates a 1.5 nanosecond (ns) setup time for each decision, the total conversion time can be reduced by 1.5 ns multiplied by the number of bits being converted, or 1.5 ns can be added to the CDAC setup time in each bit cycle to improve conversion accuracy.
[0018] Figure 1 A block diagram of an example SAR ADC 100 according to this disclosure is shown. The SAR ADC 100 includes a CDAC 102, a CDAC 104, a comparator 106, and SAR control circuitry 108. CDAC 102 and CDAC 104 are coupled to comparator 106 and SAR control circuitry 108. CDAC 102 generates an analog output signal 110 based on the charge stored in a capacitor of CDAC 102. Similarly, CDAC 104 generates an analog output signal 112 based on the charge stored in a capacitor of CDAC 104. Comparator 106 compares analog output signal 110 and analog output signal 112, and generates output signals 114 and 116 based on the comparison. Output signal 114 indicates that analog output signal 112 is greater than analog output signal 110, and output signal 116 indicates that analog output signal 110 is greater than analog output signal 112. SAR control circuit 108 receives output signals 114 and 116, and generates control signals 118 and 120 based on output signals 114 and 116. Control signal 118 sets the switching state in CDAC 102, wherein changing the switching state in CDAC 102 changes the voltage of analog output signal 110. Similarly, control signal 120 sets the switching state in CDAC 104, wherein changing the switching state in CDAC 104 changes the voltage of analog output signal 112.
[0019] Therefore, in the SAR ADC 100, the control of CDAC 102 and CDAC 104 is based on feedback that generates control signals 118 and 120 according to the analog output signal 110 of CDAC 102 and the analog output signal 112 of CDAC 104. The SAR control circuit 108 includes circuitry to reduce the time required to generate control signals 118 and 120 based on output signals 114 and 116, thereby allowing a reduction in the total conversion time of the SAR ADC 100.
[0020] Figure 2A timing diagram illustrating an example of the operation of comparator 106 in SAR ADC 100 is shown. SAR_CLK 202 controls the timing bit decision in SAR ADC 100. In each cycle of SAR_CLK 202, the value of one bit of the digital output value generated by SAR ADC 100 is determined. In cycle 206, the value of the first bit is determined, and in cycle 208, the value of the second bit is determined. COMP_CLK 204 controls comparator 106. Comparator 106 generates an output signal when COMP_CLK 204 is low. In interval 210, COMP_CLK 204 is low, and comparator 106 provides pulse 214 to output signal 114, indicating that analog output signal 112 is greater than analog output signal 110. In interval 212, COMP_CLK 204 is low, and comparator 106 provides pulse 216 to output signal 116, indicating that analog output signal 110 is greater than analog output signal 112. At any given time, comparator 106 will pulse either output signal 114 or output signal 116 (but not both).
[0021] Figure 3 A schematic level diagram of a portion of an example CDAC 300 suitable for SAR ADC 100 is shown. The CDAC 300 includes multiple capacitors 302 and multiple capacitors 303, with one capacitor 302 and one capacitor 303 operating as a pair. Capacitor 302-1 is paired with capacitor 303-1, and capacitor 302-2 is paired with capacitor 303-2. Capacitor 302-3 is paired with capacitor 303-3, and capacitor 302-4 is paired with capacitor 303-4. The top plates of capacitors 302 and 303 are connected.
[0022] Switches couple the base plate of each capacitor 302 and each capacitor 303 to a first reference voltage (RefP), a second reference voltage (RefM), or the voltage to be digitized (Vin). For example, the base plate of capacitor 302-1 is coupled to RefP via switch 304-1, to RefM via switch 304-2, and to Vin via switch 304-3. Similarly, the base plate of capacitor 303-1 is coupled to RefP via switch 305-1, to RefM via switch 305-2, and to Vin via switch 305-3. Control signals 118 (or 120) generated by the SAR control circuit 108 control switches 304 and 305. During digitization, the voltage depends on the signal V being digitized. INDepending on the voltage, some switches 304 and 305 can connect the corresponding capacitors 302 or 303 to RefP, while some switches 304 and 305 can connect the corresponding capacitors 302 or 303 to RefM. SAR control circuit 108 provides a control signal (or control signal 120) for each switch.
[0023] Figure 4 A schematic level diagram of an example CDAC control circuit 400 for reducing decision time according to this disclosure is shown. The CDAC control circuit 400 may be included in the SAR control circuit 108 to generate control signals 118 and / or 120. The CDAC control circuit 400 includes flip-flops 402 and 404, a clock generation circuit 406, selection circuits 408, 410, 412, and 414. A SAR state circuit 424 (also referred to herein as the CDAC state circuit 424) controls the analog-to-digital conversion in the SAR ADC 100 and generates control signals applied to the CDAC control circuit 400.
[0024] The trigger 402 includes a clock input terminal 402-1, a data input terminal 402-2, an enable input terminal 402-3, a preset input terminal 402-5, and an output 402-4. The clock input terminal 402-1 is coupled to the output 106-1 of the comparator 106. In some embodiments, the clock input terminal 402-1 may be coupled to the output 106-2 instead of the output 106-1. The data input terminal 402-2 is coupled to a constant voltage source. For example, the data input terminal 402-2 is... Figure 4 The circuit is grounded in the middle and can be coupled to different constant voltage sources in other embodiments of the CDAC control circuit 400. Enable input terminal 402-3 is coupled to SAR state circuit 424. Enable signal 422 generated by SAR state circuit 424 is activated to allow trigger 402 to change state in response to output signal 114. Enable signal 422 is activated when the states of switches 304 and 305 controlled by CDAC control circuit 400 are set to be part of the digitization process. Preset input terminal 402-5 is coupled to SAR state circuit 424. Sample signal 426 generated by SAR state circuit 424 sets trigger 402 to the start of digitization processing when CDAC 102 is sampling the analog signal to be digitized.
[0025] Some CDAC control circuits use a clock derived from the output signals 114 and 116 of comparator 106 to time the state of output signal 114 or output signal 116 into the flip-flop. In such implementations, the clock must be delayed to provide sufficient setup time for the flip-flop, which lengthens the bit decision time and increases the total digitization time. Because data input terminal 402-2 is coupled to a constant voltage source, the setup time of output signal 114 is not an issue, and flip-flop 402 can be timed by the edge of output signal 114 without additional delay. Therefore, in other implementations, CDAC control circuit 400 reduces bit decision time and total digitization time by eliminating the clock delay required to provide setup time.
[0026] Clock generation circuit 406 combines output signals 114 and 116 to generate clock signal 430 for timing flip-flop 404. Clock generation circuit 406 includes input 406-1 coupled to output 106-1 of comparator 106, and input 406-2 coupled to output 106-2 of comparator 106. Output 406-3 of clock generation circuit 406 provides clock signal 430 to flip-flop 404.
[0027] The trigger 404 includes a clock input terminal 404-1, a data input terminal 404-2, an enable input terminal 404-3, a preset input terminal 404-5, and an output 404-4. The clock input terminal 404-1 is coupled to the output 406-3 of the clock generation circuit 406. The data input terminal 404-2 is coupled to a constant voltage source. For example, the data input terminal 404-2 is... Figure 4 The flip-flop 404 is coupled to a logic 1 voltage source, and in other embodiments of the CDAC control circuit 400, it may be coupled to a different constant voltage source. Enable input terminal 404-3 is coupled to SAR state circuit 424. The enable signal 422 generated by SAR state circuit 424 is activated to allow flip-flop 404 to change state in response to output signal 114 or output signal 116. Enable signal 422 is activated when the states of switches 304 and 305, controlled by CDAC control circuit 400, are set as part of the digitization process. Preset input terminal 404-5 is coupled to SAR state circuit 424. At the start of the digitization process, when CDAC 102 is sampling the analog signal to be digitized, sample signal 426 generated by SAR state circuit 424 resets flip-flop 404. Flip-flop 404 generates control signal 419, which controls selection circuit 408 and selection circuit 410.
[0028] Selection circuits 408 and 410 route the output of flip-flop 402 to CDAC 102 (or CDAC 104). Selection circuit 408 includes inputs 408-1, 408-2, 408-3, and output 408-4. Input 408-1 is coupled to output 402-4 of flip-flop 402. Input 408-2 is coupled to output 404-4 of flip-flop 404. Input 408-3 is coupled to selection circuit 412. Output 408-4 is coupled to one of switches 305. When control signal 419 is active, selection circuit 408 routes the output of flip-flop 402 to switch 305. When control signal 419 is inactive, selection circuit 408 routes the output of selection circuit 412 to switch 305.
[0029] Selection circuit 410 includes inputs 410-1, 410-2, 410-3, and output 410-4. Input 410-1 is coupled to output 402-4 of flip-flop 402. Input 410-2 is coupled to output 404-4 of flip-flop 404. Input 410-3 is coupled to selection circuit 414. Output 410-4 is coupled to one of switches 304. When control signal 419 is active, selection circuit 410 routes the output of flip-flop 402 to switch 304. When control signal 419 is inactive, selection circuit 410 routes the output of selection circuit 414 to switch 304.
[0030] Figure 5 Explanation is shown Figure 4 A timing diagram illustrating an example of the operation of the CDAC control circuit 400. During cycle 512 of SAR_CLK 202, the SAR state circuit 424 activates the enable signal 422 to allow the CDAC control circuit 400 to set the states of switches 304 and 305. During interval 502 of COMP_CLK 204, comparator 106 generates a pulse 504 to the output signal 114. The data input terminal 402-2 of trigger 402 is at a constant voltage 428. The edge 514 of pulse 504 times the constant voltage 428 onto trigger 402. At 506, trigger 404 changes state in response to edge 514 to activate control signal 419. Control signal 419 causes selection circuit 408 to select the output of trigger 402 for routing to switch 305, and at 508, the output signal 418 of selection circuit 408 changes state when the output of trigger 402 is routed to switch 305.
[0031] Figure 6A schematic level diagram of a CDAC control circuit 600, another example of a CDAC control circuit for reducing decision time according to this disclosure, is shown. The CDAC control circuit 600 may be included in a SAR control circuit 108 to generate control signals 118 and / or 120. The CDAC control circuit 600 includes flip-flops 602 and 604, a selection circuit 606, and a selection circuit 608. SAR state circuit 424 ( Figure 4 (As shown) controls the analog-to-digital conversion in the SAR ADC 100 and generates control signals for use in the CDAC control circuit 600.
[0032] The trigger 602 includes a clock input terminal 602-1, a data input terminal 602-2, an enable input terminal 602-3, a preset input terminal 602-5, and an output 602-4. The clock input terminal 602-1 is coupled to the output 106-1 of the comparator 106. The data input terminal 602-2 is coupled to a constant voltage source. For example, in... Figure 6 The data input terminal 602-2 is coupled to ground. The enable input terminal 602-3 is coupled to the SAR state circuit 424. The enable signal 422 generated by the SAR state circuit 424 is activated to allow the trigger 602 to change its state in response to the output signal 114. The enable signal 422 is activated when the states of switches 304 and 305, controlled by the CDAC control circuit 600, are set to be part of the digitization process. The preset input terminal 602-5 is coupled to the SAR state circuit 424. The sample signal 426 generated by the SAR state circuit 424 sets the trigger 602 to the start of digitization processing when the CDAC 102 is sampling the analog signal to be digitized.
[0033] The trigger 604 includes a clock input terminal 604-1, a data input terminal 604-2, an enable input terminal 604-3, a reset input terminal 604-5, and an output 604-4. The clock input terminal 604-1 is coupled to the output 106-2 of the comparator 106. The data input terminal 604-2 is coupled to a constant voltage source. For example, the data input terminal 604-2 is coupled to... Figure 6 The voltage source is designated as "Logic 1". Enable input terminal 604-3 is coupled to SAR state circuit 424. Enable signal 422 generated by SAR state circuit 424 is activated to allow flip-flop 604 to change state in response to output signal 116. Enable signal 422 is activated when the states of switches 304 and 305, controlled by CDAC control circuit 600, are set as part of the digitization process. Reset input terminal 604-5 is coupled to SAR state circuit 424. At the start of the digitization process, when CDAC 102 is sampling the analog signal to be digitized, sample signal 426 generated by SAR state circuit 424 resets flip-flop 604.
[0034] Similar to CDAC control circuit 400, CDAC control circuit 600 eliminates setup time delay by applying a constant voltage to the data input terminals of flip-flops 602 and 604. CDAC control circuit 600 also reduces the load on the flip-flops, as each of flip-flops 602 and 604 drives only one load. Therefore, CDAC control circuit 600 reduces bit decision time and total digitization time by eliminating clock delay.
[0035] Selection circuit 606 routes the output of flip-flop 602 to CDAC 102 (or CDAC 104). Similarly, selection circuit 608 routes the output of flip-flop 604 to CDAC 102 (or CDAC 104). Selection circuit 606 includes inputs 606-1, 606-2, 606-3, and output 606-4. Input 606-1 is coupled to output 602-4 of flip-flop 602. Input 606-2 is coupled to a constant voltage source, such as ground. Input 606-3 is coupled to SAR state circuit 424. Output 606-4 is coupled to one of switches 305. When sample signal 426 is invalid, selection circuit 606 routes the output of flip-flop 602 to switch 305. When sample signal 426 is valid, selection circuit 606 routes the voltage at input 606-2 to switch 305.
[0036] Selection circuit 608 includes inputs 608-1, 608-2, 608-3, and output 608-4. Input 608-1 is coupled to output 604-4 of trigger 604. Input 608-2 is coupled to a constant voltage source, such as ground. Input 608-3 is coupled to SAR state circuit 424. Output 608-4 is coupled to one of switches 304. When sample signal 426 is invalid, selection circuit 608 routes the output of trigger 604 to switch 304. When sample signal 426 is valid, selection circuit 608 routes the voltage at input 608-2 to switch 304.
[0037] Figure 7 A flowchart of an example method 700 for controlling a CDAC 300 according to this disclosure is shown. Although described sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. Additionally, some embodiments may perform only some of the actions shown. Operation of method 700 may be performed by an embodiment of a SAR ADC 100, which includes CDAC control circuitry 400.
[0038] In block 702, SAR ADC 100 digitizes the analog signal. CDAC 102 and CDAC 104 generate analog output signals 110 and 112, and comparator 106 compares analog output signals 110 and 112. As a result of the comparison, comparator 106 generates a pulse for either output signal 114 or output signal 116.
[0039] In block 704, a constant voltage 428 is timed to the trigger 402 at the edge of the output signal 114 to generate a signal for controlling switches 304 and 305. The edge of the output signal 114 is not delayed to provide setup time at the data input terminal 402-2 of the trigger 402.
[0040] In block 706, clock generation circuit 406 combines output signal 114 and output signal 116 to generate clock signal 430 for timing flip-flop 404.
[0041] In block 708, a constant voltage 432 is timed to a flip-flop 404 at the edge of a clock signal 430 to generate a control signal 419 for controlling selection circuits 408 and 410.
[0042] In block 710, selection circuit 408 selectively routes the output signal generated by trigger 402 to switch 305. The routing of selection circuit 408 is controlled by control signal 419. Output signal 418 controls the switching of the reference voltage to capacitor 303 of CDAC 300.
[0043] In block 712, selection circuit 410 selectively routes the output signal generated by trigger 402 to switch 304. The routing of selection circuit 410 is controlled by control signal 419. Output signal 420 controls the switching of the reference voltage to capacitor 302 of CDAC 300.
[0044] Figure 8 A flowchart of an example method 800 for controlling a CDAC 300 according to this disclosure is shown. Although described sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. Additionally, some embodiments may perform only some of the actions shown. Operation of method 800 may be performed by an embodiment of a SAR ADC 100, which includes CDAC control circuitry 600.
[0045] In block 802, SAR ADC 100 digitizes the analog signal. CDAC 102 and CDAC 104 generate analog output signals 110 and 112, and comparator 106 compares analog output signal 110 with analog output signal 112. As a result of the comparison, the comparator generates a pulse for either output signal 114 or output signal 116.
[0046] In block 804, a constant voltage 610 is timed to trigger 602 at the edge of output signal 114 to generate a signal for controlling switch 305. The edge of output signal 114 is not delayed to provide setup time at data input terminal 602-2.
[0047] In block 806, a constant voltage 612 is timed to trigger 604 at the edge of output signal 116 to generate a signal for controlling switch 304. The edge of output signal 116 is not delayed to provide setup time at data input terminal 602-2. During any given cycle of SAR_CLK 202, comparator 106 generates a pulse for only one of output signal 114 or output signal 116.
[0048] In block 808, selection circuit 606 selectively routes the output signal generated by trigger 602 to switch 305. The routing of selection circuit 606 is controlled by sample signal 426. Output signal 618 controls the switching of the reference voltage to capacitor 303 of CDAC 300.
[0049] In block 810, selection circuit 608 selectively routes the output signal generated by trigger 604 to switch 304. The routing of selection circuit 608 is controlled by sample signal 426. Output signal 620 controls the switching of the reference voltage to capacitor 302 of CDAC 300.
[0050] The foregoing discussion is intended to illustrate the principles and various embodiments of the invention. Once the foregoing disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. The appended claims are intended to be construed as encompassing all such variations and modifications.
Claims
1. An analog-to-digital converter (ADC), comprising: Capacitive digital-to-analog converter (CDAC); A comparator coupled to the output of the CDAC; as well as A successive approximation register SAR control circuit, coupled to the output of the comparator and the input of the CDAC, the SAR control circuit comprising: The first trigger includes: A clock input terminal, which is coupled to the output of the comparator; Data input terminals, coupled to a first constant voltage source; and The output, which is coupled to the CDAC; and The second trigger includes: A clock input terminal, which is coupled to multiple outputs of the comparator; Data input terminals, coupled to a second constant voltage source; and The output is coupled to the CDAC.
2. The ADC according to claim 1, wherein the SAR control circuit includes a clock generation circuit, the clock generation circuit comprising: The first input is coupled to the first output of the comparator; The second input is coupled to the second output of the comparator; as well as The output is coupled to the clock input terminal of the second flip-flop.
3. The ADC according to claim 1, wherein the SAR control circuit further comprises: The first selection circuit includes: A first input, which is coupled to the output of the first flip-flop; The second input is coupled to the output of the second flip-flop; The third input, which is coupled to the second selection circuit; and The output is coupled to the CDAC.
4. The ADC according to claim 3, wherein the SAR control circuit further comprises: The third selection circuit includes: A first input, which is coupled to the output of the first flip-flop; The second input is coupled to the output of the second flip-flop; The third input, which is coupled to the fourth selection circuit; and The output is coupled to the CDAC.
5. The ADC according to claim 1, wherein: The output of the first flip-flop is coupled to the first input of the CDAC; The clock input terminal of the first flip-flop is coupled to the first output of the comparator; The clock input terminal of the second flip-flop is coupled to the second output of the comparator; as well as The output of the second flip-flop is coupled to the second input of the CDAC.
6. The ADC of claim 5, wherein the SAR control circuit further comprises: The first selection circuit includes: A first input, which is coupled to the output of the first flip-flop; The second input is coupled to the SAR state circuit. The output, coupled to the first input of the CDAC; and The second selection circuit includes: The first input is coupled to the output of the second flip-flop; The second input, which is coupled to the SAR state circuit; and The output is coupled to the second input of the CDAC.
7. A capacitive digital-to-analog converter (CDAC) circuit, comprising: CDAC, which includes: Multiple capacitors; and Multiple switches coupled to the capacitor; and A control circuit, coupled to the CDAC, and comprising: The first trigger includes: The clock input terminal is coupled to the comparator's output. Data input terminals, coupled to a first constant voltage source; and The output, which is coupled to the first of the switches; and The second trigger includes: A clock input terminal, which is coupled to multiple outputs of the comparator; Data input terminals, coupled to a second constant voltage source; and The output is coupled to the CDAC.
8. The CDAC circuit according to claim 7, wherein the control circuit includes a clock generation circuit, the clock generation circuit comprising: The first input is coupled to the first output of the comparator; The second input is coupled to the second output of the comparator; as well as The output is coupled to the clock input terminal of the second flip-flop.
9. The CDAC circuit according to claim 8, wherein the control circuit further comprises: The first selection circuit includes: A first input, which is coupled to the output of the first flip-flop; The second input is coupled to the output of the second flip-flop; The third input, which is coupled to the second selection circuit; and The output is coupled to the CDAC.
10. The CDAC circuit according to claim 9, wherein the control circuit further comprises: The third selection circuit includes: A first input, which is coupled to the output of the first flip-flop; The second input is coupled to the output of the second flip-flop; The third input, which is coupled to the fourth selection circuit; and The output is coupled to the CDAC.
11. The CDAC circuit according to claim 7, wherein: The clock input terminal of the first flip-flop is coupled to the first output of the comparator; The clock input terminal of the second flip-flop is coupled to the second output of the comparator; as well as The output of the second trigger is coupled to the second of the switches.
12. The CDAC circuit according to claim 11, further comprising: The first selection circuit includes: A first input, which is coupled to the output of the first flip-flop; The second input, which is coupled to the CDAC state circuit; and The output, which is coupled to the first of the switches; and The second selection circuit includes: The first input is coupled to the output of the second flip-flop; The second input, coupled to the CDAC state circuit; and The output is coupled to the second of the switches.
13. A method for signal processing, comprising: The output of the first capacitive digital-to-analog converter (CDAC) is compared with the output of the second CDAC by a comparator circuit; The signal generated at the first output of the comparator circuit is applied as a clock signal to time the first constant value into the first flip-flop; The output signal generated by the first trigger is routed to the CDAC, wherein the output signal controls the switching of the reference voltage to the first capacitor of the CDAC. The signal generated at the first output of the comparator circuit is combined with the signal generated at the second output of the comparator circuit to generate a clock signal; as well as The clock signal is applied to time the second constant value into the second flip-flop.
14. The method of claim 13, further comprising: The output signal generated by the first trigger is selectively routed based on the output of the second trigger to control the first switch of the CDAC.
15. The method of claim 14, further comprising: The output of the second trigger selectively routes the output signal generated by the first trigger to control the second switch of the CDAC.
16. The method of claim 13, wherein the method further comprises: The signal generated at the second output of the comparator circuit is applied as a clock signal to time the second constant value into the second flip-flop; and The output signal generated by the second trigger is routed to the CDAC, wherein the output signal controls the switching of the reference voltage to the second capacitor of the CDAC.
17. The method of claim 16, further comprising: The output signal generated by the first trigger is selectively routed to the first switch of the CDAC; and The output signal generated by the second trigger is selectively routed to the second switch of the CDAC.