Replay protected memory block command queue

Abstract

Disclosed herein are devices and techniques for providing improved replay protected memory block (RPMB) data frames and command queues for communications between a host device and a memory device.

Description

[0001] Priority application

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 62 / 680,405, filed on June 4, 2018, and the benefit of priority to U.S. Provisional Application No. 62 / 656,884, filed on April 12, 2018, both of which are incorporated herein by reference in their entirety. Background Art

[0003] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain data, and includes devices such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can retain stored data when not powered, and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory (such as phase change random access memory (PCRAM), resistive random access memory (RRAM), or magnetoresistive random access memory (MRAM)), etc.

[0004] A host system (e.g., a host device) typically includes a host processor, a first amount of host memory (e.g., main memory, typically volatile memory such as DRAM) to support the host processor, and one or more storage systems (e.g., typically non-volatile memory such as flash memory) in addition to or independent of the main memory to provide additional storage for retaining data.

[0005] A storage system (e.g., a solid-state drive (SSD), a universal flash storage (UFS) device, etc.) may include a control circuit system (e.g., a memory controller) and one or more memory devices, including several (e.g., multiple) dies or logical units (LUNs). In some examples, each die may include several memory arrays and peripheral circuit systems thereon, such as die logic or a die processor. The control circuit system may include an interface circuit system configured to communicate with a host device (e.g., a host processor or interface circuit system) through a communication interface (e.g., a bidirectional parallel or serial communication interface). The control circuit system may receive commands or operations associated with memory operations or instructions (e.g., read or write operations for transferring data (e.g., user data and associated integrity data, such as error data or address data, etc.) between a memory device and a host device, erase operations for erasing data from a memory device), perform drive management operations (e.g., data migration, garbage collection, block reclamation), etc. from a host system.

[0006] Memory systems are used as volatile and non-volatile data storage devices for a variety of electronic applications, including, for example, personal computers, portable memory sticks, digital cameras, cellular phones, portable music players (such as MP3 players), movie players, and other electronic devices. Memory cells may be arranged in an array, where the array is used in a memory device.

[0007] Software (e.g., programs), instructions, operating systems (OS), and other data are typically stored on storage systems and accessed by main memory for use by host processors. Main memory (e.g., RAM) is typically faster, more expensive, and has different types of memory devices (e.g., volatile memory) than most memory devices of storage systems (e.g., non-volatile memory such as SSDs, etc.). In addition to main memory, the host system may also include different forms of volatile memory, such as static memory groups (e.g., cache memory, typically SRAM), which are typically faster than main memory and, in some instances, are configured to operate at speeds approaching or exceeding the speed of the host processor, but with lower density and higher cost. Memory devices may also include static memory (e.g., SRAM) for supporting memory controllers or control circuitry. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the drawings, which are not necessarily drawn to scale, like numbers may describe similar components in different views. Like numbers with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0009] Figures 1 to 2 An example system including a host device and a memory device is described.

[0010] Figure 3 A first replay protected memory block (RPMB) data frame is described.

[0011] Figure 4 A character string describing the n first RPMB data frames.

[0012] Figure 5 Describe the second RPMB data frame.

[0013] Figure 6 Describe the third RPMB data frame.

[0014] Figure 7 Describes an example method for maintaining the RPMB command queue.

[0015] Figure 8 An example block diagram illustrating a memory device.

[0016] Fig. 9 A block diagram illustrating an example machine upon which any one or more of the techniques (eg, methodologies) discussed herein may be performed. DETAILED DESCRIPTION

[0017] The Joint Electronic Device Engineering Council (JEDEC) has issued a standard for universal flash storage (UFS) devices, embedded multimedia cards (eMMC TM ) device or one or more other storage devices. Replay Protected Memory Block (RPMB) allows access to portions of memory using hidden security keys, thereby providing secure storage for host devices to protect critical programs or data and implement copy protection. In some examples, RPMB can provide a secure way to exchange information and avoid man-in-the-middle attacks, thereby providing a kernel application programming interface (API) for a Trusted Execution Environment (TEE) device to securely calculate block frame signatures or access protected information.

[0018] Writes to the RPMB portion of memory may be authenticated using a key / mac (message authentication code), such as an HMAC SHA-256 algorithm calculated from a secure key (e.g., programmed into a host device or memory device) and a counter value that is incremented each time the RPMB portion of memory is written. The use of a counter and key / mac ensures that the message cannot be captured by an attacker and then replayed later (because the key / mac will not match due to changes in the counter).

[0019] Figure 1An example system 100 is described that includes a host device 105 and a memory device 110. The host device 105 may include a host processor, a central processing unit, or one or more other devices, processors, or controllers. The memory device 110 may include a universal flash storage (UFS) device, an embedded MMC (eMMC) device, or one or more other memory devices. The host device 105 and the memory device 110 may communicate using a communication interface (I / F) 115 (e.g., a bidirectional parallel or serial communication interface).

[0020] In an example, the memory device 110 may include a UFS device, and the communication interface 115 may include a serial bidirectional interface, such as defined in one or more Joint Electronic Device Engineering Council (JEDEC) standards (e.g., JEDEC Standard D223D (JESD223D), commonly referred to as JEDEC UFS Host Controller Interface (UFSHCI) 3.0, etc.). In another example, the memory device 110 may include an eMMC device, and the communication interface 115 may include a number of parallel bidirectional data lines (e.g., DAT[7:0]) and one or more command lines, such as defined in one or more JEDEC standards (e.g., JEDEC Standard D84-B51 (JESD84-A51), commonly referred to as JEDEC eMMC Standard 5.1, etc.). In other examples, the memory device 110 may include one or more other memory devices, or the communication interface 115 may include one or more other interfaces, depending on the host device 105 and the memory device 110.

[0021] Each of host device 105 and memory device 110 may include: a number of receiver or driver circuits that are configured to send or receive signals through communication interface 115; or interface circuits, such as data control units, sampling circuits, or other intermediate circuits, that are configured to process data to be communicated through communication interface 115 or otherwise process data received from communication interface 115 for use by host device 105, memory device 110, or one or more other circuits or devices.

[0022] The memory device 110 may include a memory array (e.g., one or more memory cell arrays, such as a NAND flash memory array, or one or more other memory arrays), a control circuit system such as a memory controller, and in some instances, an interface circuit between the memory array and the memory controller. In some instances, the memory array may include several memory dies, each memory die having control logic independent of the memory controller. The memory controller may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or one or more other processing circuits arranged or programmed to manage data transfer or operations to, from, or within the memory array. In addition, the memory device 110 may include a group of static memories (e.g., SRAM) configured to support the control circuit system.

[0023] Figure 2 An example portion of a system 200 is illustrated that includes a host device 205, a memory device 210, and a communication interface (I / F) 215. Memory device 210 may include a non-volatile memory (NVM) device 212 and control circuitry, such as a memory controller (MEM CTRL) 211 or circuit or control logic, and may use communication interface 215 to provide data from NVM device 212 to host device 205 or receive data from host device 205 for storage on NVM device 212.

[0024] The memory controller 211 may optionally include a limited amount of static memory 219 for supporting the operation of the memory controller 211. In an example, the NVM device 212 may include a number of non-volatile memory devices (e.g., dies or LUNs), such as one or more stacked flash memory devices (e.g., as illustrated with stacked dashed lines below the NVM device 212), etc., each flash memory device including non-volatile memory (NVM) 213 (e.g., one or more non-volatile memory groups) and a device controller (CTRL) 214 or other peripheral circuitry (e.g., device logic, etc.) thereon and controlled by the memory controller 211 through an internal storage system communication interface (e.g., an open NAND flash interface (ONFI) bus, etc.) that is independent of the communication interface 215. As used herein, control circuitry may refer to one or more of the memory controller 211, the device controller 214, or other peripheral circuitry in the memory device 210, the NVM device 212, etc.

[0025] The host device 205 may include a host processor 206 (e.g., a host central processing unit (CPU) or other processor or processing circuitry, such as a memory management unit (MMU), interface circuitry, etc.). In some examples, the host device 205 may include a main memory (MAIN MEM) 208 (e.g., DRAM, etc.) and optionally a static memory (STATIC MEM) 209 to support the operation of the host processor (HOST PROC) 206.

[0026] The host device 205 may include a host replay protected memory block (RPMB) circuit 216 (or other logic or encryption unit) configured to adapt host data (e.g., encrypt) for communication to the memory device 210 or receive RPMB data from the memory device 210, such as through a driver circuit 217 or other buffers. The memory device 210 may include a memory device replay protected memory block (RPMB) circuit 218 (or other logic or encryption unit) configured to receive the adapted host data from the communication interface 215, such as through one or more buffers, and check such access requests to a protected partition of the NVM device 212 (e.g., a RPMB partition 221 that is independent of a user partition or other portion of the NVM 213). If a valid command is confirmed, the memory device RPMB circuit 218 can enable communication of RPMB data between the host device 205 and the RPMB partition 221. In an example, the memory device RPMB circuit 218 and the host RPMB circuit 216 may include RPMB access logic including an authentication key circuit (eg, a one-time password (OTP)), a write counter, or one or more other circuits or logic.

[0027] Flash memory devices typically include one or more groups of single transistor, floating gate (FG) or replacement gate (RG) memory cells. Two common types of flash memory array architectures include NAND and NOR architectures. The memory cells of a memory array are typically arranged in a matrix. The gate of each memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a column of the array is coupled together in series in a source-to-drain manner between a source line and a bit line.

[0028] Each memory cell in a NOR, NAND, 3D cross-point, HRAM, MRAM, or one or more other architecture semiconductor memory array can be individually or collectively programmed to one or several programming states. A single-level cell (SLC) can represent one data bit per cell in one of two programming states (e.g., 1 or 0). A multi-level cell (MLC) can represent a data bit per cell in several programming states (e.g., 2 n , where n is the number of data bits). In some examples, MLC may refer to a memory cell that can store two data bits in one of four programmed states. A three-level cell (TLC) may represent three data bits per cell in one of eight programmed states. A quad-level cell (QLC) may represent four data bits per cell in one of 16 programmed states. In other examples, MLC may refer to any memory cell that can store more than one data bit per cell, including TLC and QLC, among others.

[0029] The memory device 210 may include a multimedia card (MMC) solid-state storage device (e.g., a micro secure digital (SD) card, etc.). The MMC device includes several parallel interfaces (e.g., an 8-bit parallel interface) with the host device 205, and is typically a removable and independent component of the host device. In contrast, an embedded MMC (eMMC) device is attached to a circuit board and is considered a component of the host device, and its read speed can be comparable to a Serial ATA (SATA)-based SSD device. As the demand for mobile device performance continues to increase, such as to fully enable virtual or augmented reality devices, take advantage of increased network speeds, etc., storage systems have transitioned from a parallel communication interface between the storage system and the host device to a serial communication interface. The UFS device, including a controller and firmware, uses a low voltage differential signaling (LVDS) serial interface with a dedicated read / write path to communicate with the host device, thereby further increasing the read / write speed between the host device and the storage system.

[0030] In three-dimensional (3D) architecture semiconductor memory device technology, vertical floating gate (FG) or replacement gate (RG) (or charge trapping) storage structures can be stacked to increase the number of levels, physical pages, and correspondingly the density of memory cells in the memory device. Data is usually stored arbitrarily on the storage system as small units. Even if accessed as a single unit, data can be received by small, random 4k to 16k single file reads (for example, 60% to 80% of operations are less than 16k). It is difficult for users and even kernel applications to indicate that data should be stored as a sequential cohesive unit. File systems are usually designed to optimize space usage and retrieve space non-sequentially.

[0031] Memory controller 211 may receive instructions from host device 205 and may communicate with NVM device 212, such as to transfer (e.g., write or erase) data to or from one or more of the memory cells of NVM device 212. Memory controller 211 may include, among other things, circuitry or firmware such as a number of components or integrated circuits. For example, memory controller 211 may include one or more memory control units, circuits, or components configured to control access across a memory array and provide a translation layer (e.g., a memory manager, one or more memory management tables, etc.) between host device 205 and storage system 200.

[0032] The memory manager may include, for example, circuitry or firmware, such as a number of components or integrated circuits, associated with various memory management functions, including, among other functions, wear leveling (e.g., garbage collection or reclamation), error detection or correction, block reclamation, or one or more other memory management functions. The memory manager may parse or format host commands (e.g., commands received from the host device 205) into device commands (e.g., commands associated with operation of a memory array, etc.), or generate device commands to the device controller 214 or one or more other components of the memory device 210 (e.g., to accomplish various memory management functions).

[0033] The memory manager may include a set of management tables configured to maintain various information associated with one or more components of the memory device 210 (e.g., various information associated with a memory array or one or more memory cells coupled to the memory controller 211). For example, the management table may include information about a block life, a block erase count, an error history, or one or more error counts (e.g., a write operation error count, a read bit error count, a read operation error count, an erase error count, etc.) of one or more memory cell blocks coupled to the memory controller 211. In certain examples, if the number of detected errors of one or more of the error counts is above a threshold, the bit error may be referred to as an uncorrectable bit error. The management table may, among other things, maintain a count of correctable or uncorrectable bit errors. In an example, the management table may include a translation table or an L2P map.

[0034] In operations involving searching the L2P table for valid pages (e.g., garbage collection), the memory manager may implement and use data structures to reduce memory device 210 latency. To this end, the memory manager is arranged to maintain a data structure of physical blocks (e.g., a table region data structure, a tracking data structure, etc.). The data structure includes an indication of an L2P mapping table region of the L2P table. In some examples, the data structure is a bitmap (e.g., a binary array). In an example, the bitmap includes a bit for each of a plurality of mutually exclusive regions across the L2P table.

[0035] NVM device 212 or NVM 213 (e.g., one or more 3D NAND architecture semiconductor memory arrays) may include a number of memory cells arranged into, for example, a number of devices, planes, blocks, physical pages, superblocks, or superpages. As one example, a TLC memory device may include 18,592 data bytes (B) per page, 1536 pages per block, 548 blocks per plane, and 4 planes per device. As another example, an MLC memory device may include 18,592 data bytes (B) per page, 1024 pages per block, 548 blocks per plane, and 4 planes per device, but with half the desired write time and twice the program / erase (P / E) cycles of a corresponding TLC memory device. Other examples may include other numbers or arrangements. A superblock may include a combination of, for example, multiple blocks from different planes, and a window may refer to a stripe of a superblock that generally matches a portion covered by a physical to logical (P2L) table group block, and a superpage may include a combination of multiple pages.

[0036] The term "super" may refer to a combination or multiple of one thing or several things. For example, a superblock may include a combination of blocks. If a memory device includes 4 planes, a superblock may refer to the same block on each plane, or a pattern of blocks across planes (e.g., a combination of block 0 on plane 0, block 1 on plane 1, block 2 on plane 2, and block 3 on plane 3, etc.). In an example, if a storage system includes multiple memory devices, the combination or pattern of blocks may extend across multiple memory devices. The term "stripe" may refer to a pattern of combinations or a pattern of one thing or several things. For example, a stripe of a superblock may refer to a combination or pattern of pages from each block in a superblock.

[0037] In operation, data is typically written to or read from the memory device 210 in pages and erased in blocks. However, as desired, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells. For example, partial updates of tag data from unloaded cells may be collected during data migration or garbage collection to ensure that they are effectively overwritten. The data transfer size of a memory device is typically referred to as a page, while the data transfer size of a host device is typically referred to as a sector. Although a data page may include several bytes of user data (e.g., a data payload including several sectors of data) and its corresponding metadata, the size of the page typically refers only to the number of bytes used to store the user data. As an example, a data page having a 4kB page size may include 4kB of user data (e.g., 8 sectors presenting a 512B sector size) and a number of bytes (e.g., 32B, 54B, 224B, etc.) of auxiliary data or metadata (e.g., integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data) corresponding to the user data.

[0038] Different types of memory cells or memory arrays may provide different page sizes, or may require different amounts of metadata associated therewith. For example, different memory device types may have different bit error rates, which may result in different amounts of metadata necessary to ensure data page integrity (e.g., a memory device with a higher bit error rate may require more bytes of error correction capability (ECC) data than a memory device with a lower bit error rate). As an example, an MLC NAND flash memory device may have a higher bit error rate than a corresponding SLC NAND flash memory device. Thus, an MLC device may require more bytes of metadata for erroneous data than a corresponding SLC device.

[0039] In an example, data in a chunk or data unit may be handled in an optimized manner throughout its occupancy on a storage system. For example, data may be managed as a unit during data migration (e.g., garbage collection, etc.) such that valid read / write properties are preserved as the data moves to its new physical location on the storage system. In some examples, the only limit on the number of chunks, data units, or blocks that may be configured for storage, tagging, etc. is the capacity of the system.

[0040] Figure 3The first RPMB data frame 300 is described. The first RPMB data frame 300 includes padding bytes 331 (e.g., 196 bytes), key / mac (message authentication code) bytes 332 (e.g., 32 bytes), data 333 (e.g., 256 bytes), random number bytes 334 (e.g., 16 bytes, randomly generated for each read command, etc.), write counter bytes 335 (e.g., 4 bytes), address bytes 336 (e.g., 2 bytes), block count bytes 337 (e.g., 2 bytes), result bytes 338 (e.g., 2 bytes) and request / response message type bytes 339 (e.g., 2 bytes). In an example, each first RPMB data frame 300 may include a total of 512 bytes, with 256 bytes of data. Therefore, the first RPMB data frame communication requires a 50% overhead between the host device and the memory device, where each data frame has 256 repetitive overhead bytes.

[0041] Figure 4 A string 400 of n first RPMB data frames is illustrated, which includes the first, second, third, fourth, fifth and nth first RPMB data frames, respectively. The first RPMB data frame is limited to 256 data bytes with 256 overhead bytes. In other examples, other numbers of data frames may be used depending on the amount of protected data sent or received. In an example, each corresponding data frame must be adapted or verified by one or more of the host RPMB circuit or the memory device RPMB circuit, thereby requiring a certain amount of processing power, time and communication bandwidth, because the first RPMB data frame read and write performance may be at least several times slower than the read and write access to the normal, unprotected portion of the memory device (e.g., user partition, etc.).

[0042] Figure 5 The second RPMB data frame 500 is described. Figure 3Compared to the second RPMB data frame 500 (described in ), the second RPMB data frame 500 separates the overhead or header (or meta) information before the data from the data, and moves the key / mac bytes to the end of the data frame after the data. The second RPMB data frame header information includes a padding byte 541 (e.g., 196 bytes), a random number byte 544 (e.g., 16 bytes), a write counter byte 545 (e.g., 4 bytes), an address byte 546 (e.g., 2 bytes), a block count byte 547 (e.g., 2 bytes), a result byte 548 (e.g., 2 bytes), and a request / response message type byte 549 (e.g., 2 bytes) for a total of 224 initial overhead bytes. After the header is data 543 (e.g., n×4kB, where n is the number of 4kB data chunks, blocks, etc.) and a key / mac byte 542 (e.g., 32 bytes). In other examples, other sizes of data (e.g., in other sizes, chunks, blocks, etc.) may be transferred between the initial bytes (e.g., 541 and 544-549) and the trailing key / mac bytes 542, thereby reducing overhead by requiring only one set of initial / header / meta bytes and key / mac bytes per data transaction. The key / mac bytes may be moved to the end of the transaction to enable streaming (on-the-fly) MAC calculations.

[0043] The inventors have recognized, among other things, further overhead / header reduction and improvements in RPMB operations and data transfer (e.g., reading, writing, etc.), including improved RPMB data frames. In an example, padding bytes may be removed from the RPMB data frame, and the order of bytes in the data frame header may be changed to be more intuitive when used in a system (e.g., used before all bytes are received, etc.). The desired write capacity increases with new generations of electronic or memory devices to accommodate changing usage conditions (e.g., memory devices storing sensitive credentials, user identity information, unique access information, tickets, etc.) or to accommodate increased system reliability or life. The write counter may be increased (e.g., from 4 bytes to 8 bytes or more, etc.) in order to increase possible RPMB usage to accommodate increased requests for sensitive data usage by electronic device users. The size of the header and total overhead may be increased from Figure 5 The 224 bytes illustrated in the second RPMB data frame 500 are reduced to only 32 bytes (or 64 bytes, with 32 bytes reserved for later use), thereby increasing efficiency, bandwidth and optimizing the process.

[0044] Figure 6The third RPMB data frame 600 is described. The header of the third RPMB data frame 600 includes a request / response message type byte 659 (e.g., 2 bytes), a result byte 658 (e.g., 2 bytes), a block count byte 657 (e.g., 2 bytes), an address byte 656 (e.g., 2 bytes), a write counter byte 655 (e.g., 8 bytes), and a random number byte 654 (e.g., 16 bytes). In an example, the initial overhead bytes before the data and key / mac bytes can be as few as 32 bytes (or 28 bytes, 4 of which are write counter bytes). In an example, the reserved / optional bytes 650 (e.g., 32 bytes) can be saved for future expansion, so that the initial overhead bytes reach 64 bytes. For example, the size of the address byte 656 can be increased (e.g., increased to 16 bytes, etc.) to achieve encryption of the address.

[0045] The header or initial overhead bytes may be followed by data 653 (e.g., n×4kB, where n is the number of 4kB data chunks, blocks, etc.) and key / mac bytes 652 (e.g., 32 bytes). In other examples, other sizes of data (e.g., in other sizes, chunks, blocks, etc.) may be transmitted between the initial bytes (e.g., 654 to 659) and the ending key / mac bytes 652, thereby reducing overhead. In an example, the key / mac bytes 652 may indicate the end of the RPMB data transmission.

[0046] The inventors have further recognized that the RPMB command queue can be implemented, for example, in a table or one or more other data structures, such as in a memory controller, a control circuit system, an RPMB circuit, or one or more other components, to further improve the RPMB process. The first RPMB data frame process is transaction-based and requires at least two security protocol input / output commands to complete the transaction. The RPMB logical unit (LU) associated with the first RPMB data frame process is limited to an effective queue depth of less than 1. Each individual security protocol input / output (e.g., step) in the transaction must be completed before the next security protocol input / output begins. This has a significant impact on overall performance, significantly reducing the first RPMB data frame performance to below read / write QD1 (queue depth 1, where one thread occurs on the drive at a time). UFS currently supports QD32 (queue depth 32, where 32 separate threads occur).

[0047] Although only one RPMB operation can be performed per RPMB area at a time, multiple RPMB operations can be queued up to the limit of the device queue depth. In addition, in some instances, the memory device may include multiple RPMB areas, each RPMB area having a separate queue. In some instances, each separate RPMB area may be regarded as a separate RPMB area with a unique key, a counter, a data area, etc. In an example, each memory device may include one or more memory dies, each memory die may include one or more memory arrays, each memory array may include one or more RPMB partitions, and each RPMB partition may include one or more RPMB areas. Since each RPMB area may be unique, the memory device can perform parallel RPMB operations as long as each operation is for a separate RPMB area. A normal LU may have 32 times the security protocol input / output steps in the queue. Although the transaction order must be retained so that the RPMB meets the requirements of the counter, there may be a certain degree of parallelism. In some examples, the memory device may read data (e.g., out of order) from the read addresses associated with the queued read commands and store the data in volatile memory (e.g., SDRAM, etc.) on the memory device until the corresponding RPMB command is executed in sequence, thereby enabling the data to be immediately transferred to the host device or one or more other devices coupled to the memory device. In some examples, RPMB transactions may be processed in sequence, while memory device operations (even those associated with RPMB transactions) may be processed in parallel.

[0048] In an example, such limitations can be addressed in several ways. For example, the operations of the RPMB LU can be ordered (e.g., write operations are strictly ordered) so that existing flows are retained on all RPMB operations to ensure that the write counter requirements are met and the steps are processed in the correct order. When an error occurs, the device can return an appropriate RPMB result code (e.g., associated with the error). The secure input / output status response can use a sense key set to a unit attention to set a check condition, thereby indicating that the device has stopped processing normal host commands. Since a suspended write command will have an invalid write counter if the current write command fails, error recovery is simplified. All unprocessed secure input / output commands in the queue (e.g., read / write, etc.) can be aborted, and a request sense operation can be sent to clear unprocessed unit attentions.

[0049] In other examples, other error options may be implemented. For example, new error states may be defined, including separate sense codes and error codes in some examples. In an example, after an error detection, the device may automatically abort a suspended RPMB command. In other examples, a new RPMB task abort mechanism may be created within the RPMB protocol.

[0050] In an example, instead of assuming an operation failed and confirming the previous command completed, it can be assumed that the command has been successfully completed until an error is received. The system can assume that the request is not an attack, thereby optimizing the success path and non-failure path until an error is detected. In addition, operations can be ordered in a way that takes advantage of device and drive efficiency. Operations can be batched. Once the data and confirmation are sent, the memory device can put the next command in the queue. The order can be maintained, but memory device pipelining can be considered to improve efficiency - for example, considering data location in random reads, etc.

[0051] For example, at different configuration speeds, the performance of the third RPMB data frame, e.g. Figure 6 The third RPMB data frame performance described in Table 1 can provide (compared with the first RPMB data frame performance, for example Figure 3 The first RPMB data frame performance described in Table 2) and Table 3 (compared with the second RPMB data frame performance, for example Figure 5 The transfer time reduction shown in the second RPMB data frame performance described in assuming the following host capabilities (PWM) and high-speed (HS) gear frequencies: PWM gear 1: 290kB / s; HS gear 1×1 channel: 130MB / s; and HS gear 4×2 channel: 2070MB / s. Various reference clock frequencies can be used without changing the HS gear frequency.

[0052]

[0053] Table 1.

[0054] For the first RPMB data frame, there is one header for every 256B of user data. A 4kB data transmission will require 16 times the header. The ratio of header to data is constant, which means that an 8kB transmission will have 32 times the header. In contrast, the third RPMB data frame requires a single header with a variable frame size for each transmission, thereby greatly improving both header and data frame transmission time and overhead.

[0055]

[0056] Table 2.

[0057] For the second RPMB data frame, there is one header per transmission, which is similar to the third RPMB data frame. However, the header size and configuration reduction are still beneficial.

[0058] The inventors have further recognized that a modified first RPMB data frame (e.g., a vendor-specific data frame, etc.) includes a request / response message type byte (e.g., 2 bytes), a result byte (e.g., 2 bytes), a block count byte (e.g., 2 bytes), an address byte (e.g., 2 bytes), a write counter byte (e.g., 8 bytes), a random number byte (e.g., 16 bytes), a key / mac (message authentication code) byte (e.g., 32 bytes), and data (e.g., 256 bytes). The modified first RPMB data frame may require a 20% overhead for communication between a host device and a memory device, where 64 overhead bytes are repeated.

[0059] Figure 7 An example method 700 is described to implement a RPMB command queue, for example, using a table or data structure of a host or memory device. In an example, the RPMB command queue may be implemented using control circuitry, RPMB circuitry, etc. In an example, the control circuitry may include the RPMB circuitry.

[0060] At 701, a RPMB command may be received, for example, at a memory device from a host device. Figures 3 to 6 According to the data structure described in , the RPMB command may include a RPMB write command, a RPMB read command, or one or more other RPMB commands.

[0061] At 702, a RPMB command queue may be maintained, for example, by a control circuit system using received RPMB commands. In an example, the commands may be queued in the order in which they are received. In some examples, write commands may be queued in the order in which they are received, and read commands may be executed out of order, as long as a write count associated with the RPMB write command is maintained between the host device and the memory device. An example queue including a first RPMB write command, three RPMB read commands, and a second RPMB write command (in a specific order) is illustrated at 703. This command queue may be maintained using a data structure in a memory device.

[0062] At 704, the RPMB operations may be performed sequentially. However, certain parallel operations may be performed to speed up the RPMB process. In an example, at 705, the RPMB read data may be pre-fetched out of order and stored in the volatile memory of the memory device at 706. When the RPMB read operation is ready to be performed at 704, the information may be retrieved from the volatile memory instead of reading the information from the RPMB portion of the non-volatile memory.

[0063] In certain examples, a memory device may include multiple RPMB partitions or regions, and a separate RPMB queue may be maintained for each region.

[0064] Figure 8 An example block diagram of a memory device 800 is illustrated, which includes a memory array 802 having a plurality of memory cells 804 and one or more circuits or components for providing communication with the memory array 802 or performing one or more memory operations on the memory array 802. Although shown with a single memory array 802, in other examples, one or more additional memory arrays, dies, or LUNs may be included here. In certain examples, in a storage system with several dies or LUNs, the memory device 800 may represent a block diagram of the circuits and components of each die or LUN. The memory device 800 may include a row decoder 812, a column decoder 814, a sense amplifier 820, a page buffer 822, a selector 824, an input / output (I / O) circuit 826, and a memory control unit 830.

[0065] The memory cells 804 of the memory array 802 may be arranged into blocks, such as a first block 802A and a second block 802B. Each block may include sub-blocks. For example, the first block 802A may include a first sub-block 802A0 and a second sub-block 802A n , and the second block 802B may include a first sub-block 802B0 and a second sub-block 802B n Each sub-block may include a number of physical pages, each page including a number of memory cells 804. Although illustrated herein as having two blocks, each block having two sub-blocks, and each sub-block having a number of memory cells 804, in other examples, the memory array 802 may include more or fewer blocks, sub-blocks, memory cells, etc. In other examples, the memory cells 804 may be arranged into a number of rows, columns, pages, sub-blocks, blocks, etc., and accessed using, for example, an access line 806, a first data line 810, or one or more select gates, source lines, etc.

[0066] The memory control unit 830 may control the memory operation of the memory device 800 according to one or more signals or instructions received on the control line 832, including, for example, one or more clock signals or control signals indicating the desired operation (e.g., write, read, erase, etc.), or address signals (A0 to AX) received on one or more address lines 816. One or more devices external to the memory device 800 may control the value of the control signal on the control line 832 or the address signal on the address line 816. Examples of devices external to the memory device 800 may include, but are not limited to, a host, a memory controller, a processor, or Figure 8 One or more circuits or components not described in the specification.

[0067] The memory device 800 may use access lines 806 and first data lines 810 to transfer (e.g., write or erase) data to or from (e.g., read) one or more of the memory cells 804. A row decoder 812 and a column decoder 814 may receive and decode address signals (A0 through AX) from address lines 816, may determine which of the memory cells 804 is to be accessed, and may provide signals to one or more of the access lines 806 (e.g., one or more of a plurality of word lines (WL0 through WLm)) or the first data lines 810 (e.g., one or more of a plurality of bit lines (BL0 through BLn)), such as described above.

[0068] The memory device 800 may include sensing circuitry, such as sense amplifiers 820, configured to use the first data line 810 to determine (e.g., read) the value of data on the memory cell 804 or to determine the value of data to be written to the memory cell 804. For example, in a selected string of memory cells 804, one or more of the sense amplifiers 820 may read the logic level in the selected memory cell 804 in response to a read current flowing in the memory array 802 through the selected string to the data line 810.

[0069] One or more devices external to the memory device 800 may communicate with the memory device 800 using I / O lines (DQ0 to DQN) 808, address lines 816 (A0 to AX), or control lines 832. Input / output (I / O) circuitry 826 may use I / O lines 808 to transfer values ​​of data into or out of the memory device 800, such as into or out of the page buffer 822 or the memory array 802, according to, for example, the control lines 832 and the address lines 816. The page buffer 822 may store data received from one or more devices external to the memory device 800 before programming the data into the associated portion of the memory array 802, or may store data read from the memory array 802 before transmitting the data to one or more devices external to the memory device 800.

[0070] The column decoder 814 may receive the address signals (A0 to AX) and decode them into one or more column select signals (CSEL1 to CSELn). The selector 824 (e.g., a selection circuit) may receive the column select signals (CSEL1 to CSELn) and select data in the page buffer 822 representing the value of the data to be read from or programmed into the memory cell 804. The second data line 818 may be used to transfer the selected data between the page buffer 822 and the I / O circuit 826.

[0071] The memory control unit 830 may receive positive and negative power supply signals, such as a supply voltage (Vcc) 834 and a negative supply voltage (Vss) 836 (e.g., ground potential) from an external source or supplier (e.g., an internal or external battery, an AC to DC converter, etc.). In certain examples, the memory control unit 830 may include a regulator 828 for internally providing the positive or negative supply signals.

[0072] Fig. 9 Description of a system on which the techniques (eg, methods) discussed herein may be performed (eg, Figure 1 900 is a block diagram of an example machine (e.g., a host system) 900 of any one or more of those technologies described in, for example, , and the like). In alternative embodiments, the machine 900 may operate as a standalone device or may be connected (e.g., via a network) to other machines. In a networked deployment, the machine 900 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, the machine 900 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 900 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network facility, an IoT device, an automotive system, or any machine capable of executing instructions (sequentially or otherwise) that specify the actions to be taken by that machine. In addition, although only a single machine is described, the term "machine" should also be understood to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein (e.g., cloud computing, software as a service (SaaS), other computer cluster configurations).

[0073] As described herein, an example may include logic, components, devices, packages, or mechanisms, or may be operated by them. A circuit system is a collection (e.g., a group) of circuits implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). The membership of the circuit system may become flexible over time and with the underlying hardware variability. The circuit system includes members that can perform specific tasks individually or in combination when in operation. In an example, the hardware of the circuit system may be designed invariably to perform specific operations (e.g., hardwired). In an example, the hardware of the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), including physically modified computer-readable media (e.g., magnetically, electrically, removably placed particles of constant mass, etc.) to encode instructions for specific operations. When connecting physical components, the basic electrical properties of the hardware composition, for example, change from an insulator to a conductor or vice versa. The instructions enable the participating hardware (e.g., execution units or loading mechanisms) to create members of the circuit system in hardware via variable connections to perform parts of specific tasks when in operation. Thus, when the device is operating, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any one of the physical components can be used in more than one member of more than one circuit system. For example, under operation, an execution unit can be used in a first circuit of a first circuit system at one point in time and can be reused by a second circuit in the first circuit system or by a third circuit in the second circuit system at a different time.

[0074] The machine (e.g., a computer system, a host system, etc.) 900 may include a processing device 902 (e.g., a hardware processor, a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, etc.), a main memory 904 (e.g., a read-only memory (ROM), a dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 906 (e.g., a static random access memory (SRAM)), etc.), and a storage system 918, some or all of which may communicate with each other via a communication interface (e.g., a bus) 930.

[0075] The processing device 902 may represent one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 902 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 902 may be configured to execute instructions 926 to perform the operations and steps discussed herein. The computer system 900 may further include a network interface device 908 for communicating over a network 920.

[0076] The storage system 918 may include a machine-readable storage medium (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 926 or software embodying any one or more of the methodologies or functions described herein. The instructions 926 may also reside completely or at least partially within the main memory 904 or within the processing device 902 during execution by the computer system 900, the main memory 904 and the processing device 902 also constituting machine-readable storage media.

[0077] The term "machine-readable storage medium" should be understood to include a single medium or multiple media storing one or more sets of instructions, or any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present invention. Thus, the term "machine-readable storage medium" should be understood to include, but not limited to, solid-state memory, optical media, and magnetic media. In an example, a collective machine-readable medium includes a machine-readable medium with multiple particles having a constant (e.g., stationary) mass. Thus, a collective machine-readable medium is not a transient propagating signal. Specific examples of collective machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0078] The machine 900 may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, one or more of the display unit, input device, or UI navigation device may be a touch screen display. The machine may include a signal generating device (e.g., a speaker) or one or more sensors, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or one or more other sensors. The machine 900 may include an output controller, such as a serial (e.g., universal serial bus (USB), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection for communicating with or controlling one or more peripheral devices (e.g., printers, card readers, etc.).

[0079] Instructions 926 (e.g., software, programs, operating system (OS), etc.) or other data stored on storage system 918 may be accessed by main memory 904 for use by processing device 902. Main memory 904 (e.g., DRAM) is typically fast but volatile, and therefore a different type of storage than storage system 918 (e.g., SSD), which is suitable for long-term storage, including when in an "off" state. Instructions 926 or data in use by a user or machine 900 are typically loaded in main memory 904 for use by processing device 902. When main memory 904 is full, virtual space from storage system 918 may be allocated to supplement main memory 904; however, because storage system 918 devices are typically slower than main memory 904, and write speeds are typically at least 1 / 2 of the read speed, the use of virtual memory greatly reduces the user experience due to storage system latency (compared to main memory 904, such as DRAM). In addition, using storage system 918 for virtual memory may greatly reduce the useful life of storage system 918.

[0080] The instructions 924 may further utilize any of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.) to be transmitted or received over the network 920 via the network interface device 908 using a transmission medium. Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, known as The IEEE 802.16 family of standards, known as IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, etc.). In an example, network interface device 908 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connecting to network 920. In an example, network interface device 908 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology. The term "transmission media" should be understood to include any intangible media capable of storing, encoding, or carrying instructions executed by machine 900, and includes digital or analog communication signals or other intangible media used to facilitate communication of such software.

[0081] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show by way of illustration specific embodiments in which the present invention can be practiced. These embodiments are also referred to herein as "examples". Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. In addition, the inventors also contemplate examples using any combination or arrangement of those elements (or one or more aspects thereof) shown or described with respect to a specific example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0082] In this document, as is common in patent documents, the term "one" or "an" is used to include one or more than one, independent of any other examples or usages of "at least one" or "one or more". In this document, unless otherwise indicated, the term "or" is used to refer to a non-exclusive or, so that "A or B" may include "A but not B", "B but not A" and "A and B". In the appended claims, the terms "include" and "in which" are used as the plain English equivalents of the corresponding terms "include" and "wherein". Moreover, in the appended claims, the terms "include" and "include" are open-ended. This term including elements other than those listed after the system, device, object or process in the claim is still considered to fall within the scope of that claim. In addition, in the appended claims, the terms "first", "second" and "third" etc. are used only as labels and are not intended to impose numerical requirements on their objects.

[0083] In various examples, the components, controllers, processors, units, engines, or tables described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including groups of processors or multi-core devices.

[0084] As used herein, operating a memory cell includes reading from the memory cell, writing to the memory cell, or erasing the memory cell. The operation of placing a memory cell in a desired state is referred to herein as "programming," and may include both writing to or erasing from a memory cell (e.g., a memory cell may be programmed to an erased state).

[0085] According to one or more embodiments of the present invention, a memory controller (e.g., a processor, controller, firmware, control circuit system, etc.) located inside or outside a memory device is capable of determining (e.g., selecting, setting, adjusting, calculating, changing, clearing, communicating, adapting, deriving, defining, utilizing, modifying, applying, etc.) a certain number of wear cycles or wear states (e.g., recording wear cycles, counting operations of the memory device as they occur, tracking operations of the memory device that it enables, evaluating memory device characteristics corresponding to the wear states, etc.).

[0086] According to one or more embodiments of the present invention, a memory access device may be configured to provide wear cycle information to a memory device at each memory operation. The memory device control circuitry (e.g., control logic) may be programmed to compensate for memory device performance variations corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0087] The method examples described herein may be at least partially machine, device, or computer-implemented. Some examples may include computer-readable media, device-readable media, or machine-readable media encoded with instructions operable to configure an electronic device to perform the methods described in the above examples. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, etc. This code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. In addition, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., optical disks and digital video disks), cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), solid-state drives (SSD), universal flash storage (UFS) devices, embedded MMC (eMMC) devices, etc.

[0088] Example 1 is a system comprising: a memory device comprising a memory array and a control circuit system, wherein the control circuit system is configured to receive a replay protected memory block (RPMB) command from a host device, use the received RPMB command to maintain an RPMB command queue and execute the RPMB commands sequentially according to the RPMB command queue, wherein the memory device is configured to prefetch read data out of order from a read address associated with a queued RPMB read command and store the prefetched read data in a volatile memory of the memory device to provide it to the host device sequentially according to the RPMB command queue.

[0089] In Example 2, the subject matter described in Example 1 optionally includes wherein the memory device is configured to sequentially execute RPMB write commands in the RPMB command queue according to the RPMB command queue and the counter, and use the prefetched read data to sequentially execute the RPMB read commands according to the RPMB command queue.

[0090] In Example 3, the subject matter described according to any one or more of Examples 1 to 2 optionally includes wherein the memory device includes a plurality of memory dies, at least two of the plurality of memory dies include corresponding RPMB regions, and wherein the memory device is configured to maintain separate RPMB command queues for the corresponding RPMB regions.

[0091] In Example 4, the subject matter described according to any one or more of Examples 1 to 3 optionally includes wherein the memory device includes a plurality of memory dies, at least two of the plurality of memory dies include corresponding RPMB regions, and wherein each of the plurality of memory dies includes control logic, wherein the control logic is configured to maintain an RPMB command queue for each corresponding RPMB region.

[0092] In Example 5, the subject matter described according to any one or more of Examples 1 to 4 optionally includes wherein the memory device includes multiple RPMB areas and is configured to maintain a separate RPMB command queue for each of the multiple RPMB areas, each of the multiple RPMB areas having a unique key, counter, and data area.

[0093] In Example 6, the subject matter described according to any one or more of Examples 1 to 5 optionally includes wherein the memory device includes a RPMB region and a RPMB circuit, and wherein the RPMB circuit is configured to control access to the RPMB region and maintain the RPMB command queue for the RPMB region.

[0094] In Example 7, the subject matter described in Example 6 optionally includes a host device, which is configured to provide the RPMB command to the memory device, the RPMB command including an RPMB data frame, the RPMB data frame including 8 write counter bytes, wherein the RPMB circuit is configured to implement a counter and utilize the received counter bytes and the counter to verify the order of the RPMB write commands.

[0095] In Example 8, the subject matter of Example 7 optionally includes wherein the RPMB data frame includes: a header byte consisting of 32 to 64 data bytes; data bytes following the header bytes; and a message authentication code (MAC) byte following the data bytes.

[0096] In Example 9, the subject matter of Example 8 optionally includes wherein the header bytes include, in sequence: 2 request / response message type bytes; 2 result bytes; 2 block count bytes; 2 address bytes; 8 write counter bytes; and 16 random number bytes.

[0097] In Example 10, the subject matter of any one or more of Examples 8 to 9 optionally includes wherein the data bytes include a number (n) of data chunks, the n data chunks consisting of all of the data bytes for a single read or write transfer, and the header bytes and the MAC bytes consisting of all of the header bytes and the MAC bytes for the single read or write transfer.

[0098] Example 11 is a method comprising: at a memory device, receiving a plurality of replay protected memory block (RPMB) commands from a host device; using a control circuit system of the memory device, using the received RPMB commands to maintain an RPMB command queue in the order received from the host device; using the control circuit system, prefetching data out of order from a read address associated with an RPMB command in the RPMB command queue and storing the prefetched read data in a volatile memory of the memory device; and using the control circuit system, executing the RPMB commands according to the RPMB command queue.

[0099] In Example 12, the subject matter described in Example 11 optionally includes executing the RPMB command comprising: sequentially executing the RPMB write commands in the RPMB command queue according to the RPMB command queue and the counter; and using the prefetched read data to sequentially execute the RPMB read commands according to the RPMB command queue.

[0100] In Example 13, the subject matter of any one or more of Examples 11-12 optionally includes wherein maintaining the RPMB command queue comprises maintaining separate RPMB command queues for respective RPMB regions of the memory device.

[0101] In Example 14, the subject matter described according to any one or more of Examples 11 to 13 optionally includes wherein the memory device includes multiple memory dies, each memory die including corresponding control logic and RPMB areas, wherein maintaining the separate RPMB command queues includes using the control logic of the memory die to maintain a corresponding RPMB command queue for each RPMB area.

[0102] In Example 15, the subject matter described according to any one or more of Examples 11 to 14 optionally includes wherein the memory device includes multiple RPMB areas and is configured to maintain a separate RPMB command queue for each of the multiple RPMB areas, each of the multiple RPMB areas having a unique key, counter, and data area.

[0103] In Example 16, the subject matter described according to any one or more of Examples 11 to 15 optionally includes wherein the memory device includes a RPMB region and a RPMB circuit, and wherein the RPMB circuit is configured to control access to the RPMB region and maintain the RPMB command queue for the RPMB region.

[0104] In Example 17, the subject matter according to Example 16 optionally includes using a host device to provide the RPMB command to the memory device, the RPMB command including an RPMB data frame, the RPMB data frame including 8 write counter bytes; and using the RPMB circuit to implement a counter and utilize the received counter bytes of the counter to verify the order of the received RPMB write commands.

[0105] In Example 18, the subject matter of Example 17 optionally includes providing the RPMB command including providing an RPMB data frame including providing: a header byte consisting of 32 to 64 data bytes; data bytes following the header byte; and a message authentication code (MAC) byte following the data byte.

[0106] In Example 19, the subject matter of Example 18 optionally includes providing the RPMB header bytes comprising providing, in sequence: 2 request / response message type bytes; 2 result bytes; 2 block count bytes; 2 address bytes; 8 write counter bytes; and 16 random number bytes.

[0107] In Example 20, the subject matter of any one or more of Examples 18 to 19 optionally includes wherein providing the data bytes comprises providing a number (n) of data chunks, the n data chunks consisting of all of the data bytes for a single read or write transfer, and wherein providing the header bytes and the MAC bytes consists of providing all of the header bytes and the MAC bytes for the single read or write transfer.

[0108] In Example 21, the subject matter (e.g., a system or device) may optionally combine any portion or combination of any one or more of Examples 1 to 20 to include "components for performing any portion of any one or more of the functions or methods described in Examples 1 to 20," or at least one "non-transitory machine-readable medium" containing instructions that, when executed by a machine, cause the machine to perform any portion of any one or more of the functions or methods described in Examples 1 to 20.

[0109] The above description is intended to be illustrative and non-restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. After reviewing the above description, other embodiments may be used by a person of ordinary skill in the art, for example. It should be understood when submitting that it will not be used to interpret or limit the scope or meaning of the claims. Moreover, in the above specific embodiments, various features may be grouped together to simplify the present invention. This should not be interpreted as unclaimed disclosure features intended to be essential for any claim. Rather, the subject matter of the invention may be less than all the features of a specific disclosed embodiment. Therefore, the attached claims are thus incorporated into the specific embodiments, wherein each claim is independently used as a separate embodiment, and it is considered that such embodiments can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined with reference to the attached claims together with the full range of equivalents to which this claim is assigned.

Claims

1. A system for memory operation, comprising: A memory device comprising a memory array and a control circuit system, wherein the control circuit system is configured to receive a replay protected memory block (RPMB) command from a host device, use the received RPMB command to maintain an RPMB command queue and execute the received RPMB command in sequence according to the RPMB command queue, wherein the memory device is configured to pre-fetch read data out of order from a read address associated with a queued RPMB read command and store the pre-fetched read data in a volatile memory of the memory device to provide it to the host device in sequence according to the RPMB command queue.

2. The system of claim 1, wherein the memory device is configured to sequentially execute RPMB write commands in the RPMB command queue according to the RPMB command queue and a counter, and to use the pre-fetched read data to sequentially execute the RPMB read commands according to the RPMB command queue.

3. The system of claim 1 , wherein the memory device comprises a plurality of memory dies, each memory die comprising a respective RPMB region, and Wherein the memory device is configured to maintain separate RPMB command queues for the respective RPMB regions.

4. The system of claim 1 , wherein the memory device comprises a plurality of memory dies, each memory die comprising a respective RPMB region, and Wherein each of the plurality of memory dies comprises control logic, wherein the control logic is configured to maintain a RPMB command queue for each respective RPMB region.

5. The system of any one of claims 1 to 4, wherein the memory device comprises a plurality of RPMB areas and is configured to maintain a separate RPMB command queue for each of the plurality of RPMB areas, each of the plurality of RPMB areas having a unique key, counter and data area.

6. The system of any one of claims 1 to 4, wherein the memory device comprises a RPMB area and a RPMB circuit, and The RPMB circuit is configured to control access to the RPMB area and maintain the RPMB command queue for the RPMB area.

7. The system according to claim 6, comprising: a host device configured to provide the RPMB command to the memory device, the RPMB command comprising a RPMB data frame, the RPMB data frame comprising 8 write counter bytes, Wherein the RPMB circuit is configured to implement a counter and utilize the received counter byte and the counter to verify the order of the RPMB write commands.

8. The system according to claim 7, wherein the RPMB data frame comprises: Header bytes, which consist of 32 to 64 data bytes; Data bytes that follow the header bytes; and A message authentication code (MAC) byte follows the data byte.

9. The system of claim 8, wherein the header bytes sequentially include: 2 request / response message type bytes; 2 result bytes; 2 block count bytes; 2 address bytes; 8 write counter bytes; and 16 random number bytes.

10. The system of claim 8, wherein the data bytes comprise n data chunks, wherein n is the number of the data chunks, the n data chunks consist of all the data bytes for a single read or write transfer, and the header bytes and the MAC bytes consist of all the header bytes and the MAC bytes for the single read or write transfer.

11. A method for memory operation, comprising: At a memory device, receiving a plurality of replay protected memory block RPMB commands from a host device; maintaining, using control circuitry of the memory device, a queue of RPMB commands in an order received from the host device using the received RPMB commands; using the control circuitry, prefetching read data out of order from read addresses associated with RPMB commands in the RPMB command queue and storing the prefetched read data in a volatile memory of the memory device; and Using the control circuitry, the received RPMB commands are executed according to the RPMB command queue.

12. The method of claim 11, wherein executing the received RPMB command comprises: Execute the RPMB write commands in the RPMB command queue in sequence according to the RPMB command queue and the counter; and The RPMB read commands are executed sequentially according to the RPMB command queue using the pre-fetched read data.

13. The method according to claim 11, wherein the memory device comprises a RPMB area and a RPMB circuit, and The RPMB circuit is configured to control access to the RPMB area and maintain the RPMB command queue for the RPMB area.

14. The method according to claim 13, comprising: using a host device to provide the RPMB command to the memory device, the RPMB command comprising a RPMB data frame, the RPMB data frame comprising 8 write counter bytes; and Using the RPMB circuit, a counter is implemented and the received counter bytes of the counter are utilized to verify the order of received RPMB write commands.

15. The method of claim 14, wherein providing the RPMB command comprises providing a RPMB data frame, comprising providing: Header bytes, which consist of 32 to 64 data bytes; data bytes following the header bytes; and A message authentication code (MAC) byte follows the data byte.

16. The method of claim 15, wherein providing the RPMB header bytes comprises providing, in order: 2 request / response message type bytes; 2 result bytes; 2 block count bytes; 2 address bytes; 8 write counter bytes; and 16 random number bytes; wherein providing the data bytes comprises providing n data chunks, wherein n is the number of the data chunks, the n data chunks consisting of all of the data bytes for a single read or write transfer, and Wherein providing the header bytes and the MAC bytes consists of providing all of the header bytes and the MAC bytes for the single read or write transfer.

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