Semiconductor device

Abstract

A semiconductor device is disclosed. In some embodiments, the semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode, and a gate electrode, the semiconductor die having a first surface and a metallization structure on the first surface. The metallization structure includes a first conductive layer on the first surface, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer, and a third conductive layer on the second insulating layer. The third conductive layer includes at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode, and at least one gate pad coupled to the gate electrode.

Description

BACKGROUND

[0001] Common transistor devices for power applications include Si CoolMOS®, Si power MOSFETs, and Si insulated gate bipolar transistors (IGBTs). Semiconductor devices, such as transistor devices, are typically provided in a package. The package can include a substrate or leadframe that provides external contacts that are used to mount the electronic component to a redistribution board, such as a printed circuit board. The package also includes internal electrical connections from the transistor device to the substrate or leadframe and a plastic molding compound that covers the semiconductor device and the internal electrical connections.

[0002] To achieve a low drain-to-source resistance R DS(on) , vertical transistor devices include a drain electrode and a source electrode on opposite surfaces. However, because the drain and source contacts are placed on opposite surfaces from one another, electrical connections must be supplied to both sides of the device. As a result, vertical transistor devices are more challenging for packaging using wafer-level chip-scale packaging technology.

[0003] US 2013 / 0277735 Al discloses an example of a wafer-level chip-scale package including a vertical transistor having a source contact, a drain contact, and a gate contact arranged on a common side. Through-silicon vias are used to electrically couple the drain region to the drain contact positioned on the opposite surface.

[0004] However, further improvements would be desirable to allow chip-scale packaging for vertical transistor devices having even lower R DSon . SUMMARY

[0005] In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode, and a gate electrode, the semiconductor die having a first surface and a metallization structure on the first surface. The metallization structure includes a first conductive layer on the first surface, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer, and a third conductive layer on the second insulating layer. The third conductive layer includes at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode, and at least one gate pad coupled to the gate electrode.

[0006] The semiconductor device includes pads suitable for electrically coupling the transistor device to a circuit board and / or external circuitry and / or external load, such that the semiconductor device can be described as a package. Because the pads are on a major surface of the semiconductor die, the semiconductor device can be described as a chip-scale or chip-size package.

[0007] In some embodiments, the metallization structure includes more than three conductive layers, and an insulating layer is disposed between each of the conductive layers.

[0008] In some embodiments, more than one device is provided within the semiconductor die, such that more complex circuits, such as half-bridge circuits, can be provided. In some embodiments, more than one transistor device is provided within the semiconductor die, such that more complex circuits, such as half-bridge circuits, can be provided. In these embodiments, the semiconductor device can also be referred to as a module.

[0009] The source electrode and the drain electrode provide power electrodes for the transistor device, and can more generally be denoted as a first power electrode and a second power electrode. In some embodiments, the source electrode and the source pad can be denoted as a first power electrode and a first power pad, respectively, and the drain electrode and the drain pad are denoted as a second power electrode and a second power pad, respectively.

[0010] In some embodiments, the first conductive layer includes a first source redistribution structure coupled to the source electrode, a first drain redistribution structure coupled to the drain electrode, and a first gate redistribution structure coupled to the gate electrode. The first source redistribution structure includes a plurality of first discrete conductive regions. The first drain redistribution structure includes a plurality of second discrete conductive regions positioned laterally between and spaced apart laterally from the first discrete conductive regions of the first source redistribution structure.

[0011] In some embodiments, the plurality of second discrete conductive regions of the first drain redistribution structure are electrically coupled together by a second conductive layer, and the plurality of first discrete conductive regions of the first source redistribution structure are electrically coupled together by a third redistribution structure.

[0012] Alternatively, the plurality of second discrete conductive regions of the first drain redistribution structure are electrically coupled together by a third conductive layer, and the plurality of first discrete conductive regions of the first source redistribution structure are electrically coupled together by a second redistribution structure.

[0013] More broadly, the discrete conductive regions coupled to the first power electrode are electrically coupled to one another in the conductive layer of the metallization structure that is different from the conductive layer of the metallization structure that electrically couples the discrete conductive portions coupled to the second power electrode. This arrangement enables the lateral connections between the discrete conductive regions coupled to the first power electrode to be positioned vertically above the lateral connections between the discrete conductive regions coupled to the second power electrode due to the insulating layer being disposed between each of the conductive layers, thus allowing the area occupied by the redistribution structure between the electrodes of the transistor device and the external contacts provided by the pads to be reduced. In some embodiments, the redistribution structure between the electrodes of the transistor device and the external contacts provided by the pads is provided entirely within the region of the semiconductor die in which the transistor device is formed.

[0014] In some embodiments, the discrete second conductive regions of the first drain redistribution structure are elongated and have a strip shape.

[0015] In some embodiments, the discrete first conductive regions of the first source redistribution structure are elongated and have a strip shape.

[0016] In some embodiments, the semiconductor device further includes one or more conductive vias extending from the first surface into the semiconductor die. The one or more conductive vias are electrically coupled to the doped drain region located within the semiconductor die and to the first drain redistribution structure on the first surface of the semiconductor die.

[0017] In some embodiments, the vertical transistor device includes an active region divided into a plurality of unit field regions. At least one conductive via coupled to the drain electrode is located between adjacent unit field regions. The conductive via can have an elongated strip shape.

[0018] The vertical transistor device can include two elongated conductive vias that extend substantially parallel to one another and are located between adjacent unit field regions. The two elongated conductive vias are coupled to the drain electrode at different lateral locations. The two elongated conductive vias are electrically coupled to a common conductive region of the second discrete conductive regions of the first drain redistribution structure.

[0019] In some embodiments, a first insulating layer is disposed on and between the first source redistribution structure and the first drain redistribution structure in the lateral direction. In some embodiments, the first insulating layer includes a first opening exposing a defined portion of the first discrete conductive regions of the first source redistribution structure and a second opening exposing a defined portion of the second discrete conductive regions of the first drain redistribution structure.

[0020] The plurality of first openings can be located on a single first discrete conductive region, and a single second opening can be provided for each second discrete conductive region.

[0021] In some embodiments, the second conductive layer includes a second source redistribution structure electrically coupled to the first source redistribution structure and a second drain redistribution structure electrically coupled to the first drain redistribution structure. The second source redistribution structure is disposed within the first opening of the first insulating layer and includes a plurality of first conductive islands disposed on the first conductive region of the first source redistribution structure. The second drain redistribution structure is disposed in the second opening of the first insulating layer and is also positioned laterally between and spaced apart laterally from the first conductive islands of the second source redistribution structure. The second drain redistribution structure can surround the first conductive islands of the second source redistribution structure laterally.

[0022] In some embodiments, the second drain redistribution structure electrically couples the second conductive regions of the first drain redistribution structure to each other.

[0023] In some embodiments, the second drain redistribution structure is disposed vertically above the first drain redistribution structure and vertically above the portion of the first source redistribution structure covered by the first insulating layer.

[0024] In some embodiments, a second insulating layer is disposed on the second source redistribution structure and on the second drain redistribution structure and has a third opening exposing a defined region of the first conductive islands of the second source redistribution structure and at least one fourth opening exposing a defined region of the second drain redistribution structure. A single third opening can be located on each first conductive island.

[0025] In some embodiments, a third conductive layer includes a third source redistribution structure electrically coupled to the second source redistribution structure and a third drain redistribution structure electrically coupled to the second drain redistribution structure. In some embodiments, the third source redistribution structure is disposed in the third opening and electrically couples the first conductive islands of the second source redistribution structure to each other. The third source redistribution structure extends above the portion of the second drain redistribution structure covered by the second insulating layer. The third drain redistribution structure is disposed in the fourth opening and includes second conductive islands spaced apart laterally from the third source redistribution structure.

[0026] In some embodiments, a plurality of fourth openings are provided in the second insulating layer, each fourth opening exposing a defined region of the second drain redistribution structure. In some embodiments, the third drain redistribution structure includes a plurality of second conductive islands spaced apart from each other and from the third source redistribution structure laterally.

[0027] In some embodiments, each second conductive island of the third drain redistribution structure has a lateral size that is greater than a lateral size of the fourth opening, such that each second conductive island extends over a portion of the second source redistribution structure that is covered by the second insulating layer.

[0028] In some embodiments, the conductive via, the first drain redistribution structure, the first source redistribution structure, and the first gate redistribution structure comprise tungsten, the first insulating layer comprises polyimide, the second drain redistribution structure, the second source redistribution structure are formed of an AlCu alloy, the second insulating layer comprises polyimide, and the third drain redistribution structure and the third source redistribution structure are formed of Cu.

[0029] Tungsten is useful because it can be used to fill a via in a semiconductor device in a vertical direction to form a conductive via, and can be deposited on a side surface such as the first surface to provide the first source redistribution structure, the first drain redistribution structure, and the first gate redistribution structure. Aluminum copper alloy is useful because it has a lower electrical resistance. Cu is useful because it forms a solderable surface for pads provided by the third conductive layer.

[0030] The outer surface of the third conductive layer can have a solderable outer surface. In some embodiments, the source pad, the drain pad, and the gate pad have a solderable outer surface. The solderable outer surface can be provided by the material of the third conductive layer, or can be provided by an additional layer disposed on the third conductive layer.

[0031] In some embodiments, the semiconductor device further comprises an epoxy layer disposed on the third conductive layer. In some embodiments, the epoxy layer includes at least one fifth opening exposing a portion of the third source redistribution layer and defining the source pad, at least one sixth opening exposing a portion of the second conductive island of the third drain redistribution structure and defining the drain pad, and at least one seventh opening defining the gate pad.

[0032] In some embodiments, the semiconductor device further comprises solder on the source pad, the drain pad, and the gate pad.

[0033] In some embodiments, the semiconductor die includes a second side opposite the first side, the second side is electrically passive and / or includes a third insulating layer or is bare.

[0034] In some embodiments, the semiconductor die includes a second side opposite the first side, the second side is electrically coupled to the drain and / or includes a second metallization layer.

[0035] In some embodiments, the semiconductor device further comprises a side surface extending between the first surface and the second surface, wherein the side surface is bare or a passivation layer or an insulating layer is arranged on the side surface.

[0036] In some embodiments, the vertical transistor device comprises an active area, and an area of the first surface of the semiconductor die is less than 130% of the active area of the transistor device or less than 120% of the active area of the transistor device. The active area can be defined as an area of a source implant in the semiconductor die. The area of the first surface of the semiconductor die is defined by the side surface of the semiconductor die without any additional packaging.

[0037] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0038] The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of various illustrated embodiments can be combined, unless they are mutually exclusive. Exemplary embodiments are depicted in the drawings and detailed description that follows.

[0039] Figure 1 Fig. illustrates a schematic cross-sectional view of a semiconductor device comprising a transistor device and a metallization structure according to an embodiment.

[0040] Figure 2 Fig. illustrates a schematic plan view of a first conductive layer of a metallization structure.

[0041] Figure 3 Fig. illustrates a schematic plan view of a first insulating layer of a metallization structure on Figure 2 the first conductive layer.

[0042] Figure 4 Fig. illustrates a schematic plan view of a second conductive layer of a metallization structure on Figure 3 the first insulating layer.

[0043] Figure 5 Fig. illustrates a schematic plan view of the second conductive layer and the underlying first conductive layer.

[0044] Figure 6 Fig. illustrates a schematic plan view of a third conductive layer on a second insulating layer, which in turn is on Figure 4 the second conductive layer.

[0045] Figure 7 Fig. illustrates a schematic plan view of Figure 6 the third conductive layer and Figure 4 the second conductive layer.

[0046] Fig. illustrates a schematic plan view ofFigure 8 a schematic plan view of an epoxy layer on a third conductive layer. Figure 7 a schematic plan view of an epoxy layer on a third conductive layer.

[0047] Figure 9 a perspective view of a semiconductor device partially cut away, illustrating a transistor cell and a metallization structure of a transistor device.

[0048] Figure 10 a schematic view of a package footprint. DETAILED DESCRIPTION

[0049] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments in which the application can be practiced. In this regard, directional terminology, such as "top," "bottom," "front," "back," "leading," "trailing," etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present application. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims.

[0050] In the following, a number of exemplary embodiments will be explained. In this context, in the figures identical structural features are identified by identical or similar reference numerals. In the context of the present description, "lateral" or "lateral direction" is to be understood as meaning a direction or extension which generally runs parallel to the lateral extension of the semiconductor material or semiconductor body. The lateral direction thus generally extends parallel to the surfaces or sides. In contrast thereto, the term "vertical" or "vertical direction" is to be understood as meaning a direction which generally runs perpendicular to these surfaces or sides and thus perpendicular to the lateral direction. The vertical direction thus runs in the thickness direction of the semiconductor material or semiconductor body.

[0051] As employed in this specification, the phrase "on" or "onto" when used with respect to an element, such as a layer, region or substrate, can mean that the element is either directly on or directly onto another element, or intervening elements can also be present. In contrast, the phrase "directly on" or "directly onto" means that there are no intervening elements present.

[0052] As employed in this specification, the phrase "connected" or "coupled" to another element, such as a layer, region or substrate, can mean that the element is either directly connected or coupled to the other element or intervening elements can also be present. In contrast, the phrase "directly connected" or "directly coupled" to another element means that there are no intervening elements present.

[0053] In vertical transistor devices such as power MOSFETs, the current typically flows from the top side of the chip (source) to the back side of the chip (drain), or the chip is flipped and the current flows the other way. In the final footprint of the package, all three pins (source, gate, drain) are located at one side only. To allow all pins to be located on a single side, the chip is placed into a package such as S3O8, SSO8, TO220 or DirectFET package. In these packages, the rewiring from the two opposite sides of the transistor device to the base and lead frame of the package and the encapsulation consume space. Typically, the footprint of the package has twice the size compared to the maximum chip size that can be placed in the package.

[0054] The embodiments described herein provide a chip scale package for vertical transistor devices such as power MOSFETs that does not require a separate packaging process. The chip scale package described herein does not use a metal can and does not have die attachment to the metal can or die pads. Three or more metallization layers are used to implement rewiring directly on the chip. All external contacts such as contact pads, metal bumps, solder bumps or solder balls are placed on the front side of the chip and are the interface to the customer's panel. The external contacts such as contact pads, metal bumps, solder bumps or solder balls of the source, gate and drain can be processed at wafer level.

[0055] This arrangement enables the footprint and chip size of the device to be almost identical, does not require a separate packaging process, enables a reduction in packaging costs due to the very small Si area used for rewiring and the Si area cost being lower than the standard packaging cost. Additionally, the risk of die attachment degradation is avoided, the chip thickness can be chosen according to customer needs or reliability needs, the package + Si substrate resistance is low and the footprint and contact layout can be easily adapted by layout changes to the metallization structure.

[0056] In some embodiments, since the drain electrode is located within the semiconductor die in the final product rather than forming the back surface of the semiconductor die, backside thinning techniques and / or backside metallization are avoided.

[0057] Figure 1 A schematic cross-sectional view of a semiconductor device 20 according to an embodiment is illustrated. The semiconductor device 20 comprises a semiconductor die 21 comprising a vertical transistor device 22. The vertical transistor device 22 can be, for example, a MOSFET or an IGBT. The vertical transistor device 22 has a source electrode 23, a drain electrode 24 and a gate electrode 25, each of which is located Figure 1The elements are simply schematically indicated as blocks so that each of the source electrode 23, drain electrode 24, and gate electrode 25 is illustrated as a functional element. The drift path between the source electrode 23 and the drain electrode 24 is vertical and substantially perpendicular to the first main surface 26 of the semiconductor die 21. The drain electrode 24 may be provided by a doped drain region positioned vertically above the source electrode 23. The drain region may be located at a second main surface 27 of the semiconductor die 21 opposite to the first main surface 26, or it may be located within the semiconductor die 21 and spaced apart from the second main surface 27, as shown in [the diagram / illustration]. Figure 1 As shown in the image.

[0058] The semiconductor device 20 further includes a metallization structure 28 located on a first surface 26 of the semiconductor die 21. The metallization structure 28 includes, in the following order: a first conductive layer 29 on the first surface 26; a first insulating layer 30 on the first conductive layer 29; a second conductive layer 31 on the first insulating layer 30; a second insulating layer 32 on the second conductive layer 31; and a third conductive layer 33 on the second insulating layer 32. The third conductive layer 33 includes at least one source pad 34 electrically coupled to a source electrode 23, at least one drain pad 35 electrically coupled to a drain electrode 24, and at least one gate pad 36 electrically coupled to a gate electrode 25.

[0059] Source pad 34, drain pad 35, and gate pad 36 are disposed on the first surface 26 of semiconductor die 21, and therefore on the common side of semiconductor device 20. Since source pad 34, gate pad 36, and drain pad 35 can be used as external contacts for transistor device 22, semiconductor device 20 can be referred to as a package. Since the total area of ​​semiconductor device 20 is not significantly larger than that of semiconductor die 21, semiconductor device 20 can be referred to as a chip-size package or chip-scale package.

[0060] The vertical transistor device 22 includes an active region that describes the area of ​​the transistor device 22 that contributes to its power switching function. In some embodiments, the area of ​​the first surface 26 of the semiconductor die 120 is less than 130% or even less than 120% of the active region of the transistor device 22, or at most 110% of the active region of the transistor device. The active region of the transistor device 22 is defined as the region of the source injection region. The region of the first surface 26 of the semiconductor die 120 is defined by the side surfaces of the semiconductor die 120.

[0061] In embodiments in which the source pad 34, the drain pad 35, and the gate pad 36 provide external contacts of the semiconductor device 20, the outermost surfaces of these pads can include a solderable material that allows solder to wet and attach to the respective pad. In some embodiments, a solder 37 is located on each of the source pad 34, the drain pad 35, and the gate pad 36. In other embodiments, a contact bump or a solder ball of a metal different from the solder can be located on each of the pads 34, 35, 36. A further layer of solder can be located on the metal bump.

[0062] The lateral area of the footprint of the semiconductor device 20 and the lateral area of the semiconductor die 21 are almost identical, since the metallization structure 28 providing the external contacts of the semiconductor device 20 is located on the first surface 26 of the semiconductor die 21. The use of a separate packaging process is thus avoided. The arrangement of the contact pads 34, 35, 36 can be adapted to a particular application by modifying the pattern of the layers of the metallization structure 28, e.g. the openings in the second insulating layer 32 and the third conductive layer 33.

[0063] The third conductive layer 33 providing the source pad 34, the drain pad 35, and the gate pad 36 can be formed of copper, the second conductive layer can be formed of an aluminum copper alloy, and the first conductive layer 29 can be formed of tungsten. In some embodiments, the first conductive layer further comprises additional one or more layers, e.g. a Ti sub-layer and a TiN sub-layer, on which the tungsten layer is deposited in order to increase the adhesion and electrical contact to the semiconductor material. In some embodiments, both the first insulating layer 30 and the second insulating layer 32 are formed of polyimide.

[0064] In some embodiments, the second side 27 of the semiconductor die 21 is electrically passive and not used for electrical connections. In these embodiments, the second surface of the semiconductor die 21 is not formed by a doped semiconductor region forming the drain electrode 24. In some embodiments, the second side 27 of the semiconductor die 21 can be a doped substrate or layer stack formed at wafer level, but which is not used for electrical connections. In some embodiments, the second side 27 comprises a further one or more metal layers located on the semiconductor die 21. A third insulating layer can be located on the second main surface 27 of the semiconductor die 21. The third insulating layer can be an epoxy layer or an epoxy foil. In some embodiments, the second main surface 27 can be bare and formed by the material of the semiconductor die 21, e.g. silicon.

[0065] In some not-illustrated embodiments, a second metallization layer is located on the second main surface 27, which is electrically floating and e.g. forms a convenient surface for attaching a heat sink.

[0066] In other embodiments, the second surface 27 of the semiconductor device 20 can be electrically coupled to the drain 24 and formed from a doped drain region. In some embodiments, a second metallization structure is located on the second major surface 27 of the semiconductor die 21 and coupled to the drain electrode 24.

[0067] The semiconductor die 21 further includes a side surface 39 extending between the first major surface 26 and the second major surface 27 of the semiconductor die 21. The side surface 39 can be bare and formed from the semiconductor material of the semiconductor die 21, or one or more passivation or insulating layers can be disposed on the side surface 39.

[0068] The metallization structure 28 forms electrically conductive redistribution structures between the source electrode 23 and the source pad 34, between the drain electrode 24 and the drain pad 35, and between the gate electrode 25 and the gate pad 36. The metallization structure 28 includes at least three electrically conductive layers that are vertically interleaved by one or more insulating layers. In some embodiments, the metallization structure 28 includes only three electrically conductive layers 29, 31, 33 and two insulating layers 30, 32. In other embodiments, the metallization structure 28 can further include additional electrically conductive and insulating layers. The lowest electrically conductive layer in contact with the semiconductor die 20 can include tungsten, and the outermost electrically conductive layer providing the pads can be formed from copper. Some or all of the insulating layers can include polyimide.

[0069] Figure 9 A cross-sectional perspective view of the semiconductor device 20 including the metallization structure 28 is shown, and the transistor device 22 is also illustrated in greater detail.

[0070] The vertical transistor device 22 can be designed such that its active region 40 is divided into a plurality of unit cell regions 41. Referring to Figure 9A perspective view of the semiconductor die 21 is shown in FIG. 1. Each cell field region 41 can include a plurality of trenches 42 separated by mesas 43. The trenches 42 extend from the first major surface 26 into the body of the semiconductor die 21. Each trench 42 can include a field plate. The trenches 42 can be elongated and extend substantially parallel to each other. Each cell of the cell field region includes a trench 42 and a mesa 43. In each cell, the mesa 43 includes a source electrode 23 formed of a doped source region on a body region doped with an opposite conductivity type. In some embodiments, a gate electrode 40 is located within each trench 42 and on and electrically isolated from the field plate 42. In other embodiments, the gate electrode is located in a gate trench located in the mesa 43 and extending through and electrically isolated from the source and body regions. The transistor device 22 further includes a doped drain region forming a drain electrode 24 spaced apart from the bottom of the trench 42 and can be continuous over the entire active region 40. A vertical electrical connection between the drain electrode 24 and the first major surface 26 is formed by at least one conductive via 44 located in the semiconductor die. The conductive via 44 extends into the first major surface 26 to the doped drain region 24. The conductive via 44 is arranged laterally between adjacent cell field regions 41. In some embodiments, two conductive vias 44 are located between adjacent cell field regions 41.

[0071] With additional reference to Figure 2 , Figure 2 A schematic plan view of a portion of the first conductive layer 29 located on the first major surface 26 of the semiconductor die 21 is shown. The first conductive layer 29 includes a first source redistribution structure 45 electrically coupled to the source electrodes 23, a first drain redistribution structure 46 electrically coupled to the drain electrode 24, and a first gate redistribution structure 47 electrically coupled to the gate electrodes 25. The first source redistribution structure 45, the first drain redistribution structure 46, and the first gate redistribution structure 47 are substantially coplanar and spaced apart from each other in the lateral direction and electrically isolated from each other, such that each of the three redistribution structures of the first conductive layer 29 can be electrically connected to a different electrical potential.

[0072] The first source redistribution structure 45 includes a plurality of first discrete conductive regions 48 located on the trenches 42 of the cell field region 41. One first conductive region 48 can be provided for each cell field region 41. The first discrete conductive regions 48 are spaced apart from one another in the lateral direction and can have the form of strips extending substantially parallel to one another. The first drain redistribution structure 46 includes a plurality of second discrete conductive regions 49, each second discrete conductive region 49 being located between two adjacent first discrete conductive regions 48. Each second discrete conductive region 49 is located on and electrically coupled to one or more conductive vias 44, which in turn are electrically coupled to the drain electrode 24. Each second discrete conductive region 49 is spaced apart from the first conductive regions 48 in the lateral direction. Each second conductive region 49 can have an elongated strip-like structure and extend substantially parallel to the first discrete conductive regions 48.

[0073] As seen in a plan view of Figure 2 The first gate redistribution structure 47 can be positioned towards the outer peripheral edge of the first major surface 26 and includes a gate runner 50 extending substantially perpendicular to the first and second discrete conductive regions 48, 49 and into a larger area gate pad portion 51, as seen in a plan view of

[0074] In some embodiments, at least some of the second discrete conductive regions 49' are interrupted and include two or more laterally separated segments 53, each segment 53 being spaced apart by a gap 52 located between two adjacent segments 53. The first discrete conductive regions 48' extend through the gaps 52 and are positioned adjacent to two opposite lateral sides of each segment 53.

[0075] Referring to Figure 9 A portion of the second discrete conductive regions 49 can be formed as the conductive material forming the conductive vias 44, as seen in a partial cross-sectional view of

[0076] Each of the first drain redistribution structure 46 and the first source redistribution structure 45 includes a plurality of discrete conductive regions separated in the lateral direction. To electrically couple the source electrodes in each cell field region 41 to one another and to the source pad 34, a plurality of first discrete conductive regions 48 are electrically coupled to one another by means of one of the conductive layers of the overlying metallization structure 28. Similarly, to couple the conductive vias 44 to one another and to the second discrete conductive regions 49 of the first drain redistribution structure 46 and also to the drain pad 24, the conductive vias 44 and the second discrete conductive regions 49 of the first drain redistribution structure 46 are electrically coupled to one another by means of one of the conductive layers of the overlying metallization structure 28.

[0077] In some embodiments, the electrical connections between the first discrete conductive regions 48 coupled to the source electrodes 23 and the electrical connections between the second discrete conductive regions 49 coupled to the drain electrodes 24 are formed in different conductive layers of the metallization structure 28.

[0078] For example, in some embodiments, the second discrete conductive regions 49 are electrically coupled to one another by means of the second conductive layer 31 and the first discrete conductive regions 48 are electrically coupled to one another by means of the third conductive layer 33. Alternatively, the second discrete conductive regions 49 are electrically coupled to one another by means of the third conductive layer 33 and the first discrete conductive regions 48 are electrically coupled to one another by means of the second conductive layer 31.

[0079] By providing lateral connections for both power electrodes (i.e., source electrodes and drain electrodes) in different conductive layers of the metallization structure 28, larger area electrical connections can be formed between the discrete conductive regions within the respective layers. Additionally, the electrical connections between a particular electrode type (e.g., source electrodes in different cell field regions 41) can be positioned vertically above the electrical connections between another type of electrode (e.g., drain electrodes and conductive vias coupled to the drain electrodes). Thus, low resistance redistribution structures between the source electrodes 23 and the source pad 34 and between the drain electrodes 24 and the drain pad 35 can be formed in smaller lateral areas. This in turn allows the overall area of the semiconductor device 20 to be kept smaller and as similar as possible to the active region 40 of the transistor device 22 that is required to provide the desired on-resistance of the device. Additional area that would simply be used for metallization and electrical redistribution structures is not required. Thus, the area and footprint of the semiconductor device 20 can be kept small.

[0080] Figure 3 The metallization structure 28 is illustrated for Figure 2a schematic plan view of the first insulating layer 30 of the transistor first conductive layer 29. The first insulating layer 30 is positioned laterally between the first source redistribution structure 45 and the first drain redistribution structure 46, and thus between the first discrete conductive region 48 and the second discrete conductive region 49. The first insulating layer 30 is also located on and at least partially covers the first discrete conductive region 48 and the second discrete conductive region 49. The first insulating layer 30 also extends over the gate redistribution structure 47 and between the gate redistribution structure 47 and the first discrete conductive region 48 and the second discrete conductive region 49.

[0081] The first insulating layer 30 comprises a first opening 54 located on the first discrete conductive region 48 of the first source redistribution structure 45 such that a defined portion of the first conductive region 48 of the first redistribution structure 45 is exposed at the bottom of the opening 54. The first insulating layer 30 further comprises a second opening 55 which exposes a defined portion of the second discrete conductive region 49 of the first drain redistribution structure 46.

[0082] The first opening 54 can be substantially smaller in lateral extension than the first discrete conductive region 48 such that two or more first openings 54 are positioned laterally adjacent to and spaced apart from each other on a single discrete conductive region 48. Each second opening 55 can have a lateral shape which substantially corresponds to the lateral shape of the strip-like second conductive region 49 and can expose a defined area which is only slightly smaller than the lateral extension of the underlying second discrete conductive region 49. The first insulating layer 30 further comprises a first opening 54' which is positioned laterally between segments 53 of the interrupted second discrete conductive region 49'. The first opening 54' is larger than the other first openings 54. In some embodiments, the first opening 54' can have an H-shape or an I-shape such that the longitudinal portions extend substantially perpendicular to the strip-like second openings 55 and the lateral portions extend substantially parallel to the strip-like second openings 55. The first insulating layer 30 comprises a further opening 56 which is located on and exposes a defined portion of the gate redistribution structure 47 and can expose at least a portion of the gate flow channel 50 in addition to a portion of the gate pad portion 51. The lateral shape of the further opening 56 can substantially correspond to the lateral shape of the underlying first gate redistribution structure 47.

[0083] Figure 4 a schematic plan view of the metallization structure 28 located Figure 3A schematic view of a second conductive layer 31 on the first insulating layer 30. The second conductive layer 31 includes a second source redistribution structure 57 electrically coupled to the first source redistribution structure 45 and a second drain redistribution structure 58 electrically coupled to the first drain redistribution structure 46. The second source redistribution structure 57 and the second drain redistribution structure 58 are laterally arranged and spaced apart from each other and are substantially co-planar.

[0084] In some embodiments, the second conductive layer 31 further includes a second gate redistribution structure 62 located on the first gate redistribution structure 47 and having a lateral shape corresponding to the lateral shape of the first gate redistribution structure 47. For example, the second gate redistribution structure 62 can include corresponding gate runner portions 63 and gate contact portions 64.

[0085] The second source redistribution structure 57 is located in the first openings 54 of the first insulating layer 30. The second source redistribution structure 57 includes a plurality of first conductive island portions 59 arranged on the first discrete conductive regions 48 of the first source redistribution structure 45. The lateral extension of each of the first conductive island portions 59 can be defined by the lateral extension of the first openings 54.

[0086] The second drain redistribution structure 58 is arranged in the second openings 55 of the first insulating layer 30 and also extends between the second openings 55 and between the second discrete conductive regions 49. The second drain redistribution structure is also laterally located between and spaced apart from the first conductive island portions 59 of the second redistribution structure 57. The second drain redistribution structure 58 laterally surrounds the first conductive island portions 59 of the second source redistribution structure 57. The second drain redistribution structure 58 thus electrically couples the second discrete conductive regions 49 of the underlying first drain redistribution structure 46 to each other as it is located in each of the second openings 55 exposing the second discrete conductive regions 49 and extends between the second openings 55 on the upper surface 60 of the first insulating layer 30. The conductive vias 44 located between the cell field regions 41 within the semiconductor die 20 are now electrically coupled to each other by means of the second drain redistribution structure 58. The drain electrode 24 is electrically coupled to the single conductive layer 58 by a plurality of vertical electrical connections spaced apart in the lateral direction.

[0087] The second drain redistribution structure 58 extends laterally above the first source redistribution structure 45 and is electrically insulated from the lower first source redistribution structure 45 by a centrally located first insulating layer 30. In the second conductive layer 31, the source electrodes 23 of the various unit field regions 41 remain electrically separated from each other because the second redistribution structure 57 includes only the upper first conductive island 59 of each of the discrete first conductive regions 48 located in the lower first source redistribution structure. The first conductive island 59 of the second source redistribution structure 57 can be considered to be located in a window 61 formed in the continuous second drain redistribution structure 58. The first conductive island 59 is laterally spaced from the sides of the window 61. The window 61 may have a lateral shape conforming to the lateral shape of the first conductive island 59.

[0088] In some embodiments, the second drain redistribution structure 58 may be in the form of a grid, wherein a first conductive island 59 is located at the center of each opening of the grid.

[0089] Figure 5 The illustration is a schematic plan view of the second conductive layer 31 located on top of the first conductive layer 29, which is shown in dashed lines below, as indicated by solid lines. Figure 5 The first insulating layer 30 located between the first conductive layer 29 and the second conductive layer 31 is not shown.

[0090] from Figure 5 As can be seen from the overlaid plan view, the second drain redistribution structure 58 extends over the separated segments 53 of the second conductive regions 49, including the interruption of the first drain redistribution structure 46, and extends laterally between the second conductive regions 49, thus electrically coupling the discrete second conductive regions 49 together. The second drain redistribution structure 58 also extends over the first discrete conductive regions 48 of the first source redistribution structure 45, whereby it is electrically insulated from the first discrete conductive regions 48 by a centrally located first insulating layer 30. The second drain redistribution structure 58 includes a plurality of windows 61 exposing a predefined area of ​​each of the first discrete conductive regions 48. The first conductive islands 59 forming the second source redistribution structure 57 are located within these windows 61 and are laterally spaced from the surrounding second drain redistribution structures 58.

[0091] In some embodiments, the second conductive layer 31 includes a second gate redistribution structure 62, which is located on the first gate redistribution structure 47 and has a lateral shape corresponding to the lateral shape of the first gate redistribution structure 47. For example, the second gate redistribution structure 62 may include a corresponding gate channel portion 63 and a gate contact portion 64.

[0092] Figure 6A schematic plan view of the third conductive layer 33 is shown with solid lines on the second insulating layer 32 indicated with dashed lines.

[0093] The second insulating layer 32 is arranged on the second source redistribution structure 57 and on the second drain redistribution structure 58 and also in the space between them, i.e. in the gap between the first conductive islands 59 and the window 61 in the second drain redistribution structure 58. The second insulating layer 32 comprises third openings 65 each of which exposes a defined area of the first conductive islands 59 of the second source redistribution structure 57 and one or more fourth openings 66 each of which exposes a defined area of the second drain redistribution structure 58. The second insulating layer 32 can also comprise further openings 67 which expose a predefined portion of the second gate redistribution structure 62 and in particular a predefined portion of the gate pad portion 64.

[0094] The third openings 65 can be arranged laterally such that one third opening 65 is located above one of the first conductive islands 59 and can have a lateral shape which substantially corresponds to the lateral shape of the first conductive islands 59. However, a third opening 65' located above an H-shaped conductive island 59' can have a lateral shape which is different from the lateral shape of the underlying first conductive island 59'. For example, the third opening 65' can have a simple rectangular form and is located on only one longitudinal bar of the first conductive island 59'.

[0095] The third conductive layer 33 comprises third source redistribution structures 68 which are electrically coupled to the second source redistribution structure 57 and third drain redistribution structures 69 which are electrically coupled to the second drain redistribution structure 58. The third source redistribution structures 68 are used to electrically couple the first conductive islands 59 of the second redistribution structure 57 to each other. The third source redistribution structures 68 are arranged in the third openings 65 and extend between the first conductive islands 59 and above the second drain redistribution structure 58. In regions where the third source redistribution structures 68 are located on and extend above the second drain redistribution structure 58, the third source redistribution structures 68 are electrically insulated from the underlying second drain redistribution structure 58 by the intervening second insulating layer 32. The third source redistribution structures 68 can substantially cover the entire first surface 26 of the semiconductor die 21 except for the areas occupied by the third drain redistribution structures 69 and the gate redistribution structures 70 which provide the gate pads 71.

[0096] A third drain redistribution structure 69 is disposed in the fourth opening 66 of the second insulating layer 32 and includes at least one second conductive island 72 spaced apart from the third redistribution structure 68 in the lateral direction. The third source redistribution structure 68 includes a window 73 laterally surrounding and spaced apart from the second conductive island 72. In embodiments in which the third drain redistribution structure includes a plurality of second conductive islands 72, each second conductive island 72 is located in the window 73 of the third source redistribution structure 68, the second conductive islands 72 can be spaced apart from each other in the lateral direction.

[0097] Figure 7 A schematic plan view of the epoxy layer 74 located on the third conductive layer 33 of the metallization structure 28. Figure 4 Figure 6 A schematic plan view of the epoxy layer 74 located on the third conductive layer 33 of the metallization structure 28.

[0098] The second conductive island 72 can have a lateral size and shape that is larger than the fourth opening 66 in the underlying second insulating layer 32 and extends over adjacent portions of the underlying second drain redistribution structure 58. In some embodiments, the second conductive island 72 also extends over at least a portion of the first conductive island 59 (e.g., portions of the first conductive island 59') of the underlying second source redistribution structure 57. In these embodiments, the second conductive island 72 is electrically insulated from the underlying first conductive island 59' by the intervening portion of the second insulating layer 32.

[0099] For embodiments in which the third conductive layer 33 of the metallization structure 28 provides a contact pad, such as embodiments in which the metallization structure 28 includes three conductive layers with two intervening insulating layers, the lateral shape, extension, and lateral position of the second conductive island 72 within the area of the first major surface 26 can substantially correspond to the footprint of the semiconductor device 20.

[0100] Figure 8 A schematic plan view of the epoxy layer 74 located on the third conductive layer 33 of the metallization structure 28. Figure 7 A schematic plan view of the epoxy layer 74 located on the third conductive layer 33 of the metallization structure 28.

[0101] ​The epoxy layer 74 provides electrical insulation and passivation of the underlying third conductive layer 33, in some embodiments the epoxy can be replaced by another suitable material. The epoxy layer 74 can completely cover the third conductive layer 33 and include at least one fifth opening 75 exposing a predefined portion of the third source redistribution structure 68. The exposed portion of the third source redistribution structure 68 provides a source pad 76 for the semiconductor device 20. The epoxy layer 74 further includes at least one sixth opening 77 exposing at least a portion of the second conductive island 72 of the third drain redistribution structure 69, such that the sixth opening 77 defines a drain pad 78 of the package footprint. The lateral extension of the sixth opening 77 can be slightly smaller than the lateral extension of the second conductive island 72, such that the epoxy layer 74 is located on and covers a peripheral region of the second conductive island 72. The epoxy layer 74 further includes a seventh opening 79 located above the third gate redistribution structure 70 and defining a gate pad 80.

[0102] Figure 9 A perspective view of the semiconductor device 20 is illustrated, partially cut away, and illustrates the transistor cells and cell field region 41 of the transistor device 22 and the metallization structure 28.

[0103] Figure 10 A schematic view of a package footprint of the semiconductor device 20 is illustrated, which can be used Figure 1 A schematic view of a package footprint of the semiconductor device 20 is illustrated, which can be used

[0104] The external contact pads of the footprint can be arranged in a regular grid pattern. In some embodiments, such as in Figure 10 The semiconductor device 20 has a package footprint including at least one row of drain contact pads 78 and at least one row of source contact pads 76, as illustrated in

[0105] Solder or metal bumps, optionally with a solder coating on the metal bumps, or solder balls can be positioned on each of the contact pads 76, 78, 80.

[0106] A chip scale semiconductor device is provided that includes a vertical transistor device and a metallization structure, wherein a vertical conductive redistribution structure from a drain region to a first surface is provided by at least one conductive via within the semiconductor die and a drain redistribution structure that includes three or more conductive layers arranged on the first surface. An opposite second surface can be electrically passive and does not form part of the drain region since it does not need to be contacted for the drain redistribution structure. This enables the thickness of the semiconductor die to be variable and also enables the second surface to be used more easily for other purposes (since the second surface is electrically passive). For example, the second surface can be used as a contact surface for a heat sink or for product marking, e.g. by laser inscription into the second surface.

[0107] The plurality of conductive vias within the semiconductor die that are electrically coupled to the drain electrode are spaced apart from each other in the lateral direction. The lateral electrical connections between the conductive vias are provided in conductive layers of the metallization structure that are spaced apart in the vertical direction from the lowermost conductive layer of the metallization structure.

[0108] The lateral electrical connections between the source electrodes that are spaced apart in the lateral direction are provided in conductive layers of the metallization structure that are spaced apart in the vertical direction from the lowermost conductive layer of the metallization structure and that are different from and spaced apart in the vertical direction from the conductive layers of the metallization structure that are used to connect the conductive vias. In some embodiments, the outermost conductive layers of the metallization structure are used to electrically connect the source electrodes.

[0109] This arrangement of lateral connections between two power electrodes stacked one on top of the other on a major surface of the semiconductor die avoids the need for separate packaging processing and enables the footprint and die size of the device to be nearly the same, thus providing a chip scale package that can be made at wafer level.

[0110] Spatially relative terms such as "under", "below", "lower", "above", "upper" and the like, are used to describe an element's position as relating to the position of another element. These terms are intended to encompass different orientations of the device in addition to those depicted in the figures. Further, terms such as "first", "second", and the like, are also used to describe various elements, regions, sections, etc. and are not intended to be limiting. Like terms refer to like elements throughout the description.

[0111] As used herein, the terms "have," "has," "having," "include," "includes," "including," "contain," "contains," "containing," and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude the presence or addition of one or more other elements or features. The terms "a," "an," and "the" are intended to include both singular and plural referents, unless the context clearly dictates otherwise. It is to be understood that the features of the various embodiments described herein can be combined with each other, unless specifically noted otherwise.

[0112] While specific embodiments have been illustrated and described herein, it will be appreciated that various changes can be made to the embodiments without departing from the scope of the application. The application is not intended to be limited to the embodiments discussed herein, but is to be accorded the full scope of the claims and their equivalents.

Claims

1. A semiconductor device (20), comprising: Semiconductor die (21) includes a vertical transistor device (22) having a source electrode (23), a drain electrode (24) and a gate electrode (25), and the semiconductor die (21) has a first surface (26); A metallized structure (28) is located on the first surface (26). The metallized structure (28) includes a first conductive layer (29) on the first surface (26), a first insulating layer (30) on the first conductive layer (29), a second conductive layer (31) on the first insulating layer (30), a second insulating layer (32) on the second conductive layer (31), and a third conductive layer (33) on the second insulating layer (32). The third conductive layer (33) includes at least one source pad (34; 76) coupled to the source electrode (23), at least one drain pad (35; 78) coupled to the drain electrode (24), and at least one gate pad (36; 80) coupled to the gate electrode (25). The first conductive layer (29) includes a first source redistribution structure (45) coupled to the source electrode (23), a first drain redistribution structure (46) coupled to the drain electrode (24), and a first gate redistribution structure (47) coupled to the gate electrode (25). The first source redistribution structure (45) includes multiple discrete first conductive regions (48). The first drain redistribution structure (46) includes a plurality of discrete second conductive regions (49), which are laterally positioned between the first discrete conductive regions (48) of the first source redistribution structure (45) and laterally spaced from the first discrete conductive regions (48) of the first source redistribution structure (45). In this process, the plurality of discrete second conductive regions (49) of the first drain redistribution structure (46) are electrically coupled together through the second drain redistribution structure (58) in the second conductive layer (31), and The plurality of discrete first conductive regions (48) of the first source redistribution structure (45) are electrically coupled together through the third source redistribution structure (68) in the third conductive layer (33).

2. The semiconductor device (20) according to claim 1, wherein, The discrete second conductive region (49) of the first drain redistribution structure (46) has a strip shape.

3. The semiconductor device (20) according to claim 1 or 2, further comprising one or more conductive vias (44) extending from the first surface (26) into the semiconductor die (21), in, The one or more conductive vias (44) are electrically coupled to a doped drain region located within the semiconductor die (21) and to a first drain redistribution structure (46) on the first surface (26) of the semiconductor die (21).

4. The semiconductor device (20) according to claim 3, wherein, The vertical transistor device (22) includes an active region (40) divided into multiple unit field regions (41). Two elongated conductive vias (44) extending parallel to each other are positioned between adjacent unit field regions (41) and electrically coupled to a common conductive region in the second discrete conductive region (49) of the first drain distribution structure (46).

5. The semiconductor device (20) according to claim 1 or 2, wherein, The first insulating layer (30) is disposed on the first source redistribution structure (45) and the first drain redistribution structure (46) and is disposed laterally between the first source redistribution structure (45) and the first drain redistribution structure (46). The first insulating layer (30) includes The first opening (54) exposes a defined portion of the first discrete conductive region (48) of the first source redistribution structure (45), and The second opening (55) exposes a defined portion of the second discrete conductive region (49) of the first drain redistribution structure (46).

6. The semiconductor device (20) according to claim 5, wherein, The second conductive layer (31) includes a second source redistribution structure (57) electrically coupled to the first source redistribution structure (45) and a second drain redistribution structure (58) electrically coupled to the first drain redistribution structure (46). The second source redistribution structure (57) is disposed in the first opening (54) of the first insulating layer (30), and includes a plurality of first conductive islands (59) disposed on the first conductive region (48) of the first source redistribution structure (45), and The second drain redistribution structure (58) is arranged in the second opening (55) of the first insulating layer (30) and is laterally positioned between the first conductive islands (59) of the second source redistribution structure (57) and spaced laterally from the first conductive islands (59) of the second source redistribution structure (57), wherein the second drain redistribution structure (58) surrounds the first conductive islands (59) of the second source redistribution structure (57) laterally.

7. The semiconductor device (20) according to claim 6, wherein, The second drain redistribution structure (58) is arranged vertically above the first drain redistribution structure (46) and vertically above the portion of the first source redistribution structure (45) covered by the first insulating layer (30).

8. The semiconductor device (20) according to claim 7, wherein, The second insulating layer (32) is disposed on the second source redistribution structure (57) and on the second drain redistribution structure (58), and has a third opening (65) of a defined area exposing the first conductive island portion (59) of the second source redistribution structure (57) and at least one fourth opening (66) of a defined area exposing the second drain redistribution structure (58).

9. The semiconductor device (20) according to claim 8, wherein, The third source redistribution structure (68) in the third conductive layer (33) is electrically coupled to the second source redistribution structure (57), and the third conductive layer (33) also includes a third drain redistribution structure (69) electrically coupled to the second drain redistribution structure (58). The third source redistribution structure (68) is arranged in the third opening (65) and electrically couples the first conductive island portions (59) of the second source redistribution structure (57) to each other. The third source redistribution structure (68) extends above the portion of the second drain redistribution structure (67) covered by the second insulating layer (32). The third drain redistribution structure (67) is arranged in the fourth opening (66) and includes at least one second conductive island (72) spaced laterally from the third source redistribution structure (68).

10. The semiconductor device (20) according to claim 9, wherein, Each of the second conductive islands (72) of the third drain redistribution structure (67) has a lateral size such that each second conductive island (72) extends over the portion of the second source redistribution structure (57) covered by the second insulating layer (32).

11. The semiconductor device (20) according to claim 8, in, The conductive via (44), the first drain redistribution structure (46), the first source redistribution structure (45), and the first gate redistribution structure (47) comprise tungsten. The first insulating layer (30) comprises polyimide. The second drain redistribution structure (58) and the second source redistribution structure (57) are formed of AlCu alloy. The second insulating layer (32) comprises polyimide. The third drain redistribution structure (69) and the third source redistribution structure (68) are formed of Cu.

12. The semiconductor device (20) according to claim 1 or 2, further comprising an epoxy resin layer (74) disposed on a third conductive layer (33), wherein the epoxy resin layer (74) comprises: At least one fifth opening (75) exposes a portion of the third source redistribution layer (33) and defines the source pad (76). At least one sixth opening (77) exposes a portion of the second conductive island (72) of the third drain redistribution structure (69) and defines a drain pad (78), and At least one seventh opening (79) defines a gate pad (80).

13. The semiconductor device (20) according to claim 1, further comprising a third insulating layer located on a second surface (27) of the semiconductor die opposite to the first surface.

14. The semiconductor device (20) according to claim 13, wherein the third insulating layer is an epoxy resin layer or an epoxy resin foil.

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