Integrated assembly and method of forming the same

Abstract

The present invention relates to an integrated assembly and a method for forming an integrated assembly. Some embodiments include an integrated memory having a word line, a shielding plate and an access device. The access device includes a first diffusion region, a second diffusion region and a channel region. The channel region is vertically disposed between the first diffusion region and the second diffusion region. The access device is adjacent to the word line and adjacent to the shielding plate. A portion of the word line is close to a first side surface of the channel region, with the intervention of a first insulating region therebetween. A portion of the shielding plate is close to a second side surface of the channel region, with the intervention of a second insulating region therebetween. The first insulating region includes an insulating material. The second insulating region includes a gap. Some embodiments include a memory array. Some embodiments include a method for forming an integrated assembly.

Description

Technical Field

[0001] An integrated assembly, such as a memory array. The integrated assembly includes a space between an active area and a conductive shield. A method of forming the integrated assembly. Background Art

[0002] Modern computing architectures utilize memory to store data. One type of memory is dynamic random access memory (DRAM). Compared to alternative types of memory, DRAM offers the advantages of simple structure, low cost, and high speed.

[0003] DRAM may utilize memory cells, each memory cell having a capacitor in combination with a transistor (so-called 1T-1C memory cells), where the capacitor is coupled to the source / drain region of the transistor. DRAM cells may be utilized in DRAM arrays having hundreds, thousands, millions, etc. of memory cells. The transistors of the memory array have gates coupled to word lines (i.e., access lines). The memory cells of the memory array are addressed using bit lines (i.e., digit lines, sense lines) in combination with the word lines.

[0004] A continuing goal of integrated circuit fabrication is to scale integrated circuit systems to ever increasing levels of integration. It is desirable to develop memory arrangements suitable for scaling to highly integrated configurations. Summary of the invention

[0005] In one aspect, the present invention relates to an integrated memory, comprising: a word line; a shielding plate; an access device, comprising a first diffusion region, a second diffusion region and a channel region, the first diffusion region, the second diffusion region and the channel region being vertically arranged so that the channel region is between the first diffusion region and the second diffusion region; and wherein the access device is adjacent to the word line and the shielding plate, so that a portion of the word line is close to a first side surface of the channel region with the intervention of a first insulating region therebetween, and a portion of the shielding plate is close to a second side surface of the channel region with the intervention of a second insulating region therebetween; the first insulating region comprises an insulating material, and the second insulating region comprises a gap.

[0006] In another aspect, the present invention relates to a memory array, comprising: vertically extending semiconductor pillars; each of the semiconductor pillars includes a transistor channel region vertically disposed between a first source / drain region and a second source / drain region; the semiconductor pillars are arranged in rows and columns of the memory array; the rows extend along a row direction, and the columns extend along a column direction; word lines extend along a row direction; the word lines are adjacent to the transistor channel regions of the semiconductor pillars; each row of the memory array includes a plurality of semiconductor pillars along an associated one of the word lines; the associated one of the word lines has a first lateral surface and an opposite second lateral surface; the plurality of semiconductor pillars are associated with the one of the word lines subdivided in a first set along the first lateral surface and in a second set along the second lateral surface; the semiconductor pillars of the first set are spaced apart from the associated one of the word lines by a gate dielectric material between the first lateral surface and the transistor channel region of the semiconductor pillars of the first set; the second The semiconductor pillars of the collection are separated from the associated one of the word lines by a gate dielectric material between a second lateral surface and a transistor channel region of a second set of semiconductor pillars; a conductive shielding material, which is between the semiconductor pillars; a bit line, which extends along the column direction and is coupled to the first source / drain region; a storage element, which is coupled to the second source / drain region; each of the storage elements is uniquely addressed by a combination of one of the word lines and one of the bit lines; and wherein a cross-section along the column direction passes through the word lines, through a series of semiconductor pillars, and through a series of conductive plates of the conductive shielding material; the word lines along the cross-section have their first lateral surface along the channel region of the semiconductor pillar and are separated from the channel region of the semiconductor pillar by the gate dielectric material; the word lines along the cross-section have their second lateral surface separated from the conductive plate by the gate dielectric material; the conductive plate along the cross-section is separated from the transistor channel region of the semiconductor pillar by an intervening insulating region; the intervening insulating region includes a gap.

[0007] On the other hand, the present invention relates to a method for forming an assembly, which includes: forming a structure of columns having semiconductor material; the columns are arranged in rows; the columns have a first side and a second side in a relative relationship to each other along a cross-section; forming a first insulating material along the first side of the column; forming a conductive shielding material adjacent to the first insulating material and separated from the first side of the column by a first region including the first insulating material; forming a second insulating material along the second side of the column; forming a word line material adjacent to the second insulating material and separated from the second side of the column by a second region including the second insulating material; the word line material is configured as a word line extending along a first direction, wherein the first direction is the direction of the row; forming a first source / drain region and a second source / drain region along vertically opposite regions of the column; each of the columns includes a transistor channel region vertically disposed between the first source / drain region and the second source / drain region associated with the column; forming a bit line to be electrically connected to the first source / drain region and extending along a second direction intersecting the first direction; forming a storage element to be electrically connected to the second source / drain region; and removing at least some of the first insulating material to form a gap within the first region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A and 1B Accordingly are diagrammatic cross-sectional top and side views of an example assembly at example process stages of an example method for fabricating an example array of memory cells. Figure 1A The view along Figure 1B The line AA, and Figure 1B The view along Figure 1A Line BB.

[0009] Figure 2A and 2B Accordingly, Figure 1A and 1B The instance process phase after the instance process phase of Figure 1A and 1B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example assembly of. Figure 2A The view along Figure 2B The line AA, and Figure 2B The view along Figure 2A Line BB.

[0010] Figure 3A and 3B Accordingly, Figure 2A and 2B The instance process phase after the instance process phase of Figure 1A and 1B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example assembly of. Figure 3A The view along Figure 3BThe line AA, and Figure 3B The view along Figure 3A Line BB.

[0011] Figure 4A and 4B Accordingly, Figure 3A and 3B The instance process phase after the instance process phase of Figure 1A and 1B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example assembly of. Figure 4A The view along Figure 4B The line AA, and Figure 4B The view along Figure 4A Line BB.

[0012] Figure 5A and 5B Accordingly, Figure 3A and 3B The instance process phase after the instance process phase of Figure 1A and 1B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example assembly of Figure 4A and 4B An alternative to the view. Figure 5A The view along Figure 5B The line AA, and Figure 5B The view along Figure 5A Line BB.

[0013] Fig. 6A and 6B Accordingly, Figure 4A and 4B The instance process phase after the instance process phase of Figure 1A and 1B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example assembly of. Fig. 6A The view along Figure 6B The line AA, and Figure 6B The view along Fig. 6A Line BB.

[0014] Fig. 7A and 7B Accordingly, Fig. 6A and 6B The instance process phase after the instance process phase of Figure 1A and 1B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of a region of an example assembly. Fig. 7A The view along Figure 7B The line AA, and Figure 7B The view along Fig. 7A Line BB.

[0015] Fig. 8A and 8B Accordingly are diagrammatic cross-sectional top and side views of an example assembly at example process stages of an example method for fabricating an example array of memory cells. Fig. 8A The view along Figure 8B The line AA, and Figure 8B The view along Fig. 8A Line BB.

[0016] Fig.9A and 9B Accordingly, Fig. 8A and 8B The instance process phase after the instance process phase of Fig. 8A and 8B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example assembly of. Fig.9A The view along Fig. 9B The line AA, and Fig. 9B The view along Fig.9A Line BB.

[0017] Fig. 10A and 10B Accordingly, Fig.9A and 9B The instance process phase after the instance process phase of Fig. 8A and 8B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example assembly of. Fig. 10A The view along Fig. 10B The line AA, and Fig. 10B The view along Fig. 10A Line BB.

[0018] Fig.11A and 11B Accordingly, Fig. 10A and 10B The instance process phase after the instance process phase of Fig. 8A and 8B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example assembly of. Fig.11A The view along Fig. 11B The line AA, and Fig. 11B The view along Fig.11A Line BB.

[0019] Fig. 12A and 12B Accordingly, Fig.11A and 11B The instance process phase after the instance process phase of Fig. 8A and 8BA diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example assembly of. Fig. 12A The view along Fig. 12B The line AA, and Fig. 12B The view along Fig. 12A Line BB.

[0020] Fig.13A and 13B Accordingly, Fig. 12A and 12B The instance process phase after the instance process phase of Fig. 8A and 8B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example assembly of. Fig.13A The view along Fig. 13B The line AA, and Fig. 13B The view along Fig.13A Line BB.

[0021] Fig.14A and 14B Accordingly, Fig.13A and 13B The instance process phase after the instance process phase of Fig. 8A and 8B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example assembly of. Fig.14A The view along Fig. 14B The line AA, and Fig. 14B The view along Fig.14A Line BB.

[0022] Fig.15A , 15B 15C is a diagrammatic cross-sectional top view of an example assembly at an example process stage of an example method for fabricating an example array of memory cells ( Fig.15A ) and diagrammatic cross-sectional side view ( Fig. 15B and 15C ). Fig.15A , 15B The process stages of 15A and 15C may be used as an example of the process shown in FIG. 8 . Fig.15A The view along Fig. 15B and 15C Line AA; Fig. 15B The view along Fig.15A line BB; and Fig. 15C The view along Fig.15A Line CC.

[0023] Fig.16A , 16B 16C is a diagrammatic cross-sectional top view of an example assembly at an example process stage of an example method for fabricating an example array of memory cells ( Fig.16A ) and diagrammatic cross-sectional side view ( Fig. 16B and 16C ). Fig.16A , 16B and 16C process stages can be followed Fig.15A , 15B and 15C process. Fig.16A The view along Fig. 16B and 16C Line AA; Fig. 16B The view along Fig.16A line BB; and Fig. 16C The view along Fig.16A Line CC.

[0024] Fig.17A , 17B 17C is a diagrammatic cross-sectional top view of an example assembly at an example process stage of an example method for fabricating an example array of memory cells ( Fig.17A ) and diagrammatic cross-sectional side view ( Fig. 17B and 17C ). Fig.17A , 17B and 17C process stages can be used as Fig.9A and 9B An example of the process shown in Fig.16A , 16B and the process stage of 16C. Fig.17A The view along Fig. 17B and 17C Line AA; Fig. 17B The view along Fig.17A line BB; and Fig. 17C The view along Fig.17A Line CC.

[0025] Fig.18 is a diagrammatic schematic illustration of a region of an example memory array.

[0026] Fig.19 is a diagrammatic cross-sectional side view of a region of an example assembly including stacked levels. DETAILED DESCRIPTION

[0027] Some embodiments include an integrated assembly having shielding material between memory cells (e.g., DRAM cells). The shielding material can suppress interference between adjacent components. The memory cell can have a vertically extending channel region. The shielding material can be separated from such a channel region by a gap, which can improve the on-current along the channel region compared to a configuration lacking a gap between the shielding material and the channel region. Example embodiments are described with reference to FIGS. 1 to 19.

[0028] A first example method of forming a first example DRAM array is described with reference to FIGS. 1-7.

[0029] refer to Figure 1A and 1B , construction 10 includes islands 80 of semiconductor material 14 extending upwardly from a mass 82 of semiconductor material. Semiconductor material 14 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of: one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; wherein the term III / V semiconductor material refers to a semiconductor material including elements selected from Group III and Group V of the periodic table (wherein Group III and Group V are old nomenclature and are now referred to as Groups 13 and 15). In some embodiments, semiconductor material 14 may include, consist essentially of, or consist of single crystal silicon.

[0030] The islands are capped with protective material 104. Protective material 104 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silicon nitride.

[0031] Relative to Figure 1A and Figure 1B An x, y, z axis system is provided to assist the reader in understanding the relationship of the structures shown in the figure. In some embodiments, the x-axis direction and the y-axis direction may be referred to as the first direction and the second direction, respectively. In some embodiments, the island 80 may be considered to be arranged in a matrix having rows and columns; and the x-axis direction and the y-axis direction may be considered as the row direction and the column direction, respectively.

[0032] refer to Figure 2A and 2B , the areas between islands 80 are lined with insulating material 40, then conductive shielding material 42 is deposited and recessed, and then additional insulating material 40 is provided over the shielding material.

[0033] Insulating material 40 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of silicon nitride. In some embodiments, insulating material 40 may be referred to as a first insulating material.

[0034] Conductive shield material 42 may include any suitable composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, conductive shield material 42 may include, consist essentially of, or consist of conductive doped semiconductor materials (e.g., conductive doped polysilicon). The conductive doped semiconductor materials may be doped to any suitable concentration, and in some embodiments may be doped to at least about 1 x 10 20 Atom / cm 3 In other words, in some example embodiments, the mask material 42 may include a polycrystalline semiconductor material (eg, polysilicon) heavily doped with one or more impurities (eg, one or more of phosphorus, arsenic, boron, etc.).

[0035] In some embodiments, semiconductor material 14 and shielding material 42 may both include, consist essentially of, or consist of silicon; wherein the silicon of semiconductor material 14 is single crystalline and the silicon of shielding material 42 is polycrystalline (and in some applications, referred to as polysilicon).

[0036] refer to Figure 3A and 3B , protective material 104( Figure 2A and 2B ) is removed, and subsequently doped regions 22 are formed along upper portions of islands 80. In the illustrated embodiment, doped regions 22 are formed after protective material 104 is removed. In other embodiments, semiconductor material 14 may be blanket doped before the material is patterned into islands 80, and thus doped regions 22 may be formed at the same level as islands 80. Figure 3A and 3B The doped regions 22 correspond to source / drain regions.

[0037] Capacitor 62 is formed to be coupled to (electrically connected to) source / drain region 22. The illustrated capacitors are container-type capacitors; and each includes a container-shaped electrode 106, a dielectric material 108 within the container-shaped electrode, and another electrode 110 above the dielectric material 108 and within the container-shaped electrode. Electrodes 106 and 110 may include any suitable composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). Dielectric material 108 may include any suitable composition; and in some embodiments may include one or more of silicon dioxide, silicon nitride, and silicon oxynitride. Although capacitors are specifically illustrated, it should be understood that structure 62 may generally refer to any suitable memory element; including, for example, resistive memory, phase change memory, etc.

[0038] Insulating material 112 is provided over capacitors 62 and between capacitors 62. Insulating material 112 may include any suitable composition; and in some embodiments may include one or both of silicon dioxide and silicon nitride.

[0039] Semiconductor material 14 , shielding material 42 , insulating material 40 , capacitor 62 , and insulating material 112 may together be considered to form a subassembly 114 .

[0040] refer to Figure 4A and 4B , subassembly 114 is bonded to handle structure 94 via bonding region 96, and is subsequently inverted. Handle structure 94 may include any suitable configuration, and in some embodiments may correspond to a semiconductor wafer (e.g., a single crystal silicon wafer) or other suitable semiconductor substrate. For purposes of interpreting the present invention, the term "semiconductor substrate" means any construction including semiconductor material, including but not limited to integral semiconductor material, such as a semiconductor wafer (alone or in an assembly including other materials), and a layer of semiconductor material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrates described above.

[0041] The bonding of the subassembly 114 to the handle structure 94 may be achieved using any suitable process; including, for example, techniques in which two silicon dioxide surfaces are placed relative to one another and subjected to an appropriate treatment to induce covalent bonding between the surfaces and thereby form a composite structure. Thus, the bonding region 96 may include silicon dioxide. The treatment for inducing covalent bonding may be a thermal treatment. Such thermal treatment may utilize temperatures in excess of 800° C. Alternatively, one or both of the silicon dioxide surfaces may be subjected to a plasma treatment prior to the thermal treatment, and the temperature of the subsequent thermal treatment may be reduced to a temperature in the range of from about 150° C. to about 200° C. The bonding of the silicon dioxide surfaces to one another may be referred to as “hybrid bonding” (or “smart cutting”); wherein example hybrid bonding procedures are described in U.S. Pat. Nos. 9,666,573 and 10,103,053, both of which are assigned to Micron Technology, Inc., and both of which list Mitsunari Sukekawa as an inventor.

[0042] The mass 82 of semiconductor material 14 ( Figure 3B ) is removed by appropriate processing (e.g., CMP), which exposes region 98 of semiconductor material 14 (in some embodiments, region 98 may be considered to correspond to Figure 3B The source / drain region 20 is formed along the region 98 and may be formed in some embodiments by implanting appropriate dopants into the region 98. In some embodiments, the source / drain regions 20 and 22 may be referred to as the first source / drain region and the second source / drain region, respectively.

[0043] The trench 116 is formed to extend into the island 80 ( Figure 3B ) and extends from the island into the pattern pillar 48. The trench 116 extends along the x-axis direction (ie, a first direction, a row direction).

[0044] The trenches 116 are lined with gate dielectric material 52, and then wordline material 54 is formed within such lined trenches and patterned into wordlines 58. Subsequently, additional insulating material is formed over the wordlines. In the embodiment shown, the additional insulating material is the same composition as material 52.

[0045] The insulating material 52 may be referred to as a second insulating material to distinguish it from the first insulating material 40 .

[0046] The conductive shielding material 42 is patterned through the trenches 116 to form a shielding plate 43 .

[0047] Figure 4A and 4BThe embodiment of FIG. 1 shows that the trench 116 is etched deep enough to reach the doped region 22. In alternative embodiments, the trench 116 may be etched less deeply, and the doped extension may be formed to extend from the bottom of the trench to the doped region 22. For example, Figure 5A and 5B Shows an alternative Figure 4A and 4B 1 and 14. The embodiment of the ...

[0048] refer to Fig. 6A and 6B , showing that in Figure 4A and 4B 1. The bit line 32 is formed over the subassembly 114 and is coupled to the source / drain region 20. The bit line includes a bit line material 18. The bit line material 18 may include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some example embodiments, the bit line material 18 may include one or more of tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, etc.

[0049] The conductive shield plate 43 is coupled to (i.e., electrically connected to) a reference source (i.e., a reference voltage node, a reference structure, a reference terminal, etc.) 70. The reference source is configured to provide a desired voltage to the shield plate 43. Such a voltage may be any suitable voltage, and in some embodiments may be a ground voltage (i.e., the shield plate 43 may be electrically grounded).

[0050] Shielding material 42 may include any suitable composition; for example, a metal (e.g., tungsten, titanium, etc.), a metal-containing material (e.g., a metal silicide, a metal nitride, a metal carbide, etc.), and / or a doped semiconductor material (e.g., doped silicon, doped germanium, etc.). In embodiments where the conductive shielding material includes a doped semiconductor material, doped regions 20 and 22 may be considered to include a first semiconductor material (i.e., material 14), and conductive shielding material 42 may be considered to include a second semiconductor material. If shielding material 42 includes conductive doped silicon, then the shielding material may be doped to the same conductivity type as doped regions 20 and 22, or may be doped to an opposite conductivity type than doped regions 20 and 22 (where p-type and n-type are understood to be opposite conductivity types).

[0051] Fig. 6A and 6B The configuration of can be considered to correspond to an assembly including a memory array 60. The memory array includes bit lines 32 extending along a second direction along the y-axis (i.e., extending along columns 68 of the memory array 60), and includes word lines 58 extending along a first direction along the x-axis (i.e., extending along rows 66 of the memory array). The word lines 58 are vertically offset from the bit lines 32 and cross the bit lines (specifically, relative to the bit lines). Figure 6B configuration crosses below the bit lines).

[0052] The pillars 48 are arranged in rows 66 and columns 68 of the memory array 60. The pillars 48 along a given column 68 are those pillars coupled to a common bit line 32. The pillars 48 along a given row 66 are those pillars coupled to a common word line. The word lines 58 are labeled 58a, 58b, and 58c so that they can be different from each other. The rows 66 are labeled 66a, 66b, and 66c so that they can be different from each other; wherein row 66a includes pillars 48 associated with word line 58a, row 66b includes pillars 48 associated with word line 58b, and row 66c includes pillars associated with word line 58c. Individual pillars 48 are identified with respect to a particular one of the rows 66a, 66b, and 66c with which the pillar is associated. The pillars associated with row 66a are labeled 166a, the pillars associated with row 66b are labeled 166b, and the pillars associated with row 66c are labeled 166c. It is noteworthy that each row includes a first series of pillars (i.e., a first set) on one side of the word line, and a second series of pillars (i.e., a second set) on the opposite side of the word line. For example, one of the pillars in pillar 166a is labeled 166a-1 to show that it is part of the first series on one side of word line 58a, and the other pillars in pillar 166a are labeled 166a-2 to show that they are part of the second series on the opposite side of word line 58a. The pillars of the first set alternate with the pillars of the second set along row 66a. Similarly, pillar 166b includes a first set 166b-1 and a second set 166b-2, and pillar 166c includes a first set 166c-1 and a second set 166c-2 (not shown).

[0053] The opposite side of word line 58 is identified along Fig. 6A and 6B The sides 55 and 57 of the cross-sectional view of the word line. The sides 55 and 57 of the word line may be referred to as a first lateral surface and a second lateral surface of the word line.

[0054] The first source / drain region 20 and the second source / drain region 22 are along vertically opposing regions of the semiconductor pillars 48. Each of the semiconductor pillars 48 includes a channel region (i.e., a transistor channel region) 25 vertically disposed between the first source / drain region 20 and the second source / drain region 22. The channel region can be considered to be within the body region 24 of the transistor 132, wherein such body region extends between the first source / drain region and the second source / drain region. The word line 58 is adjacent to the channel region and is separated from the channel region by an intervening insulating region including a gate dielectric material 52. The gate dielectric material is between the first lateral surface 55 and the channel region of the first set of semiconductor pillars 48 (e.g., pillar 166a-1 is along word line 58a), and the gate dielectric material is between the second lateral surface 57 and the second set of semiconductor pillars 48 (e.g., the pillars labeled 166a-2 are along word line 58a). The conductive shield material 42 is between the first set and the second set of semiconductor pillars.

[0055] Figure 6B The embodiment of FIG. 5 shows that the gate dielectric material 52 separates the shielding material 42 from the second lateral side 57 of the word line 58 a and separates the channel region 25 from the first lateral side 55 of the word line 58 a. In other embodiments, the insulating material separating the shielding material from one lateral side of the word line may not be the same as the insulating material separating the transistor channel material from the other side of the word line.

[0056] Figure 6B The cross-sections of can be considered as cross-sections along the column direction (i.e., along the y-axis direction). Such cross-sections pass through the series of first semiconductor pillars (specifically, the pillars are identified as 166a-1, 166b-1, and 166c-1), and through the series of conductive plates 43 of the shielding material 42. The word lines (58a, 58b, and 58c) along the cross-sections have their first lateral surfaces 55 along the channel regions 25 of the semiconductor pillars (i.e., along the channel regions of the transistors included in the active regions within the semiconductor pillars) and are separated from such channel regions by the gate dielectric material 52; and have their second lateral surfaces 57 along the conductive plates 43 and are separated from the conductive plates by the gate dielectric material 52. The shielding plates 43 illustrated are pillars extending vertically along the cross-sections, without regions of shielding material extending below the word lines 58a-c.

[0057] Fig. 6A and 6BThe configuration may be considered to include a memory cell 130 that includes a capacitor 62 and a transistor 132. The various features of the memory cell may be patterned by any suitable process. In some embodiments, at least some of the components described herein may be patterned using a lithographically patterned masking material (e.g., a photolithographically patterned photoresist). A lithographic (e.g., photolithographic) process will have a minimum feature size "F" associated with it. A goal of integrated circuit manufacturing may be to form components to reduce size in order to achieve increased levels of integration. The size of a component may be expressed in terms of the minimum feature size F of the lithographic process utilized during the manufacture of the component. Some of the embodiments described herein include adaptations to be defined as 4F 2 130 within an area of ​​. For example, Fig. 6A Diagrammatically illustrate the size 2Fx2F (i.e., area 4F 2 ) and such frame contains the entire lateral perimeter of the memory cell 130.

[0058] In some embodiments, Figure 6B The configuration of may be viewed as including a first region 85 between the shield plate 43 and the semiconductor pillar 48 , and including a second region 87 between the word line 58 and the semiconductor pillar.

[0059] Shielding plates 43 may advantageously suppress interference (eg, capacitive coupling and / or other mechanisms of crosstalk) between adjacent structures within memory array 60 .

[0060] refer to Fig. 7A and 7B , remove the first insulating material 40 ( Fig. 6A and 6B ) to form void 83. The illustrated embodiment removes all of insulating material 40. In other embodiments, only some of the insulating material may be removed. If all of material 40 is removed, then material 40 is a sacrificial material; and may or may not include insulating material.

[0061] Material 40 may include Fig. 7A and 7B In some embodiments, material 40 may include low-density silicon nitride (porous silicon nitride) and may be removed by wet etching using phosphoric acid.

[0062] The gap 83 is formed in the first region 85 ; and is formed exclusively between the shielding plate 43 and the channel region 25 .

[0063] The void 83 may be considered as a low dielectric constant region between the shield plate 43 and the channel region 25. The low dielectric constant region may advantageously improve the on-current within the channel region 25 during operation of the transistor 132 as compared to a configuration having a higher dielectric constant region between the shield plate 43 and the channel region 25. In some applications, it has been found that the utilization of the void 83 may improve the on-current by at least about 10 times as compared to a configuration having a higher dielectric constant material present in place of such a void.

[0064] 1-7, void 83 is formed after bit line 32 and memory element 62. In other embodiments, at least a portion of void 83 may be formed before one or both of bit line 32 and memory element 62.

[0065] In some embodiments, Fig. 7A and 7B The configuration can be considered to include an integrated memory. The integrated memory includes a word line 58, a shield plate 43, and an access device 132. The access device includes a first source / drain region 20 and a second source / drain region 22, and includes a channel region 25 vertically disposed between the first source / drain region and the second source / drain region.

[0066] Access device 132 is adjacent to word line 58 and shield plate 43. Insulation region 85 is interposed between channel region 25 and shield plate 43, and insulation region 87 is interposed between channel region 25 and portions of word line 58 proximate such channel region. Figure 7B The cross-section of can be viewed as showing each of the channel regions 25 having a side surface 89 proximate a portion of the word line 58 and another (opposite) side surface 91 proximate a portion of the shield plate 43. The insulating region 85 is along the side surface 91, and the insulating region 87 is along the side surface 89. One of the side surfaces 89 and 91 can be referred to as a first side surface, and the other as a second side surface; and one of the insulating regions 85 and 87 can be referred to as a first insulating region and the other as a second insulating region.

[0067] The insulating region 85 includes a void 83. In the illustrated embodiment, the void 83 completely fills the insulating region 85. In other embodiments, the void 83 may only partially fill the insulating region 85.

[0068] Insulating material (dielectric material) 52 is within insulating region 87. In some embodiments, such insulating material may include, consist essentially of, or consist of silicon dioxide.

[0069] In some embodiments, Figure 7B A cross section (a cross section along the column direction corresponding to the y-axis) can be viewed as passing through the word line 58, through the series of semiconductor pillars 48, and through the series of conductive plates 43. Figure 7BThe word lines 58 of the cross section of FIG. 4 have their first lateral surfaces 55 along the channel regions 25 of the illustrated semiconductor pillars 48 and are spaced apart from such channel regions 25 by the gate dielectric material 52. Figure 7B The word lines 58 of the cross section of FIG. 5 have their second lateral surfaces 57 adjacent to the conductive plate 43 and are spaced apart from the conductive plate by the gate dielectric material 52. Figure 7B The conductive plate 43 of the cross section of FIG. 8 is separated from the transistor channel region 25 by an intervening insulating region 85 including a gap 83. Figure 7B In the illustrated embodiment of FIG. 8 , void 83 extends below conductive plate 43 and extends above conductive plate 43. In other embodiments, void 83 may not extend above conductive plate 43, and / or may not extend below conductive plate 43.

[0070] The embodiments of Figures 1 to 7 show that the capacitor is formed above the semiconductor substrate, followed by inversion of the substrate and bonding it to the handle, and then forming the bit line. In an alternative process, the bit line can be formed above the semiconductor substrate, followed by inversion of the substrate and formation of the capacitor. Examples of such alternative processes are described with reference to Figures 8 to 14.

[0071] refer to Fig. 8A and 8B , construction 10a includes an island 80 of semiconductor material 14 extending upwardly from a mass 82 of semiconductor material. The island is covered with a protective material 104.

[0072] refer to Fig.9A and 9B , the areas between the islands 80 are lined with insulating material 40 (first material 40), then shielding material 42 is deposited and recessed, and then additional insulating material 40 is provided over the shielding material.

[0073] refer to Fig. 10A and 10B , protective material 104( Fig.9A and 9B ) is removed, and a doped region (first source / drain region) 20 is formed at the top of the semiconductor material island 80. Subsequently, a bit line 32 is formed over the doped region 20. A portion of the doped region 20 is formed at Fig. 10A 20 to assist the reader in visualizing the relationship of the bit lines to the region 20, but are shown in dashed (dashed) view to indicate that they are from Fig. 10A The plane of the cross section. Fig. 10A and 10B The structures form a subassembly 114 similar to those described above.

[0074] refer to Fig.11A and 11B, the subassembly 114 is coupled to the handle structure 94 and is utilized similarly to the above reference Figure 4A and 4B The hybrid bonds described are inverted.

[0075] The mass 82 of semiconductor material 14 ( Fig. 10B ) is removed by appropriate processing (e.g., CMP), which exposes region 98 of semiconductor material 14 (in some embodiments, region 98 can be considered to correspond to the bottom region of island 80).

[0076] refer to Fig. 12A and 12B , a second source / drain region 22 is formed along an upper portion of the semiconductor material 14 .

[0077] The trenches 116 are formed to extend along a first direction of the x-axis. The trenches 116 pattern the semiconductor material 14 into the pillars 48.

[0078] The trenches 116 are lined with a gate dielectric material (second insulating material) 52, and then a word line material 54 is formed within such lined trenches and patterned into word lines 58. Subsequently, additional insulating material is formed over the word lines. In the embodiment shown, the additional insulating material is the same composition as material 52 (in other embodiments, the additional insulating material may have another composition).

[0079] The conductive shielding material 42 is patterned into a shielding plate 43 .

[0080] exist Fig. 12A and 12B In the illustrated embodiment, the doped extension 118 is formed to extend from the bottom of the trench 116 to the doped region 20 .

[0081] refer to Fig.13A and 13B , capacitors 62 (shown as blocks) are electrically coupled to source / drain regions 22. Insulating material 102 is provided between capacitors 62. Shield plate 43 is coupled to reference voltage 70.

[0082] Fig.13A and 13B The memory cell 130 of the embodiment may be configured to have a 2 The lateral perimeter within an area, such as relative to Fig.13A shown.

[0083] refer to Fig.14A and 14B , remove the first insulating material 40 ( Fig.13A and 13B) to form void 83. The illustrated embodiment removes all of insulating material 40. In other embodiments, only some of the insulating material may be removed. If all of material 40 is removed, then material 40 is a sacrificial material; and may or may not include insulating material. Material 40 may be removed by similar means to that described above with reference to Fig. 7A and 7B The processing of the described process is removed.

[0084] The void 83 is formed in the first region 85; and is formed exclusively between the shield plate 43 and the channel region 25. The insulating material 52 (gate dielectric material) remains in the second region 87; and remains exclusively between the word line 58 and the channel region 25.

[0085] Fig.14A and 14B The configuration can be referred to above Fig. 7A and 7B The configuration described is the same; and only with respect to Fig. 7A and 7B The configuration is shown in an inverted configuration.

[0086] In some embodiments, the conductive shield material 42 may be formed to directly contact the body region 24 of the access device 132. In such embodiments, the shield material 42 may include a suitable composition at a suitable reference voltage to enable the shield material to mitigate floating body effects (i.e., charge accumulation) that may be associated with the body region 24 during operation of the access device associated with the memory array 60. For example, in some embodiments, the shield material may include a doped semiconductor material, wherein such doped semiconductor material has an opposite type of conductivity relative to the source / drain regions 20 and 22. For example, if the source / drain regions 20 and 22 are n-type, then the shield material may be p-type. The voltage source 70 may be configured to operate in conjunction with the shield plate 43 for mitigation of floating body effects within the body region 24.

[0087] Example methods for forming shielding material 42 to directly contact body region 24 are described with reference to FIGS. 15 through 17 .

[0088] refer to Figures 15A to 15C , in a similar Fig. 8A and 8B The construction 10a is shown at a process stage of the process stage of FIG. Fig.15AThe islands 80 in the top view of the memory array can be viewed as being assembled in a cell 301 having a central pillar 300 and having six peripheral pillars 302 arranged substantially hexagonally around the central pillar. The term "substantially hexagonally" means hexagonally within reasonable tolerances of manufacturing and measurement. The illustrated cell 301 can be viewed as a repeating unit of a pattern formed across a semiconductor substrate during the manufacture of a memory array.

[0089] Four of the pillars 302 together define the corners of the rectangle 304. The unit 301 has a first dimension D1 from the central pillar 300 to any of the six surrounding pillars 302, and has a second dimension D2 between the pillars 302 along the edge of the rectangle 304. The second dimension D2 is greater than the first dimension D1.

[0090] refer to Figures 16A to 16C , insulating material 40 is formed between islands 80 (although material 40 is referred to as "insulating material", it should be understood that in some embodiments material 40 may be sacrificial; and in such embodiments material 40 may or may not be insulating). In some embodiments, material 40 may completely fill the area between islands 80. Structure 10a is then subjected to directional etching, which etches faster along the wider dimension D2 than along the narrower dimension D1. The directional etching removes some of the insulating material 40 from between the islands 80 to form deep trenches 149 between the islands. The deep trenches have narrow areas 151 between the islands separated by dimension D1, and have wide areas 153 between the islands separated by dimension D2. Material 40 remains after directional etching of the lines outside the lateral surfaces of islands 80. Deep trenches 149 do not penetrate material 40 along the first dimension D1, but do penetrate material 40 along the second dimension D2 to expose areas 155 of islands 80 along the second dimension D2. Area 155 is shown along Fig. 16C A cross-sectional side view of Fig.16A A top cross-sectional view is illustrated diagrammatically.

[0091] refer to Figures 17A to 17C , the conductive shielding material 42 is formed in the deep trench 149 ( Figures 16A to 16C ), and then additional insulating material 40 is formed over the shielding material 42. Figures 17A to 17C The processing stage can be compared with the above reference Fig.9A and 9B The processing stages described are identical. Figures 17A to 17C The configuration can then be processed to form a memory array by the same process as described above with reference to FIGS. 10 to 14 . However, such a memory array will have shielding material 42 directly contacting conductive plates 43 of body regions 24 of access devices 132 .

[0092] The memory array 60 described herein may be a DRAM array and may include a memory cell having one transistor combined with one capacitor (1T-1C memory cell). Fig.18 A portion of an example DRAM array 60 is schematically illustrated. Bit lines (digit lines) 32 are shown corresponding to bit lines BL1, BL2, BL3, and BL4; and word lines 58 are shown corresponding to word lines WL1, WL2, WL3, and WL4. Memory cells 130 extend across the array, wherein each of the memory cells includes a capacitor 62 and a transistor (access device) 132. The access device may include an active region (described above) within pillar 48; wherein such active region includes a pair of source / drain regions 20 and 22 (described above), and a channel region 25 (described above) between the source / drain regions. Fig.18 Each of the memory cells 130 within the memory array 60 is uniquely addressed by a combination of one of the word lines and one of the bit lines. The memory array may contain any suitable number of memory cells; and in some embodiments may include hundreds, millions, tens of millions, etc. of memory cells.

[0093] In some embodiments, a memory array 60 of any of the types described herein may be within a memory hierarchy (ie, memory strata) that is within a vertically stacked arrangement of strata (or strata). For example, Fig.19 A portion of an integrated assembly 140 is shown that includes levels (labeled as levels 1-4) arranged vertically stacked. The vertical stacked arrangement can be extended upward to include additional levels. Levels 1-4 can be considered as examples of one level stacked on top of another. The levels can be located in different semiconductor dies, or at least two of the levels can be located in the same semiconductor die.

[0094] The bottom level (layer 1) may include control circuitry and / or sensing circuitry (e.g., may include word line drivers, sense amplifiers, etc.); and in some applications may include CMOS circuitry (illustrated diagrammatically as CMOS circuitry 142). One or more of the upper levels (layers 2-4) may include memory arrays, such as memory array 60 of any of the types described herein. If multiple levels include memory arrays, the memory arrays within the various levels may be identical to one another (e.g., may all be DRAM arrays), or may be different relative to one another (e.g., some may be DRAM arrays while others are NAND arrays). Fig.19The memory array 60 is diagrammatically indicated as being within a second level (Level 2), and electrical connections 143 are shown between the CMOS circuitry 142 of Level 1 and components of the memory array 60 of Level 2. In some embodiments, the CMOS circuitry 142 may be electrically coupled to word lines and / or bit lines of the memory 60; and may include, for example, word line drivers, sense amplifiers, etc.

[0095] The assemblies and structures discussed above may be utilized within integrated circuits (the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0096] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or to be developed including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0097] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. The terms are considered synonymous in the present invention. The use of the term "dielectric" in some instances and the term "insulating" (or "electrically insulating") in other instances may be used within the present invention to provide language changes to simplify the premise basis within the appended claims, and is not used to indicate any significant chemical or electrical differences.

[0098] The terms "electrically connected" and "electrically coupled" may both be used in the present invention. The terms are considered synonymous. The use of one term in some instances and another term in other instances may be to provide language variations within the present disclosure to simplify the premise basis within the appended claims.

[0099] The specific orientations of the various embodiments in the drawings are for illustration purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The descriptions and appended claims provided herein are directed to any structure having the described relationships between the various features, whether the structure is in a specific orientation of the figures or rotated relative to such orientation.

[0100] Unless otherwise specified, the cross-sectional views in the accompanying drawings only show features within the plane of the cross-section and do not show material behind the plane of the cross-section in order to simplify the drawings.

[0101] When a structure is referred to as being "on," "adjacent to," or "against" another structure, the structure may be directly on the other structure or there may also be intervening structures. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly against" another structure, there are no intervening structures. The terms "directly below," "directly over," and the like do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

[0102] A structure (eg, layer, material, etc.) may be referred to as "vertically extending" to indicate that the structure extends generally upward from an underlying base (eg, substrate). A vertically extending structure may or may not extend substantially orthogonally relative to an upper surface of a base.

[0103] Some embodiments include an integrated memory having a word line, a shield plate, and an access device. The access device includes a first diffusion region and a second diffusion region and a channel region. The channel region is vertically disposed between the first diffusion region and the second diffusion region. The access device is adjacent to the word line and adjacent to the shield plate. A portion of the word line is close to a first side surface of the channel region with the intervention of a first insulating region therebetween. A portion of the shield plate is close to a second side surface of the channel region with the intervention of a second insulating region therebetween. The first insulating region includes an insulating material. The second insulating region includes a gap.

[0104] Some embodiments include a memory array comprising vertically extending semiconductor pillars. Each of the semiconductor pillars includes a transistor channel region vertically disposed between a first source / drain region and a second source / drain region. The semiconductor pillars are arranged in rows and columns of the memory array. The rows extend along a row direction, and the columns extend along a column direction. The word lines extend along the row direction. The word lines are adjacent to the transistor channel regions of the semiconductor pillars. Each row of the memory array includes a plurality of semiconductor pillars along an associated one of the word lines. The associated one of the word lines has a first lateral surface and an opposite second lateral surface. The plurality of semiconductor pillars associated with one of the word lines are subdivided in a first set along the first lateral surface and in a second set along the second lateral surface. The semiconductor pillars of the first set are spaced apart from the associated one of the word lines by a gate dielectric material between the first lateral surface and the transistor channel region of the semiconductor pillars of the first set. The semiconductor pillars of the second set are spaced apart from the associated one of the word lines by a gate dielectric material between the second lateral surface and the transistor channel region of the semiconductor pillars of the second set. Conductive shielding material is between the semiconductor pillars. The bit lines extend along the column direction and are coupled to the first source / drain region. The storage elements are coupled to the second source / drain region. Each of the storage elements is uniquely addressed by a combination of one of the word lines and one of the bit lines. A cross section along the column direction passes through the word lines, through a series of first semiconductor pillars, and through a series of conductive plates of conductive shielding material. The word lines along the cross section have their first lateral surfaces along the channel region of the first semiconductor pillar and are separated from the channel region of the first semiconductor pillar by a gate dielectric material. The word lines along the cross section have their second lateral surfaces separated from the conductive plates by a gate dielectric material. The conductive plates along the cross section are separated from the transistor channel region of the semiconductor pillar by an intervening insulating region. The intervening insulating region includes a gap.

[0105] Some embodiments include a method of forming an assembly. A structure is formed as a column having a semiconductor material. The columns are arranged in a row. Along a cross section, the column has a first side and a second side in an opposing relationship to each other. A first insulating material is formed along the first side of the column. A conductive shielding material is formed adjacent to the first insulating material and is spaced apart from the first side of the column by a first region including the first insulating material. A second insulating material is formed along the second side of the column. A word line material is formed adjacent to the second insulating material and is spaced apart from the second side of the column by a second region including the second insulating material. The word line material is configured as a word line extending along a first direction, wherein the first direction is the direction of the row. A first source / drain region and a second source / drain region are formed along vertically opposite regions of the column. Each of the columns includes a transistor channel region vertically disposed between a first source / drain region and a second source / drain region associated with the column. A bit line is formed to be electrically connected to the first source / drain region and to extend along a second direction intersecting the first direction. A storage element is formed to be electrically connected to the second source / drain region. At least some of the first insulating material is removed to form a void within the first region.

[0106] As specified, the subject matter disclosed herein has been described in language more or less specific in terms of structural and methodological features. However, it is to be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Therefore, the claims have the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated memory comprising: word line; Shielding plate; an access device including a first diffusion region and a second diffusion region and a channel region, the first diffusion region and the second diffusion region and the channel region being arranged vertically such that the channel region is between the first diffusion region and the second diffusion region; and The access device is adjacent to the word line and the shielding plate, so that a portion of the word line is close to the first side surface of the channel region with the intervention of a first insulating region therebetween, and a portion of the shielding plate is close to the second side surface of the channel region with the intervention of a second insulating region therebetween; the first insulating region includes an insulating material, and the second insulating region includes a gap. 2 . The integrated memory according to claim 1 , wherein the gap fills the entirety of the second insulating region.

3. The integrated memory of claim 1, wherein the insulating material comprises silicon dioxide.

4. The integrated memory according to claim 1, further comprising: a bit line electrically connected to the first diffusion region; as well as A storage element is electrically connected to the second diffusion region.

5. The integrated memory of claim 1, wherein the shielding plate comprises a polycrystalline semiconductor material doped with impurities.

6. The integrated memory of claim 5, wherein the first and second diffusion regions and the shielding plate are of the same conductivity type.

7. The integrated memory of claim 6, wherein the first diffusion region and the second diffusion region are of n-type, and wherein the shielding plate is also of n-type.

8. The integrated memory of claim 5, wherein the first and second diffusion regions are of a first conductivity type, and wherein the shielding plate is of a second conductivity type opposite to the first conductivity type.

9. The integrated memory according to claim 8, wherein the first diffusion region and the second diffusion region are of n-type, and wherein the shielding plate is of p-type.

10. The integrated memory of claim 9, wherein the channel region is within a body region of the access device, and wherein the shielding plate directly contacts the body region of the access device.

11. The integrated memory of claim 1, wherein the shielding plate is coupled to a reference source having a ground voltage.

12. The integrated memory according to claim 1, comprising a memory cell including the access device and comprising a storage element coupled to one of the first diffusion region and the second diffusion region.

13. The integrated memory according to claim 12, wherein the lateral perimeter of the memory cell is adapted to 4F 2 within the area.

14. A memory array comprising: A vertically extending semiconductor column; Each of the semiconductor pillars includes a transistor channel region vertically disposed between a first source / drain region and a second source / drain region; The semiconductor pillars are arranged in rows and columns of the memory array; the rows extend along a row direction, and the columns extend along a column direction; a word line extending along the row direction; The word lines are adjacent to the transistor channel regions of the semiconductor pillars; each row of the memory array includes a plurality of the semiconductor pillars along an associated one of the word lines; the associated one of the word lines having a first lateral surface and an opposing second lateral surface; the plurality of semiconductor pillars being associated with the one of the word lines subdivided along the first lateral surface in a first set and along the second lateral surface in a second set; the semiconductor pillars of the first set being spaced apart from the associated one of the word lines by a gate dielectric material between the first lateral surface and the transistor channel regions of the semiconductor pillars of the first set; the semiconductor pillars of the second set being spaced apart from the associated one of the word lines by the gate dielectric material between the second lateral surface and the transistor channel regions of the semiconductor pillars of the second set; a conductive shielding material between the semiconductor pillars; a bit line extending along the column direction and coupled to the first source / drain region; a storage element coupled to the second source / drain region; each of the storage elements being uniquely addressed by a combination of one of the word lines and one of the bit lines; as well as wherein a cross section along the column direction passes through the word lines, through the series of semiconductor pillars, and through the series of conductive plates of the conductive shielding material; the word lines along the cross section have their first lateral surfaces along the channel regions of the semiconductor pillars and are separated from the channel regions of the semiconductor pillars by the gate dielectric material; the word lines along the cross section have their second lateral surfaces separated from the conductive plates by the gate dielectric material; the conductive plates along the cross section are separated from the transistor channel regions of the semiconductor pillars by intervening insulating regions; the intervening insulating regions include gaps.

15. The memory array of claim 14 wherein the gap fills the intervening insulating region.

16. The memory array of claim 14 wherein the void extends below the conductive plate.

17. The memory array of claim 14 wherein the void extends above the conductive plate.

18. The memory array of claim 14 wherein the void extends below the conductive plate and extends above the conductive plate.

19. The memory array of claim 14, being within a hierarchy; the hierarchy being within a hierarchy of a vertically stacked arrangement and above at least one other of the hierarchies within the vertically stacked arrangement.

20. The memory array of claim 14, wherein the memory array is within a hierarchy; the hierarchy being within a hierarchy of a vertically stacked arrangement and being above another one of the hierarchies within the vertically stacked arrangement, the another one of the hierarchies comprising a CMOS circuit system electrically coupled to the word lines and / or the bit lines.

21. The memory array of claim 14 wherein the transistor channel region is within a body region of the semiconductor pillar, and wherein the conductive shield material directly contacts the body region.

22. A method of forming an assembly, comprising: forming a configuration of pillars having a semiconductor material; the pillars being arranged in rows; The post has a first side and a second side in opposing relationship to each other along a cross section; forming a first insulating material along the first side of the pillar; forming a conductive shielding material adjacent to the first insulating material and spaced apart from the first side of the pillar by a first region including the first insulating material; forming a second insulating material along the second side of the pillar; forming a word line material adjacent to the second insulating material and spaced apart from the second side of the pillar by a second region including the second insulating material; the word line material being configured as a word line extending along a first direction, wherein the first direction is a direction of the row; forming first and second source / drain regions along vertically opposing regions of the pillars; each of the pillars comprising a transistor channel region vertically disposed between the first and second source / drain regions associated with the pillar; forming a bit line to be electrically connected to the first source / drain region and to extend along a second direction intersecting the first direction; forming a storage element to be electrically connected to the second source / drain region; as well as At least some of the first insulating material is removed to form a void within the first region.

23. The method of claim 22, wherein the void is formed after the bit line and the memory element are formed.

24. The method of claim 22 wherein each word line is associated with one of the rows; and wherein the pillars along each of the rows alternate between a first pillar on a first side of the word line associated with the row and a second pillar on an opposite second side of the word line associated with the row.

25. The method of claim 22, wherein said forming of said structure comprises: forming islands of said semiconductor material extending upwardly from said mass of semiconductor material; as well as The islands are patterned into the pillars.

26. The method of claim 25, further comprising: forming the first insulating material to line the outer lateral surface of the island; as well as The conductive shielding material is formed between islands of the liner.

27. The method of claim 26, comprising forming the first source / drain region in an upper region of the island; wherein the island, the first insulating material and the conductive shielding material together form a structure; The method further comprises: forming the bit line to extend across the upper region of the island and to be electrically connected to the first source / drain region within the upper region; the bit line and the structure together forming a subassembly; keying the subassembly to a handle structure and inverting the subassembly; removing the proof mass from the inverted subassembly to expose a bottom of the island, and forming the second source / drain region along the exposed bottom of the island; forming grooves to extend into the bottoms of the islands and patterning the islands into the pillars, the grooves extending along the first direction; lining the trench with the second insulating material; and The word line material is formed within the lined second trench to pattern the word line material into the word line.

28. The method of claim 27, further comprising forming the storage element to be coupled to the second source / drain region after the patterning of the word line material into the word line.

29. The method of claim 28, wherein the storage element is a capacitor.

30. The method of claim 26, comprising forming the second source / drain region in an upper region of the island; wherein the island, the first insulating material, and the conductive shielding material together form a structure; The method further comprises: forming the memory element above the upper region of the island and electrically connected to the second source / drain region in the upper region; The storage element and the structure together form a subassembly; keying the subassembly to a handle structure and inverting the subassembly; removing the proof mass from the inverted subassembly to expose a bottom of the island, and forming the first source / drain region along the exposed bottom of the island; forming grooves to extend into the bottoms of the islands and patterning the islands into the pillars, the grooves extending along the first direction; lining the groove with the second insulating material; forming the word line material within the lined second trench to pattern the word line material into the word line; as well as The bit line is formed to extend across the first source / drain region and to be electrically coupled with the first source / drain region.

31. The method of claim 30, wherein the pillar has a body region between the first and second source / drain regions, and wherein the conductive shielding material directly contacts such body region.

32. The method of claim 31 , wherein the islands are in an arrangement comprising a repeating unit having a central pillar and six peripheral pillars arranged substantially hexagonally around the central pillar; the six peripheral pillars comprising a set of four pillars that together define the corners of a rectangle; the repeating unit having a first dimension from the central pillar to any one of the six peripheral pillars and having a second dimension along an edge of the rectangle; the method further comprising: forming the first insulating material filling area between the islands; as well as utilizing etching conditions to remove regions of the first insulating material from between the islands and thereby form deep trenches extending between the islands while leaving remaining portions of the first insulating material as the first insulating material lining the exterior lateral surfaces of the islands; The deep trench does not penetrate the first insulating material along the first dimension, and penetrates the first insulating material along the second dimension to expose a region of the island along the second dimension; The forming of the conductive shielding material includes forming the conductive shielding material to contact the exposed area of ​​the island; the exposed area of ​​the island becomes a portion directly contacting the main area of ​​the conductive shielding material.

33. The method of claim 30, wherein the pillar has a body region between the first and second source / drain regions, and wherein the conductive shielding material is completely electrically isolated from such body region by the void.

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