Electronic panel and electronic device having the same

Abstract

An electronic panel and an electronic device having the same are provided. The electronic panel includes: a substrate layer; signal lines disposed on the substrate layer; and an insulating layer disposed on the substrate layer and including an opening edge that contacts the signal lines and defines an opening region, wherein when viewed in a plan view, the opening region exposes a part of the substrate layer and ends of the signal lines, and wherein the insulating layer has a first thickness at a first point spaced apart from the opening edge and has a second thickness at a second point disposed farther from the opening edge than the first point, and the second thickness is greater than the first thickness.

Description

Technical Field

[0001] Exemplary embodiments of the invention generally relate to an electronic panel and an electronic device having the electronic panel, and more particularly, to an electronic panel having reduced defects and an electronic device having the electronic panel. Background Art

[0002] Electronic devices such as smart phones, tablet computers, laptop computers, and smart televisions are being developed, and the electronic devices generally include a display device for providing information. In addition to the display device, the electronic devices also include various electronic modules such as an electronic panel.

[0003] When manufacturing an electronic device by assembling a display device and an electronic module, defects may occur while assembling the display panel and the electronic module.

[0004] The above information disclosed in this background art section is only for understanding the background art of the inventive concept, and thus, it may include information that does not constitute the prior art. Summary of the Invention

[0005] An electronic panel constructed according to an exemplary embodiment of the invention and an electronic device including the electronic panel can reduce cracks in an insulating layer.

[0006] Additional features of the inventive concept will be set forth in the description below, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0007] An electronic panel according to an exemplary embodiment includes: a substrate layer; signal lines disposed on the substrate layer; and an insulating layer disposed on the substrate layer and including an opening edge that contacts the signal lines and defines an opening region, and when observed in a plan view, the opening region exposes a part of the substrate layer and ends of the signal lines, wherein the insulating layer has a first thickness at a first point spaced apart from the opening edge and has a second thickness at a second point disposed farther from the opening edge than the first point, and the second thickness is greater than the first thickness.

[0008] The thickness of the insulating layer may gradually decrease from the second point to the opening edge.

[0009] The insulating layer may have a step between the second point and the opening edge.

[0010] The insulating layer may include an organic layer that contacts the signal lines.

[0011] The electronic panel may further include an input sensing electrode connected to the signal lines.

[0012] The signal lines may include a first signal line and a second signal line. The first signal line is disposed on a first surface of the substrate layer, and the second signal line is disposed on a second surface of the substrate layer opposite to the first surface. And the insulating layer may include: a first insulating layer disposed on the first surface of the substrate layer, stacked with the first signal line, and defining a first opening region exposing a part of the substrate layer and an end portion of the first signal line; and a second insulating layer disposed on the second surface of the substrate layer, stacked with the second signal line, and defining a second opening region exposing another part of the substrate layer and an end portion of the second signal line. And when observed in a plan view, the first opening region of the first insulating layer may not overlap with the second opening region of the second insulating layer.

[0013] The electronic panel may further include pixels electrically connected to the signal lines.

[0014] The pixels may include light emitting diodes.

[0015] The electronic panel may further include: a circuit element layer disposed on the substrate layer and including transistors; a display element layer disposed on the circuit element layer and including light emitting diodes; a packaging layer disposed on the display element layer; and input sensing electrodes disposed on the packaging layer, wherein the signal lines may be electrically connected to the input sensing electrodes.

[0016] When observed in a plan view, the opening region may extend to the edge of the substrate layer.

[0017] An electronic panel according to another exemplary embodiment includes: a substrate layer; signal lines disposed on the substrate layer; and an insulating layer disposed on the substrate layer and having a covering region and an edge region. The insulating layer includes an opening edge in contact with the signal lines and defining an opening region. When observed in a plan view, the opening region exposes a part of the substrate layer and an end portion of the signal lines. Wherein, the thickness of the insulating layer is constant in the covering region and gradually decreases toward the opening edge in the edge region.

[0018] An electronic device according to yet another exemplary embodiment includes a first electronic panel and a second electronic panel electrically connected to the first electronic panel. The first electronic panel includes: a substrate layer; signal lines disposed on the substrate layer; and an insulating layer disposed on the substrate layer and including an opening edge in contact with the signal lines and defining an opening region. When observed in a plan view, the opening region exposes an edge of the substrate layer, a part of the substrate layer extending from the edge of the substrate layer, and an end portion of the signal lines. Wherein, a first width of a region of the opening region overlapping with the signal lines is larger than a second width of a region of the opening region not overlapping with the signal lines.

[0019] The second electronic panel may include a circuit board.

[0020] The opening region may include a first region having a first width and a second region having a second width, and the circuit board may be stacked with the first region and the second region and may not be stacked with a first portion of the first region.

[0021] The electronic device may further include an anisotropic conductive material disposed between an end of the signal line and the circuit board.

[0022] The anisotropic conductive material may be stacked with the first portion of the first region.

[0023] The insulating layer may have a first thickness at a first point spaced apart from the opening edge and may have a second thickness at a second point disposed farther from the opening edge than the first point, and the second thickness is greater than the first thickness.

[0024] The first electronic panel may further include an input sensing electrode connected to the signal line.

[0025] The first electronic panel may further include pixels electrically connected to the signal line.

[0026] The first electronic panel may further include: a circuit element layer disposed on a substrate layer and including transistors; a display element layer disposed on the circuit element layer and including light-emitting diodes; a thin film encapsulation layer disposed on the display element layer; and an input sensing electrode disposed on the thin film encapsulation layer and electrically connected to the signal line.

[0027] It will be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. Description of the Drawings

[0028] The drawings are included to provide a further understanding of the invention, and the drawings are incorporated in and constitute a part of this specification, the drawings illustrate exemplary embodiments of the invention, and together with the description are used to explain the inventive concept.

[0029] Figure 1 is a perspective view showing an electronic device according to an exemplary embodiment.

[0030] Figure 2A is an exploded perspective view showing an electronic device according to an exemplary embodiment.

[0031] Figure 2B is a cross-sectional view showing a display panel according to an exemplary embodiment.

[0032] Figure 2C is a cross-sectional view showing an electronic device according to an exemplary embodiment.

[0033] Figure 2D is a cross-sectional view showing an electronic device according to an exemplary embodiment.

[0034] Figure 3A is a cross-sectional view showing an input sensing panel according to an exemplary embodiment.

[0035] Figure 3B is a plan view showing an input sensing panel according to an exemplary embodiment.

[0036] Figure 3C is an enlarged plan view showing a bonding area of an input sensing panel according to an exemplary embodiment.

[0037] Figure 3D , Figure 3E , Figure 3F and Figure 3G is a cross-sectional view showing an input sensing panel according to an exemplary embodiment.

[0038] Figure 3H is an enlarged plan view showing a bonding area of an input sensing panel according to an exemplary embodiment.

[0039] Figure 4A and Figure 4B is a cross-sectional view showing a bonding process of an electronic device according to a comparative embodiment.

[0040] Figure 4C and Figure 4D is a cross-sectional view showing a bonding process of an electronic device according to an exemplary embodiment.

[0041] Figure 5A is a cross-sectional view showing a display module according to an exemplary embodiment.

[0042] Figure 5B is an enlarged cross-sectional view showing a display module according to an exemplary embodiment.

[0043] Figure 5C is a plan view showing a display panel according to an exemplary embodiment.

[0044] Figure 5D is a plan view showing an input sensor according to an exemplary embodiment.

[0045] Figure 6A is an enlarged plan view showing a bonding area of a display panel according to an exemplary embodiment.

[0046] Figure 6B and Figure 6C is a cross-sectional view showing a bonding area of a display panel according to an exemplary embodiment.

[0047] Figure 7A is an enlarged plan view showing a bonding area of an electronic panel according to an exemplary embodiment.

[0048] Figure 7B and Figure 7C is a cross-sectional view showing a bonding area of an electronic panel according to an exemplary embodiment.

[0049] Figure 8A 、 Figure 8B and Figure 8C is a cross-sectional view showing a bonding area of an electronic panel according to an exemplary embodiment.

[0050] Figure 9A and Figure 9B is an enlarged plan view showing a bonding area of an electronic panel according to an exemplary embodiment. DETAILED DESCRIPTION

[0051] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable terms and are non-limiting examples of a device or method employing one or more inventive concepts disclosed herein. However, it is clear that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Additionally, the various exemplary embodiments may be different but not necessarily exclusive. For example, without departing from the inventive concept, the specific shapes, configurations, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0052] Unless otherwise stated, the exemplary embodiments shown are understood to provide exemplary features of variations in some ways in which the inventive concept may be implemented in practice. Thus, unless otherwise stated, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be otherwise combined, separated, interchanged, and / or rearranged without departing from the inventive concept.

[0053] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of cross-hatching or shading does not express or imply any preference or requirement for the specific material, material properties, dimensions, proportions, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the dimensions and relative dimensions of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process sequences may be performed in a different order than described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals denote the same elements.

[0054] When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or there can be intervening elements or intervening layers. However, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or intervening layers. For this reason, the term "connected" can refer to physical connection, electrical connection, and / or fluid connection with or without intervening elements. In addition, the DR1 axis, DR2 axis, and DR3 axis are not limited to the three axes of a rectangular coordinate system such as the x-axis, y-axis, and z-axis, and can be interpreted in a broader sense. For example, the DR1 axis, DR2 axis, and DR3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be understood to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as by way of example XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0055] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be named the second element without departing from the teachings of the disclosure.

[0056] For descriptive purposes, spatial relative terms such as "under", "below", "beneath", "lower", "above", "upper", "on top of", "higher", "side" (e.g., as in "sidewall") may be used herein and are thus used to describe the relationship of one element to another (other) element as shown in the figures. Spatial relative terms are intended to include different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "under" or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary term "under" can include both an upper and a lower orientation. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatial relative descriptors used herein are to be interpreted accordingly.

[0057] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. Additionally, the terms "comprises" and / or "comprising", and variations thereof, when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, and thus are used to interpret the inherent deviations in measured, calculated, and / or provided values that would be recognized by one of ordinary skill in the art.

[0058] The various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances are to be expected. Accordingly, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the particular shapes shown in the regions, but will include shape deviations resulting, for example, from manufacturing. In this manner, the regions shown in the figures are essentially schematic in nature, and the shapes of these regions may not reflect the actual shape of the regions of the device, and thus are not necessarily intended to be limiting.

[0059] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0060] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0061] Figure 1 is a perspective view showing an electronic device ED according to an exemplary embodiment. In the exemplary embodiment shown, the electronic device ED is exemplarily shown as a display device applied to a smart phone. However, the inventive concept is not limited thereto. The electronic device ED may include two or more panels (or substrates) electrically connected to each other. In addition, a plurality of electronic devices may be connected to each other to form one electronic device ED.

[0062] Referring to Figure 1 , a display surface for displaying an image is formed substantially parallel to a plane defined by a first direction axis DR1 and a second direction axis DR2. The display surface includes a display area DA and a non-display area NDA disposed adjacent to the display area DA. The non-display area NDA surrounds the display area DA. Specifically, the non-display area NDA forms an edge of the display surface. In some exemplary embodiments, the non-display area NDA may be provided only in two areas facing each other on the first direction axis DR1, or only in two areas facing each other on the second direction axis DR2. In other exemplary embodiments, the non-display area NDA may not be provided on the display surface.

[0063] A third direction axis DR3 indicates a normal direction of the display surface, for example, a thickness direction of the electronic device ED. A front surface (or an upper surface or a first surface) and a rear surface (or a lower surface or a second surface) of each component are defined to be distinguishable from each other with respect to the direction of the displayed image. Hereinafter, a first direction, a second direction, and a third direction corresponding to the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 are assigned the same reference numerals as the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3.

[0064] Referring to Figure 1, the electronic device ED may include a window WM and a display module DM. The window WM provides the front surface of the electronic device ED. The display module DM is disposed on the rear surface of the window WM and generates an image. In addition, the display module DM senses a user input, e.g., a user's touch and / or a user's pressure. The display module DM may be electrically connected to other electronic modules via a flexible circuit board or an electronic component connector.

[0065] Figure 2A is an exploded perspective view showing an electronic device ED according to an exemplary embodiment. Figure 2B is a cross-sectional view showing a display panel DP according to an exemplary embodiment. Figure 2C is a cross-sectional view showing an electronic device ED according to an exemplary embodiment. Figure 2D is a cross-sectional view showing an electronic device ED according to an exemplary embodiment.

[0066] Referring to Figure 2A , the electronic device ED includes a window WM and a display module DM. The window WM includes a substrate layer BS (refer to Figure 2C ) and a bezel layer BZL disposed on the lower surface of the substrate layer BS (refer to Figure 2C ). The area in which the bezel layer BZL is disposed is defined as the Figure 2A non-display area NDA shown in. In the illustrated exemplary embodiment, the window WM has a flat shape in the display area DA. However, the shape of the window WM may be changed in other exemplary embodiments. The edges of the window WM facing each other in the first direction DR1 may be provided with curved surfaces.

[0067] The substrate layer BS may be a glass substrate, a sapphire substrate, or a plastic substrate. The substrate layer BS may have a single-layer structure or a multi-layer structure. For example, the substrate layer BS may include a plurality of synthetic resin films bonded to each other by an adhesive. The substrate layer BS may include a glass substrate and a synthetic resin film bonded to the glass substrate by an adhesive member.

[0068] The bezel layer BZL may be directly disposed on the lower surface of the glass substrate or directly disposed on one surface of the synthetic resin film. An organic material and / or an inorganic material may be directly deposited or printed on the glass substrate to form the bezel layer BZL. The synthetic resin film on which the bezel layer BZL is formed may be attached to the lower surface of the glass substrate.

[0069] The border layer BZL can have a single-layer structure or a multi-layer structure. The multi-layer border layer BZL can include a buffer layer for improving adhesion, a pattern layer for providing a predetermined pattern, and an achromatic layer. The pattern layer can provide a pattern called a hairline. The achromatic layer can include an organic mixture containing a black pigment or dye. For example, these layers can be formed by a deposition method, a printing method, or a coating method. In some exemplary embodiments, the window WM can further include a functional coating provided on the upper surface of the substrate layer BS. For example, the functional coating can include an anti-fingerprint layer, an anti-reflection layer, and a hard coating.

[0070] Referring to Figure 2A , the display module DM can include an input sensing panel ISP, an optical sheet LS, a display panel DP, a protective film PF, a drive control module DCM, connection circuit substrates (or referred to as connection circuit boards) FCB1, FCB2, and FCB3, a lower member LM, and a stress control film SCF. In some exemplary embodiments, at least one of the optical sheet LS, the protective film PF, and the stress control film SCF can be omitted.

[0071] The display module DM can substantially form the electronic device ED. In addition, each of the input sensing panel ISP, the display panel DP, the drive control module DCM, and the connection circuit substrates FCB1, FCB2, and FCB3 can be defined as an electronic panel (or an electronic substrate).

[0072] An adhesive member can be provided between the input sensing panel ISP and the optical sheet LS, between the optical sheet LS and the display panel DP, between the display panel DP and the protective film PF, and between the protective film PF and the lower member LM. The adhesive member can include a conventional adhesive and can be provided in a sheet type or a resin type. The adhesive member can be a pressure-sensitive adhesive (PSA) film, an optically clear adhesive (OCA) film, or an optically clear resin (OCR).

[0073] The input sensing panel ISP obtains coordinate information about a user's input. The input sensing panel ISP can sense various types of inputs provided from the outside of the electronic device ED. For example, the input sensing panel ISP can sense an input from a user's body and can sense various types of external inputs (such as light, heat, or pressure). In addition, the input sensing panel ISP can sense not only an input in contact with the sensing surface but also an input occurring near the sensing surface. The input sensing panel ISP can be a capacitive touch panel or an electromagnetic induction touch panel.

[0074] Figure 2AThe optical sheet LS shown in the figure may include a polarizer and a retarder. The polarizer and the retarder may include a stretched polarizing film and a stretched retardation film, respectively. The number of retarders and the phase retardation length (λ / 4 or λ / 2) of the retarders may be determined according to the operating principle of the optical sheet LS. In an exemplary embodiment, the polarizer and the retarder may be a coated polarizing film and a coated retardation film obtained by coating a liquid crystal composition on a substrate film and aligning the liquid crystal composition, respectively. The stacking order of the optical sheet LS and the input sensing panel ISP may be interchanged.

[0075] Figure 2A The display panel DP shown in the figure may be a flexible display panel, for example, an organic light-emitting display panel. When observed in a plan view, the display panel DP includes a pixel region PXA in which pixels PX are disposed and a non-pixel region NPXA adjacent to the pixel region PXA. The pixels PX are not disposed in the non-pixel region NPXA, and peripheral components such as signal lines and insulating patterns are disposed in the non-pixel region NPXA. The pixel region PXA and the non-pixel region NPXA may correspond to a display region DA and a non-display region NDA, respectively. However, the inventive concept is not limited to the illustrated exemplary embodiments.

[0076] The pixels PX may be provided in plurality, and the pixels PX may be respectively connected to a signal line SGL. The pixel PX may include a first thin film transistor TR1, a second thin film transistor TR2, a capacitor CP, and a light-emitting element ELD.

[0077] The first thin film transistor TR1 is connected to a gate line GL and a data line DL. The light-emitting element ELD receives a power voltage provided through a power line PL. Pads (or referred to as “bond pads”) connected to the data line DL and the power line PL are disposed in the non-pixel region NPXA.

[0078] Figure 2B Schematically shows a stacked structure of the display panel DP according to an exemplary embodiment. As Figure 2B shown, the display panel DP includes a substrate layer BL, a circuit element layer CL, a display element layer LEL, and a packaging layer ECL.

[0079] The substrate layer BL may include a synthetic resin film (e.g., a polyimide (PI) film), however, the material for the substrate layer BL is not particularly limited. The circuit element layer CL is disposed on an upper surface of the substrate layer BL. The circuit element layer CL has a multi-layer structure of an insulating layer, a conductive layer, and a semiconductor layer. The circuit element layer CL includes a pixel circuit (such as the first thin film transistor TR1, the second thin film transistor TR2, and the capacitor CP) and a signal line SGL.

[0080] The display element layer LEL is disposed on the upper surface of the circuit element layer CL. The display element layer LEL may include light-emitting elements ELD, for example, organic light-emitting elements. The encapsulation layer ECL is disposed on the display element layer LEL to encapsulate the display element layer LEL. The encapsulation layer ECL may have a multi-layer structure of an inorganic layer / an organic layer / an inorganic layer and is referred to as a thin film encapsulation (TFE). The encapsulation layer ECL covers the pixel area PXA and may not be disposed on at least a part of the non-pixel area NPXA. For example, the encapsulation layer ECL may not be disposed around the bonding area and may not be disposed at the bonding area. However, in some exemplary embodiments, the encapsulation layer ECL may include only an inorganic layer or only an organic layer. The display panel DP may include an encapsulation substrate and a sealant instead of the encapsulation layer ECL. The encapsulation substrate may be bonded to the display element layer LEL by the sealant.

[0081] As Figure 2A and Figure 2B shown, the display panel DP may include three regions. Specifically, the display panel DP may include a first non-bending region (or flat region) NBA1, a bending region BA configured to bend with respect to the first non-bending region NBA1, and a second non-bending region (or opposing region) NBA2 extending from the bending region BA. In the bent state, the second non-bending region NBA2 may face the first non-bending region NBA1. The bending region BA has a predetermined curvature in the bent state.

[0082] The substrate layer BL and the circuit element layer CL may be disposed corresponding to the first non-bending region NBA1, the second non-bending region NBA2, and the bending region BA. The display element layer LEL and the encapsulation layer ECL may be disposed at least in the first non-bending region NBA1.

[0083] The shape of the display panel DP when observed in a plan view will be described in more detail based on the unfolded state of the display panel DP. The width of the display panel DP in the first direction DR1 (for example, the width in a direction substantially parallel to the bending axis BX (refer to Figure 2C and Figure 2D )) may vary according to the region. The bending region BA may have a width smaller than the width of the first non-bending region NBA1. Since the bending region BA has a relatively small width, the bending region BA can be easily bent.

[0084] The bending region BA includes a region where the width of the bending region BA in the first direction DR1 gradually decreases as the distance from the first non-bending region NBA1 increases. However, in some exemplary embodiments, the width of the bending region BA may be uniform.

[0085] Refer to Figure 2A and Figure 2B, a protective film PF is disposed on the lower surface of the display panel DP. In the illustrated exemplary embodiment, the protective film PF may include a first protective film PF1 and a second protective film PF2 that are disposed to be spaced apart from each other.

[0086] The protective film PF may include a synthetic resin film as its base film. The protective film PF may include a synthetic resin film containing at least one of polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), poly(arylene ether sulfone), and combinations thereof.

[0087] The material for the protective film PF is not particularly limited to plastic resins, and in some exemplary embodiments, the material for the protective film PF may include an organic / inorganic composite material. For example, the protective film PF may include a porous organic layer and an inorganic material filled in the pores of the porous organic layer.

[0088] The display panel DP and the protective film PF may be bonded to each other by an adhesive member (hereinafter referred to as the "fourth adhesive member") AM4. The fourth adhesive member AM4 may include a first adhesive portion AM4-1 and a second adhesive portion AM4-2 corresponding to the first protective film PF1 and the second protective film PF2, respectively.

[0089] As Figure 2A shown, the driving control module DCM may include a first circuit board (or driving circuit board) MCB, a second circuit board FCB connecting the first circuit board MCB to the display panel DP, and a driving chip F-IC mounted on the second circuit board FCB. In some exemplary embodiments, a plurality of passive devices and a plurality of active devices may be mounted on the first circuit board MCB. The first circuit board MCB may be a rigid circuit board or a flexible circuit board, and the second circuit board FCB may be a flexible circuit board.

[0090] In some exemplary embodiments, the driving chip F-IC may be omitted from the driving control module DCM. In this case, the driving control module DCM may be mounted on the display panel DP.

[0091] In the illustrated exemplary embodiment, the driving chip of the input sensing panel ISP may be mounted on the first circuit board MCB. Connecting circuit boards FCB1, FCB2, and FCB3 may be connected to the first circuit board MCB. In addition, the first circuit board MCB may be electrically connected to other electronic modules via an electronic component connector.

[0092] The lower member LM may be disposed on the lower surface of the protective film PF and may include a support panel or a pressure sensing sensor. The support panel is disposed on the lower surface of the protective film PF to support the display panel DP and the protective film PF. The support panel may be a metal plate having a rigidity greater than a reference value. For example, the support panel may be a stainless steel plate. The support panel may have a black color to block external light from traveling to the display panel DP.

[0093] The pressure sensing sensor may sense an external pressure applied to the display module DM. The pressure sensing sensor may include a substrate layer, a piezoelectric element, and a signal line connected to the piezoelectric element.

[0094] Referring Figure 2A and Figure 2B and, the display module DM may further include a stress control film SCF disposed on the circuit element layer to correspond to at least the bending region BA. Approximately 50% or more of the entire area of the stress control film SCF may be disposed in the bending region BA. A part of the stress control film SCF may overlap with the first non-bending region NBA1 and the second non-bending region NBA2. The stress control film SCF may include a synthetic resin film. One of the synthetic resin films for the above protective film PF may be applied to the stress control film SCF.

[0095] The stress control film SCF may be bonded to the display panel DP by an adhesive, or may be formed by coating a synthetic resin on the display panel DP and curing the synthetic resin.

[0096] Figure 2C and Figure 2D Exemplarily shown are cross-sections of the electronic device ED that intersect the first connection circuit board FCB1 and the second connection circuit board FCB2 and correspond to a cutting plane substantially parallel to the second direction DR2. The first connection circuit board FCB1 is bonded to the front surface of the input sensing panel ISP, and the second connection circuit board FCB2 is bonded to the rear surface of the input sensing panel ISP.

[0097] As Figure 2C and Figure 2D shown in, an adhesive member AM1 is disposed between the input sensing panel ISP and the window WM, an adhesive member AM2 is disposed between the input sensing panel ISP and the optical sheet LS, an adhesive member AM3 is disposed between the optical sheet LS and the display panel DP, an adhesive member AM4 is disposed between the display panel DP and the protective film PF, and an adhesive member AM5 is disposed between the protective film PF and the lower member LM. In addition, an adhesive member AM6 is disposed between the second protective film PF2 and the lower member LM, and an adhesive member AM7 is further disposed between the first circuit board MCB and the lower member LM.

[0098] The bonding member AM6 can be used as a spacer for maintaining the radius of curvature and the gap between the second protective film PF2 and the lower member LM. Most regions of the stress control film SCF are bent together with the bending region BA of the display panel DP with respect to the bending axis BX.

[0099] Figure 3A It is a cross-sectional view showing an input sensing panel ISP according to an exemplary embodiment. Figure 3B It is a plan view showing an input sensing panel ISP according to an exemplary embodiment. Figure 3C It is an enlarged plan view showing a bonding area AA of an input sensing panel ISP according to an exemplary embodiment. Figures 3D to 3G It is a cross-sectional view showing an input sensing panel ISP according to an exemplary embodiment. Figure 3H It is an enlarged plan view showing a bonding area AA of an input sensing panel ISP according to an exemplary embodiment.

[0100] Referring to Figure 3A , the input sensing panel ISP may include a substrate layer IS-B, a first conductive layer IS-CL1, a first insulating layer IS-IL1, a second conductive layer IS-CL2, and a second insulating layer IS-IL2. The first conductive layer IS-CL1 and the first insulating layer IS-IL1 may be disposed on one surface of the substrate layer IS-B, and the second conductive layer IS-CL2 and the second insulating layer IS-IL2 may be disposed on the other surface of the substrate layer IS-B.

[0101] The substrate layer IS-B may include a glass substrate or a synthetic resin film. Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may have a single-layer structure, or may have a multi-layer structure of layers stacked along a third direction DR3. The multi-layer conductive layer may include at least two of a transparent conductive layer and a metal layer. The multi-layer conductive layer may include metal layers containing different metal materials from each other. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, or graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum, and their alloys. For example, each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may have a two-layer structure of ITO / copper. As another example, each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may have a three-layer structure of titanium / aluminum / titanium.

[0102] Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may include a plurality of conductive patterns. Hereinafter, the first conductive layer IS-CL1 will be described as including first conductive patterns, and the second conductive layer IS-CL2 will be described as including second conductive patterns. Each of the first conductive patterns and the second conductive patterns may include input sensing electrodes and signal lines connected to the input sensing electrodes.

[0103] Each of the first insulating layer IS-IL1 and the second insulating layer IS-IL2 may include an inorganic layer and / or an organic layer. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, silicone resin, polyimide resin, polyamide resin, and perylene resin. In the illustrated exemplary embodiment, each of the first insulating layer IS-IL1 and the second insulating layer IS-IL2 may be an organic layer. However, the inventive concept is not limited thereto.

[0104] As Figure 3B shown, the input sensing panel ISP may include a sensing region IS-DA and a line region IS-NDA corresponding to a display region DA (refer to Figure 1 ) and a non-display region NDA (refer to Figure 1 ), respectively. The size and shape of the sensing region IS-DA may match the size and shape of the display region DA (refer to Figure 1 ) or may be different from the size and shape of the display region DA (refer to Figure 1 ).

[0105] The input sensing panel ISP may include a first electrode group EG1, a second electrode group EG2, a first signal line group SG1 connected to a part of the first electrode group EG1, a second signal line group SG2 connected to another part of the first electrode group EG1, and a third signal line group SG3 connected to the second electrode group EG2.

[0106] According to an exemplary embodiment, among the electrodes IE1-1 to IE1-10 of the first electrode group EG1, the odd-numbered electrodes may be connected to the first signal line group SG1, and the even-numbered electrodes may be connected to the second signal line group SG2. Each of the electrodes IE1-1 to IE1-10 of the first electrode group EG1 includes a plurality of first sensor portions SP1 and a plurality of first connection portions CP1. Each of the electrodes IE2-1 to IE2-8 of the second electrode group EG2 includes a plurality of second sensor portions SP2 and a plurality of second connection portions CP2. The shapes of the electrodes IE1-1 to IE1-10 of the first electrode group EG1 and the electrodes IE2-1 to IE2-8 of the second electrode group EG2 are not particularly limited.

[0107] The first electrode group EG1, the first signal line group SG1, and the second signal line group SG2 may be formed of Figure 3A the first conductive layer IS-CL1. The second electrode group EG2 and the third signal line group SG3 may be formed of Figure 3A the second conductive layer IS-CL2. More specifically, the first electrode group EG1, the first signal line group SG1, and the second signal line group SG2 may be provided on different layers from the second electrode group EG2 and the third signal line group SG3.

[0108] The electrode group and the corresponding signal line group may have different stacking structures from each other. For example, the electrode group may include a transparent conductive layer having an ITO single-layer structure, and the signal line group may include a transparent conductive layer and a metal layer provided on the transparent conductive layer.

[0109] Figure 3B The first pad PD1 to the third pad PD3 shown in

[0110] may respectively include the ends of the signal lines of the first signal line group SG1 to the third signal line group SG3. The first pad PD1 to the third pad PD3 may also include conductive patterns formed on the ends of the signal lines through an additional process.

[0110] As Figure 2A , Figure 2C and Figure 2D shown, the first connection circuit board FCB1 and the third connection circuit board FCB3 are connected to the upper surface of the input sensing panel ISP. The first connection circuit board FCB1 and the third connection circuit board FCB3 may be respectively connected to Figure 3B the first pad PD1 and the second pad PD2. In some exemplary embodiments, the first connection circuit board FCB1 and the third connection circuit board FCB3 may be replaced with one connection circuit board connected to the first pad PD1 and the second pad PD2.

[0111] The second connection circuit board FCB2 is connected to the lower surface of the input sensing panel ISP. The second connection circuit board FCB2 may be connected to Figure 3BThe third pad PD3. The position of the bonding region of the input sensing panel ISP (front connection position or bottom connection position) can be determined according to the positions of the first pad PD1 to the third pad PD3 relative to the substrate layer IS-B. In the illustrated exemplary embodiment, when viewed in a plan view, the three bonding regions are spaced apart from each other.

[0112] Figure 3C There is shown a bonding region AA having Figure 2A and Figure 3B the shape shown in Figure 3D There is shown a bonding region AA having Figure 3B the shape shown in Figure 3D Specifically, Figure 3C is a cross-sectional view taken along line I-I' of

[0113] Referring to Figure 3C and Figure 3D , the end portion PP of each signal line SL is exposed and not covered by the first insulating layer IS-IL1. In the illustrated exemplary embodiment, the end portion PP and the line portion LP of the signal line SL have different line widths from each other to distinguish them, however, the inventive concept is not limited thereto. In some exemplary embodiments, the line width of the signal line SL may be substantially constant. In the illustrated exemplary embodiment, the end portion PP of the signal line SL corresponds to Figure 3B the first pad PD1 shown in

[0114] When viewed in a plan view, an opening region OA is defined in the first insulating layer IS-IL1 to expose some regions IS-BA of the substrate layer IS-B. The opening edge OE corresponds to the portion of the edge of the first insulating layer IS-IL1 that defines the opening region OA. When viewed in a plan view, the opening region OA extends to the edge IS-BE of the substrate layer IS-B. The opening edge OE is in contact with the signal line SL. As will be described in more detail later, the edge region IL1-EA is in contact with the substrate layer IS-B.

[0115] In the illustrated exemplary embodiment, when viewed in a plan view, the first connection circuit board FCB1 may completely cover the opening region OA. The anisotropic conductive material ACF electrically connects the exposed end portion PP of the signal line SL to the pad of the first connection circuit board FCB1. The pads of the signal lines connected to the first circuit board MCB (refer to Figure 2A ) are provided in the first connection circuit board FCB1 to correspond to the end portion PP of the signal line SL.

[0116] Referring to Figure 3D, the first thickness TH1 of the first insulating layer IS-IL1 measured at a first point P1 spaced apart from the opening edge OE is smaller than the second thickness TH2 of the first insulating layer IS-IL1 measured at a second point P2 farther from the opening edge OE than the first point P1. The distances of the first point P1 and the second point P2 from the opening edge OE are measured along the second direction DR2.

[0117] The first point P1 and the second point P2 may be provided in the edge region IL1-EA of the first insulating layer IS-IL1. The edge region IL1-EA is defined along the opening edge OE, and the thickness of the first insulating layer IS-IL1 varies along the second direction DR2 in the edge region IL1-EA. For example, the thickness of the edge region IL1-EA may gradually decrease along the second direction DR2 as the distance to the opening edge OE decreases. Thus, the thickness of the first insulating layer IS-IL1 gradually decreases from the second point P2 to the opening edge OE.

[0118] A region where the thickness of the first insulating layer IS-IL1 does not change in the second direction DR2 may be defined as the covering region IL1-CA. A third point P3 farther from the opening edge OE than the second point P2 may be provided in the covering region IL1-CA of the first insulating layer IS-IL1.

[0119] Figure 3E and Figure 3F shows a first insulating layer IS-IL1 according to an exemplary embodiment, each of the first insulating layers IS-IL1 having a cross-section different from that of the Figure 3D first insulating layer IS-IL1. Figure 3E and Figure 3F The first insulating layer IS-IL1 shown in also has a thickness that varies from the first point P1 to the third point P3. As Figure 3E shown, the edge region IL1-EA of the first insulating layer IS-IL1 according to the shown exemplary embodiment may have a curved profile. As Figure 3F shown, the edge region IL1-EA of the first insulating layer IS-IL1 according to the shown exemplary embodiment may have a curved profile with an inflection point.

[0120] Referring to Figure 3G , the first insulating layer IS-IL1 provided in the edge region IL1-EA has a thickness smaller than that of the first insulating layer IS-IL1 provided in the covering region IL1-CA. Thus, a step difference is defined between the third point P3 and the first point P1. The step difference may be formed by two insulating layers. Two insulating layers may be provided in the covering region IL1-CA, and one insulating layer may be provided in the edge region IL1-EA. The step difference may be formed in a stepped manner toward the opening edge OE in the edge region IL1-EA.

[0121] Figures 3C to 3G The bonding region AA of the first pad PD1 is shown. However, the above features can be equivalently applied to the bonding regions of the second pad PD2 and the third pad PD3. For example, the bonding region of the second pad PD2 can be substantially the same as the bonding region AA of the first pad PD1.

[0122] The structure of the bonding region of the third pad PD3 can be substantially the same as the structure obtained by flipping the bonding region AA of the first pad PD1 upside down. Specifically, the cross-sectional structure of the bonding region of the third pad PD3 can be the same as the cross-sectional structure obtained by flipping the Figures 3D to 3G cross-sectional structure shown in it upside down.

[0123] Two points having the same conditions as the first point P1 and the second point P2 of the first insulating layer IS-IL1 can be defined in the second insulating layer IS-IL2. Referring to Figure 3B and Figure 3C , two opening regions (e.g., the opening region OA provided in the bonding region AA of the first pad PD1 and the opening region provided in the bonding region of the second pad PD2) are defined in the first insulating layer IS-IL1, and one opening region (e.g., the opening region provided in the bonding region of the third pad PD3) is defined in the second insulating layer IS-IL2. When observed in a plan view, the three opening regions do not overlap each other.

[0124] As Figure 3H shown, when observed in a plan view, the opening edge OE can form a closed line. The cross-sectional shape of the first insulating layer IS-IL1 intercepted along one direction with respect to the opening edge OE can be substantially the same as one of the cross-sectional shapes of the first insulating layer IS-IL1 shown in Figures 3D to 3G .

[0125] Figure 4A and Figure 4B are cross-sectional views showing the bonding process of the electronic device ED according to a comparative embodiment. Figure 4C and Figure 4D are cross-sectional views showing the bonding process of the electronic device ED according to an exemplary embodiment. Figure 4C and Figure 4D Exemplarily shows the Figure 3D insulating layer.

[0126] Referring to Figure 4A and Figure 4B, a pressing tool BT is used in the bonding process of the input sensing panel ISP and the first connection circuit board FCB1. An anisotropic conductive material ACF is provided between the bonding area AA of the input sensing panel ISP and the bonding area of the first connection circuit board FCB1. The anisotropic conductive material ACF can be provided after the anisotropic conductive material ACF is provided on one of the bonding area AA of the input sensing panel ISP and the bonding area of the first connection circuit board FCB1.

[0127] According to the comparative example, the edge region IL1-EA of the first insulating layer IS-IL1 may have an inverted conical shape. This is because the upper part of the first insulating layer IS-IL1 covered by the mask is developed relatively less during the patterning of the first insulating layer IS-IL1.

[0128] Since the edge region IL1-EA of the first insulating layer IS-IL1 is pressed by the pressing tool BT or the first connection circuit board FCB1 during the bonding process, cracks CR are generated in the first insulating layer IS-IL1. In this case, when moisture penetrates through the cracks CR, the signal line SL is corroded.

[0129] According to Figure 4C and Figure 4D , the edge region IL1-EA of the first insulating layer IS-IL1 according to the exemplary embodiment may not have an inverted conical shape. In other words, in the exemplary embodiment, the edge region IL1-EA of the first insulating layer IS-IL1 may be in contact with the signal line SL and / or the base layer IS-B, and no gap is formed between the edge region IL1-EA of the first insulating layer IS-IL1 and the signal line SL and / or the base layer IS-B. In this case, when the edge region IL1-EA of the first insulating layer IS-IL1 is directly pressed by the pressing tool BT or the first connection circuit board FCB1, the signal line SL and / or the base layer IS-B can support the edge region IL1-EA of the first insulating layer IS-IL1. Therefore, cracks CR in the first insulating layer IS-IL1 can be prevented from being generated.

[0130] In the process of patterning the first insulating layer IS-IL1, the upper region (for example, some regions defined in the thickness direction) of the edge region IL1-EA of the first insulating layer IS-IL1 is developed. For example, the upper region of the edge region IL1-EA of the first insulating layer IS-IL1 can be partially removed by exposing and developing the upper region where the completely removed region of the first insulating layer IS-IL1 is relatively small.

[0131] Figure 5A is a cross-sectional view showing a display module DM according to an exemplary embodiment. Figure 5Bis an enlarged cross-sectional view showing a display module DM according to an exemplary embodiment. Figure 5C is a plan view showing a display panel DP according to an exemplary embodiment. Figure 5D is a plan view showing an input sensor ISL according to an exemplary embodiment.

[0132] Figure 5A The display module DM shown in Figure 2B includes the display panel DP shown in Figure 3A and an input sensor ISL directly disposed on the display panel DP. As used herein, the expression "the input sensor ISL is directly disposed on the display panel DP" may mean that no adhesive layer is disposed between the input sensor ISL and the display panel DP. The input sensor ISL is formed on a substrate surface provided by the display panel DP through a continuous process. Different from the above-described input sensing panel ISP (refer to Figure 3A ), according to the shown exemplary embodiment, the substrate layer IS-B (refer to ) may be omitted from the laminated input sensor ISL.

[0133] Figure 5A Figure 2A The display module DM shown in

[0134] is electrically connected to the drive control module DCM shown in Figure 5B . The display module DM and the drive control module DCM may form an electronic device ED.

[0135] Figure 5C As shown in Figure 2A , the display panel DP according to the shown exemplary embodiment includes a substrate layer BL, a circuit element layer CL, a display element layer LEL, and a packaging layer ECL. The input sensor ISL is directly disposed on a substrate surface provided by the packaging layer ECL. The input sensor ISL may include a first insulating layer ISL-IL1, a first conductive layer ISL-CL1, a second insulating layer ISL-IL2, a second conductive layer ISL-CL2, and a third insulating layer ISL-IL3. The first insulating layer ISL-IL1 may be in contact with the packaging layer ECL. In some exemplary embodiments, the first insulating layer ISL-IL1 may be omitted.

[0135] Figure 5C As shown in Figure 2A , the display panel DP according to the shown exemplary embodiment includes a substrate layer BL, a circuit element layer CL, a display element layer LEL, and a packaging layer ECL. The input sensor ISL is directly disposed on a substrate surface provided by the packaging layer ECL. The input sensor ISL may include a first insulating layer ISL-IL1, a first conductive layer ISL-CL1, a second insulating layer ISL-IL2, a second conductive layer ISL-CL2, and a third insulating layer ISL-IL3. The first insulating layer ISL-IL1 may be in contact with the packaging layer ECL. In some exemplary embodiments, the first insulating layer ISL-IL1 may be omitted. Figure 5C shows a display panel DP that is partially different from the display panel DP shown in Figure 2A . Hereinafter, the features in which the display panel DP shown in Figure 2A differ from the display panel DP shown in Figure 5C will be mainly described. In some exemplary embodiments, the display panel DP shown in

[0136] The driving circuit GDC may be disposed in the non-pixel area NPXA. The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate gate signals. The gate driving circuit may include a plurality of transistors, and the plurality of transistors may be formed by the same process as the driving circuit for forming the pixel PX (e.g., low temperature polycrystalline silicon (LTPS) process or low temperature polycrystalline oxide (LTPO) process).

[0137] The signal line SGL may further include a control signal line CSL and an auxiliary signal line SSL. The control signal line CSL may apply a control signal to the driving circuit GDC. The auxiliary signal line SSL may be a signal line connected to the input sensor ISL.

[0138] The signal line SGL may include a plurality of portions disposed on different layers from each other. Figure 5C Exemplarily, a data line DL including four portions PT1 to PT4 and an auxiliary signal line SSL including two portions PT10 and PT20 are shown. The four portions PT1 to PT4 are connected to each other through contact holes CNT, and the two portions PT10 and PT20 are connected to each other through contact holes CNT. The first portion PT10 of the auxiliary signal line SSL is connected to signal line groups SG1 and SG2 of the input sensor ISL to be described later through contact holes CNT (refer to Figure 5D ). One portion PT3 of the data line DL and the first portion PT10 of the auxiliary signal line SSL may be disposed in the bending area BA. Similarly, the control signal line CSL may include three portions connected to each other through contact holes CNT, and the power line PL may include four portions connected to each other through contact holes CNT.

[0139] Unlike Figure 2A , as Figure 5C shows, the display panel DP and the driving control module DCM according to the shown exemplary embodiment are separated from each other. In Figure 5C , an anisotropic conductive material ACF for electrically connecting the display panel DP and the circuit board FCB is shown. The driving chip F-IC may include a timing control circuit TC and an input sensing circuit ISL-C.

[0140] As Figure 5D shows, the input sensor ISL includes a first electrode group EG1, a second electrode group EG2, and a signal line group connected to the first electrode group EG1 and the second electrode group EG2. In the shown exemplary embodiment, the input sensor ISL is exemplarily shown as including two signal line groups SG1 and SG2. The input sensor ISL includes a sensing area ISL-DA and a line area ISL-NDA.

[0141] The signal lines of the first signal line group SG1 and the signal lines of the second signal line group SG2 can be connected to the auxiliary signal line SSL through the contact holes CNT (refer to Figure 5C ). The contact holes CNT pass through the insulating layer provided between the signal lines of the first signal line group SG1 and the second signal line group SG2 and the auxiliary signal line SSL.

[0142] Figure 5C A plurality of pads DP-PD and ISL-PD are shown. The first pad DP-PD is connected to the pixel PX, and the second pad ISL-PD is connected to the first electrode group EG1 and the second electrode group EG2 through the auxiliary signal line SSL. The first pad DP-PD includes the ends of the data line DL, the control signal line CSL, and the power line PL, and the second pad ISL-PD includes the end of the auxiliary signal line SSL. In addition, a plurality of pads can be provided in the pad region PCB-P of the second circuit board FCB and can be connected to the corresponding pads DP-PD or ISL-PD among the pads DP-PD and ISL-PD through the anisotropic conductive material ACF to electrically connect the drive control module DCM to the display panel DP.

[0143] Figure 5C The two bonding regions BB shown in Figures 6A to 6C can be substantially the same as each other. Hereinafter, the bonding region BB will be described in detail with reference to

[0144] Figure 6A is an enlarged plan view showing the bonding region BB of the display panel DP according to an exemplary embodiment. Figure 6B and Figure 6C are cross-sectional views showing the bonding region BB of the display panel DP according to an exemplary embodiment. In Figure 6A , the size of the anisotropic conductive material ACF and the size of the circuit board FCB are shown to be smaller than the size of the anisotropic conductive material ACF and the size of the circuit board FCB in Figure 5C .

[0145] Figure 6A The bonding region BB shown in Figure 3C can be substantially the same as the bonding region AA shown in Figure 6A An opening region OA extending to the edge DP-E of the display panel DP is exemplarily shown.

[0146] However, the cross-sectional structure of the bonding region BB can be partially different from the cross-sectional structure of the bonding region AA in Figure 3D . The insulating layer ISL-IL is shown to have a cross-sectional shape corresponding to the cross-sectional shape of the first insulating layer IS-IL1 in Figure 3D , however, the inventive concept is not limited thereto. For example, in some exemplary embodiments, the insulating layer ISL-IL can have a cross-sectional shape corresponding to Figures 3E to 3GThe cross-sectional shape of the first insulating layer IS-IL1 shown in any one of the figures is substantially the same cross-sectional shape.

[0147] Figure 6A The signal line SL shown in can be Figure 5C the data line DL, the control signal line CSL, the power line PL, or the auxiliary signal line SSL shown in, and can be disposed on the substrate surface provided by the display panel DP. As Figure 6B shown, the signal line SL can be disposed on the plurality of insulating layers 10 to 30 of the display element layer LEL. At least one of the insulating layers 10 to 30 can be Figure 5C superposed on the pixel region PXA and the non-pixel region NPXA shown in.

[0148] The insulating layer ISL-IL that covers the signal line SL and exposes the end portion PP of the signal line SL can be one of the first insulating layer ISL-IL1, the second insulating layer ISL-IL2, and the third insulating layer ISL-IL3 described above with reference to Figure 5B . For example, in the exemplary embodiment shown, the insulating layer ISL-IL can be the first insulating layer ISL-IL1. In the exemplary embodiment shown, the insulating layer ISL-IL can include an organic layer.

[0149] Referring to Figure 5D and Figure 6B , the insulating layer ISL-IL can be in contact with the signal line SL in the line region ISL-NDA and can be in contact with the input sensing electrodes in the first electrode group EG1 and the second electrode group EG2 in the sensing region ISL-DA.

[0150] Referring to Figure 6C , according to another exemplary embodiment, the edge region IL-EA of the insulating layer ISL-IL can be formed by a step difference between the insulating layers ISL-IL1, ISL-IL2, and ISL-IL3. The covering region IL-CA can be defined as the region where the insulating layers ISL-IL1, ISL-IL2, and ISL-IL3 are superposed on each other.

[0151] Figure 7A is an enlarged plan view showing the bonding region CC of the electronic panel according to an exemplary embodiment. Figure 7B and Figure 7C are cross-sectional views showing the bonding region CC of the electronic panel according to an exemplary embodiment. Figures 8A to 8C is a cross-sectional view showing the bonding region CC of the electronic panel according to an exemplary embodiment.

[0152] The bonding region CC can be applied to Figure 3B the bonding region AA of or Figure 5C one of the bonding regions BB of.Figures 7B to 8C Relative to the Figure 3B and Figure 3C The cross-section corresponding to the cross-section exemplarily shows the bonding region CC.

[0153] Referring to Figure 7A , the opening region OA has widths W1 and W2 according to its region. The widths W1 and W2 are lengths in the second direction DR2 corresponding to the extending direction of the signal line SL. The widths W1 and W2 of the extending opening region OA are substantially the same as the lengths from the edge IS-BE of the base layer IS-B to the opening edge OE in the second direction DR2. Figure 3H The width of the closed opening region OA shown in

[0154] is substantially the same as the length between two points on the opening edge OE facing each other in the second direction DR2. The opening region OA includes a first region OA1 having a first width W1 and a second region OA2 having a second width W2 smaller than the first width W1. The first region OA1 is provided in a plurality to correspond to the signal line SL. The second region OA2 is provided between two adjacent first regions OA1.

[0155] The first connection circuit board FCB1 is stacked on the first region OA1 and the second region OA2. The anisotropic conductive material ACF is provided between the first connection circuit board FCB1 and the opening region OA. The first connection circuit board FCB1 does not overlap with a part of the first region OA1. In the bonding process described with reference to Figures 4A to 4D , the region where the maximum stress is applied to the first insulating layer IS-IL1 is the region corresponding to the edge of the first connection circuit board FCB1. Specifically, the region where the maximum stress is applied to the first insulating layer IS-IL1 is the region overlapping with the signal line SL corresponding to the edge of the first connection circuit board FCB1. According to the exemplary embodiment shown, the first insulating layer IS-IL1 is not provided in the region corresponding to the region where the edge of the first connection circuit board FCB1 and the signal line SL overlap each other. In this way, cracks CR generated in the first insulating layer IS-IL1 during the bonding process can be prevented or at least suppressed (refer to Figure 4B ).

[0156] Since the signal line SL is not provided in the second region OA2, the stress applied to the second region OA2 can be distributed by the base layer IS-B. Due to the second region OA2, the non-overlapping region between the first insulating layer IS-IL1 and the first connection circuit board FCB1 can be reduced.

[0157] Referring to Figure 7B and Figure 7C, even if the edge region IL1-EA has an inverted conical shape, cracks CR in the first insulating layer IS-IL1 can be prevented because the edge region IL1-EA is not directly pressed by the first connection circuit board FCB1 (refer to Figure 4B ).

[0158] As Figure 7C shown, the anisotropic conductive material ACF can be disposed in a portion of the first region OA1 that does not overlap with the first connection circuit board FCB1. The anisotropic conductive material ACF can cover the exposed portion of the signal line SL. When observed in a plan view, the anisotropic conductive material ACF can completely cover Figure 7A the opening region OA shown in

[0159] Refer to Figures 8A to 8C , the edge region IL1-EA has a cross-sectional shape that is substantially the same as the cross-sectional shape of the edge region IL1-EA shown in Figure 3D . However, in some exemplary embodiments, the edge region IL1-EA can have a cross-sectional shape that is substantially the same as the cross-sectional shape of the edge region IL1-EA shown in any one of the figures in Figures 3E to 3G . As Figure 8C shown, the first connection circuit board FCB1 can completely cover the first region OA1.

[0160] Figure 9A And Figure 9B are enlarged plan views showing the bonding region CC of an electronic panel according to an exemplary embodiment. Hereinafter, repeated descriptions of elements that are the same as those described with reference to Figures 7A to 8C will be omitted.

[0161] Refer to Figure 9A , a portion of the opening edge OE that defines the first region OA1 can have a curved shape. Refer to Figure 9B , a portion of the opening edge OE that defines the first region OA1 can have a serrated shape.

[0162] According to an exemplary embodiment, cracks can be prevented from occurring in a region of the insulating layer adjacent to the edge of the insulating layer by controlling the thickness of the region of the insulating layer adjacent to the edge of the insulating layer. Even if a pressing tool is used in the process of bonding the electronic panel and pressure is applied to the insulating layer, cracks can be prevented or at least suppressed from occurring. In this way, the signal line can be prevented from being corroded.

[0163] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments, but rather to the claims and the broader scope of various obvious modifications and equivalent arrangements that will be apparent to those of ordinary skill in the art.

Claims

1. An electronic panel, the electronic panel comprising: A substrate layer; An input sensing electrode disposed on the substrate layer; A signal line disposed on the substrate layer, electrically connected to the input sensing electrode, and including a line portion and an end portion, wherein the line portion has a line width smaller than that of the end portion, and the line portion is disposed between the input sensing electrode and the end portion; and An insulating layer disposed on the substrate layer, and including an opening edge in contact with the line portion and defining an opening region, when viewed in a plan view, the opening region exposes a part of the substrate layer, a part of the line portion, and the end portion, Wherein, the opening region is a region surrounded by the opening edge where the insulating layer is not provided, and Wherein, the insulating layer has a first thickness at a first point spaced apart from the opening edge, and has a second thickness at a second point disposed farther from the opening edge than the first point, the second thickness being larger than the first thickness.

2. The electronic panel according to claim 1, wherein, The thickness of the insulating layer gradually decreases from the second point to the opening edge.

3. The electronic panel according to claim 1, wherein, The insulating layer has a step between the second point and the opening edge.

4. The electronic panel according to claim 1, wherein, The insulating layer includes an organic layer in contact with the signal line.

5. The electronic panel according to claim 1, wherein: The signal line includes a first signal line and a second signal line, the first signal line is disposed on a first surface of the substrate layer, and the second signal line is disposed on a second surface of the substrate layer opposite to the first surface; The insulating layer includes: A first insulating layer disposed on the first surface of the substrate layer, stacked with the first signal line, and defining a first opening region exposing a part of the substrate layer and an end portion of the first signal line; and A second insulating layer disposed on the second surface of the substrate layer, stacked with the second signal line, and defining a second opening region exposing another part of the substrate layer and an end portion of the second signal line; and When viewed in a plan view, the first opening region of the first insulating layer does not overlap with the second opening region of the second insulating layer.

6. The electronic panel according to claim 1, the electronic panel further comprising a pixel electrically connected to the signal line.

7. The electronic panel according to claim 6, wherein, The pixel includes a light emitting diode.

8. The electronic panel according to claim 1, the electronic panel further comprising: A circuit element layer disposed on the substrate layer, and including a transistor; A display element layer disposed on the circuit element layer, and including a light emitting diode; A packaging layer disposed on the display element layer, Wherein, the input sensing electrode is disposed on the packaging layer.

9. The electronic panel according to claim 1, wherein, When viewed in a plan view, the opening region extends to an edge of the substrate layer.

10. An electronic panel, the electronic panel comprising: A substrate layer; An input sensing electrode disposed on the substrate layer; A signal line disposed on the substrate layer, electrically connected to the input sensing electrode, and including a line portion and an end portion, wherein the line portion has a line width smaller than that of the end portion, and the line portion is disposed between the input sensing electrode and the end portion; and An insulating layer is disposed on the substrate layer and has a covering region and an edge region. The insulating layer includes an opening edge that contacts the wire portion and defines an opening region. When observed in a plan view, the opening region exposes a part of the substrate layer, a part of the wire portion, and the end portion. wherein the opening region is a region that does not have the insulating layer disposed therein and is surrounded by the opening edge, and wherein the thickness of the insulating layer is constant in the covering region and gradually decreases toward the opening edge in the edge region.

11. An electronic device, the electronic device comprising: a first electronic panel; and a second electronic panel electrically connected to the first electronic panel. The first electronic panel includes: a substrate layer; a signal line disposed on the substrate layer; and an insulating layer disposed on the substrate layer and including an opening edge that contacts the signal line and defines an opening region. When observed in a plan view, the opening region exposes an edge of the substrate layer, a part of the substrate layer extending from the edge of the substrate layer, and an end portion of the signal line. wherein the opening region is a region that does not have the insulating layer disposed therein and is surrounded by the opening edge, and wherein a first width of a region of the opening region that overlaps with the signal line is larger than a second width of a region of the opening region that does not overlap with the signal line.

12. The electronic device according to claim 11, wherein, The second electronic panel includes a circuit board.

13. The electronic device according to claim 12, wherein: the opening region includes a first region having the first width and a second region having the second width; and the circuit board overlaps with the first region and the second region and does not overlap with a first part of the first region.

14. The electronic device according to claim 13, the electronic device further comprising an anisotropic conductive material disposed between the end portion of the signal line and the circuit board.

15. The electronic device according to claim 14, wherein, The anisotropic conductive material overlaps with the first part of the first region.

16. The electronic device according to claim 11, wherein, The insulating layer has a first thickness at a first point spaced apart from the opening edge and a second thickness at a second point disposed farther from the opening edge than the first point, and the second thickness is larger than the first thickness.

17. The electronic device according to claim 11, wherein, The first electronic panel further includes an input sensing electrode connected to the signal line.

18. The electronic device according to claim 11, wherein, The first electronic panel further includes a pixel electrically connected to the signal line.

19. The electronic device according to claim 11, wherein, The first electronic panel further includes: a circuit element layer disposed on the substrate layer and including transistors; a display element layer disposed on the circuit element layer and including light emitting diodes; a thin film encapsulation layer disposed on the display element layer; and an input sensing electrode disposed on the thin film encapsulation layer and electrically connected to the signal line.

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