Word line modulation circuit

Abstract

This invention provides a word line modulation circuit. The word line modulation circuit includes at least one inverter, a power switch circuit, at least one first capacitor, and at least one second capacitor. The inverter is coupled to a word line and an inverted word line to receive an inverted word line signal and generate a word line signal, and is coupled to the first capacitor via the word line. The power switch circuit is coupled to the inverter and is used to receive a power switch control signal. The second capacitor is coupled to the inverter and the power switch circuit at an internal node and is used to receive a boost signal.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application generally relate to word line modulation circuit technology, and more particularly to word line modulation circuit technology for implementing a charging sharing (CS)-word line under-driving (WLUD) mechanism and a capacitive coupling (CC)-word line over-driving (WLOD) mechanism by a word line modulation circuit. BACKGROUND

[0002] Using read / write assist techniques is an important means to improve the yield of storage devices under advanced processes. For example, using a read assist technique can improve the access disturb margin (ADM) to reduce the probability of read damage, and using a write assist technique can improve the write margin (WM) to reduce the probability of write failure.

[0003] Among various assist techniques, word line modulation is a commonly used method. Word line modulation can include word line under-driving (WLUD) and word line over-driving (WLOD), the principle of which is to control the driving capability of the pass gate transistor in the bit cell (or referred to as "bit cell") of the storage device.

[0004] However, the conventional use of word line under-driving (WLUD) and the use of word line over-driving (WLOD) need to configure a DC voltage dividing circuit on the chip, or increase the external power supply to achieve. Therefore, the area and power consumption of the storage device will be increased. SUMMARY

[0005] In view of the above problems of the prior art, embodiments of the present application provide a word line modulation circuit, a method of a charging sharing-word line under-driving mechanism, and a method of a capacitive coupling-word line over-driving mechanism.

[0006] A word line modulation circuit is provided according to an embodiment of the present invention. The word line modulation circuit includes at least one inverter, a power switch circuit, at least one first capacitor, and at least one second capacitor. The inverter is coupled to a word line and an inverted word line to receive an inverted word line signal and generate a word line signal, and coupled to a first capacitor via the word line. The power switch circuit is coupled to the inverter to receive a power switch control signal. The second capacitor is coupled to the inverter and the power switch circuit at an internal node to receive a boosted signal.

[0007] According to an embodiment of the present invention, the inverter includes a first P-type transistor and a first N-type transistor, wherein a gate of the first P-type transistor is coupled to a gate of the first N-type transistor, and the gates of the first P-type transistor and the first N-type transistor are coupled to the inverted word line to receive the inverted word line signal.

[0008] According to an embodiment of the present invention, a drain of the first P-type transistor is coupled to a drain of the first N-type transistor, and the drains of the first P-type transistor and the first N-type transistor are coupled to the word line to generate the word line signal, wherein the word line is coupled to one end of the first capacitor, and another end of the first capacitor is coupled to a ground node.

[0009] According to an embodiment of the present invention, a first source of the first P-type transistor is coupled to the power switch circuit and the second capacitor at the internal node, and a second source of the first N-type transistor is coupled to the ground node.

[0010] According to an embodiment of the present invention, the power switch circuit includes at least one second P-type transistor.

[0011] According to an embodiment of the present invention, a gate of the second P-type transistor receives the power switch control signal, a drain of the second P-type transistor is coupled to the inverter and the second capacitor at the internal node, and a source of the second P-type transistor is coupled to a power node.

[0012] According to an embodiment of the present invention, one end of the second capacitor is coupled to the inverter and the power switch circuit at an internal node, and another end of the second capacitor receives the boosted signal.

[0013] A method of charge sharing-word line inhibition driving mechanism is provided according to an embodiment of the present application. The method of charge sharing-word line inhibition driving mechanism can be applied to an auxiliary read operation of a word line modulation circuit. The method of charge sharing-word line inhibition driving mechanism includes the following steps: turning off a first P-type transistor of an inverter of the word line modulation circuit and turning on a second P-type transistor of a power switch circuit of the word line modulation circuit; pre-charging a voltage of an internal node to a power voltage, wherein the inverter is coupled with a first capacitor via a word line, and the inverter and the power switch circuit are coupled with a second capacitor at the internal node; increasing a voltage of a power switch control signal to turn off the second P-type transistor of the power switch circuit; decreasing an inverted word line voltage of an inverted word line signal to turn on the first P-type transistor P1 of the inverter; transferring charges of the internal node to the word line; and determining whether a time of voltage decrease of the power switch control signal is earlier than a time of voltage increase of the inverted word line voltage of the inverted word line signal after the read operation is finished. When the time of voltage decrease of the power switch control signal is earlier than the time of voltage increase of the inverted word line voltage of the inverted word line signal, a word line voltage of a word line signal temporarily increases to the power voltage first, and after the inverted word line voltage of the inverted word line signal starts to increase, the word line voltage of the word line signal starts to discharge to 0. When the time of voltage increase of the inverted word line voltage of the inverted word line signal is earlier than the time of voltage decrease of the power switch control signal, after the inverted word line voltage of the inverted word line signal starts to increase, the word line voltage of the word line signal starts to discharge to 0.

[0014] A method of a capacitive coupling-wordline overdrive mechanism is provided according to an embodiment of the present application. The method of the capacitive coupling-wordline overdrive mechanism is applied to an auxiliary write operation of a wordline modulation circuit. The method of the capacitive coupling-wordline overdrive mechanism includes: turning off a first P-type transistor of an inverter of the wordline modulation circuit, and turning on a second P-type transistor of a power switch circuit of the wordline modulation circuit; lowering a complementary wordline voltage of a complementary wordline signal to turn on the first P-type transistor of the inverter, and pre-charging a wordline voltage of a wordline signal on a wordline to a power supply voltage in advance; increasing a voltage of the power switch control signal to turn off the second P-type transistor of the power switch circuit; increasing a voltage of a boost signal to inject charges into an internal node, wherein the inverter is coupled to a first capacitor via the wordline, and the inverter and the power switch circuit are coupled to a second capacitor at the internal node; transferring the charges on the internal node to the wordline; and determining whether a time of voltage decrease of the power switch control signal is earlier than a time of voltage increase of the complementary wordline voltage of the complementary wordline signal when the write operation is finished. When the time of voltage decrease of the power switch control signal is earlier than the time of voltage increase of the complementary wordline voltage of the complementary wordline signal, the wordline voltage of the wordline signal temporarily decreases to the power supply voltage in advance, and the wordline voltage of the wordline signal starts to discharge to 0 after the complementary wordline voltage of the complementary wordline signal starts to increase. When the time of voltage increase of the complementary wordline voltage of the complementary wordline signal is earlier than the time of voltage decrease of the power switch control signal, the wordline voltage of the wordline signal starts to discharge to 0 after the complementary wordline voltage of the complementary wordline signal starts to increase

[0015] Other additional features and advantages of the present application will be readily appreciated by those skilled in the art upon reading the above description of embodiments of the present application in conjunction with the drawings, it being understood that every maximum possible modification and variation is to be included within the spirit and scope of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 FIG. 1 is a block diagram showing a wordline modulation circuit 100 according to an embodiment of the present application.

[0017] Figures 2A-2E FIG. 2 is a waveform diagram showing a method of a charge sharing-wordline inhibition drive mechanism according to an embodiment of the present application.

[0018] Figures 3A-3E FIG. 3 is a waveform diagram showing a method of a charge sharing-wordline inhibition drive mechanism according to another embodiment of the present application.

[0019] Figures 4A-4E This is a waveform diagram showing the use of a capacitively coupled word line overdrive mechanism according to an embodiment of the present invention.

[0020] Figures 5A-5E This is a waveform diagram showing the use of a capacitively coupled word line overdrive mechanism according to another embodiment of the present invention.

[0021] Figures 6A-6E This is a waveform diagram showing the combination of charge sharing-word line suppression driving mechanism and capacitive coupling-word line overdrive mechanism according to an embodiment of the present invention.

[0022] Figure 7 This is a flowchart of a method for a charge-sharing-word-line suppression driving mechanism according to an embodiment of the present invention.

[0023] Figure 8 This is a flowchart of a capacitively coupled word line overdrive mechanism according to an embodiment of the present invention.

[0024] [Symbol Explanation]

[0025] 100: Word line modulation circuit

[0026] 110: Inverter

[0027] 120: Power switch circuit

[0028] 130: First capacitor

[0029] 140: Second capacitor

[0030] BST: Boost signal

[0031] N1: First N-type transistor

[0032] P1: First P-type transistor

[0033] P2: Second P-type transistor

[0034] PG: Power switch control signal

[0035] VDDPG: Internal Node

[0036] VDD: Power Node

[0037] VSS: Ground Node

[0038] WLB: Inverting word line signal

[0039] WL: Word line signal

[0040] S710~S780, S810~S880: Steps Detailed Implementation

[0041] This section describes preferred embodiments of the invention and is intended to illustrate the spirit of the invention rather than to limit its scope of protection. The scope of protection of the invention shall be determined by the appended claims.

[0042] Figure 1 This is a block diagram showing a word line modulation circuit 100 according to an embodiment of the present invention. The word line modulation circuit 100 can be applied to a memory device, such as a static random access memory (SRAM), but the present invention is not limited thereto. Figure 1 As shown, the word line modulation circuit 100 may include an inverter 110, a power switch circuit 120, a first capacitor 130, and a second capacitor 140. Note that in... Figure 1 The block diagrams shown are for illustrative purposes only and are not intended to represent embodiments of the present invention. Figure 1 This is limited. Other components may also be included in the word line modulation circuit 100. Furthermore, it should be specifically noted that... Figure 1 The illustrated word line modulation circuit 100 includes an inverter, a first capacitor, a second capacitor, and a power switch circuit, but the invention is not limited thereto. According to one embodiment of the invention, the word line modulation circuit 100 may also include multiple inverters, multiple first capacitors, multiple power switch circuits, and multiple second capacitors, wherein each inverter corresponds to one first capacitor and one second capacitor. Furthermore, according to one embodiment of the invention, the power switch circuit 120 can be used to simultaneously couple multiple inverters to control the multiple inverters.

[0043] like Figure 1As shown, inverter 110 may include a first P-type transistor (e.g., a P-type metal-oxide-semiconductor field-effect transistor). A P-type transistor (PMOSFET) P1 and a first N-type transistor (e.g., an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET)) N1. The gate of the first P-type transistor P1 is coupled to the gate of the first N-type transistor N1, and the gates of the first P-type transistor P1 and the first N-type transistor N1 are coupled to an inverting word line to receive an inverted word line signal WLB. The drain of the first P-type transistor P1 is coupled to the drain of the first N-type transistor N1, and the drains of the first P-type transistor P1 and the first N-type transistor N1 are coupled to a word line to generate a word line signal WL. The source of the first P-type transistor P1 is coupled to the power switch circuit 120 and the second capacitor 140 at an internal node VDDPG. The source of the first N-type transistor N1 is coupled to a ground node VSS.

[0044] In addition, such as Figure 1 As shown, the power switch circuit 120 may include a second P-type transistor P2. The gate of the second P-type transistor P2 may receive a power switch control signal PG. The source of the second P-type transistor P2 may be coupled to a power node VDD to receive the power supply voltage V. DD The drain of the second P-type transistor P2 can be coupled to the inverter 110 (the source of the first P-type transistor P1) and the second capacitor 140 at the internal node VDDPG. According to another embodiment of the present invention, the power switch circuit 120 may also include a plurality of second P-type transistors.

[0045] In addition, such as Figure 1 As shown, one end of the first capacitor 130 can be coupled to the word line, and the other end of the first capacitor 130 can be coupled to the ground node VSS. One end of the second capacitor 140 can be coupled to the inverter 110 (the source of the first P-type transistor P1) and the power switch circuit 120 (the drain of the second P-type transistor P2) at the internal node VDDPG, and the other end of the second capacitor 140 can receive the boost signal BST.

[0046] According to one embodiment of the present invention, when the memory device is performing a read operation, the word line modulation circuit 100 can be used to perform a charging sharing (CS)-word-line under-driving (WLUD) mechanism to assist the read operation performed by the memory device. Its working principle will be described in detail below.

[0047] In an initial state, the second P-type transistor P2 of the power switch circuit 120 is turned on, and the first P-type transistor P1 of the inverter 110 is turned off. Furthermore, the voltage at the internal node VDDPG is pre-charged to the supply voltage V. DD Furthermore, inverter 110 maintains the word line voltage of word line signal WL at 0. When the voltage of power switch control signal PG rises, the second P-type transistor P2 of power switch circuit 120 turns off. Since the first P-type transistor P1 of inverter 110 is still off when the voltage of power switch control signal PG begins to rise, the voltage of internal node VDDPG will be maintained at the power supply voltage V. DD When the inverted word line voltage of the inverted word line signal WLB begins to decrease, the first P-type transistor P1 of inverter 110 turns on. Due to the charge-sharing effect, when the first P-type transistor of inverter 110 turns on, the charge in the internal node VDDPG is transferred to the word line. Furthermore, since the first N-type transistor N1 of inverter 110 is turned off when the first P-type transistor P1 is on, the charge is maintained on the word line and the internal node VDDPG. At this time, the voltage of the word line signal WL is determined by the following formula:

[0048]

[0049] Where V WL The word line voltage and C represent the word line signal WL. CS This indicates the capacitance value of the second capacitor 140, C. WL This indicates the capacitance value of the first capacitor 130, and V. DD This represents the power supply voltage. After the read operation is complete, the voltage of the power switch control signal PG will begin to decrease, and the voltage of the inverted word line signal WLB will begin to rise. If the voltage of the power switch control signal PG decreases before the voltage of the inverted word line signal WLB rises, the word line voltage of the word line signal WLB will temporarily rise to the power supply voltage V. DD Only after the inverted word line voltage of the inverted word line signal WLB begins to rise will the word line voltage of the word line signal WL begin to discharge to 0. The word line voltage of the word line signal WL will temporarily rise to the power supply voltage V. DDThe timing depends on the delay between the power switch control signal PG and the inverted word line signal WLB. Furthermore, in this case (where the voltage drop of the power switch control signal PG occurs earlier than the rise of the inverted word line voltage of the inverted word line signal WLB), the duration of the charge sharing-word line suppression drive mechanism depends on the time between the drop of the inverted word line voltage of the inverted word line signal WLB and the drop of the power switch control signal PG. When the rise of the inverted word line voltage of the inverted word line signal WLB occurs earlier than the drop of the power switch control signal PG, the word line voltage of the word line signal WL will begin to discharge to 0 after the inverted word line voltage of the inverted word line signal WLB begins to rise. Furthermore, in this case (where the rise of the inverted word line voltage of the inverted word line signal WLB occurs earlier than the drop of the power switch control signal PG), the duration of the charge sharing-word line suppression drive mechanism depends on the time between the drop of the inverted word line voltage of the inverted word line signal WLB and the rise of the inverted word line voltage of the inverted word line signal WLB. Furthermore, in this embodiment, the voltage of the boost signal BST will be maintained at a certain value. The following will use... Figures 2A-2E Let's explain this with points 3A-3E.

[0050] Figures 2A-2E This is a waveform diagram showing the use of a charge-sharing-word-line suppression driving mechanism according to an embodiment of the present invention. Figure 2A This is the waveform diagram of the power switch control signal PG. Figure 2B This is the waveform diagram corresponding to the inverted word line signal WLB. Figure 2C This is the waveform diagram corresponding to the boost signal BST. Figure 2D This is a waveform diagram of the voltage corresponding to the internal node VDDPG. Figure 2E This is the waveform diagram of the corresponding word line signal WL. Furthermore, in Figures 2A-2E In the middle, the power supply voltage V DD Assume it is 1 volt (V). Figures 2A-2E As shown, when the voltage of the power switch control signal PG rises to the power supply voltage V... DD After a period of time, the inverted word line voltage of the inverted word line signal WLB begins to decrease. Charge from the internal node VDDPG begins to transfer to the word line (i.e., the word line voltage of the word line signal WL begins to rise, the magnitude of which is determined by the formula mentioned above). Furthermore, from... Figure 2E It can be seen that, under the action of the charge sharing-word line suppression driving mechanism, the word line voltage of the word line signal WL will be less than the power supply voltage V. DDAfter the read operation is completed, the voltage of the power switch control signal PG will begin to decrease, and the voltage of the inverted word line signal WLB will begin to rise. In this embodiment, since the voltage of the power switch control signal PG decreases earlier than the voltage of the inverted word line signal WLB rises, the word line voltage of the word line signal WLB will temporarily rise to the power supply voltage V. DD The word line voltage of the word line signal WL will only begin to discharge to 0 after the inverted word line voltage of the inverted word line signal WLB starts to rise.

[0051] Figures 3A-3E This is a waveform diagram showing the use of a charge-sharing-word-line suppression driving mechanism according to another embodiment of the present invention. Figure 3A This is the waveform diagram of the power switch control signal PG. Figure 3B This is the waveform diagram corresponding to the inverted word line signal WLB. Figure 3C This is the waveform diagram corresponding to the boost signal BST. Figure 3D This is a waveform diagram of the voltage corresponding to the internal node VDDPG. Figure 3E This is the waveform diagram of the corresponding word line signal WL. Furthermore, in Figures 3A-3E In the middle, the power supply voltage V DD Assume it is 1 volt (V). Figures 3A-3E As shown, when the voltage of the power switch control signal PG rises to the power supply voltage V... DD After a period of time, the inverted word line voltage of the inverted word line signal WLB begins to decrease. Charge from the internal node VDDPG begins to transfer to the word line (i.e., the word line voltage of the word line signal WL begins to rise, the magnitude of which is determined by the formula mentioned above). Furthermore, from... Figure 3E It can be seen that, under the action of the charge sharing-word line suppression driving mechanism, the word line voltage of the word line signal WL will be less than the power supply voltage V. DD After the read operation is completed, the voltage of the power switch control signal PG will begin to decrease, and the voltage of the inverted word line signal WLB will begin to rise. In this embodiment, since the rise time of the inverted word line signal WLB is earlier than the drop time of the power switch control signal PG, the word line voltage of the word line signal WL will begin to discharge to 0 after the inverted word line voltage of WLB begins to rise. That is to say, before the word line voltage of the word line signal WL begins to discharge to 0, the word line voltage of the word line signal WL will be affected by the charge sharing-word line suppression driving mechanism (i.e., the word line voltage of the word line signal WL will be less than the power supply voltage V). DD ).

[0052] According to one embodiment of the present invention, when the memory device is performing a write operation, the word line modulation circuit 100 can be used to perform a capacitive coupling (CC)-word-line over-driving (WLOD) mechanism to assist the write operation performed by the memory device. Its working principle will be described in detail below.

[0053] In an initial state, the second P-type transistor P2 of the power switch circuit 120 is turned on, and the first P-type transistor P1 of the inverter 110 is turned off. Furthermore, when the inverted word line voltage of the inverted word line signal WLB begins to decrease, the first P-type transistor P1 of the inverter 110 is turned on to precharge the word line voltage of the word line signal WL to the power supply voltage V. DD When the inverted word line voltage of the inverted word line signal WLB begins to decrease, the second P-type transistor P2 of the power switch circuit 120 remains on. When the voltage of the power switch control signal PG begins to rise, the second P-type transistor P2 of the power switch circuit 120 turns off. Then, the voltage of the boost signal BST rises. Due to capacitive coupling, as the voltage of the boost signal BST rises, it injects charge into the internal node VDDPG. Furthermore, due to charge sharing, the charge on the internal node VDDPG is simultaneously transferred to the word line. Additionally, since the first N-type transistor N1 of the inverter 110 is off when the first P-type transistor P1 of the inverter 110 is on, the charge remains on the word line and the internal node VDDPG. At this time, the voltage of the word line signal WL is determined by the following formula:

[0054]

[0055] Where V WL The word line voltage and C represent the word line signal WL. CS This indicates the capacitance value of the second capacitor 140, C. WL This indicates the capacitance value of the first capacitor 130, and V. DD This represents the power supply voltage. After the write operation is complete, the voltage of the power switch control signal PG will begin to decrease, and the voltage of the inverted word line signal WLB will begin to rise. If the voltage of the power switch control signal PG decreases before the voltage of the inverted word line signal WLB rises, the word line voltage of the word line signal WL will temporarily drop to the power supply voltage V. DD Once the inverted word line voltage of the inverted word line signal WLB begins to rise, the word line voltage of the word line signal WL will begin to discharge to 0. The word line voltage of the word line signal WL will temporarily drop to the power supply voltage V. DDThe timing depends on the delay between the power switch control signal PG and the inverted word line signal WLB. Furthermore, in this case (where the voltage drop of the power switch control signal PG occurs earlier than the rise of the inverted word line voltage of the inverted word line signal WLB), the duration of the capacitive coupling-word line overdrive mechanism depends on the time between the rise of the boost signal BST and the fall of the power switch control signal PG. When the rise of the inverted word line voltage of the inverted word line signal WLB occurs earlier than the fall of the power switch control signal PG, the word line voltage of the word line signal WL will begin to discharge to 0 after the inverted word line voltage of the inverted word line signal WLB begins to rise. Furthermore, in this case (where the rise of the inverted word line voltage of the inverted word line signal WLB occurs earlier than the fall of the power switch control signal PG), the duration of the capacitive coupling-word line overdrive mechanism depends on the time between the rise of the boost signal BST and the rise of the inverted word line voltage of the inverted word line signal WLB. Furthermore, when the voltage of the power switch control signal PG begins to drop, the voltage of the internal node VDDPG will also begin to drop. The following will be... Figures 4A-4E and Figures 5A-5E Let me explain.

[0056] Figures 4A-4E This is a waveform diagram showing the use of a capacitively coupled word line suppression driving mechanism according to an embodiment of the present invention. Figure 4A This is the waveform diagram of the power switch control signal PG. Figure 4B This is the waveform diagram corresponding to the inverted word line signal WLB. Figure 4C This is the waveform diagram corresponding to the boost signal BST. Figure 4D This is a waveform diagram of the voltage corresponding to the internal node VDDPG. Figure 4E This is the waveform diagram of the corresponding word line signal WL. Furthermore, in Figures 4A-4E In the middle, the power supply voltage V DD Assume it is 1 volt (V). Figures 4A-4E As shown, after the inverted word line voltage of the inverted word line signal WLB starts to decrease, the word line voltage of the word line signal WL will start to rise to the power supply voltage V. DD Furthermore, the voltage at the internal node VDDPG will first drop and then return to the supply voltage V. DD When the word line voltage of the word line signal WL rises to the power supply voltage V... DD Afterwards, the voltage of the power switch control signal PG rises to the power supply voltage V. DD Next, the voltage of the boost signal BST will rise. Due to the capacitive coupling effect, as the voltage of the boost signal BST rises, it will inject charge into the internal node VDDPG, thus causing the voltage of the internal node VDDPG to rise from the supply voltage V. DDIt begins to rise. Furthermore, due to the charge-sharing effect, the charge on the internal node VDDPG will also be transferred to the word line simultaneously, causing the word line voltage of the word line signal WL to begin to rise from the supply voltage V. DD The voltage rise of the word line signal WL is determined by the formula mentioned above. From Figure 4E It can be seen that, under the capacitive coupling-word line overdrive mechanism, the word line voltage of the word line signal WL will be greater than the power supply voltage V. DD After the write operation is completed, the voltage of the power switch control signal PG will begin to decrease, and the voltage of the inverted word line signal WLB will begin to rise. In this embodiment, since the rise time of the inverted word line signal WLB is earlier than the drop time of the power switch control signal PG, the word line voltage of the word line signal WL will begin to discharge to 0 after the inverted word line voltage of WLB begins to rise. That is to say, before the word line voltage of the word line signal WL begins to discharge to 0, the word line voltage of the word line signal WL will be affected by the capacitive coupling-word line overdrive mechanism (i.e., the word line voltage of the word line signal WL will be greater than the power supply voltage V). DD Furthermore, in this embodiment, when the voltage of the boost signal BST drops, the voltage of the internal node VDDPG will first drop from the power supply voltage V. DD It drops, then returns to the power supply voltage VDD.

[0057] Figures 5A-5E This is a waveform diagram showing the use of a charge-sharing-word-line suppression driving mechanism according to another embodiment of the present invention. Figure 5A This is the waveform diagram of the power switch control signal PG. Figure 5B This is the waveform diagram corresponding to the inverted word line signal WLB. Figure 5C This is the waveform diagram corresponding to the boost signal BST. Figure 5D This is a waveform diagram of the voltage corresponding to the internal node VDDPG. Figure 5E This is the waveform diagram of the corresponding word line signal WL. Furthermore, in Figures 5A-5E In the middle, the power supply voltage V DD Assume it is 1 volt (V). Figures 5A-5E As shown, after the inverted word line voltage of the inverted word line signal WLB starts to decrease, the word line voltage of the word line signal WL will start to rise to the power supply voltage V. DD Furthermore, the voltage at the internal node VDDPG will first drop and then return to the supply voltage V. DD When the word line voltage of the word line signal WL rises to the power supply voltage V... DD Afterwards, the voltage of the power switch control signal PG rises to the power supply voltage V. DDNext, the voltage of the boost signal BST will rise. Due to capacitive coupling, as the voltage of the boost signal BST rises, it injects charge into the internal node VDDPG, causing the voltage of the internal node VDDPG to rise from the supply voltage VDD. Furthermore, due to charge sharing, the charge on the internal node VDDPG will also be transferred to the word line, causing the word line voltage of the word line signal WL to rise from the supply voltage VDD. DD The voltage rise of the word line signal WL is determined by the formula mentioned above. From Figure 5E It can be seen that, under the capacitive coupling-word line overdrive mechanism, the word line voltage of the word line signal WL will be greater than the power supply voltage V. DD After the write operation is complete, the voltage of the power switch control signal PG will begin to decrease, and the voltage of the inverted word line signal WLB will begin to rise. In this embodiment, because the voltage of the power switch control signal PG decreases earlier than the voltage of the inverted word line signal WLB rises, the word line voltage of the word line signal WLB will temporarily decrease to the power supply voltage V. DD The word line voltage of the word line signal WL will only begin to discharge to 0 after the inverted word line voltage of the inverted word line signal WLB starts to rise. Furthermore, in this embodiment, when the voltage of the boost signal BST drops, the voltage of the internal node VDDPG will first drop from the power supply voltage V... DD It drops, then returns to the power supply voltage V. DD .

[0058] According to one embodiment of the present invention, when the memory device performs a read / write operation (i.e., generates two power switch control signal pulses within a word line signal WL pulse), the word line modulation circuit 100 can alternately use a charge sharing-word line suppression driving mechanism and a capacitive coupling-word line overdrive mechanism to assist the read / write operation performed by the memory device. Its working principle will be described in detail below.

[0059] First, in an initial state, the second P-type transistor P2 of the power switch circuit 120 is turned on, and the first P-type transistor P1 of the inverter 110 is turned off. Furthermore, the voltage at the internal node VDDPG is pre-charged to the supply voltage V. DDThe inverter 110 maintains the word line voltage of the word line signal WL at 0. When the voltage of the power switch control signal PG rises, the second P-type transistor P2 of the power switch circuit 120 turns off. When the inverted word line voltage of the inverted word line signal WLB begins to fall, the first P-type transistor P1 of the inverter 110 turns on. Due to the charge sharing effect, when the first P-type transistor of the inverter 110 turns on, the charge on the internal node VDDPG is transferred to the word line to realize the charge sharing-word line suppression drive mechanism. When the voltage of the power switch control signal PG begins to fall, the second P-type transistor P2 of the power switch circuit 120 turns on, so that the voltage of the internal node VDDPG and the word line voltage of the word line signal WL return to the power supply voltage V. DD (That is, the charge sharing-word line suppression driving mechanism ends at this point). Next, the voltage of the power switch control signal PG rises again, and the second P-type transistor P2 of the power switch circuit 120 turns off. Then, the voltage of the boost signal BST rises. Due to capacitive coupling, as the voltage of the boost signal BST rises, it injects charge into the internal node VDDPG, causing the voltage of the internal node VDDPG to rise above the supply voltage V. DD Furthermore, due to the charge-sharing effect, the charge on the internal node VDDPG will also be transferred to the word line, causing the word line voltage of the word line signal WL to rise above the supply voltage V. DD This is to achieve the capacitive coupling-word line overdrive mechanism. In this embodiment, the operation of the charge sharing-word line suppression drive mechanism and the capacitive coupling-word line overdrive mechanism is similar to the operation described in the above embodiments, and therefore will not be repeated. The following will use... Figures 6A-6E This embodiment will be explained below.

[0060] Figures 6A-6E This is a waveform diagram showing the combination of the share-word line suppression driving mechanism and the capacitive coupling-word line overdrive mechanism according to another embodiment of the present invention. Figure 6A This is the waveform diagram of the power switch control signal PG. Figure 6B This is the waveform diagram corresponding to the inverted word line signal WLB. Figure 6C This is the waveform diagram corresponding to the boost signal BST. Figure 6D This is a waveform diagram of the voltage corresponding to the internal node VDDPG. Figure 6E This is the waveform diagram of the corresponding word line signal WL. Furthermore, in Figures 6A-6E In the middle, the power supply voltage V DD Assume it is 1 volt (V). Figures 6A-6EAs shown, the operation in the first half of the waveform corresponds to the charge-sharing-word-line suppression driving mechanism, while the operation in the second half corresponds to the capacitive coupling-word-line overdrive mechanism. In this embodiment, the operations of the charge-sharing-word-line suppression driving mechanism and the capacitive coupling-word-line overdrive mechanism are similar to those described above. Figures 2A-2E The operations described in the embodiments 3A-3E, 4A-4E and 5A-5E are therefore not repeated here.

[0061] Note that, Figures 2A-2E The waveforms shown in 3A-3E, 4A-4E, 5A-5E, and 6A-6E are only used to illustrate embodiments of the present invention, but the present invention is not limited thereto. Furthermore, the power switch control signal PG and boost signal BST described in the embodiments of the present invention can be provided by an external control device (not shown).

[0062] Figure 7 This is a flowchart of a charge-sharing-word-line suppression driving mechanism method according to an embodiment of the present invention. The charge-sharing-word-line suppression driving mechanism method described in this embodiment can be applied to a situation where a word-line modulation circuit 100 assists in a read operation. Figure 7 As shown, in step S710, the second P-type transistor P2 of the power switch circuit 120 of the word line modulation circuit 100 is turned on, and the first P-type transistor P1 of the inverter 110 of the word line modulation circuit 100 is turned off.

[0063] In step S720, the voltage of the internal node VDDPG is pre-charged to the supply voltage V. DD Inverter 110 is coupled to a first capacitor 130 via a word line, and inverter 110 and power switch circuit 120 are coupled to a second capacitor 140 at internal node VDDPG.

[0064] In step S730, the voltage of the power switch control signal PG rises to turn off the second P-type transistor P2 of the power switch circuit 120.

[0065] In step S740, the inverted word line voltage of the inverted word line signal WLB drops to turn on the first P-type transistor P1 of the inverter 110.

[0066] In step S750, the charge of the internal node VDDPG is transferred to the word line.

[0067] In step S760, after the read operation is completed, it is determined whether the voltage drop time of the power switch control signal PG is earlier than the voltage rise time of the inverted word line signal WLB.

[0068] When the voltage drop of the power switch control signal PG occurs earlier than the rise time of the inverted word line voltage of the inverted word line signal WLB, step S770 is performed. In step S770, the word line voltage of the word line signal WL will temporarily rise to the power supply voltage V. DD The word line voltage of the word line signal WL will only start to discharge to 0 after the inverted word line voltage of the inverted word line signal WLB begins to rise.

[0069] When the rise time of the inverted word line voltage of the inverted word line signal WLB is earlier than the fall time of the voltage of the power switch control signal PG, step S780 is performed. In step S780, after the inverted word line voltage of the inverted word line signal WLB begins to rise, the word line voltage of the word line signal WL will begin to discharge to 0.

[0070] Figure 8 This is a flowchart of a capacitively coupled word line overdrive mechanism method according to an embodiment of the present invention. The capacitively coupled word line overdrive mechanism method described in this embodiment can be applied to a situation where a word line modulation circuit 100 assists in a write operation. Figure 8 As shown, in step S810, the second P-type transistor P2 of the power switch circuit 120 of the word line modulation circuit 100 is turned on, and the first P-type transistor P1 of the inverter 110 of the word line modulation circuit 100 is turned off.

[0071] In step S820, the inverted word line voltage of the inverted word line signal WLB decreases to turn on the first P-type transistor P1 of the inverter 110, and the word line voltage of the word line signal WL on the word line is pre-charged to the power supply voltage V. DD .

[0072] In step S830, the voltage of the power switch control signal PG rises to turn off the second P-type transistor P2 of the power switch circuit 120.

[0073] In step S840, the voltage of the boost signal BST increases to inject charge into the internal node VDDPG. Inverter 110 is coupled to a first capacitor 130 via a word line, and inverter 110 and power switch circuit 120 are coupled to a second capacitor 140 at the internal node VDDPG.

[0074] In step S850, the charge on the internal node VDDPG is transferred to the word line.

[0075] In step S860, after the write operation is completed, it is determined whether the voltage drop of the power switch control signal PG occurs earlier than the voltage rise of the inverted word line signal WLB.

[0076] When the voltage drop of the power switch control signal PG occurs earlier than the rise time of the inverted word line voltage of the inverted word line signal WLB, step S870 is performed. In step S870, the word line voltage of the word line signal WL will temporarily drop to the power supply voltage V. DD The word line voltage of the word line signal WL will only start to discharge to 0 after the inverted word line voltage of the inverted word line signal WLB begins to rise.

[0077] When the rise time of the inverted word line voltage of the inverted word line signal WLB is earlier than the fall time of the voltage of the power switch control signal PG, step S880 is performed. In step S880, after the inverted word line voltage of the inverted word line signal WLB begins to rise, the word line voltage of the word line signal WL will begin to discharge to 0.

[0078] The word line modulation circuit 100 proposed in the embodiments of the present invention can implement both the charge sharing-word line suppression drive mechanism and the capacitive coupling-word line overdrive mechanism using only a single word line modulation circuit 100 architecture. Therefore, compared to known word line modulation circuits, the word line modulation circuit 100 proposed in the embodiments of the present invention can reduce the area occupied by the word line modulation circuit. Furthermore, since the word line modulation circuit 100 proposed in the embodiments of the present invention does not generate quiescent current, it can reduce the power consumption of the memory device.

[0079] The serial numbers in this specification and the claims, such as "first," "second," etc., are for ease of explanation only and do not have any sequential relationship with each other.

[0080] The steps of the methods and algorithms disclosed in this specification can be directly applied to hardware and software modules or a combination of both by executing a processor. A software module (including execution instructions and related data) and other data can be stored in a data storage device, such as random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), temporary registers, hard disks, portable hard disks, optical disc read-only memory (CD-ROM), DVDs, or any other computer-readable storage medium format known in the art. A storage medium can be coupled to a machine device, for example, such as a computer / processor (referred to as a processor in this specification for convenience), through which the processor can read information (such as program code) and write information to the storage medium. A storage medium can integrate a processor. An application-specific integrated circuit (ASIC) includes a processor and a storage medium. A user equipment includes an application-specific integrated circuit. In other words, the processor and storage medium are included in the user equipment in a manner that is not directly connected to the user equipment. Furthermore, in some embodiments, any product suitable for a computer program includes a readable storage medium, wherein the readable storage medium includes program code associated with one or more of the disclosed embodiments. In some embodiments, the product of the computer program may include packaging material.

[0081] The preceding paragraphs use multiple levels of description. Clearly, the teachings herein can be implemented in various ways, and any particular architecture or functionality disclosed in the examples is merely a representative case. Based on the teachings herein, those skilled in the art will understand that the various levels disclosed herein can be implemented independently or that two or more levels can be implemented in combination.

[0082] Although this disclosure has been provided above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of the invention shall be determined by the scope defined in the appended claims.

Claims

1. A word line modulation circuit, comprising: a first capacitor; at least one inverter coupled to a word line and an inverted word line to receive an inverted word line signal and generate a word line signal, and coupled to the first capacitor via the word line; a power switch circuit coupled to the inverter to receive a power switch control signal; and at least one second capacitor coupled to the inverter and the power switch circuit at an internal node to receive a boost signal, wherein each inverter corresponds to a first capacitor and a second capacitor; wherein one end of the second capacitor is coupled to the inverter and the power switch circuit at the internal node, and the other end of the second capacitor receives the boost signal, wherein the boost signal injects charge into the internal node during a write operation, and the voltage of the boost signal is maintained at a certain value during a read operation.

2. The word line modulation circuit of claim 1, wherein the inverter comprises a first P-type transistor and a first N-type transistor, wherein a gate of the first P-type transistor is coupled to a gate of the first N-type transistor, and the gates of the first P-type transistor and the first N-type transistor are coupled to the inverted word line to receive the inverted word line signal.

3. The word line modulation circuit of claim 2, wherein a drain of the first P-type transistor is coupled to a drain of the first N-type transistor, and the drains of the first P-type transistor and the first N-type transistor are coupled to the word line to generate the word line signal, wherein the word line is coupled to one end of the first capacitor, and the other end of the first capacitor is coupled to a ground node.

4. The word line modulation circuit of claim 3, wherein a source of the first P-type transistor is coupled to the power switch circuit and the second capacitor at the internal node, and a source of the first N-type transistor is coupled to the ground node.

5. The word line modulation circuit of claim 1, wherein the power switch circuit comprises at least one second P-type transistor.

6. The word line modulation circuit of claim 5, wherein a gate of the second P-type transistor receives the power switch control signal, a drain of the second P-type transistor is coupled to the inverter and the second capacitor at the internal node, and a source of the second P-type transistor is coupled to a power supply node.

7. The word line modulation circuit of claim 1, wherein during a read operation, when an inverted word line voltage of the inverted word line signal drops, charge at the internal node is transferred to the word line.

8. The word line modulation circuit of claim 1, wherein during a write operation, when an inverted word line voltage of the inverted word line signal drops, the inverter charges a word line voltage of the word line to a power supply voltage, and a voltage of the boost signal rises to inject charge into the internal node, and charge at the internal node is transferred to the word line.

9. A method of charge sharing-word line suppression driving mechanism, applied to an auxiliary read operation of the word line modulation circuit of claim 1, comprising: ​ turning off a first P-type transistor of an inverter of the word line modulation circuit and turning on a second P-type transistor of a power switch circuit of the word line modulation circuit; pre-charging a voltage of an internal node to a power supply voltage, wherein the inverter is coupled to a first capacitor via a word line, and the inverter and the power switch circuit are coupled to a second capacitor at the internal node; increasing a voltage of a power switch control signal to turn off the second P-type transistor of the power switch circuit; decreasing an inverted word line voltage of an inverted word line signal to turn on the first P-type transistor P1 of the inverter; transferring a charge at the internal node to the word line; and determining whether a time of voltage decrease of the power switch control signal is earlier than a time of voltage increase of the inverted word line voltage of the inverted word line signal after the read operation is completed.

10. The method of charge sharing-word line inhibition driving mechanism of claim 9, further comprising: temporarily increasing a word line voltage of a word line signal to the power supply voltage first when the time of voltage decrease of the power switch control signal is earlier than the time of voltage increase of the inverted word line voltage of the inverted word line signal, and discharging the word line voltage of the word line signal to 0 after the inverted word line voltage of the inverted word line signal starts to increase; and discharging the word line voltage of the word line signal to 0 after the inverted word line voltage of the inverted word line signal starts to increase when the time of voltage increase of the inverted word line voltage of the inverted word line signal is earlier than the time of voltage decrease of the power switch control signal.

11. The method of capacitive coupling-word line overdrive mechanism, applied to an auxiliary write operation of the word line modulation circuit of claim 1, comprising: turning off a first P-type transistor of an inverter of the word line modulation circuit and turning on a second P-type transistor of a power switch circuit of the word line modulation circuit; decreasing an inverted word line voltage of an inverted word line signal to turn on the first P-type transistor of the inverter, and pre-charging a word line voltage of a word line signal on the word line to a power supply voltage; increasing a voltage of a power switch control signal to turn off the second P-type transistor of the power switch circuit; increasing a voltage increase of a boost signal to inject a charge to an internal node, wherein the inverter is coupled to a first capacitor via the word line, and the inverter and the power switch circuit are coupled to a second capacitor at the internal node; transferring the charge at the internal node to the word line; and determining whether a time of voltage decrease of the power switch control signal is earlier than a time of voltage increase of the inverted word line voltage of the inverted word line signal after the write operation is completed.

12. The method of capacitive coupling-word line overdrive mechanism of claim 11, further comprising: temporarily increasing a word line voltage of a word line signal to the power supply voltage first when the time of voltage decrease of the power switch control signal is earlier than the time of voltage increase of the inverted word line voltage of the inverted word line signal, and discharging the word line voltage of the word line signal to 0 after the inverted word line voltage of the inverted word line signal starts to increase; and discharging the word line voltage of the word line signal to 0 after the inverted word line voltage of the inverted word line signal starts to increase when the time of voltage increase of the inverted word line voltage of the inverted word line signal is earlier than the time of voltage decrease of the power switch control signal. When the time of the voltage drop of the power switch control signal is earlier than the time of the voltage rise of the inverted word line signal, the word line voltage of the word line signal temporarily drops to the power voltage first, and after the inverted word line voltage of the inverted word line signal starts to rise, the word line voltage of the word line signal starts to discharge to 0; and When the time of the voltage rise of the inverted word line signal is earlier than the time of the voltage drop of the power switch control signal, after the inverted word line voltage of the inverted word line signal starts to rise, the word line voltage of the word line signal starts to discharge to 0.

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