Semiconductor device and method of manufacturing semiconductor device

Abstract

Semiconductor devices and methods for manufacturing semiconductor devices. In one example, a semiconductor device includes: a substrate and an electronic device on a top side of the substrate; a leadframe on the top side of the substrate, above the electronic device, wherein the leadframe includes connecting bars and leads; a component on the top side of the leadframe, mounted to the connecting bars and leads; and an encapsulation on the top side of the substrate, wherein the encapsulation contacts one side of the electronic device and one side of the component. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly, to semiconductor devices and methods of fabricating semiconductor devices. Background Art

[0002] Previous semiconductor packages and methods of forming semiconductor packages are inadequate, for example, resulting in excessive cost, reduced reliability, relatively low performance, or excessively large package sizes. Other limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with the present disclosure and referring to the drawings. Summary of the Invention

[0003] Various aspects of the present disclosure provide a semiconductor device comprising a substrate and an electronic device on a top side of the substrate; a leadframe on the top side of the substrate above the electronic device, wherein the leadframe includes connecting bars and leads; a component on the top side of the leadframe, mounted to the connecting bars and leads; and an encapsulation on the top side of the substrate, wherein the encapsulation contacts one side of the electronic device and one side of the component. In the semiconductor device, the leadframe includes a solder pad and a downwardly disposed portion from the solder pad to the connecting bar, wherein the component is mounted to the connecting bar and the lead at a level below the top side of the solder pad. The semiconductor device further comprises an additional component on the top side of the substrate below the solder pad. In the semiconductor device, the additional component is thermally coupled to the solder pad. In the semiconductor device, the electronic device is below the component. In the semiconductor device, the top side of the encapsulation is coplanar with the top side of the leadframe. In the semiconductor device, a gap is provided between the connecting bar and the lead, and the component is mounted to span the gap. In the semiconductor device, the substrate comprises a prefabricated substrate. In the semiconductor device, the substrate comprises a redistribution layer (RDL) substrate. In the semiconductor device, the lead comprises a connection region electrically coupled to a conductive path of the substrate.

[0004] Various aspects of the present disclosure provide a method for manufacturing a semiconductor device, comprising: providing a substrate having a top side; providing an electronic device on the top side of the substrate; mounting a component on the top side of a lead frame, wherein the component is mounted between connecting bars and leads of the lead frame; connecting the lead frame to the top side of the substrate; and providing an encapsulation on the top side of the substrate, which contacts one side of the electronic device and one side of the component. In the method, the mounting includes providing interconnects on the connecting bars and the leads and electrically connecting the component to the lead frame at the interconnects. The method further includes providing an additional component on the top side of the substrate. In the method, the additional component is below a pad of the lead frame. The method further includes thermally coupling the additional component to the lead frame.

[0005] Various aspects of the present disclosure provide a semiconductor structure comprising: a substrate having a top side and a conductive path; a leadframe comprising a heat sink, a connecting bar, a downwardly disposed portion between the heat sink and the connecting bar, and a lead electrically coupled to the conductive path, wherein the connecting bar is lower than the heat sink; a first component on the top side of the substrate and coupled to the heat sink; a second component on the top side of the leadframe between the connecting bar and the lead; and an encapsulant on the top side of the substrate, contacting a side of the second component. The semiconductor structure further comprises an interface component between the top side of the first component and the bottom side of the heat sink. In the semiconductor structure, the interface component comprises a thermal interface material. In the semiconductor structure, the lead comprises a mounting area, a connection area, and an additional downwardly disposed portion between the mounting area and the connection area, wherein the lead is electrically coupled to the conductive path at the connection area. The semiconductor structure further comprises an electronic device on the top side of the substrate, below the mounting area, and below the second device. In the semiconductor structure, the electronic device is thermally coupled to the lead frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A cross-sectional view of an example semiconductor device is shown.

[0007] Figure 2 A plan view showing the lead frame on which the example component is mounted.

[0008] Figures 3A to 3G Cross-sectional views are shown of an example method of fabricating an example semiconductor device.

[0009] Figures 4A to 4C Plan and cross-sectional views illustrating an example method for mounting a component on an example lead frame.

[0010] Figure 5A and 5B A cross-sectional view illustrating an example method for mounting a component on an example lead frame.

[0011] Figure 6 A cross-sectional view of an example semiconductor device is shown.

[0012] Figure 7 A cross-sectional view of an example semiconductor device is shown. DETAILED DESCRIPTION

[0013] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0014] The figures illustrate general constructions and may omit descriptions and details of well-known features and techniques to avoid unnecessarily obscuring the present disclosure. Furthermore, the elements in the figures are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help improve understanding of the examples discussed in this disclosure. Identical reference numerals in different figures denote identical elements.

[0015] The term "or" means any one or more of the items in the list connected by "or". As an example, "x or y" means any element of the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0016] The terms "include" and / or "comprising" are "open" terms and specify the presence of the stated features, but do not preclude the presence or addition of one or more other features. The terms "first," "second," etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element discussed in this disclosure could be referred to as a second element without departing from the teachings of this disclosure.

[0017] Unless otherwise specified, the term "coupled" can be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. For example, if element A is coupled to element B, element A can be directly in contact with element B or indirectly connected to element B through an intervening element C. Similarly, the terms "over" or "on" can be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements.

[0018] In one example, a semiconductor device includes a substrate and an electronic device on a top side of the substrate; a lead frame on the top side of the substrate above the electronic device, wherein the lead frame includes connecting bars and leads; a component on the top side of the lead frame mounted to the connecting bars and the leads; and an encapsulation on the top side of the substrate, wherein the encapsulation contacts one side of the electronic device and one side of the component.

[0019] In another example, a method of manufacturing a semiconductor device includes providing a substrate having a top side; providing an electronic device on the top side of the substrate; mounting a component on the top side of a lead frame, wherein the component is mounted between connecting bars and leads of the lead frame; connecting the lead frame to the top side of the substrate; and providing an encapsulation on the top side of the substrate that contacts one side of the electronic device and one side of the component.

[0020] In yet another example, a semiconductor structure includes a substrate having a top side and a conductive path; a lead frame including a heat sink, a connecting bar, a downset between the heat sink and the connecting bar, and a lead electrically coupled to the conductive path, wherein the connecting bar is lower than the heat sink; a first component on the top side of the substrate and coupled to the heat sink; a second component on the top side of the lead frame between the connecting bar and the lead; and an encapsulation on the top side of the substrate contacting a side of the second component.

[0021] Other examples are included in the present disclosure. Such examples can be found in the figures, claims and / or description of the present disclosure.

[0022] Figure 1 A cross-sectional view of an example semiconductor device 100 is shown. Figure 1 In the example shown in , semiconductor device 100 may include substrate 110 , electronic devices 120A and 120B, components 130A, 130B, 140A, and 140B, a leadframe 150 , encapsulation 160 , and external interconnects 170 .

[0023] Substrate 110 may include dielectric structure 111 including one or more dielectric layers, wiring patterns 112a, 112b, 112c, and 113, conductive paths 114 and 115, and passivation layers 116 and 117. In some examples, passivation layers 116 and 117 may be considered part of one or more dielectric layers of dielectric structure 111.

[0024] The electronic devices 120A and 120B may include terminals 121 and interconnects 122. The components 130A, 130B, 140A, and 140B may also include terminals 131, 141 and interconnects 132, 142. The electronic devices 120A and 120B may be on the top side of the substrate 110.

[0025] Leadframe 150 may include pads 151, connecting bars 153 having downwardly disposed portions 153a, mounting areas 154a, downwardly disposed portions 154b, leads 154 having connection areas 154c, and interconnects 155. In some examples, leads 154 may be electrically coupled to one or more of conductive paths 114 and 115 of substrate 110 via one or more interconnects 155. Furthermore, components 140A and 140B may be mounted on leadframe 150. In some examples, one or more of components 140A and 140B may be mounted to connecting bars 153 and leads 154 on the top side of leadframe 150. Furthermore, gaps 156a may be provided between connecting bars 153 and leads 154. Leadframe 150 may be on the top side of substrate 110, above one or more of electronic devices 120A and 120B. In some examples, lead frame 150 can include tie bars 153 and leads 154 over one or more of electronic devices 120A and 120B.

[0026] Encapsulant 160 may encapsulate electronic devices 120A and 120B, components 130A, 130B, 140A, and 140B, and lead frame 150 positioned on substrate 110. In some examples, one or more of components 130A and 130B may be coupled to pads 151 or a heat sink. External interconnects 170 may be connected to substrate 110. Encapsulant 160 may be on the top side of substrate 110 and may contact one side of one or more of electronic devices 120A and 120B or one side of one or more of components 130A, 130B, 140A, and 140B.

[0027] Substrate 110, lead frame 150, encapsulant 160, and external interconnect 170 may be referred to as a semiconductor package 190 for electronic devices 120A and 120B and components 130A, 130B, 140A, and 140B. Semiconductor package 190 may protect electronic devices 120A and 120B and components 130A, 130B, 140A, and 140B from exposure to external factors and / or conditions. In addition, semiconductor package 190 may provide electrical coupling between external devices and interconnect 170.

[0028] Figure 2 A plan view of a lead frame 150 is shown with example components 140A, 140B, 140C, and 140D mounted thereon. Figure 2In the example shown, the lead frame 150 may include a pad 151, a tie bar 152 having downwardly disposed portions 152a and 152b, a connecting bar 153 connected to the pad 151 and the tie bar 152, and a lead 154 having a downwardly disposed portion 154b. In some examples, the pad 151 may be a heat sink that transfers heat from one or more of the components 130A and 130B to the surrounding environment. Figure 1 As can be seen in FIG, connecting bar 153 may be located at a lower level in encapsulation 160 than pad 151 or a heat sink. In some examples, components 140A and 140B may be electrically connected between connecting bar 153 and leads 154 and may be located at a level lower than the top side of pad 151 or a heat sink. In some examples, components 140C and 140D may be electrically connected between adjacent leads 154. In some examples, gap 156a may be provided between connecting bar 153 and leads 154 connected by components 140A and 140B. Furthermore, in some examples, gap 156b may be provided between adjacent leads 154 connected by components 140C and 140D.

[0029] In some examples, the pad 151 may be substantially flat, and the tie bar 152 may extend diagonally outward from the edge of the pad 151. The tie bar 152 may include a downwardly disposed portion 152a formed at one end adjacent to the pad 151 and a downwardly disposed portion 152b formed at the other end adjacent to the frame of the lead frame 150. In some examples, a connecting bar 153 may connect the two tie bars 152 to each other. In some examples, the connecting bar 153 may be connected to the tie bar 152 between the two downwardly disposed portions 152a and 152b of the tie bar 152. In some examples, the connecting bar 153 may be directly connected to the pad 151 via the downwardly disposed portion 153a. In some examples, the connecting bar 153 may be connected only to the tie bar 152 or only to the pad 151. The top surfaces of the components 130A and 130B may be in contact with the pad 151 to allow for rapid dissipation of heat generated from the components 130A and 130B.

[0030] In some examples, the leads 154 may be arranged at a region facing one of the four sides of the pad 151. In some examples, when the pad 151 has four sides, different leads 154 may also be positioned at one or more regions corresponding to these four sides. In some examples, the length direction of the leads 154 may be substantially perpendicular to one of the four sides of the pad 151 to which they correspond. In some examples, the leads 154 may include a mounting region 154a facing the connecting bar 153, a downwardly disposed portion 154b extending from the mounting region 154a, and a connection region 154c extending from the downwardly disposed portion 154b to be connected to the substrate 110. The interconnect 155 may be formed at the bottom end of the connection region 154c to be connected to the substrate 110. In some examples, the leads 154 may be electrically coupled to one or more of the conductive paths 114 and 115 via one or more of the interconnects 154, for example, at the connection region 154c. Components 140A, 140B, 140C, and 140D may be attached to leads 154 and may be electrically connected to substrate 110 .

[0031] In some examples, leadframe 150 may be made of a copper alloy (including at least one of Ni, Si, P, and Ti in Cu), an iron-nickel alloy, or a Cu / SUS / Cu clad metal. In some examples, leadframe 150 may be formed using etching or stamping. In some examples, leadframe 150 may include a plating layer (not shown) made of, for example, tin, nickel, palladium, gold, or silver. To reduce costs, the plating layer may be selectively formed only on portions of components 140A, 140B, 140C, and 140D to be mounted. Furthermore, in some examples, an anti-corrosion layer may be formed on portions of components 140A, 140B, 140C, and 140D to be mounted. In some examples, leadframe 150 may have a thickness ranging from approximately 0.1 mm to approximately 0.3 mm. In some examples, the plating layer may have a thickness ranging from approximately 1 μm to approximately 100 μm.

[0032] Figures 3A to 3G A cross-sectional view of an example method of fabricating an example semiconductor device 100 is shown. Figure 3A A cross-sectional view of substrate 110 is shown at an initial stage of fabrication.

[0033] exist Figure 3A In the example shown, a substrate 110 may be provided and may include a dielectric structure 111, upper wiring patterns 112a, 112b, and 112c, a lower wiring pattern 113, conductive paths 114 and 115, an upper passivation layer 116, and a lower passivation layer 117. In some examples, at least one of the lower wiring pattern 113, the conductive paths 114 and 115, the upper passivation layer 116, and / or the lower passivation layer 117 may be omitted.

[0034] In some examples, substrate 110 may be referred to as a printed circuit board (PCB), a printed wiring board, a single-sided PCB, a double-sided PCB, a multi-layer PCB, a through-hole PCB, a non-through-hole PCB, a rigid PCB, a flexible PCB, a phenolic paper PCB, a glass epoxy PCB, a polyimide PCB, a polyester PCB, a molded plastic PCB, a ceramic PCB, an etched foil PCB, an additive PCB, a pre-molded lead frame, etc. Examples include substrate 110 being a build-up substrate having one or more conductive layers and dielectric layers built upon each other on a carrier without a core (e.g., fiberglass) layer.

[0035] In some instances, substrate 110 may be a redistribution layer (“RDL”) substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers that may be (a) formed layer by layer over an electronic device to be electrically coupled to the RDL substrate or (b) formed layer by layer over a carrier that may be completely or at least partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate may be manufactured layer by layer as a wafer-level substrate on a circular wafer using a wafer-level process and / or as a panel-level substrate on a rectangular or square panel carrier using a panel-level process. The RDL substrate may be formed using an additive buildup process that may include alternating one or more dielectric layers with one or more conductive layers defining corresponding conductive redistribution patterns or traces that are configured to collectively (a) fan the electrical traces out of the footprint of the electronic device and / or (b) fan the electrical traces into the footprint of the electronic device. The conductive pattern may be formed using a plating process such as an electroplating process or an electroless plating process. The conductive pattern may include a conductive material, such as copper or other plateable metals. The location of the conductive pattern may be made using a photopatterning process, such as a photolithography process and a photoresist material for forming a photolithography mask. The dielectric layer of the RDL substrate may be patterned using a photopatterning process, which may include a photolithography mask through which light is exposed to desired features of the photopattern, such as through-holes in the dielectric layer. The dielectric layer may be made of a photo-definable organic dielectric material such as polyimide (PI), benzocyclobutene (BCB) or polybenzoxazole (PBO). Such dielectric materials may be spin-coated or otherwise applied in liquid form, rather than attached in the form of a prefabricated film. In order to allow the desired photo-defined features to be properly formed, such photo-definable dielectric materials may omit structural reinforcements, or may be filler-free and free of strands, woven fabrics or other particles that may interfere with the light from the photopatterning process. In some instances, such unfilled properties of the unfilled dielectric material can result in a reduced thickness of the resulting dielectric layer. Although the photodefinable dielectric material described above can be an organic material, in other instances, the dielectric material of the RDL substrate can include one or more inorganic dielectric layers. Some examples of one or more inorganic dielectric layers can include silicon nitride (Si3N4), silicon oxide (SiO2) and / or SiON. The one or more inorganic dielectric layers can be formed not by using a photodefined organic dielectric material but by growing an inorganic dielectric layer using an oxidation or nitridation process. Such inorganic dielectric layers can be unfilled and have no strands, woven fabrics or other different inorganic particles.In some examples, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates may be referred to as coreless substrates.Other substrates in the present disclosure may also include RDL substrates.

[0036] In some instances, substrate 110 may be a prefabricated substrate. The prefabricated substrate may be manufactured before being attached to the electronic device and may include a dielectric layer between the corresponding conductive layers. The conductive layer may include copper and may be formed using an electroplating process. The dielectric layer may be a relatively thick, non-photoimageable layer that can be attached in the form of a prefabricated film rather than in the form of a liquid, and may include a resin with fillers such as strands, woven fabrics, and / or other inorganic particles for rigidity and / or structural support. Since the dielectric layer is non-photodefinable, features such as through holes or openings may be formed by using drilling or lasers. In some instances, the dielectric layer may include prepreg material or Ajinomoto Buildup Film (ABF). The prefabricated substrate may include a permanent core structure or carrier, for example, a dielectric material including bismaleimide triazine (BT) or FR4, and the dielectric layer and the conductive layer may be formed on the permanent core structure. In other examples, the prefabricated substrate can be a coreless substrate that omits a permanent core structure, and the dielectric layer and the conductive layer can be formed on a sacrificial carrier that is removed after the dielectric layer and the conductive layer are formed and before being attached to the electronic device. The prefabricated substrate can be referred to as a printed circuit board (PCB) or a laminate substrate. Such a prefabricated substrate can be formed by a semi-additive process or a modified semi-additive process. Other substrates in the present disclosure may also include a prefabricated substrate.

[0037] In some examples, dielectric structure 111 may be substantially flat, having a top surface and a bottom surface. In some examples, dielectric structure 111 may include or be referred to as one or more dielectric layers. In some examples, dielectric structure 111 may comprise epoxy, phenolic, glass epoxy, polyimide, polyester, epoxy molding compound, ceramic, etc. In some examples, dielectric structure 111 may have a thickness ranging from approximately 0.1 mm to approximately 0.3 mm. Dielectric structure 111 may allow substrate 110 to remain substantially flat. Furthermore, dielectric structure 111 may allow wiring patterns 112 a, 112 b, 112 c, and 113 a positioned on or within dielectric structure 111, conductive paths 114 and 115, etc. to be insulated from one another.

[0038] The upper wiring patterns 112a, 112b, and 112c may be formed on the top surface of the dielectric structure 111, and the lower wiring pattern 113 may be formed on the bottom surface of the dielectric structure 111. In some examples, the upper wiring patterns 112a, 112b, and 112c and the lower wiring pattern 113 may include or be referred to as patterns, traces, pads, under-bump metallization (UBM), or conductors. In some examples, the upper wiring patterns 112a, 112b, and 112c and / or the lower wiring pattern 113 may include copper, iron, nickel, gold, silver, palladium, or tin. In some examples, the upper wiring patterns 112a, 112b, and 112c and / or the lower wiring pattern 113 may have a thickness, width, and spacing ranging from approximately 0.1 mm to approximately 0.3 mm. The upper wiring patterns 112a, 112b, and 112c and the lower wiring pattern 113 may electrically connect the electronic devices 120A and 120B to the components 130A and 130B, electrically connect the electronic devices 120A and 120B to an external device (not shown), or electrically connect the components 130A and 130B to an external device.

[0039] Conductive paths 114 and 115 may electrically connect upper wiring patterns 112a, 112b, and 112c to lower wiring pattern 113 while passing through dielectric structure 111. In some examples, conductive paths 114 and 115 may include or be referred to as traces, conductive vias, or conductive through-holes. Conductive paths 114 and 115 may be formed from portions of a plurality of conductive layers alternately stacked with the plurality of dielectric layers of dielectric structure 111. In some examples, conductive paths 114 and 115 may include copper, iron, nickel, gold, silver, palladium, or tin. In some examples, conductive paths 114 and 115 may have a thickness ranging from approximately 0.1 mm to approximately 0.3 mm. In some examples, conductive paths 114 and 115 may electrically connect any one of upper wiring patterns 112a, 112b, and 112c to another of upper wiring patterns 112a, 112b, and 112c. Furthermore, in some examples, the conductive paths 114 and 115 may electrically connect any one of the lower wiring patterns 113 to another one of the lower wiring patterns 113 .

[0040] Upper passivation layer 116 may substantially cover the top surface of dielectric structure 111 and / or a portion of upper wiring patterns 112a, 112b, and 112c, and lower passivation layer 117 may substantially cover the bottom surface of dielectric structure 111 and / or a portion of lower wiring pattern 113. In some examples, upper passivation layer 116 and / or lower passivation layer 117 may be referred to as a dielectric layer, solder resist, or solder resist. In some examples, the area where upper wiring patterns 112a, 112b, and 112c of electronic devices 120A and 120B and / or components 130A and 130B are to be mounted may not be covered by upper passivation layer 116. Additionally, the area of ​​lower wiring pattern 113 where external interconnect 170 is to be connected may not be covered by lower passivation layer 117. In some examples, upper passivation layer 116 and / or lower passivation layer 117 may include a polymer, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), a molding material, a phenolic resin, an epoxy resin, a silicone, or an acrylate polymer. In some examples, upper passivation layer 116 and / or lower passivation layer 117 may have a thickness ranging from approximately 0.1 mm to approximately 0.3 mm. Upper passivation layer 116 may protect upper wiring patterns 112 a, 112 b, and 112 c during semiconductor device fabrication, and lower passivation layer 117 may protect lower wiring pattern 113 during semiconductor device fabrication. In some examples, upper passivation layer 116 and / or lower passivation layer 116 may be considered part of dielectric structure 111.

[0041] The substrate 110 may support the electronic devices 120A and 120B, the components 130A, 130B, 140A and 140B, and / or the lead frame 150, and may allow the electronic devices 120A and 120B, the components 130A, 130B, 140A and 140B, and / or the lead frame 150 to exchange electrical signals with external devices. The substrate 110 is provided merely as an example substrate for better understanding of the present disclosure. In some examples, the substrate 110 may have a single-layer structure rather than a multi-layer structure. In addition, substrates having various structures not yet illustrated or described may be applied to the present disclosure.

[0042] Figure 3B The electronic devices 120A and 120B and / or components 130A and 130B are shown mounted on the substrate 110 at a later stage of manufacturing. Figure 3B In the example shown, electronic devices 120A and 120B may be disposed on the top side of substrate 110 and may be connected to upper wiring patterns 112a of substrate 110. In some examples, electronic devices 120A and 120B may be semiconductor dies, semiconductor chips, or packages including one or more electronic devices.

[0043] In some examples, electronic devices 120A and 120B may include active and inactive areas. Furthermore, the active areas may include terminals 121. In some examples, terminals 121 may include or be referred to as die pads, bonding pads, conductive posts, or conductive pillars. Terminals 121 may include, for example, a conductive material such as a metal material, aluminum, copper, an aluminum alloy, or a copper alloy.

[0044] In some examples, an interconnect 122 may be interposed between the terminal 121 and / or the upper wiring pattern 112a to electrically connect the terminal 121 and the upper wiring pattern 112a to each other. In some examples, the interconnect 122 may include or be referred to as a bump, a solder ball, a solder tip, etc. In some examples, the electronic devices 120A and 120B having the terminal 121 and the interconnect 122 may be mounted on the upper wiring pattern 112a of the substrate 110, and the terminals 121 of the electronic devices 120A and 120B may then be electrically connected to the upper wiring pattern 112a of the substrate 110 via the interconnect 122 using a reflow process, a thermal compression process, and / or a laser-assisted bonding process. Here, the electronic devices 120A and 120B may have a thickness in the range of about 100 μm to about 1,000 μm. In some examples, electronic devices 120A and 120B may be logic dies, microcontroller units, memories, digital signal processors, network processors, power management units, audio processors, RF circuits, wireless baseband system-on-chip processors, application-specific integrated circuits, or their equivalents.

[0045] In some examples, the electronic devices 120A and 120B may alternatively be connected to the upper wiring pattern 112a of the substrate 110 via conductive wires, such as gold wires, copper wires, or aluminum wires. In the same or other examples, the inactive areas of the electronic devices 120A and 120B are adhered to the substrate 110 using an adhesive, and the terminals 121 formed in the inactive areas of the electronic devices 120A and 120B may be bonded to the upper wiring pattern 112a of the substrate 110 using the conductive wires.

[0046] In addition, Figure 3B In the example shown, components 130A and 130B can be connected to the upper wiring pattern 112b of substrate 110. In some examples, components 130A and 130B can be passive components, such as resistors, capacitors, or inductors. In some examples, components 130A and 130B can also include terminals 131.

[0047] In some examples, the interconnect 132 may be inserted between the terminal 131 and / or the upper wiring pattern 112b to be electrically connected to each other. In some examples, after the components 130A and 130B having the terminal 131 and the interconnect 132 are mounted on the upper wiring pattern 112b of the substrate 110, the terminals 131 of the components 130A and 130B may be electrically connected to the upper wiring pattern 112b of the substrate 110 via the interconnect 132 using a reflow process, a hot pressing process, and / or a laser-assisted bonding process. Here, the components 130A and 130B may have a thickness in the range of about 100 μm to about 10,000 μm. In addition, the thickness of the components 130A and 130B may be greater than or less than the thickness of the electronic devices 120A and 120B.

[0048] Figure 3C Lead frame 150 is shown with components 140A and 140B mounted thereon. In some examples, components 140A and 140B can include terminals 141. In some examples, components 140A and 140B can be mounted on the top side of lead frame 150 and can be connected between connecting bars 153 and leads 154 of lead frame 150 via terminals 141 and interconnects 142. In some examples, components 140C and 140D can be connected via terminals 141 and interconnects 142 (see FIG. Figure 2 ) are electrically connected between the leads 154 of the lead frame 150.

[0049] In some examples, interconnects 142, such as solder paste, may first be formed on connecting bars 153 and leads 154 and / or leads 154 using dispensing, stencil printing, or the like. Thereafter, components 140A and 140B having terminals 141 may be positioned on solder paste 142 and then electrically and / or mechanically connected to lead frame 150 using a reflow process, a heat press process, and / or a laser-assisted bonding process. In some examples, the thickness of components 140A and 140B may be equal to or less than the height of downwardly disposed portion 153a. In some examples, components 140A and 140B may have a thickness ranging from approximately 100 μm to approximately 10,000 μm.

[0050] Figure 3D The lead frame 150 is shown connected to the top side of the substrate 110 at a later stage of manufacture. Figure 3D In the illustrated example, the connection region 154 c of the lead frame 150 may be electrically, mechanically, and / or thermally connected to the upper wiring pattern 112 c disposed on the substrate 110 via the interconnection 155 .

[0051] In some examples, in a state where an interconnect 155, such as solder paste, is formed on the upper wiring pattern 112 c of the substrate 110 and the connection area 154 c of the lead frame 150 is located thereon, the lead frame 150 can be electrically, mechanically, and / or thermally connected to the substrate 110 using a reflow process, a heat pressing process, and / or a laser-assisted bonding process.

[0052] In some examples, the top surfaces of components 130A and 130B mounted on substrate 110 can be coupled to the bottom surface of pads 151 of leadframe 150. Such coupling can be achieved directly or using a coupling material (e.g., thermal interface material (TIM) or adhesive) between pads 151 and components 130A and 130B. As a result, heat generated from components 130A and 130B can be quickly dissipated through leadframe 150.

[0053] In some examples, the top surfaces of the electronic devices 120A and 120B mounted on the substrate 110 can be coupled to the bottom surfaces of the connecting bars 153 and / or leads 154 of the lead frame 150. Such coupling can be achieved directly or using a coupling material (e.g., a thermal interface material (TIM) or adhesive) between the connecting bars 153 and / or leads 154 and the electronic devices 120A and 120B. As a result, heat generated from the electronic devices 120A and 120B can also be quickly dissipated via the lead frame 150.

[0054] In addition, since lead frame 150 generally surrounds electronic devices 120A and 120B and / or components 130A and 130B, it is possible to shield electronic devices 120A and 120B and / or components 130A and 130B from electromagnetic interference (EMI). Furthermore, since connection area 154c of lead frame 150 is also electrically, mechanically, and / or thermally connected to substrate 110 via interconnect 155, heat from substrate 110 can also be quickly dissipated via lead frame 150. Here, components 140A, 140B, 140C, and 140D positioned on lead frame 150 and substrate 110 can exchange electrical signals via interconnect 155.

[0055] Figure 3E The resulting state is shown after encapsulation is performed using encapsulant 160 at a later stage of manufacturing. Figure 3EIn the example shown, encapsulant 160 may be disposed on the top side of substrate 110 and may encapsulate electronic devices 120A and 120B, components 130A, 130B, 140A, and 140B, and leadframe 150 mounted on the top side of substrate 110. In some examples, encapsulant 160 may not encapsulate the top surface of pads 151 of leadframe 150. Thus, the top surface of encapsulant 160 may be coplanar with the top surface of pads 151. In some examples, coplanar may mean that the top surface of pads 151 or leadframe 150 may be substantially in the same plane as the top surface of encapsulant 160, with some tolerance. In some examples, the top surface of the pad 151 or lead frame 150 can have an average flatness of 0.005 mm per 2.54 mm of lateral distance, measured from the center of the pad 151 or lead frame 150 to any of its corners. In some examples, the top surface of the pad 151 or lead frame can have a flatness that deviates from the flat top surface of the pad 151 or lead frame 150 by no more than a total of 0.02 mm. In this manner, the top surface of the pad 151 can be exposed to the outside through the encapsulation 160, thereby further enhancing the heat dissipation performance of the lead frame 150. In some examples, the top surface of the pad 151 or lead frame 150 can protrude slightly above the top surface of the encapsulation 160, or the top surface of the pad 151 or lead frame 160 can be slightly recessed relative to the top surface of the encapsulation 160. It should be noted that these are merely examples describing the relationship between the top surface of the pad 151 or lead frame 150 and the top surface of the encapsulant 160 , and the scope of the present disclosure is not limited in these respects.

[0056] In some examples, encapsulant 160 may include or be referred to as an epoxy molding compound, epoxy molding resin, or sealant. Furthermore, in some examples, encapsulant 160 may include or be referred to as a molding portion, a sealing portion, an encapsulating portion, a protective portion, an encapsulation, or a body portion. In some examples, encapsulant 160 may include, but is not limited to, an organic resin, an inorganic filler, a curing agent, a catalyst, a colorant, a flame retardant, and the like.

[0057] The molded portion of the encapsulant 160 can be formed using any of a variety of processes. In some examples, the molded portion 160 can be formed using, but is not limited to, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, paste printing, or film-assisted molding. The encapsulant 160 can have a thickness ranging from approximately 200 μm to approximately 10,000 μm. The encapsulant 160 can encapsulate the lead frame 150 on which the electronic devices 120A and 120B, components 130A and 130B, and components 140A and 140B are mounted, thereby protecting the encapsulated electronic devices 120A and 120B, components 130A and 130B, and components 140A and 140B from external factors or conditions.

[0058] Figure 3F The connection process of the external interconnect 170 is shown at a later stage of manufacturing. Figure 3F In the example shown, the external interconnect 170 can be connected to the lower wiring pattern 113 of the substrate 110 exposed to the outside through the lower passivation layer 117. In some examples, the external interconnect 170 may include or be referred to as a solder ball, a solder bump, a conductive ball, a conductive bump, a copper pillar, a copper pillar, a conductive pillar, or a conductive pillar. In some examples, a volatile flux can be dotted on the exposed lower wiring pattern 113, and the external interconnect 170 can be dropped on the flux. Thereafter, the flux can be completely volatilized to be removed using a reflow process, and the external interconnect 170 can be melted to be mechanically and / or electrically connected to the lower wiring pattern 113. Next, the external interconnect 170 can be hardened using a cooling process, and then completely mechanically and / or electrically connected to the lower wiring pattern 113. In some examples, external interconnect 170 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-AU, Sn-Bi, Sn-Ag-Cu, and equivalents thereof. External interconnect 170 may allow semiconductor device 100 to connect to an external device. External interconnect 170 may have a thickness in a range of about 60 μm to about 400 μm and a width in a range of about 50 μm to about 500 μm. External interconnect 170 may be used to electrically connect semiconductor device 100 or a semiconductor package to an external device (not shown).

[0059] Figure 3G The sawing or singulation process is shown as being handled at a later manufacturing stage. Essentially, to improve the productivity of semiconductor devices 100, multiple semiconductor devices 100 and / or semiconductor packages can be manufactured in parallel on substrate 110. Therefore, the sawing or singulation process can be performed at a later manufacturing stage to complete individual semiconductor devices 100 and / or individual semiconductor packages. In some examples, encapsulant 160, leadframe 150, and substrate 110 can be sawed or singulated using a diamond blade 191 or a laser beam in the order described or in reverse order to complete individual semiconductor devices 100. In some examples, after sawing or singulation, the side surfaces of substrate 110, leadframe 150, and / or encapsulant 160 can become coplanar due to process characteristics. In some examples, the side surfaces of leads 154 of leadframe 150 can be made coplanar with the side surfaces of encapsulant 160 and substrate 110.

[0060] Figures 4A to 4C Plan and cross-sectional views of an example method for mounting components 140A, 140B, 140C, and 140D on an example lead frame 150 are shown. Figure 4A Plan and cross-sectional views of an example lead frame 150 are shown.

[0061] exist Figure 4A In the example shown, the lead frame 150 may have a generally rectangular shape and may include, for example, three units 158. Here, a single unit 158 ​​may be incorporated into a discrete semiconductor device 100 at a later stage. In some examples, the units 158 may be arranged in a row or matrix. In some examples, each unit 158 ​​may include a pad 151, a tie bar 152 having one end connected to the pad 151 and the other end connected to the frame 157, a connecting bar 153 connected between the tie bars 152, and a lead 154 connected to the frame 157 and then extending toward the pad 151 or the connecting bar 153. In some examples, the tie bar 152 may include downwardly disposed portions 152a and 152b formed at opposite ends thereof. In some examples, the connecting bar 153 may be connected to the pad 151 via a downwardly disposed portion 153a. In some examples, the lead 154 may include a mounting region 154a extending toward the connecting bar 153, a connecting region 154c connected to the frame 157, and a downwardly disposed portion 154b formed between the mounting region 154a and the connecting region 154c. In this manner, when manufacturing the semiconductor device 100, the pad 151 and the connecting bar 153 may be supported by connecting the tie bar 152 to the frame 157 and connecting one end of the lead 154 to the frame 157.

[0062] Figure 4B 1 shows a plan view showing a state where the interconnection member 142 is formed on the lead frame 150. Figure 4B In the example shown, interconnects 142 may be pre-formed on the regions of leadframe 150 where components 140A, 140B, 140C, and 140D are to be mounted. In some examples, interconnects 142 may be formed on mounting regions 154a of adjacent leads 154. In some examples, interconnects 142 may be formed on mounting regions 154a of adjacent leads 154 and on regions of connecting bars 153. In some examples, interconnects 142, such as solder paste, may be pre-formed on mounting regions 154a of adjacent leads 154 and / or connecting bars 153 using a universal dispenser.

[0063] Figure 4C A plan view is shown showing a state where components 140A, 140B, 140C, and 140D are mounted on a lead frame 150. Figure 4CIn the example shown, components 140A, 140B, 140C, and 140D can be mounted on a region of lead frame 150 where interconnects 142 are formed. In some examples, components 140A and 140B can be mounted on interconnects 142 formed on mounting regions 154 a of adjacent leads 154 and regions of tie bars 153. In some examples, components 140C and 140D can be mounted on interconnects 142 formed on mounting regions 154 a of adjacent leads 154. In some examples, components 140A, 140B, 140C, and 140D can be electrically connected to lead frame 150 using a reflow process, a heat press process, and / or a laser-assisted bonding process.

[0064] Through Figure 3D , the lead frame 150 on which the components 140A, 140B, 140C, and 140D are mounted may be electrically, mechanically, and / or thermally connected to the upper wiring pattern 112 c of the substrate 110 via the interconnects 155. In some examples, the connection regions 154 c of the lead frame 150 may be connected to the upper wiring pattern 112 c of the substrate 110.

[0065] In addition, Figure 3E In the sawing process shown in FIG, a diamond blade or a laser beam may be used to saw the encapsulation 160, the substrate 110, and the lead frame 150. In some examples, the encapsulation 160, the substrate 110, and the lead frame 150 may be sawed along the Figure 4C The dotted lines shown in FIG. 1 and FIG. 2 saw the lead frame 150. Therefore, due to the sawing process, the pads 151 and the leads 154 may be electrically disconnected from each other.

[0066] Figure 5A and Figure 5B A cross-sectional view of an example method for mounting components 140A, 140B, 140C, and 140D on an example lead frame 150 is shown. Figure 5A A cross-sectional view of an example template 180 and lead frame 150 is shown.

[0067] exist Figure 5A In the example shown, template 180 may include a plurality of through-holes 181 for forming interconnects 142 (e.g., solder paste) on lead frame 150. Through-holes 181 may be formed in areas corresponding to the mounting areas of components 140A, 140B, 140C, and 140D, as described above. In some examples, template 180 may include receiving grooves 182 formed to receive pads 151 of lead frame 150. In some examples, lead frame 150 may include temporary supports 183 for supporting template 180.

[0068] Figure 5B A process for forming interconnects on an example lead frame 150 is shown. Figure 5BIn the example shown, after solder paste 142 is positioned on stencil 180, blade 185 is moved in one direction to allow solder paste 142 to be mounted on a predetermined area of ​​lead frame 150 through through-hole 181 of stencil 180. Thereafter, after stencil 180 is removed and components 140A, 140B, 140C, and 140D are then positioned, components 140A, 140B, 140C, and 140D may be mounted on lead frame 150 using a reflow process, a heat press process, and / or a laser-assisted bonding process, as described above.

[0069] Figure 6 A cross-sectional view of an example semiconductor device 200 is shown. Figure 6 In the example shown, the top surfaces of electronic devices 120A and 120B and / or the top surfaces of components 130A and 130B may be contacted or adhered to lead frame 150 .

[0070] In some examples, the top surfaces of electronic devices 120A and 120B can be coupled or adhered to the bottom surfaces of leads 154 and tie bars 153 using interfacing or covering members 210A and 210B. In some examples, the top surfaces of components 130A and 130B can be coupled or adhered to the bottom surface of pads 151 using covering members 220A and 220B. Interface members 210A, 210B, 220A, and 220B can be, for example, thermal interface materials (TIMs) and / or can include an inorganic heat dissipative coating compound having a highly thermally conductive filler (e.g., aluminum nitride (AlN), boron nitride (BN), silicon carbide (SiC), etc.) fused with a binder (e.g., a polymer resin). In the same or other examples, the cover members 210A, 210B, 220A, and 220B may be a thermally conductive coating material comprising a heat-resistant binder, a thermally conductive material, and additives prepared by a sol-gel process, and may have a high thermal conductivity of approximately 100 watts per meter-Kelvin (W / mK) to 400 W / mK. In some examples, the cover members 210A, 210B, 220A, and 220B may be formed on the top surfaces of the electronic devices 120A and 120B and / or the components 130A and 130B using any of a variety of processes (e.g., spray coating, dipping, or screen coating). In some examples, the cover members 210A, 210B, 220A, and 220B may have a coating thickness ranging from approximately 20 μm to approximately 40 μm. In this way, the lead frame 150 can efficiently emit heat generated from the semiconductor device 200, and the electronic devices 120A and 120B and / or components 130A and 130B can be brought into contact with or adhered to the lead frame 150 using the covering parts 210A, 210B, 220A, and 220B to enhance the heat dissipation performance of the semiconductor device 200.

[0071] Figure 7 A cross-sectional view of an example semiconductor device 300 is shown. Figure 7 In the illustrated example, the top surfaces and opposing side surfaces of the electronic devices 120A and 120B and / or the top surfaces and opposing side surfaces of the components 130A and 130B may be covered by cover members 310A, 310B, 320A, and 320B. The top surfaces of the electronic devices 120A and 120B and / or the top surfaces of the components 130A and 130B may be coupled to the lead frame 150 via the cover members 310A, 310B, 320A, and 320B.

[0072] In some cases, regardless of whether the top surfaces of the electronic devices 120A and 120B and / or the top surfaces of the components 130A and 130B are separated from the lead frame 150 or regardless of whether the top surfaces of the electronic devices 120A and 120B and / or the top surfaces of the components 130A and 130B are coupled to the lead frame 150, the top surfaces and opposing side surfaces of the electronic devices 120A and 120B and / or the top surfaces and opposing side surfaces of the components 130A and 130B may be coated with covering members 310A, 310B, 320A, 320B (which are thermally and / or electrically conductive materials), as long as there is no risk of electrical shorting of the lead frame 150. In some examples, the cover members 310A, 310B, 320A, and 320B may comprise an inorganic heat-dissipating coating composite having a high-thermal-conductivity filler (e.g., carbon fiber, graphite, carbon nanotubes, graphene, etc.) fused with a binder (e.g., a polymer resin). Here, the aforementioned high-thermal-conductivity filler, such as carbon fiber, graphite, carbon nanotubes, or graphene, may have very high thermal conductivity in the axial or surface direction, but relatively low thermal conductivity in the orthogonal direction. Therefore, the high-thermal-conductivity filler can be prepared into a composite material by controlling the orientation of such a heat-dissipating filler.

[0073] In some examples, the cover members 310A, 310B, 320A, and 320B may have a thermal conductivity of approximately 100 W / mK to 400 W / mK and / or an electrical conductivity in the range of approximately 3.0 Siemens per centimeter (S / cm) to approximately 5.0 S / cm, and thus may perform a heat dissipation function and / or an electromagnetic interference (EMI) shielding function. In some examples, the lead frame 150 may perform not only a heat dissipation function but also an EMI shielding function. As described above, the cover members 310A, 310B, 320A, and 320B, which are thermally and electrically conductive materials, may further surround the electronic devices 120A and 120B and / or the components 130A and 130B to enhance the heat dissipation performance and / or EMI shielding performance of the semiconductor device 300.

[0074] This disclosure includes references to certain examples. However, those skilled in the art will understand that various changes may be made and equivalents may be substituted without departing from the scope of this disclosure. In addition, modifications may be made to the disclosed examples without departing from the scope of this disclosure. Therefore, it is intended that this disclosure is not limited to the disclosed examples, but rather that the disclosure will encompass all examples within the scope of the appended claims.

Claims

1. A semiconductor device comprising: a substrate and an electronic device on a top side of the substrate; a lead frame on the top side of the substrate above the electronic device, wherein the lead frame includes tie bars and leads; an assembly on a top side of the lead frame mounted to the tie bars and the leads; and an encapsulation on the top side of the substrate, wherein the encapsulation contacts a side of the electronic device and a side of the component; wherein the assembly comprises a first terminal coupled to a top side of the connecting bar and a second terminal coupled to a top side of the lead; and The top side of the encapsulant is coplanar with the top side of the lead frame. 2 . The semiconductor device according to claim 1 , wherein the lead frame includes a pad and a downwardly disposed portion from the pad to the connecting bar, wherein the component is mounted to the connecting bar and the lead at a level lower than a top side of the pad. 3 . The semiconductor device of claim 2 , further comprising additional components on the top side of the substrate below the pad. The semiconductor device of claim 3 , wherein the additional component is thermally coupled to the pad. The semiconductor device according to claim 1 , wherein the electronic device is below the component. 6 . The semiconductor device of claim 1 , wherein a gap is formed between the tie bar and the lead, and the component on the top side of the lead frame is mounted across and over the gap. The semiconductor device according to claim 1 , wherein the substrate comprises a prefabricated substrate.

8. The semiconductor device of claim 1, wherein the substrate comprises a redistribution layer (RDL) substrate. 9 . The semiconductor device of claim 1 , wherein the lead includes a connection area electrically coupled to a conductive path of the substrate. 10 . The semiconductor device of claim 1 , wherein the first terminal and the second terminal are on a bottom side of the component.

11. A method for manufacturing a semiconductor device, comprising: providing a substrate having a top side; providing an electronic device on the top side of the substrate; mounting a component on a top side of a lead frame, wherein the component is mounted between tie bars and leads of the lead frame; connecting the lead frame to the top side of the substrate; as well as providing an encapsulation on the top side of the substrate that contacts a side of the electronic device and a side of the component; wherein a gap is provided between the tie bar and the lead, and the component is mounted on the top side of the lead frame to span over the gap; and Wherein mounting the assembly includes providing interconnects on the tie bars and the leads and electrically connecting the assembly to the lead frame at the interconnects.

12. The method of claim 11, further comprising providing additional components onto the top side of the substrate. The method of claim 12 , wherein the additional component is below a pad of the lead frame.

14. The method of claim 12, further comprising thermally coupling the additional component to the lead frame.

15. A semiconductor structure comprising: a substrate having a top side and a conductive path; a lead frame comprising a heat sink, a connecting bar, a downwardly disposed portion between the heat sink and the connecting bar, and a lead electrically coupled to the conductive path, wherein the connecting bar is lower than the heat sink; a first component on the top side of the substrate and coupled to the heat sink; a second component on a top side of the lead frame between the tie bars and the leads; an encapsulant on the top side of the substrate contacting a side of the second component; wherein the lead comprises a mounting area, a connection area, and an additional downwardly disposed portion between the mounting area and the connection area; and wherein the lead is electrically coupled to the conductive path at the connection region; as well as An electronic device is on the top side of the substrate, below the mounting area, and below the second component.

16. The semiconductor structure of claim 15, further comprising an interface component between a top side of the first component and a bottom side of the heat sink. The semiconductor structure of claim 16 , wherein the interface component comprises a thermal interface material.

18. The semiconductor structure of claim 15, wherein the electronic device is thermally coupled to the lead frame.

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