Semiconductor module and power conversion device

Abstract

The semiconductor module (1) comprises: an upper branch module (3) including semiconductor chips (7, 9, 11); and a lower branch module (13) including semiconductor chips (7, 9, 11). The lower branch module (13) comprises: a relative arrangement portion (81) in which a lead frame (31) and a lead frame (32) are arranged so that the main surface of the strip-shaped lead frame (31) and the main surface of the strip-shaped lead frame (32) are opposite to each other; and a non-relative arrangement portion (83) in which the lead frame (31) and the lead frame (32) are arranged so that the main surface of the lead frame (31) and the main surface of the lead frame (32) are not opposite to each other.

Description

Technical Field

[0001] The present invention relates to a semiconductor module and a power conversion device, and in particular to a semiconductor module having a direct wire bonding structure and a power conversion device using the semiconductor module. Background Art

[0002] In recent years, the demand for high-speed driving has also increased from the perspective of long-term reliability and loss reduction of semiconductor modules. As one of the solutions to achieve both, there is a DLB (Direct Lead Bonding) structure in which a lead frame is directly bonded to a semiconductor chip using a bonding material such as solder.

[0003] In the case of a DLB structure, generally, compared to a wire bonding structure, the life span can be extended and the parasitic inductance that hinders high-speed driving can be easily reduced, but compared to a wire bonding structure, there are more design restrictions. For example, in semiconductor chips connected in parallel, there is a problem that the current between the semiconductor chips connected in parallel is easily offset due to the influence of different parasitic inductances in the current loop of each semiconductor chip.

[0004] A semiconductor module that solves such a problem is proposed in Patent Document 1. In the semiconductor module proposed in Patent Document 1, wiring conductors are completely opposed to each other to reduce parasitic inductance, and parasitic inductance in current loops between semiconductor chips electrically connected in parallel is equalized to make current between semiconductor chips uniform.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2015-018943 Summary of the invention

[0008] In the conventional method, when the number of semiconductor chips electrically connected in parallel is two, the effect of equalizing the current between the semiconductor chips can be obtained. However, when three or more semiconductor chips are electrically connected in parallel in the same direction, a portion with excessive mutual inductance may be formed sometimes. In addition, on the contrary, a portion with excessive mutual inductance may be formed sometimes. Therefore, it is difficult to equalize the current between the semiconductor chips, and sometimes it is impossible to eliminate the offset of the current between the semiconductor chips electrically connected in parallel.

[0009] The present invention has been made to solve the above-mentioned problems, and one object is to provide a semiconductor module capable of eliminating the current deviation between semiconductor chips, and another object is to provide a power conversion device using such a semiconductor module.

[0010] The semiconductor module involved in the present invention has a substrate, a plurality of semiconductor chips, a first wiring conductor and a second wiring conductor. The substrate has a main surface and includes at least any material of a conductor and an insulator. The plurality of semiconductor chips are respectively mounted on the main surface of the substrate. The first wiring conductor is electrically connected to each of the plurality of semiconductor chips in a manner that the plurality of semiconductor chips are electrically connected in parallel. The second wiring conductor is electrically connected to the first wiring conductor. In the first wiring conductor and the second wiring conductor, there are provided a relative configuration portion in which the first wiring conductor and the second wiring conductor are arranged in a manner opposite to each other and a non-relative configuration portion in which the first wiring conductor and the second wiring conductor are arranged in a manner that they are not opposite to each other.

[0011] The power conversion device according to the present invention comprises: a main conversion circuit having the semiconductor module described above and converting input power to output the converted power; and a control circuit outputting a control signal for controlling the main conversion circuit to the main conversion circuit.

[0012] According to the semiconductor module of the present invention, the opposing arrangement portion and the non-opposing arrangement portion are provided in the first wiring conductor and the second wiring conductor, so that the current flowing through each of the plurality of semiconductor chips can be made uniform.

[0013] According to the power conversion device according to the present invention, by including the semiconductor module, it is possible to make the current flowing through each of the plurality of semiconductor chips uniform. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a circuit diagram of a semiconductor module according to each embodiment of the present invention.

[0015] Figure 2 This is a partial top view of the semiconductor module according to the first embodiment of the present invention.

[0016] Figure 3 In this embodiment, Figure 2 A partial cross-sectional view along section line III-III is shown.

[0017] Figure 4 1 is a partial cross-sectional view showing an opposing arrangement portion and a non-opposing arrangement portion in the semiconductor module in this embodiment.

[0018] Figure 5 This is a diagram showing an outline of an equivalent circuit of a semiconductor module in this embodiment.

[0019] Figure 6 FIG. 1 is a partial cross-sectional view showing a semiconductor module sealed with a sealing material in this embodiment.

[0020] Figure 7 It is a partial cross-sectional view of a semiconductor module according to a modification of the embodiment.

[0021] Figure 8 It is a partial cross-sectional view showing an opposing arrangement portion and a non-opposing arrangement portion in a semiconductor module according to a modification example of the embodiment.

[0022] Fig. 9 It is a partial cross-sectional view of a semiconductor module according to Embodiment 2 of the present invention.

[0023] Fig.10 1 is a partial cross-sectional view showing an opposing arrangement portion and a non-opposing arrangement portion in the semiconductor module in this embodiment.

[0024] Fig.11 It is a partial cross-sectional view of a semiconductor module according to a modification of the embodiment.

[0025] Fig.12 It is a partial cross-sectional view showing an opposing arrangement portion and a non-opposing arrangement portion in a semiconductor module according to a modification example of the embodiment.

[0026] Fig.13 This is a partial top view of a semiconductor module according to Embodiment 3 of the present invention.

[0027] Fig.14 In this embodiment, Fig.13 A partial cross-sectional view along section line XIV-XIV is shown.

[0028] Fig.15 1 is a partial plan view showing an opposing arrangement portion and a non-opposing arrangement portion in the semiconductor module in this embodiment.

[0029] Fig.16 In this embodiment, Fig.15 A partial cross-sectional view of the opposing arrangement portion and the non-opposing arrangement portion of the semiconductor module taken along the section line XVI-XVI is shown.

[0030] Fig.17 This is a block diagram of a power conversion device using a semiconductor module according to a fourth embodiment of the present invention.

[0031] (Explanation of symbols)

[0032] 1: semiconductor module; 3: upper branch module; 5: upper branch element; 7, 9, 11, 17, 19, 21: semiconductor chip; 13: lower branch module; 15: lower branch element; 31, 32, 33, 34, 35, 36, 37, 38, 39: lead frame; 41: substrate; 43: insulator; 45, 47: conductor; 61, 62, 63, 64, 65, 66, 67, 68, 69: bonding material; 71: sealing material; 73: heat sink; 81: relative configuration part; 83: non-relative configuration part; P, N: terminals; AC: external terminal; G: gate electrode; S: source electrode. DETAILED DESCRIPTION

[0033] First, a circuit diagram of a semiconductor module according to each embodiment will be described. Figure 1 FIG. 1 shows a circuit diagram of a semiconductor module 1. Figure 1 As shown, the semiconductor module 1 corresponds to one phase of a three-phase inverter. A three-phase motor (not shown) is driven by electrically connecting three semiconductor modules 1 in parallel. In addition, the semiconductor module 1 can also be used as a single-phase inverter or a single-phase converter.

[0034] The semiconductor module 1 has a terminal P, a terminal N, and an external terminal AC. The terminal P is electrically connected to the anode of the power source or the anode of the smoothing capacitor. The terminal N is electrically connected to the cathode of the power source or the cathode of the smoothing capacitor. The external terminal AC is electrically connected to a motor or the like.

[0035] The semiconductor chips 7, 9, 11 electrically connected in parallel between the terminal P and the external terminal AC are referred to as upper arm elements 5. The semiconductor chips 7, 9, 11 constitute an upper arm module 3 as a part of the semiconductor module 1.

[0036] The semiconductor chips 17, 19, 21 electrically connected in parallel between the external terminal AC and the terminal N are referred to as lower arm elements 15. The semiconductor chips 17, 19, 21 form a lower arm module 13 as another part of the semiconductor module 1.

[0037] In each of the upper arm element 5 and the lower arm element 15 in the semiconductor module 1, three MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are electrically connected in parallel. Figure 1 In the circuit diagram of the semiconductor module 1 shown, only MOSFETs are used as the upper arm element 5 and the lower arm element 15 , respectively. However, the MOSFETs and freewheeling diodes may be electrically connected in anti-parallel.

[0038] In addition, an IGBT (Insulated Gate Bipolar Transistor) and a freewheeling diode may be electrically connected in anti-parallel instead of a MOSFET. Furthermore, three semiconductor chips are electrically connected in parallel in each of the upper arm element 5 and the lower arm element 15, but four or more semiconductor chips may be electrically connected in parallel.

[0039] like Figure 1 As shown, in each of the MOSFETs of the upper branch element and the lower branch element, a gate electrode G and a source electrode S are provided as control electrodes. As control electrodes of the MOSFET, in addition to the gate electrode G and the source electrode S, for example, an electrode connected to a temperature sensing diode for detecting the temperature of a semiconductor chip may also be provided. Alternatively, an electrode connected to a current detection diode for detecting a current flowing through a semiconductor chip may also be provided. The structure of the semiconductor module 1 is described in detail below. In addition, in each embodiment, for ease of description, the XYZ coordinate axis is used for description.

[0040] Implementation method 1.

[0041] Here, a first example of the lower arm module 13 as a part of the semiconductor module 1 will be described.

[0042] like Figure 2 as well as Figure 3 As shown, the lower arm module 13 includes semiconductor chips 17, 19, and 21. The semiconductor chips 17, 19, and 21 are mounted on a substrate 41 as a base material. The substrate 41 includes, for example, an insulator 43, a conductor 45, and a conductor 47. The conductor 45 is bonded to one surface of the insulator 43. The conductor 47 is bonded to the back surface of the insulator 43.

[0043] The semiconductor chip 17 is thermally and electrically connected to the conductor 45 via the conductive bonding material 61. The semiconductor chip 19 is thermally and electrically connected to the conductor 45 via the conductive bonding material 62. The semiconductor chip 21 is thermally and electrically connected to the conductor 45 via the conductive bonding material 63.

[0044] The conductor 45 and the conductor 47 are each formed of a metal such as copper or aluminum. For example, the insulator 43 is formed of an insulating sheet made of ceramics such as silicon nitride or aluminum nitride or a resin. The conductor 47 is preferably used from the viewpoint of long-term reliability and heat dissipation, but is not necessarily required. As the bonding materials 61, 62, and 63, for example, solder, silver, copper, etc. are used.

[0045] The conductor 45 is electrically connected to the lead frame 33 by the bonding material 68. The lead frame 33 and the external terminal AC (see Figure 1) is electrically connected. The lead frame 33 is formed of a metal such as copper. The bonding material 68 is made of, for example, solder, silver, copper, or the like. Instead of the bonding material 68, the lead frame 33 may be directly bonded to the conductor 45 using ultrasound or laser. In addition, instead of the lead frame 33, a wire or a ribbon made of metal may be used.

[0046] The lead frame 32 is electrically connected to the upper surface of the semiconductor chip 17 via a bonding material 64. The lead frame 32 is electrically connected to the upper surface of the semiconductor chip 19 via a bonding material 65. The lead frame 32 is electrically connected to the upper surface of the semiconductor chip 21 via a bonding material 66. The lead frame 32 is used as a first wiring conductor. For example, solder, silver, copper, etc. are used for the bonding materials 64, 65, and 66. The lead frame 32 is formed of a metal such as copper, for example.

[0047] The lead frame 32 is electrically connected to the lead frame 31 through the bonding material 67. The lead frame 31 is connected to a portion of the lead frame 32 located between the semiconductor chip 19 and the semiconductor chip 21. The lead frame 31 is used as a second wiring conductor. The bonding material 67 is made of, for example, solder, silver, copper, etc. The lead frame 31 is made of, for example, a metal such as copper. The lead frame 31 and the lead frame 32 each have a width and extend in a strip shape. Instead of the lead frame 31 and the lead frame 32, a strip made of metal or the like may be used.

[0048] A control electrode (not shown) is formed in each of the three MOSFETs (semiconductor chips 17, 19, and 21). The control electrode is electrically connected to a control terminal through a metal wire such as aluminum, copper, or gold. The control terminal is electrically connected to an external control substrate (not shown) or the like.

[0049] The control substrate has a function of outputting a signal for turning on and off the MOSFETs of the semiconductor chips 17, 19, and 21. In addition, the control substrate has a function of detecting an overvoltage or an excessive rise in chip temperature. The control substrate can be provided inside or outside the semiconductor module 1.

[0050] The conductor 47 is connected to the heat sink 73 for heat dissipation. When the conductor 47 is connected, a bonding member such as grease, an insulating sheet, solder, etc. (all not shown) or a metal etc. may be interposed between the conductor 47 and the heat sink 73. In addition, a structure in which a fin is directly formed on the conductor 47 may also be adopted.

[0051] In the semiconductor module 1, the semiconductor chips 17, 19, 21, etc. are sealed by a sealing material 71 in order to ensure insulation and the like (see Figure 6As the sealing material 71, for example, gel, epoxy resin, etc. are used. In addition, a housing (not shown) used when hardening the sealing material 71 may be provided as needed.

[0052] like Figure 2 As shown, in the lower branch module 13, the semiconductor chips 17, 19, 21 are arranged along the X-axis at intervals. The strip-shaped lead frame 31 and the lead frame 32 are arranged to extend in the X-axis direction corresponding to the arrangement of the semiconductor chips 17, 19, 21. Figure 4 As shown, in the lower arm module 13 , a facing arrangement portion 81 is provided in which the lead frame 31 and the lead frame 32 are arranged so that the main surface of the strip-shaped lead frame 31 and the main surface of the strip-shaped lead frame 32 face each other.

[0053] On the other hand, from the portion of the lead frame 31 where the lead frame 31 is bonded to the lead frame 32 to the end portion of the lead frame 32, the lead frame 32 is not opposed to the lead frame 31. This portion is a non-opposing arrangement portion 83 where the main surface of the lead frame 31 and the main surface of the lead frame 32 are not opposed to each other. The area where the main surface of the lead frame 31 and the main surface of the lead frame 32 are opposed in the opposing arrangement portion 81 is larger than the area where the main surface of the lead frame 31 and the main surface of the lead frame 32 are not opposed to each other in the non-opposing arrangement portion 83.

[0054] In the opposed arrangement portion 81, when the semiconductor chips 17, 19, and 21 are turned on, a current flows in the positive direction of the X axis through the lead frame 32. On the other hand, a current flows in the negative direction of the X axis through the lead frame 31. That is, in the opposed arrangement portion 81, the direction of the current flowing through the lead frame 31 and the direction of the current flowing through the lead frame 32 are opposite.

[0055] Therefore, the magnetic field generated by the current flowing through the lead frame 31 and the magnetic field generated by the current flowing through the lead frame 32 cancel each other out. By canceling out the two magnetic fields, the parasitic inductance of the semiconductor module 1 can be reduced.

[0056] Here, parasitic inductance is explained. Figure 5 In the figure, the main parasitic inductance is recorded to show the Figure 3 The circuit diagram corresponds to the arrangement relationship of the semiconductor chips 7, 9, 11 and the lead frames 31, 32 in the lower branch module 13 shown.

[0057] like Figure 3 as well as Figure 5 As shown, in the lead frame 32, there is a self-inductance L caused by a portion (portion A) of the lead frame 32 located between the source side of the semiconductor chip 17 and the source side of the semiconductor chip 19. AIn addition, in the lead frame 32, there is a self-inductance L caused by a portion (portion B) of the lead frame 32 located between the source side of the semiconductor chip 19 and the portion where the lead frame 31 is bonded by the bonding material 67. B Furthermore, there is a self-inductance L caused by a portion of the lead frame 32 located between a portion of the lead frame 31 bonded by the bonding material 67 and the source side of the semiconductor chip 21. C .

[0058] In addition, a voltage is induced in the lead frame 32 by the current flowing through the lead frame 31. At this time, the component of the mutual inductance associated with the portion A of the lead frame 32 and the portion of the lead frame 31 corresponding to the portion A is referred to as the mutual inductance M. A The component of the mutual inductance associated with the portion B of the lead frame 32 and the portion of the lead frame 31 corresponding to the portion B is defined as the mutual inductance M. B In addition, there is mutual inductance caused by the current flowing through the conductor 45, but the influence is small and is therefore ignored here.

[0059] The current flowing through each of the semiconductor chips 17, 19, and 21 is strongly affected by the magnitude of the voltage between the gate and the source when the semiconductor chips 17, 19, and 21 are turned on. The gates of the semiconductor chips 17, 19, and 21 are electrically connected in parallel, and the sources are also electrically connected in parallel. However, on the source side, due to the inductance of the circuit of the lower branch module 13, different induced voltages are sometimes generated when the current changes. The difference in the generated induced voltage will cause the current to be uneven, so in the lower branch module 13 (semiconductor module 1), it is best to have a structure in which the source potential of each of the semiconductor chips 17, 19, and 21 becomes uniform.

[0060] Here, the voltage at the portion where the lead frame 31 is bonded to the lead frame 32 is set as the reference voltage V s_N The current flowing through the semiconductor chip 17 is set to I 17 , the current flowing through the semiconductor chip 19 is set to I 19 , the current flowing through the semiconductor chip 21 is set to I 21 The voltage on the source side of the semiconductor chip 17 is set to V s_17 , the voltage on the source side of the semiconductor chip 19 is set to V s_19 , the voltage on the source side of the semiconductor chip 21 is set to V s_21 .

[0061] Therefore, the voltage on the source side of each of the semiconductor chips 17 , 19 , and 21 is expressed by the following equations (1), (2), and (3).

[0062] V s_21 -V s_N=L C ·d(I 21 ) / dt…(1)

[0063] V s_19 -V s_N =L B ·d(I 17 +I 19 ) / dt-M B ·d(I 17 +I 19 +I 21 ) / dt…(2)

[0064] V s_17 -V s_N =L A ·d(I 17 ) / dt+L B ·d(I 17 +I 19 ) / dt-(M A +M B )·d(I 17 +I 19 +I 21 ) / dt…(3)

[0065] When it is assumed that the impedance of the wiring of the control system in each of the semiconductor chips 17, 19, and 21 is the same, and when it is assumed that the characteristics of the semiconductor chips 17, 19, and 21 are the same, when current flows uniformly, and when the uniformly flowing current is set to I, the following equations (4) and (5) are satisfied.

[0066] I 17 =I 19 =I 21 =I…(4)

[0067] V s_17 =V s_19 =V s_21 …(5)

[0068] According to equations (1) to (5), the following relationships of equations (6) and (7) are obtained.

[0069] L A =3M A …(6)

[0070] L C =2L B -3M B …(7)

[0071] When the distance between the lead frame 31 and the lead frame 32 is adjusted so as to satisfy the equation (6), the following equation (8) is also satisfied according to the structure of the lower arm module 13 .

[0072] L B =3M B …(8)

[0073] When equation (8) is substituted into equation (7), the following relationship of equation (9) is obtained.

[0074] L C =2L B -3M B =L B …(9)

[0075] In the above-mentioned ideal conditions, first, the lead frame interval is set so as to satisfy the formula (6). Then, the lead frame 31 is bonded to the lead frame 32 via the bonding material 67 at the midpoint between the semiconductor chip 19 and the semiconductor chip 21 so as to satisfy the formula (9). By arranging the lead frame 31 and the lead frame 32 in this way, the current flowing through each semiconductor chip 17, 19, 21 can be completely uniform.

[0076] However, in reality, the optimum position of the joint portion of the lead frame 31 and the lead frame 32 may deviate from the midpoint due to the difference in impedance of the control wiring or the deviation in the characteristics of the semiconductor chip, etc. However, it is usually not used under the condition that the joint portion must be moved to the end of the side where the semiconductor chip 21 is arranged or the end of the side where the semiconductor chip 17 is arranged.

[0077] Therefore, even when there are variations in the characteristics of the semiconductor chips 17, 19, 21, by providing the non-opposing arrangement portion 83 where a portion of the lead frame 31 and the lead frame 32 are not opposed to each other, the non-opposing arrangement portion 83 becomes an adjustment margin for the variations in the characteristics of the semiconductor chips 17, 19, 21, and the current flowing through each semiconductor chip 17, 19, 21 can be made uniform. A >3M A , L B >3M B In the case of L, the connection position of the bonding material 67 is moved in the negative direction of the X axis to increase L C , so that the parasitic inductance can be adjusted in a manner that makes it uniform.

[0078] Thus, in the lower arm module 13 (semiconductor module 1), as the arrangement structure of the lead frame 31 and the lead frame 32, the relative arrangement portion 81 and the non-relative arrangement portion 83 are provided, so that the DLB structure excellent in terms of long-term reliability and parasitic inductance can be adopted, and the deviation of the current of the semiconductor chips 17, 19, and 21 electrically connected in parallel can be suppressed. The upper arm module 3 is also arranged with semiconductor chips 7, 9, and 11 in the same manner as the lower arm module 13 (see Figure 1 ) and a lead frame (not shown).

[0079] In the semiconductor module 1 described above, the case where the lead frame 31 and the lead frame 32 are bonded together by the bonding material 67 has been described. However, a lead frame in which two lead frames are integrated may be used for connection.

[0080] In addition, if Figure 6 As shown, in the semiconductor module 1, the sealing material 71 as an insulating material is sealed, and the sealing material 71 exists between the lead frame 31 and the lead frame 32. Therefore, even when the lead frame 31 is brought close to the lead frame 32, electrical insulation can be ensured.

[0081] Thus, when the current flowing through lead frame 31 and the current flowing through lead frame 32 flow in opposite directions, the magnetic field is cancelled out, thereby reducing parasitic inductance. Insulating material different from sealing material 71 may be provided between lead frame 31 and lead frame 32 .

[0082] like Figure 2 as well as Figure 3 As shown, the lead frame 31 and the lead frame 32 are arranged opposite to each other above the conductor 45, so that the lower arm module 13 can be miniaturized, the length of the conductor 45 can be shortened, and the parasitic inductance can be reduced. That is, by arranging the relative arrangement portion 81 on the side opposite to the side where the substrate 41 is arranged with respect to the semiconductor chips 17, 19, 21, the parasitic inductance can be reduced.

[0083] In addition, if Figure 7 as well as Figure 8 As shown, a lead frame 34 may be used instead of the lead frame 31. The lead frame 34 has a bent portion that is different from the shape of the lead frame 31. By providing the bent portion in the lead frame 34, two different distances are set as the distance between the lead frame 34 and the lead frame 32 in the opposing arrangement portion 81 on the semiconductor chips 17, 19, and 21.

[0084] Thus, the mutual inductance M between the lead frame 34 and the lead frame 32 can be adjusted. A and mutual inductance M BIn addition to adjusting the distance between the lead frame 34 having the bent portion and the lead frame 32, the self-inductance L can also be adjusted by adjusting the width of the lead frames 31 and 32. A , L B , L C (Refer to Figure 5 ).

[0085] Furthermore, the case where the semiconductor chips 17, 19, and 21 are arranged in one row in one direction (X-axis direction) in the semiconductor module 1 (lower branch module 13) is described as an example. As for the arrangement of semiconductor chips, as long as three or more semiconductor chips are arranged in one direction, it is not limited to one row, and a structure in which the semiconductor chips are arranged in multiple rows is also possible.

[0086] However, as semiconductor chips, for example, there are semiconductor chips using wide bandgap semiconductors with a larger bandgap than silicon (Si). In semiconductor modules using wide bandgap semiconductors, for manufacturing reasons, a large number of small semiconductor chips are often used by being electrically connected in parallel. In addition, in order to reduce the power loss of the semiconductor module, the switching speed is often increased.

[0087] Therefore, the values ​​of dI / dt shown in the equations (1), (2) and (3) become larger, and in the structure of the conventional semiconductor module, the current flowing through each semiconductor chip is biased compared to the semiconductor chip made of silicon (Si), and the current tends to become non-uniform. Therefore, it is more effective to mount a semiconductor chip using a wide bandgap semiconductor as the semiconductor module 1.

[0088] Implementation method 2.

[0089] Here, a second example of the lower arm module which is a part of the semiconductor module will be described.

[0090] like Fig. 9 as well as Fig.10 As shown, in the lower branch module 13, a lead frame 35 and a lead frame 36 are arranged. The lead frame 35 is electrically connected to each of the semiconductor chips 17, 19, and 21. The lead frame 36 extends to the end of the lead frame 35 on the semiconductor chip 21 side. The lead frame 36 is bonded to the lead frame 35 from the portion of the lead frame 35 located between the semiconductor chip 19 and the semiconductor chip 21 to the end of the lead frame 35.

[0091] The portion where the lead frame 35 and the lead frame 36 face each other at a distance is the opposing arrangement portion 81. The portion where the lead frame 36 is joined to the semiconductor chip 21 through the portion of the lead frame 35 joined to the semiconductor chip 21 by the joining material 66 is the non-opposing arrangement portion 83. Figure 2 as well as Figure 3 The semiconductor modules 1 (lower arm modules 13 ) shown have the same structure, so the same reference numerals are given to the same parts, and the description thereof will not be repeated unless necessary.

[0092] Regarding the semiconductor module 1, the voltage on the source side of each of the semiconductor chips 17, 19, and 21 can be obtained in the same manner as in the case of the semiconductor module 1, and a relational expression corresponding to equation (6) and a relational expression corresponding to equation (9) can be derived. By setting the relative arrangement portion 81 and the non-relative arrangement portion 83 according to the relational expression, the current flowing through each of the semiconductor chips 17, 19, and 21 can be made uniform.

[0093] In the semiconductor module 1 described above, the lead frame 36 is bonded to the lead frame 35 from the portion of the lead frame 35 located between the semiconductor chip 19 and the semiconductor chip 21 until it reaches the end of the lead frame 35. Instead of such a structure, a bus bar that integrates the portion where the lead frame 36 is bonded to the lead frame 35 may be used.

[0094] In addition, you can also Fig.11 as well as Fig.12 As shown, a lead frame 37 is used instead of the lead frame 36. By providing the bent portion in the lead frame 37, two different distances are set as the distance between the lead frame 37 and the lead frame 35 in the facing arrangement portion 81 on the semiconductor chips 17, 19, and 21.

[0095] Thus, the mutual inductance M between the lead frame 37 and the lead frame 35 can be adjusted. A and mutual inductance M B In addition to adjusting the distance between the lead frame 37 having the bent portion and the lead frame 35, the width of the lead frames 37 and 35 can also be adjusted to adjust the self-inductance L. A , L B , L C (Refer to Figure 5 ).

[0096] Furthermore, similarly to the description in the first embodiment, it is more effective when a semiconductor chip to which a wide bandgap semiconductor is applied is mounted as the semiconductor module 1 .

[0097] Implementation method 3.

[0098] Here, a third example of the lower arm module which is a part of the semiconductor module will be described.

[0099] like Fig.13 as well as Fig.14 As shown, in the lower branch module 13, a lead frame 38 and a lead frame 39 are arranged. The lead frame 38 is formed by a first portion 38a, a second portion 38b, and a third portion 38c. The first portion 38a has a width in the Y-axis direction and extends in the X-axis direction. The second portion 38b also has a width in the Y-axis direction and extends in the X-axis direction.

[0100] The third portion 38c has a width in the Z-axis direction and extends in the X-axis direction. The third portion 38c is bent at about 90 degrees with respect to the first portion 38a and the second portion 38b. The lead frame 39 has a width in the Z-axis direction and extends in the X-axis direction.

[0101] The first portion 38a is bonded to the semiconductor chip 17 via a bonding material 64 and bonded to the semiconductor chip 19 via a bonding material 65. The second portion 38b is bonded to the semiconductor chip 21 via a bonding material 66. The third portion 38c is bonded to the lead frame 39 via a bonding material 69.

[0102] like Fig.15 as well as Fig.16 As shown in FIG. 1 , a portion where the third portion 38 c and the lead frame 39 face each other is an opposing portion 81 . A portion where the first portion 38 a and the lead frame 39 are arranged so as to intersect each other is a non-opposing portion 83 .

[0103] Regarding the semiconductor module 1, the voltage on the source side of each of the semiconductor chips 17, 19, and 21 can be obtained in the same manner as in the case of the semiconductor module 1 described in Embodiment 1, and a relational expression corresponding to equation (6) and a relational expression corresponding to equation (9) can be derived. By setting the relative arrangement portion 81 and the non-relative arrangement portion 83 according to the relational expression, the current flowing through each of the semiconductor chips 17, 19, and 21 can be made uniform.

[0104] Furthermore, by changing the surfaces opposite to the third portion 38c of the lead frame 38 and the lead frame 39, and by changing the shape of the first portion 38a of the lead frame 38, it is not only easy to adjust the self-inductance for each of the semiconductor chips 17, 19, and 21, but also it is easy to apply the upper branch module.

[0105] In the semiconductor module 1, the third portion 38c of the lead frame 38 and the lead frame 39 are bonded by the bonding material 69, but the third portion 38c of the lead frame 38 and the lead frame 39 may be bonded by welding. Alternatively, an integrated lead frame (busbar) may be used.

[0106] In addition, in the above-mentioned semiconductor module 1 (lower branch module 13), the case where semiconductor chips 17, 19, and 21 are arranged in one row in one direction (X-axis direction) is used as an example for explanation, but as long as more than three semiconductor chips are arranged in one direction, it is not limited to one row, and the semiconductor chips can also be arranged in multiple rows.

[0107] Furthermore, similarly to the description in the first embodiment, it is more effective when a semiconductor chip to which a wide bandgap semiconductor is applied is mounted as the semiconductor module 1 .

[0108] In each embodiment, the substrate 41 having the insulator 43 and the conductors 45 and 47 is described as an example. The substrate is not limited to the substrate 41, and may include at least any material of a conductor and an insulator, such as an insulating sheet or a conductive plate.

[0109] Implementation method 4.

[0110] Here, a power conversion device to which the semiconductor module 1 according to the above-mentioned Embodiments 1 to 3 is applied will be described. The present invention is not limited to a specific power conversion device, and the case where the present invention is applied to a three-phase inverter will be described below as Embodiment 4.

[0111] Fig.17 This is a block diagram showing the configuration of a power conversion system to which the power conversion device according to the present embodiment is applied. Fig.17 The power conversion system shown includes a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various power supplies, for example, it can be composed of a DC system, a solar cell, and a storage battery. In addition, it can also be composed of a rectifier circuit or an AC / DC converter connected to an AC system. In addition, the power supply 100 can also be composed of a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

[0112] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. Fig.17As shown, it includes: a main conversion circuit 201 that converts DC power into AC power and outputs it; and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201.

[0113] Load 300 is a three-phase motor driven by AC power supplied from power converter 200. Load 300 is not limited to a specific use, and is a motor mounted on various electrical devices, for example, a motor used for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioners.

[0114] The power conversion device 200 is described in detail below. The main conversion circuit 201 includes a switching element and a freewheeling diode (neither of which is shown in the figure). The DC power supplied from the power supply 100 is converted into AC power by switching the switching element and supplied to the load 300. There are various examples of the specific circuit structure of the main conversion circuit 201, but the main conversion circuit 201 involved in this embodiment is a 2-level three-phase full-bridge circuit, which can be composed of 6 switching elements and 6 freewheeling diodes connected in anti-parallel with each switching element as needed.

[0115] In at least any device of each switching element and each freewheeling diode of the main conversion circuit 201, the semiconductor module 1 involved in any of the above-mentioned embodiments 1 to 3 is configured as a semiconductor module 202. With respect to the six switching elements, every two switching elements are connected in series to form upper and lower branches, and each upper and lower branch constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. Moreover, the output terminals of each upper and lower branch, that is, the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0116] In addition, the main conversion circuit 201 is provided with a driving circuit (not shown) for driving each switching element, but the driving circuit may be built into the semiconductor module 202 or may be a structure that has the driving circuit independently of the semiconductor module 202. The driving circuit generates a driving signal for driving the switching element of the main conversion circuit 201 and supplies it to the control electrode of the switching element of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203 described later, a driving signal for turning the switching element into a conducting state and a driving signal for turning the switching element into an off state are output to the control electrode of each switching element. When the switching element is maintained in the conducting state, the driving signal is a voltage signal (conduction signal) above the threshold voltage of the switching element, and when the switching element is maintained in the off state, the driving signal is a voltage signal (off signal) below the threshold voltage of the switching element.

[0117] The control circuit 203 controls the switch elements of the main conversion circuit 201 in such a manner that the desired power is supplied to the load 300. Specifically, the time (on-time) when each switch element of the main conversion circuit 201 should be in the on state is calculated according to the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switch element according to the voltage to be output. In addition, a control instruction (control signal) is output to the drive circuit of the main conversion circuit 201 in such a manner that an on signal is output to the switch element that should be in the on state and an off signal is output to the switch element that should be in the off state at each time point. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switch element in accordance with the control signal.

[0118] In the power conversion device involved in this embodiment, the semiconductor module 1 involved in any of embodiments 1 to 3 is used as the semiconductor module 202 in at least any device of the switching element and the freewheeling diode of the main conversion circuit 201, so the reliability of the power conversion device can be improved.

[0119] In this embodiment, an example of applying the present invention to a 2-level three-phase inverter is described, but the present invention is not limited thereto and can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is used, but a 3-level or multi-level power conversion device may also be used. When power is supplied to a single-phase load, the present invention may also be applied to a single-phase inverter. In addition, when power is supplied to a DC load, the present invention may also be applied to a DC / DC converter or an AC / DC converter.

[0120] In addition, the application of the power conversion device of the present invention is not limited to the case where the above-mentioned load is an electric motor. For example, it can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system.

[0121] Furthermore, the semiconductor modules described in the respective embodiments can be combined in various ways as necessary.

[0122] The embodiments disclosed this time are illustrative and non-limiting. The present invention is indicated by the claims rather than the scope described above, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0123] Industrial Applicability

[0124] The present invention is effectively used in a semiconductor module having a direct wire bonding structure.

Claims

1. A semiconductor module comprising: A substrate having a main surface, the substrate comprising at least one of a conductor and an insulator; A plurality of semiconductor chips are mounted on the main surface of the substrate respectively; a first wiring conductor electrically connected to each of the plurality of semiconductor chips so as to electrically connect the plurality of semiconductor chips in parallel; as well as a second wiring conductor electrically connected to the first wiring conductor; In the first wiring conductor and the second wiring conductor, there are provided: an opposing arrangement portion, wherein the first wiring conductor and the second wiring conductor are arranged to be opposed to each other; as well as a non-opposing arrangement portion, wherein the first wiring conductor and the second wiring conductor are arranged so as not to be opposed to each other, The relative arrangement portion is positioned so as to straddle adjacent semiconductor chips among the plurality of semiconductor chips. In the non-opposing arrangement portion, the second wiring conductor is connected to a portion of the first wiring conductor located between a pair of adjacent semiconductor chips.

2. The semiconductor module according to claim 1, wherein: In the opposing arrangement portion and the non-opposing arrangement portion, an area of ​​a portion where the first wiring conductor and the second wiring conductor face each other is larger than an area of ​​a portion where the first wiring conductor and the second wiring conductor do not face each other.

3. The semiconductor module according to claim 1, wherein: The opposing arrangement portion is located on a side of the semiconductor chip opposite to a side where the substrate is located.

4. The semiconductor module according to claim 1, wherein: The plurality of semiconductor chips are arranged along one direction on the main surface of the substrate. The first wiring conductor and the second wiring conductor are arranged along the one direction in a plan view of the main surface.

5. The semiconductor module according to claim 1, wherein: The opposing arrangement portion and the non-opposing arrangement portion are arranged along one direction in a plan view of the main surface of the substrate.

6. The semiconductor module according to claim 1, wherein: An insulating material is filled between the first wiring conductor and the second wiring conductor.

7. The semiconductor module according to claim 1, wherein: The semiconductor chip includes a wide bandgap semiconductor.

8. A semiconductor module comprising: A substrate having a main surface, the substrate comprising at least one of a conductor and an insulator; A plurality of semiconductor chips are mounted on the main surface of the substrate respectively; a first wiring conductor electrically connected to each of the plurality of semiconductor chips so as to electrically connect the plurality of semiconductor chips in parallel; as well as a second wiring conductor electrically connected to the first wiring conductor, In the first wiring conductor and the second wiring conductor, there are provided: an opposing arrangement portion, wherein the first wiring conductor and the second wiring conductor are arranged to be opposed to each other; as well as a non-opposing arrangement portion, wherein the first wiring conductor and the second wiring conductor are arranged so as not to be opposed to each other, The first wiring conductor comprises: The first portion of the first wiring conductor is located on the first plane; as well as The second portion of the first wiring conductor is located on a second plane intersecting the first plane. The second wiring conductor is located on a third plane opposite to the second plane. In the opposing arrangement portion, the first wiring conductor second portion and the second wiring conductor are opposed to each other, In the non-opposing arrangement portion, the first wiring conductor first portion and the second wiring conductor are arranged to intersect each other.

9. The semiconductor module according to claim 8, wherein: In the opposed arrangement portion, the first wiring conductor second portion and the second wiring conductor are positioned so as to intersect the main surface of the substrate. In the non-opposing arrangement portion, the first wiring conductor first portion is positioned parallel to the main surface of the base material.

10. A semiconductor module comprising: A substrate having a main surface, the substrate comprising at least one of a conductor and an insulator; A plurality of semiconductor chips are mounted on the main surface of the substrate respectively; a first wiring conductor electrically connected to each of the plurality of semiconductor chips so as to electrically connect the plurality of semiconductor chips in parallel; as well as a second wiring conductor electrically connected to the first wiring conductor; In the first wiring conductor and the second wiring conductor, there are provided: an opposing arrangement portion, wherein the first wiring conductor and the second wiring conductor are arranged to be opposed to each other; as well as a non-opposing arrangement portion, wherein the first wiring conductor and the second wiring conductor are arranged so as not to be opposed to each other, In the relative configuration part, there are provided: In the first part, the first wiring conductor and the second wiring conductor are separated by a first distance; and In the second portion, the first wiring conductor and the second wiring conductor are separated by a second distance different from the first distance, A sealing material that seals the first wiring conductor and the second wiring conductor is filled so as to include a space between the first wiring conductor and the second wiring conductor.

11. The semiconductor module according to claim 10, wherein: In the non-opposing arrangement portion, the second wiring conductor is connected to a portion of the first wiring conductor located between a pair of adjacent semiconductor chips.

12. A power conversion device comprising: A main conversion circuit, comprising the semiconductor module according to any one of claims 1 to 11, the main conversion circuit converting input power and outputting the power; and The control circuit outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

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