Convolutional Interleaver, Convolutional Interleaving Method, Convolutional Deinterleaver, and Convolutional Deinterleaving Method

Abstract

The convolutional interleaver included in the time interleaver and performing convolutional interleaving has: a first switch that switches the connection destination of the input of the convolutional interleaver to one end of a certain branch among multiple branches; FIFO memories provided in some of the multiple branches except for one branch, with different numbers among these some branches; a second switch that switches the connection destination of the output of the convolutional interleaver to the other end of a certain branch among multiple branches; the first and second switches switch the above connection destination when a plurality of data units equal in number to the number of codewords per frame have passed, and the switching of the connection destination is performed by sequentially repeating the multiple branches to connect the destination branches.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 201580013616.5, with the invention title of "Time Interleaver and Time Deinterleaver, and Time Interleaving Method and Time Deinterleaving Method", filed on September 10, 2015. Technical Field

[0002] The present invention relates to the field of digital communication, and more particularly, to a time interleaver for time interleaving multiple data units and a corresponding time deinterleaver, etc. Background Art

[0003] Conventionally, a time interleaver that time interleaves multiple data units generated by a bit-interleaved coding and modulation (BICM) encoder using a quasi-cyclic low-density parity-check code (QCLDPC code) and quadrature amplitude modulation (QAM) in a transmitter, and a time deinterleaver corresponding to the time interleaver in a receiver have been known.

[0004] As such a time interleaver and a corresponding time deinterleaver, for example, there are a hybrid interleaver that performs hybrid interleaving combining block interleaving and convolutional interleaving described in the standard book of DVB-NGH (Non-Patent Document 1), and a corresponding hybrid deinterleaver.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: WO2010 / 061184

[0008] Non-Patent Documents

[0009] Non - Patent Document 1: DVB - NGH specification DVB BlueBook A160 (Draft ETSI EN303 105) "Digital Video Broadcasting (DVB); Next Generation broadcasting system to Handheld physical layer specification (DVB - NGH)", November 2012

[0010] Non - Patent Document 2: DVB - T2 implementation guidelines ETSI TS 102 831 "Digital Video Broadcasting (DVB); Implementation guidelines for a second generation digital terrestrial television broadcasting system (DVB - T2)", v1.2.1, August 2012

[0011] Non - Patent Document 3: DVB - C2 specification ETSI EN 302 769 "Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital transmission system for cable systems (DVB - C2)", v1.2.1, April 2011 Summary of the Invention

[0012] The time interleaver according to one embodiment of the present invention is a time interleaver that performs time interleaving including convolutional interleaving on a plurality of data units. The convolutional interleaver that performs the above-mentioned convolutional interleaving includes: a first switch that switches the connection destination of the input of the convolutional interleaver to one end of a certain branch among a plurality of branches equal in number to the number of interleaving units in which the data units to be interleaved are arranged; FIFO (first in, first out) memories provided in a part of the plurality of branches except for one branch, and having different numbers among the branches of this part; a second switch that switches the connection destination of the output of the convolutional interleaver to the other end of a certain branch among the plurality of branches; the first switch switches the connection destination when a plurality of data units equal in number to the number of codewords per frame have passed, and the switching of the connection destination is performed by sequentially repeating the plurality of branches to connect to the destination branch; the second switch switches the connection destination when a plurality of data units equal in number to the number of codewords per frame have passed, and the switching of the connection destination is performed by sequentially repeating the plurality of branches to connect to the destination branch. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a block diagram showing a structural example of a communication circuit on the transmitter side including bit-interleaved coded modulation.

[0014] Figure 2 It is a diagram showing a schematic example of the logical representation of data input to the time interleaver.

[0015] Figure 3A It is a schematic diagram showing a schematic operation example of the logic of a time interleaver conforming to the DVB-NGH standard book.

[0016] Figure 3B It is a schematic diagram showing a schematic operation example of the logic of a time interleaver conforming to the DVB-NGH standard book.

[0017] Figure 3C It is a schematic diagram showing a schematic operation example of the logic of a time interleaver conforming to the DVB-NGH standard book.

[0018] Figure 4A It is a schematic diagram showing a schematic operation example of the logic of a time deinterleaver conforming to the DVB-NGH standard book.

[0019] Figure 4B It is a schematic diagram showing a schematic operation example of the logic of a time deinterleaver conforming to the DVB-NGH standard book.

[0020] Figure 4CIt is a schematic diagram showing an example of the operation of a time deinterleaver that complies with the DVB-NGH standard book.

[0021] Figure 5 It is a block diagram showing the structure of an installation example of a time interleaver according to an embodiment of the present invention.

[0022] Figure 6A It is showing Figure 5 a schematic diagram of an example of the operation of a column-row block interleaver.

[0023] Figure 6B It is showing Figure 5 a schematic diagram of an example of the operation of a block interleaver.

[0024] Figure 6C It is showing Figure 5 a schematic diagram of another example of the operation of a block interleaver.

[0025] Figure 6D It is showing Figure 5 a schematic diagram of yet another example of the operation of a block interleaver.

[0026] Figure 6E It is showing Figure 5 a schematic diagram of an example of the operation of a switch on the input side of a convolutional interleaver.

[0027] Figure 6F It is showing Figure 5 a schematic diagram of an example of the operation of a switch on the input side of a convolutional interleaver.

[0028] Figure 6G It is showing Figure 5 a schematic diagram of an example of the operation of a convolutional interleaver.

[0029] Figure 7 It is showing the Figure 5 block diagram of the structure of an installation example of a time deinterleaver corresponding to the time interleaver.

[0030] Figure 8 It is a schematic diagram showing an installation example of a block interleaver according to an embodiment of the present invention.

[0031] Figure 9 It is a schematic diagram showing simulation results.

[0032] Figure 10 It is a block diagram showing the structure of another installation example of a time interleaver according to an embodiment of the present invention.

[0033] Figure 11 It is showing the Figure 10 block diagram of the structure of an installation example of a time deinterleaver corresponding to the time interleaver. Detailed Embodiments

[0034] <<Matters Studied by the Inventors>>

[0035] In the DVB-NGH standard book (Non-Patent Document 1), only the transmission sequence of multiple time-interleaved data units (cells) is described, and no actual method for generating the transmission sequence is described.

[0036] The present invention will disclose a specific installation method and apparatus for a time interleaver and a corresponding time deinterleaver.

[0037] In addition, it goes without saying that the application object of the present invention is not limited to, for example, broadcasting based on DVB-NGH, the coding method is not limited to the coding method using QC LDPC codes, and the modulation method is not limited to QAM.

[0038] Figure 1 It is a block diagram showing a structural example of a communication circuit on the transmitter side including bit-interleaved coding and modulation (BICM).

[0039] The transmitter 100 includes an input processing unit 110, a BICM encoder 120, a time interleaver 130, a modulator 140, an RF (radio frequency) front end 150, and an antenna 160.

[0040] The input processing unit 110 changes the form of the input bits into a block of a specified length called a baseband frame. The BICM encoder 120 transforms the baseband frame into a plurality of complex-valued data units and outputs them. The plurality of complex-valued data units are also processed by a circuit including at least the time interleaver 130, the modulator 140, and the RF front end 150. The time interleaver 130 performs time interleaving on the output of the BICM encoder 120 and outputs it. The modulator 140 performs processing such as using orthogonal frequency-division multiplexing (OFDM) modulation on the output of the time interleaver 130, performing time interleaving and frequency interleaving commonly used to improve diversity. The RF front end 150 transforms the digital signal output from the modulator 140 into an analog RF (radio frequency) signal and performs power amplification of the analog RF signal. And the RF front end 150 outputs the power-amplified analog RF signal to the antenna 160 and outputs the power-amplified analog RF signal as radio waves from the antenna 160.

[0041] In Figure 1In this case, a time interleaver 130 is configured between the BICM encoder 120 and the modulator 140.

[0042] The purpose of the time interleaver 130 is to mitigate burst errors. In fact, in the presence of burst errors, when multiple data units are interleaved with respect to time, a large number of data units that were originally adjacent in the original data stream are no longer affected by burst errors. Thus, time interleaving, for example, in the case of using a forward error correction code method, makes it easier to recover lost data.

[0043] Some time interleaving techniques are known in the technical field of communication systems such as DVB-C2, DVB-T2, DVB-NGH, etc. Most systems use multi-segment interleaving. The theoretical explanation behind all time interleaving methods is to reconfigure multiple data units across several codewords.

[0044] For example, the time interleaving used in DVB-T2 is row-column block interleaving. Conceptually, row-column block interleaving is a method of writing multiple data units column-wise into a matrix and reading out the written multiple data units row-wise from the matrix.

[0045] Another type of time interleaving is convolutional interleaving. Convolutional interleaving is a method of writing multiple data units into a larger-sized FIFO (first in, first out) shift register. Convolutional interleaving can achieve the same time interleaving depth with half the memory size of block interleaving.

[0046] In the standard book of DVB-NGH (Non-Patent Document 1), a hybrid interleaving scheme that combines block interleaving and convolutional interleaving is adopted in time interleaving. Conceptually, the time interleaver of DVB-NGH convolves and interleaves multiple blocks each composed of multiple data units. Here, one block is called an interleaving unit (IU).

[0047] The combination of this block interleaving and convolutional interleaving is mainly selected to enable time-frequency slicing (TFS), which is a promising technique for increasing the multiplexing capacity.

[0048] Hereinafter, the time interleaver 130 and the corresponding time deinterleaver will be further described.

[0049] Figure 2Schematic example showing the logic of the data input to the time interleaver 130. Among them, in Figure 2 a frame 204 is shown.

[0050] The frame 204 includes a plurality of codewords 202, and each codeword 202 includes a plurality of data units 201. Here, the number of codewords per frame is expressed as N FEC_TI , and the number of data units per codeword is expressed as N cells . In Figure 2 's example, N FEC_Ti = 2, N cells = 12, and each frame 204 includes N FEC_TI × N cells = 2 × 12 = 24 data units.

[0051] Furthermore, each frame 204 is logically divided into a plurality of interleaving units 203. Here, the number of interleaving units per frame is expressed as N IU . In Figure 2 's example, N IU = 3.

[0052] Figure 2 The data structure illustrated in Figure 2 is used to clarify how the time interleaver 130 operates. The present invention is not limited to FEC_TI the data structure illustrated in cells , and it is obvious that it can be implemented according to other values of N IU .

[0053] In addition, in Figure 2 , the smallest square corresponds to the data unit, but only a part is labeled 201 for simplicity of illustration. In addition, the first character of the two characters in each data unit is a value temporarily assigned to identify the codeword, and the second character is a value temporarily assigned to identify the data unit in each codeword. The same applies to other figures.

[0054] In the DVB-NGH standard, as Figure 3A - Figure 3C and Figure 4A - Figure 4C show, the input and output of the time interleaver 130 and the input and output of the corresponding time deinterleaver are clearly described.

[0055] Hereinafter, the time interleaver 130 will be described using Figure 3A - Figure 3C .

[0056] Figure 3ASchematic of an example of the initial operation of the time interleaver 130 compliant with the DVB-NGH standard book. The initial operation of the time interleaver 130 includes the process of block interleaving the codewords that generate the interleaving units.

[0057] In Figure 3A the example, as the input to the delay unit 310 in the time interleaver 130, three consecutive input frames IN(m−2), IN(m−1), IN(m) are shown. Also, the input frames are input to the delay unit 310 in the order of IN(m−2), IN(m−1), IN(m) as described.

[0058] The respective multiple interleaving units IU0, IU1, IU2 of the input frames IN(m−2), IN(m−1), IN(m) are subject to mutually different time delays through the delay unit 310. Also, the time delay “0” is included in this time delay.

[0059] In Figure 3A the example, each interleaving unit is subject to the following time delay.

[0060] The interleaving unit IU0 of each input frame in the delay unit 310 is output without being delayed as indicated by the absence of a delay line in the corresponding row.

[0061] The interleaving unit IU1 of each input frame in the delay unit 310 is output after being delayed by the amount of one interleaving unit as indicated by the presence of one delay line 310−11 in the corresponding row.

[0062] The interleaving unit IU2 of each input frame in the delay unit 310 is output after being delayed by the amount of two interleaving units as indicated by the presence of two delay lines 310−21, 310−22 in the corresponding row.

[0063] In Figure 3A the example, the output of the delay unit 310 in the initial operation of the time interleaver 130 is represented by the intermediate frames INT(n−2), INT(n−1), IN(n), INT(n+1), INT(n+2). Also, the intermediate frames are output from the delay unit 310 in the order of INT(n−2), INT(n−1), INT(n), INT(n+1), INT(n+2) as described.

[0064] In Figure 3AIn the example, only the middle frame INT(n) is complete, while the middle frames before and after it are not. The unillustrated input frames are input into the delay unit 310, processed by the delay unit 310, and output from the delay unit 310, thus becoming complete.

[0065] Furthermore, the delay circuits 310-11, 310-21, 310-22 in the delay unit 310 act on a group of data units, i.e., the interleaving unit, rather than on a single data unit as in typical convolutional interleaving.

[0066] Figure 3B and Figure 3C shows an example outline of the second operation of the time interleaver 130 that follows the DVB-NGH standard book. The second operation of the time interleaver 130 includes stacking a plurality of interleaving units 203 horizontally from left to right for each middle frame, and then reading out the data units row by row.

[0067] More specifically, regarding the middle frame INT(n), as Figure 3B shown, the interleaving units IU0, IU1, IU2 are stacked horizontally from left to right by the stacking unit 320 within the time interleaver 130. Then, as Figure 3C shown, the data units of the stacked interleaving units IU0, IU1, IU2 are read out and output row by row through the readout unit 330 within the time interleaver 130. The output result is represented by the output string OUT(n) in Figure 3C , and the data units are output in the recording order of 40, 50, 24,..., 19, 42,..., 37, 0B, 1B.

[0068] It can be seen that in the output string OUT(n), how multiple data units are advantageously spread out more in the codewords within the time interleaving depth. This is achieved by the stacking operation performed by the stacking unit 320.

[0069] When the data unit stream corresponding to the output string OUT(n) is received in the receiver, the time deinterleaver of the receiver performs the opposite operation to the operation described for the time interleaver 130. In short, multiple data units are divided into multiple interleaving units, the multiple interleaving units are stacked vertically from top to bottom for frame reconstruction, and are further subject to time delay.

[0070] Hereinafter, Figure 4A - Figure 4C is used to describe the time deinterleaver.

[0071] Figure 4A and Figure 4BSchematic of an example of the initial operation of a time deinterleaver that complies with the DVB-NGH standard book. The initial operation of the time deinterleaver includes the reception process of the input stream IN(n) corresponding to the output string OUT(n) output from the time interleaver 130 on the transmitter side.

[0072] As Figure 4A shown, multiple data units of the input stream IN(n) are input to the separation unit 410 in the order of recording 40, 50, 24, …, 19, 42, …, 37, 0B, 1B, and are reconstructed into interleaving units by the separation unit 410.

[0073] As Figure 4B shown, multiple interleaving units are input to the de-stacking unit 420 and are reconstructed into frames by the de-stacking unit 420.

[0074] Figure 4C Schematic of an example of the second operation of a time deinterleaver that complies with the DVB-NGH standard book.

[0075] In Figure 4C the example, as the input to the delay unit 430 in the time deinterleaver, five consecutive intermediate frames INT(n−2), INT(n−1), INT(n), INT(n+1), INT(n+2) are shown. In addition, the intermediate frames are input to the delay unit 430 in the order of recording INT(n−2), INT(n−1), INT(n), INT(n+1), INT(n+2). In addition, for convenience of explanation, some of the intermediate frames are incomplete in the illustration.

[0076] The delay unit 430 performs a time delay opposite to that of the delay unit 310 on multiple interleaving units. In Figure 4C the example, for the interleaving unit IU0 of each intermediate frame, the delay unit 430 performs a delay of the amount of two interleaving units and outputs it as indicated by the presence of two delay circuits (delay line) 430-01, 430-02 in the corresponding row. For the interleaving unit IU1 of each intermediate frame, the delay unit 430 performs a delay of the amount of one interleaving unit and outputs it as indicated by the presence of one delay circuit (delay line) 430-11 in the corresponding row. For the interleaving unit IU2 of each intermediate frame, the delay unit 430 outputs without performing a delay as indicated by the absence of a delay circuit (delay line) in the corresponding row.

[0077] Through the above processing, the frames OUT(p), OUT(p+1), OUT(p+2) corresponding to the originally transmitted frames IN(m−2), IN(m−1), IN(m) are restored.

[0078] However, the above descriptions of the time interleaver and the time deinterleaver are only logical descriptions of the operations of the devices and methods of the time interleaver 130 and the time deinterleaver. Their implementation and installation do not necessarily use the described units 310 - 330 and units 410 - 430, and can be obtained by some methods. In particular, just as the defined two-dimensional matrix is arranged in different spatially related positions, the data arrangement and data movement in the defined two-dimensional matrix are only selected to simplify the understanding of the time interleaving process and the time deinterleaving process. In a preferred implementation and installation, the physical recording of data can also be systematized in a memory having a two-dimensional array structure, but as described above, the data does not necessarily need to be physically reconfigured, and can also be logically reconfigured simply, for example, using an appropriate addressing scheme.

[0079] The present invention provides a method for implementing and installing the above time interleaving and time deinterleaving, which is accompanied by a reduction in the use of resources, preferably accompanied by a reduction in the use of memory in the time deinterleaver. The reduction in the use of memory in the time deinterleaver is effective because a time interleaver is sometimes incorporated in a small and potentially portable electronic device, and the reduction in memory also effectively brings about a reduction in size and cost.

[0080] Hereinafter, the time interleaving and time deinterleaving related thereto will be described.

[0081] <<Embodiment>>

[0082] Figure 5 Shows the structure of an installation example of a time interleaver according to an embodiment of the present invention. In addition, Figure 5 the time interleaving performed by the time interleaver is a hybrid interleaving that combines block interleaving and convolutional interleaving.

[0083] The time interleaver 500 includes a row-column block interleaver (BI 0 ) 510, a block interleaver (BI 1 ) 520, and a convolutional interleaver 530. The convolutional interleaver 530 logically includes a switch 540, memory cells (M 1 , 0 , M 2，0 , M 2，1 ) 545 - 11, 545 - 21, 545 - 22, and a switch 550. The output of the row-column block interleaver 510 is connected to the input of the block interleaver 520, and the output of the block interleaver 520 is connected to the input of the convolutional interleaver 530.

[0084] However, Figure 5For logical display only, although the time interleaver 500 is not physically implemented, i.e., it does not have physical switches, it is obvious to those skilled in the art that it can be implemented using, for example, a memory and a processor.

[0085] Hereinafter, Figure 5 the row-column block interleaver 510 will be described.

[0086] The row-column block interleaver 510 includes a matrix with the same number of rows as N cells / N IU and the same number of columns as N IU where N IU is the number of interleaving units per frame, and N cells is the number of data units per codeword. For example, in the case of the Figure 2 frame structure, N cells = 12 and N IU = 3.

[0087] In Figure 6A it shows an installation example of the row-column block interleaver 510 in the case of N cells = 12 and N IU = 3. Additionally, in the example of Figure 6A the 12 data units of the first codeword are input to the row-column block interleaver 510 in the recording order of 00, 01, 02,..., 09, 0A, 0B.

[0088] According to Figure 6A it can be seen that the data units 00 - 0B are written by the row-column block interleaver 510 in the input order in the column direction of the matrix, and after writing, they are read out in the row direction of the matrix. As a result, the 12 data units of the first codeword are output from the row-column block interleaver 510 in the recording order of 00, 04, 08, 01, 05, 09, 02, 06, 0A, 03, 07, 0B.

[0089] For those skilled in the art, it is obvious that the implementation and installation of this row-column block interleaver 510 can be advantageously obtained using, for example, linear memory blocks that operate according to the addressing schemes used in the installation guide of DVB-T2 (Non-Patent Document 2) or described in Patent Document 1. Additionally, Non-Patent Document 2 and Patent Document 1 are fully incorporated in this application.

[0090] In particular, this row-column block interleaver tracks the memory locations where the next data unit will be read out and re-uses these memory locations to write the incoming data units. Specifically, the address a of the i-th element of the j-th time interleaving block (i，j)Calculated based on the following mathematical expressions 1 and 2. Additionally, the j-th time-interleaved block and the i-th element respectively correspond to each codeword including N cells (in the case of the Figure 2 frame structure of

[0091] it is 12) data units and the i-th data unit of each codeword.

[0092] a (i,j) =(a (i-i,j) +k (j) ) mod M+(a (i-i,j) +k (j) ) div M

[0093] Here, k (0) =1, a (0，j) =0, M = Nr × Nc.

[0094] Among them, Nr is the number of rows and Nc is the number of columns. Additionally, like j = 0,..., each time a codeword is input, it increases by 1 each time, and i = 0,..., N cells - 1 -1 (in the case of the Figure 2 frame structure of cells it is 11), and Nr and Nc respectively correspond to N IU (in the case of the Figure 2 frame structure of IU it is 12 / 3 = 4), N Figure 2 (in the case of the

[0095] frame structure of (j) it is 3).

[0096] [Mathematical Expression 2]

[0097] k (j) =(k (j-1) × Nr) mod M + kx j-1) div Nc

[0098] The advantage of this method is that data units can be read and written through a single cache, eliminating the need to switch between two caches for write and read operations. This enables the use of a single block of linear RAM (random access memory) for both row-column block interleaving and similarity-based row-column block deinterleaving. In this regard, the memory sizes of the actual row-column block interleaver and row-column block deinterleaver can be conceptually the same. For example, to perform row-column block interleaving or row-column block deinterleaving on a frame consisting of 12 data units, a memory block with a memory space of 12 data units can be used.

[0099] Hereinafter, Figure 5 the block interleaver 520 will be described.

[0100] The block interleaver 520 includes a matrix with the same number of rows as N cells and the same number of columns as N FEC _. TI where N cells is the number of data units per code word, and N FEC_TI is the number of code words per frame. For example, in the case of the Figure 2 frame structure, N cells = 12 and N FEC_Ti = 2. Additionally, the block interleavers 520A and 520B described later also include matrices with the same number of rows as N cells and the same number of columns as N FEC_TI .

[0101] In Figure 6B an example where N cells = 12 and N FEC_Ti = 2, an installation example of the block interleaver 520 is shown. Additionally, in the example of Figure 6B , the 12 data units of the first code word within one frame are input to the block interleaver 520 in the order in which they are output from the row-column block interleaver 510, here in the recording order of 00, 04, 08,..., 03, 07, 0B. Subsequently, the 12 data units of the next code word within the same frame are input to the block interleaver 520 in the order in which they are output from the row-column block interleaver 510, here in the recording order of 10, 14, 18,..., 13, 17, 1B.

[0102] As Figure 6BAs shown, the data units 00 - 0B of the initial codeword are written by the block interleaver 520 in the column direction of the matrix in the order output by the row-column block interleaver 510. The data units 10 - 1B of the subsequent codeword are written by the block interleaver 520 in the column direction of the matrix in the order output by the row-column block interleaver 510. The data units 00 - 0B and 10 - 1B written into the matrix are read out by the block interleaver 520 in the row direction of the matrix. As a result, the 24 data units of the first frame are output from the block interleaver 520 in the recording order of 00, 10, 04, …, 19, 02, … 17, 0B, 1B.

[0103] In this case, the block interleaver 520 operates as a row-column block interleaver like the row-column block interleaver 510. Therefore, the same considerations made for the row-column block interleaver 510 can be applied, especially to the implementation and installation of the addressing scheme described using Formulas 1 and 2. Additionally, when applied to the block interleaver 520, the j-th time interleaved block and the i-th element respectively correspond to each frame including N FEC_TI ×N cells (in the case of the Figure 2 frame structure, it is 2 × 12 = 24) data units and the i-th data unit of each frame. As j = 0, …, thus, every time an input frame is received, it increases by 1 each time, and i = 0, …, N FEC_TI ×N cells－1 (in the case of the Figure 2 frame structure, it is 2 × 12 - 1 = 23), and Nr and Nc respectively correspond to N cells (in the case of the Figure 2 frame structure, it is 12) and N FEC_TI (in the case of the Figure 2 frame structure, it is 2).

[0104] Next, another installation example of the block interleaver (BI 1 ) within the time interleaver 130 will be described.

[0105] In Figure 6C shows the same numerical example as Figure 6B , that is, another installation example of the block interleaver (BI cells = 12, N FEC_Ti = 2). However, in 1 , the block interleaver (BI Figure 6C ) is denoted as the block interleaver 520A. Additionally, it is assumed that the input data units in 1 are the same as the input data units in Figure 6C . Figure 6B

[0106] In the present invention, in the case of referring to the block interleaver 520, it is obvious that in addition to the block interleaver 520, the block interleaver 520A can also be implemented and installed.

[0107] As Figure 6C shown, the 12 data units 00 - B of the original codeword are written into the matrix by the block interleaver 520A in the order output by the row - column block interleaver 510. Then, the data units 10 - 1B of the following codeword are written into the matrix by the block interleaver 520A in the order output by the row - column block interleaver 510. However, the data units 00 - 0B, 10 - 1B are not written in the column direction like the block interleaver 520, but are written diagonally. And the data units 00 - 0B, 10 - 1B written into the matrix are read out by the block interleaver 520A from the row direction of the matrix in the same way as the block interleaver 520. As a result, as Figure 6C shown, the 24 data units of one frame are output from the block interleaver 520A in the recording order of 00, 1B, 10, …, 09, 02, …, 13, 17, 0B.

[0108] For those skilled in the art of this technical field, it is obvious that the implementation and installation of this block interleaver 520A can be advantageously obtained by using a linear memory block operating through an addressing scheme used, for example, in the DVB - C2 standard book (Non - Patent Document 3). Additionally, Non - Patent Document 3 is fully incorporated in this application.

[0109] In particular, this block interleaver tracks the memory positions where the next data unit is to be read out and re - uses these memory positions to write the incoming data units. Specifically, the address a (i , j) of the i - th element of the j - th time - interleaved block is calculated based on the following Equation 3. Additionally, the j - th time - interleaved block and the i - th element respectively correspond to each frame including N FEC _ TI ×N cells (in the case of the frame structure of Figure 2 it is 2×12 = 24) data units and the i - th data unit of each frame.

[0110] [Equation 3]

[0111] a (i，j ) = Nc×r (i，j ) + c (i，j)

[0112] Here,

[0113] i = 0, …, Nr×Nc - 1

[0114] c (i，j) = mod(j, Nc)

[0115] s (i，j) = mod(j × c (i，j) , Nr)

[0116] r (i，j ) = mod(floor(i / Nc) - s (i，j) , Nr)

[0117] where Nr is the number of rows, Nc is the number of columns, e.g., j = 0,..., so that whenever an input frame is received, it is incremented by 1 each time, and i = 0,..., N FEC_TI × N cells - 1 (in the case of the Figure 2 frame structure is 2 × 12 - 1 = 23), Nr and Nc respectively correspond to the N cells (in the case of the Figure 2 frame structure is 12) and N FEC_TI (in the case of the Figure 2 frame structure is 2).

[0118] Next, another installation example of the block interleaver (BI 1 ) in the time interleaver 130 will be described.

[0119] In Figure 6D it shows the case where it is the same as the numerical example in Figure 6B , that is, N cells = 12, N FEC_Ti = 2, another installation example of the block interleaver (BI 1 ). However, in Figure 6D , the block interleaver (BI 1 ) is represented as the block interleaver 520B. Additionally, it is assumed that the input data unit in Figure 6D is the same as the input data unit in Figure 6B .

[0120] In the present invention, when referring to the block interleaver 520, it is obvious that in addition to the block interleaver 520, the block interleaver 520B can also be implemented and installed.

[0121] As Figure 6D shown, the 12 data units 00 - 0B of the first codeword are written in the column direction of the matrix by the block interleaver 520B in the order output by the row - column block interleaver 510. The data units 10 - 1B of the next codeword are written in the column direction of the matrix by the block interleaver 520B in the order output by the row - column block interleaver 510. However, before the data units are read out, the row twisting process is performed by the block interleaver 520B. After the row twisting, the data units 00 - 0B, 10 - 1B are read out by the block interleaver 520B from the row direction of the matrix.

[0122] In a different description method, the data units 00 - 0B of the code word are written in the column direction of the matrix, and then the data units 10 - 1B of the following code word are written in the column direction of the matrix. Moreover, the data units 00 - 0B and 10 - 1B written into the matrix are read diagonally from the matrix.

[0123] As a result, as Figure 6D shown, the 24 data units of one frame are output from the block interleaver 520B in the recording order of 00, 14, 08,..., 1B, 04,..., 17, 0B, 10.

[0124] The implementation and installation of this block interleaver 520B can be advantageously obtained by using a linear memory block that operates with an addressing scheme that tracks the memory locations where the next data unit is read and re - uses these memory locations to write the incoming data units. Specifically, the address a of the i - th element among the j - th time blocks is (i，j) calculated based on the following Equation 4. Additionally, the j - th time interleaving block and the i - th element respectively correspond to each frame of the N FEC_TI ×N cells (in the case of the Figure 2 frame structure, it is 2×12 = 24) data units and the i - th data unit of each frame.

[0125] [Equation 4]

[0126]

[0127] where Nr is the number of rows, Nc is the number of columns, and Nr and Nc respectively correspond to the N cells (in the case of the Figure 2 frame structure, it is 12) and N FEC_TI (in the case of the Figure 2 frame structure, it is 2) described above.

[0128] The block interleavers 520A and 520B have the advantage of supplementing or replacing the data unit interleaver. If not, they have the advantage of being configured before the row - column block interleaver 510, so they are better than the block interleaver 520. In particular, in DVB - NGH, the data unit interleaver is required to perform a quasi - random rearrangement of the data units within the code word before the row - column block interleaver 510. By using the block interleavers 520A and 520B, this data unit interleaver can be omitted.

[0129] Next, the convolutional interleaver 530 of Figure 5 will be described.

[0130] The switches 540 and 550 are in NFEC_TI After one data unit passes through, the position of the connection destination is moved by an amount. The number of positions of the connection switch, which is the number of branches in the convolutional interleaver 530, is equal to the number of interleaving units N IU is equal.

[0131] In Figure 6E represents the case of the frame structure exemplified above, that is, N Figure 2 In the case of the frame structure shown above, that is, N cells = 12, N FEC_Ti = 2, N IU = 3, the first three steps of the switch 540 and the respective output data units are shown in Figure 6F represents the next three steps and the respective output data units. However, in Figure 6E , Figure 6F as the input data unit, the output data unit of the block interleaver 520 shown in Figure 6B is used. The 24 data units of one frame arrive at the switch 540 in the recording order of 00, 10, 04,..., 19, 02,..., 17, 0B, 1B.

[0132] According to Figure 6E , Figure 6F it can be seen that if N FEC_Ti = 2 data units pass through, the switch 540 moves the connection destination from the uppermost or second segment position to the next lower segment position, or from the lowermost segment position to the uppermost segment position.

[0133] The data unit output from the switch 540 passes through the branch currently connected to the switch 540. The uppermost branch does not contain a delay component, and the branches below the uppermost branch each add another delay component to the branch above it, and successively contain 1, 2, 3, 4, etc. numbers of delay components from the upper segment to the lower segment.

[0134] Each delay component M x，y functions as a FIFO (first in, first out) shift register and contains N cells / N IU ×N FEC_TI memory data units. For example, in Figure 2 the frame structure of, that is, in the case where N cells = 12, N FEC_Ti = 2, N IU = 3, each delay component M x，y contains 12 / 3×2 = 8 memory data units. In addition, the delay component M x，y corresponds to Figure 5 the memory units 545 - 11, 545 - 21, 545 - 22.

[0135] The data units that have passed through each branch reach switch 550. And if N FEC_Ti = 2 data units pass through, switch 550 moves the connection destination from the uppermost or second segment position to the next lower segment position, or from the lowermost segment position to the uppermost segment position.

[0136] Figure 6G Schematically shows an operation example of the convolutional interleaver 530 for the first 3 frames. The empty data units in the output are obtained because the stored contents in the memory units 545-11, 545-21, 545-22 advance stage by stage. In particular, in this example, the three memory units 545-11, 545-21, 545-22 hold 24 data units, which is 3 times the total of 8 data units corresponding to the 24 empty data units in the output. Starting from data unit 40, the data units exist continuously.

[0137] For those skilled in the art of this technology, it is obvious that a circular buffer can be used to implement and install the delay line or the memory units 545-11, 545-21, 545-22. In addition, the circular buffer has the advantage of avoiding physical copying of the memory units. In this method, power consumption is effectively suppressed, which brings significant advantages for portable devices.

[0138] Figure 7 Shows the structure of an installation example of the time deinterleaver related to the embodiment of the present invention. In addition, the Figure 7 time deinterleaving performed by the time deinterleaver is a hybrid deinterleaving that combines convolutional deinterleaving and block deinterleaving.

[0139] The time deinterleaver 700 includes a convolutional deinterleaver 730, a block deinterleaver (BDI1) 720, and a row-column block deinterleaver (BDI0) 710. The convolutional deinterleaver 730 logically includes switches 740, memory units (M 1，0 , M1, 1, M 2，0 ) 745-01, 745-02, 745-11, and switch 750. The output of the convolutional deinterleaver 730 is connected to the input of the block deinterleaver 720, and the output of the block deinterleaver 720 is connected to the input of the row-column block deinterleaver 710. It can be seen that the time deinterleaver 700 is sufficiently symmetric with respect to the time interleaver 500.

[0140] The convolutional deinterleaver 730, in particular, for the number of data units held by the memory units 745-01, 745-02, 745-02, and the moving speeds of switches 740 and 750, in relation to the use of Figure 6E - Figure 6Goperates in a manner similar to that of the described convolutional interleaver 530.

[0141] The memory cells 745-01, 745-02, 745-02 include N cells / N IU ×N FEC _ TI memory data units. If N FEC _ TI data units pass through, the switch 740, 750 moves the connection destination from the uppermost or second segment position to the next lower segment position, or from the lowermost segment position to the uppermost segment position.

[0142] Furthermore, further detailed description is omitted here.

[0143] Hereinafter, Figure 7 the row-column block deinterleaver 710 will be described.

[0144] The row-column block deinterleaver 710 includes N cells / N IU rows and N IU columns of matrix.

[0145] A memory installation example of the row-column block deinterleaver 710 is symmetric to the row-column block interleaver 510 and can be obtained by using a memory with the following addressing scheme. That is, the address a (i , j) of the i-th element of the j-th time interleaved block is calculated using the following equations 5 and 6. In addition, the j-th time interleaved block and the i-th element respectively correspond to each codeword including N cells (12 in the case of the Figure 2 frame structure) data units and the i-th data unit of each codeword.

[0146] [Equation 5]

[0147] a (i,j) =(a (i-i,j) +k (j) ) mod M+(a (i-i,j) +k (j) ) div M

[0148] Here, k (0) =1, a (0，j) =0, M = Nr × Nc.

[0149] Among them, Nr is the number of rows and Nc is the number of columns. As j = 0,..., it increases by 1 every time an input codeword is received, and i = 0,..., N cells－1 -1 (in the case of Figure 2In the case of the frame structure of 11), Nr and Nc respectively correspond to N as described above cells / N IU (In Figure 2 the case of the frame structure of 12 / 3 = 4), N IU (In Figure 2 the case of the frame structure of 3).

[0150] In the row-column block deinterleaver 710 on the receiver side, k (j) is calculated using the following Equation 6.

[0151] [Equation 6]

[0152] k (j) =(k (j-1) × Nc) mod M + k (j-1) div Nr

[0153] Next, Figure 7 the block deinterleaver 720 is described.

[0154] The block deinterleaver 720 includes an N cells row by N IUFEC _ TI column matrix.

[0155] An example of the memory installation of the block deinterleaver 720 is symmetric to the block interleaver 520. Similar to the row-column block deinterleaver 710 above, it is obtained by a memory adopting the addressing scheme described by Equations 5 and 6 for the deinterleaving addressing on the receiver side. In addition, when applied to the block deinterleaver 720, the j-th time interleaved block and the i-th element respectively correspond to each frame and the i-th data unit of each frame of N FEC _ TI × N cells (in Figure 2 the case of the frame structure of 2 × 12 = 24) data units, such as when j = 0,..., each time an input codeword is received, it increases by 1, and i = 0,..., N FEC _ TI × N cells (in Figure 2 the case of the frame structure of 2 × 12 - 1 = 23), and Nr and Nc respectively correspond to N as described above cells (in Figure 2 the case of the frame structure of 12) and N FEC _ TI (in Figure 2 the case of the frame structure of 2).

[0156] Alternatively, in the case of using the block interleaver 520A, its corresponding block deinterleaver is implemented and installed by using the following addressing scheme. That is, the address a of the i-th element of the j-th time-interleaved block is (i , j) calculated using the following Equation 7. In addition, the j-th time-interleaved block and the i-th element respectively correspond to each frame and the i-th data unit of each frame among the N FEC _ TI ×N cells (in the case of the Figure 2 frame structure, it is 2 × 12 = 24) data units.

[0157] [Equation 7]

[0158] a (i，j) = Nc × r (i，j) + c (i，j)

[0159] Here,

[0160] i = 0,..., Nr × Nc - 1

[0161] c (i，j) = mod(i, N c )

[0162] s (i，j) = mod(j × c (i，j) , Nr)

[0163] r (i，j) = mod(s (i，j) + floor(i / Nc), Nr)

[0164] where Nr is the number of rows, Nc is the number of columns, and as j = 0,..., it increases by 1 each time an input codeword is received, and i = 0,..., N FEC_TI ×N cells - 1 (in the case of the Figure 2 frame structure, it is 2 × 12 - 1 = 23), and Nr and Nc respectively correspond to the N cells (in the case of the Figure 2 frame structure, it is 12) and N FEC_TI (in the case of the Figure 2 frame structure, it is 2).

[0165] Alternatively, in the case of using the block interleaver 520B, its corresponding block deinterleaver is implemented and installed by using the following addressing scheme. That is, the address a of the i-th element of the j-th time-interleaved block is (i，j) calculated using the following Equation 8. In addition, the j-th time-interleaved block and the i-th element respectively correspond to the NFEC_TI ×N cells pieces (in the case of the frame structure of Figure 2 it is 2 × 12 = 24 pieces) of each frame of data units and the i-th data unit of each frame.

[0166] [Equation 8]

[0167]

[0168] where Nr is the number of rows, Nc is the number of columns, and Nr and Nc respectively correspond to N described above cells (in the case of the frame structure of Figure 2 it is 12) and N FEC_TI (in the case of the frame structure of Figure 2 it is 2).

[0169] Next, as another embodiment of the present invention, a simplified time interleaver and a time deinterleaver are described. In addition, the time interleaver performs a hybrid interleaving that combines block interleaving and convolutional interleaving, and the time deinterleaver performs a hybrid deinterleaving that combines block deinterleaving and convolutional deinterleaving.

[0170] The row-column block interleaver 510 is the conventional row-column block interleaver when the number of data units N per code word cells is an integer multiple of the number of interleaving units N IU . However, in the case where this is not the case, a block interleaver that skips the subsequent data units and advances is required.

[0171] According to the DVB-NGH standard book, L (IU，min) = floor(N cells / N IU ). Where floor(x) is the largest integer not exceeding x. N large = mod(N cells , N IU ), N small = N IU - N large . Furthermore, the first N large interleaving units include L (IU，min) + 1 data units, and the subsequent N small interleaving units include L (IU，min) data units. As a result, N cells = (L (IU，min) + 1) × N large + L (IU，min) × N small .

[0172] In Figure 8The figure shows a schematic of an example of the row-column block interleaver. It can be seen that this block interleaver cannot be directly implemented and installed using the DVB-T2 addressing scheme that suppresses the use of memory. This countermeasure requires skipping the reading of a large-scale and complex logic-defined data unit.

[0173] However, the inventors have conceived that the row-column block interleaver 510 and the row-column block deinterleaver 710 form outer components of the overall time interleaver circuit and the overall time deinterleaver circuit. Therefore, the row-column block interleaver 510 and the row-column block deinterleaver 710 can be simply removed from the time interleaver circuit and the time deinterleaver circuit without affecting the overall function and degrading the performance. In Figure 9 The figure shows simulation results supporting this discovery.

[0174] In Figure 10 The figure shows a structural example of the corresponding time interleaver 1000.

[0175] Figure 10 The time interleaver 1000 of has a block interleaver (BI 1 ) 1020 and a convolutional interleaver 1030. The convolutional interleaver 1030 has a switch 1040, a plurality of FIFO registers 1045, and a switch 1050. In addition, Figure 10 The square blocks in the convolutional interleaver 1030 in are respectively FIFO registers 1045. Further, the FIFO register 1045 that is the j-th one from the switch 1040 to the switch 1050 in the branch between the position i (1 to N IU - 1) on the switch 1040 side and the position i (1 to N IU - 1) on the switch 1050 side is denoted as M i，j .

[0176] The dispersion of the codeword is determined by the switch 1040.

[0177] In one embodiment, after N FEC－TI data units pass through, the switch 1040 moves the connection destination position by incrementing by 1 (0, 1, 2,..., N IU - 2, N IU - 1, 0, 1,...). The operation of the switch 1050 replicates the operation of the switch 1040. That is, after NFEC-TI data units pass through, the switch 1050 moves the connection destination position by incrementing by 1 (0, 1, 2,..., N IU - 2, N IU - 1, 0, 1,...).

[0178] The present invention is not limited to the switch 1040, 1050 incrementing the connection destination position by 1 after N FEC_TIAfter a data unit passes, the position of the connection destination is moved to increase by 1, and other increases can also be made. In the latter case, the sizes of the respective FIFO registers 1045 are adjusted. For example, in the case where switches 1040 and 1050 are switched every other jump (i.e., in the case of first moving to all even positions 0, 2, 4, … and then moving to all odd positions 1, 3, 5, …), at the first N large positions where the switch 1040 related to the first N large interleaving units is connected, each FIFO register (Mi,j) 1045 needs to be a memory for (L (IU，min) +1)×N FEC_TI memory data units. At the remaining N small positions where the switch 1040 related to the remaining N small interleaving units is connected, each FIFO register (M i，j ) 1045 is a memory for L (IU，min) ×N FEC_TI memory data units. Its advantage is that the codeword is extended over a larger time span.

[0179] For the block interleaver 1020, regardless of which of the above block interleavers it is, all possible implementations and installations described specifically for block interleavers 520, 520A, 520B can be used.

[0180] In the transmitter, the size of each FIFO register (M i，j ) 1045 is a (L large +1)×N large memory data unit for i = 1, …, N (IU，min) −1, j = 1, …, i associated with the first N FEC_TI interleaving units, and is a L small ×N large memory data unit for i = N IU , ···, N (IU，min) −1, j = 1, …, i associated with the next N FEC_TI interleaving units.

[0181] The time deinterleaver 1100 corresponding to the Figure 10 time interleaver 1000 reflects the function of the time interleaver 1000, and a structural example of the time deinterleaver 1100 is shown in Figure 11 .

[0182] Figure 11 The time deinterleaver 1100 of 1) At 1120, the convolutional deinterleaver 1130 includes a switch 1140, multiple FIFO registers 1145, and a switch 1150. Additionally, Figure 10 the square blocks within the convolutional deinterleaver 1130 in IU are respectively FIFO registers 1145. Further, the branch between position i (0 to N IU -2) on the switch 1140 side and position i (0 to N i，i+k－1 -2) on the switch 1050 side, where the k-th FIFO register 1045 from the switch 1140 to the switch 1150 is denoted as M’ i，j .

[0183] Here, the switches 1140 and 1150 operate corresponding to the switches 1040 and 1050. That is, the switches 1140 and 1150 switch the connection destination position after N FEC－TI data units pass through, and the order of switching positions is the same as that of the switches 1040 and 1050. The considerations made for the block deinterleaver 720 above are equally applicable to the block deinterleaver 1120.

[0184] Depending on whether N cells is an integer multiple of N IU , the sizes of the FIFO registers (M’ i，j ) 1145 are different from those of the registers paired with the FIFO registers (M i，j ) 1045 of the transmitter.

[0185] In particular, when N cells is an integer multiple of N IU , all the FIFO registers 1145 are of the same size, that is, N cells / N IU ×N FEC_TI .

[0186] As a general conclusion, when N cells is not an integer multiple of N IU ,

[0187] the memory size of the FIFO register M’ i，j , for i = 0,..., N large -1, j = i,..., N IU -2, is (L (IU，min) +1)×N FEC_TI memory data units,

[0188] for i = N large ,..., N IU -2, j = i,..., N IU -2 is L (IU，min) ×NFEC_TI Memory data unit.

[0189] The block deinterleaver 1120 cancels the function of the block interleaver 1020. As discussed in the block deinterleaver 720, it can be based on a block of RAM and its associated addressing scheme, through a certain implementation of the above-mentioned block deinterleaver.

[0190] Since the overall communication scheme is packed by the delay circuit through the block interleaver and the block deinterleaver, it can be seen that only the block interleaver and the block deinterleaver are faced.

[0191] As proposed in this embodiment, the outer row-column block interleaver (BI 0 ) 510 and the row-column block deinterleaver (BDI 0 ) 710 removal will change Figure 3C the transmission order of the transmitter shown, but has the advantage of making the implementation and installation easier.

[0192] Figure 9 Schematically shows the simulation results comparing the performance of the time interleaver of DVB-NGH with the performance of the time interleaver 1000 of this embodiment. Among them, Figure 9 it is represented by using the error curve for the signal-to-noise power ratio (SNR). It can be seen from Figure 9 that the performance of the time interleaver 1000 will not decline by removing the outer row-column block interleaver (BI 0 ) 510 and the row-column block deinterleaver (BDI 0 ) 710, that is, the error curve of the time interleaver of DVB-NGH is in good agreement with the error curve of the time interleaver 1000 of this embodiment.

[0193] In Figure 9 the simulation showing the results includes the Rayleigh burst fading channel with a fixed disappearance burst occurring during the center period of the interleaved data unit. This is to simulate the transmission of a wireless communication path with significant shielding. The disappearance rate (20%, 40%) is related to the time interleaving depth of the time interleaver. Furthermore, the simulation parameters are "modulation method: 256 non-uniform QAM", "LDPC codeword length Nldpc = 64800, coding rate 9 / 15", "number of interleaving units: N IU = 15", "number of codewords per interleaving unit: N FEC_Ti = 8", "number of interleaving frames: 30".

[0194] Some embodiments are described respectively, but for those skilled in the art of this technology, it is obvious that they can be combined in order to obtain alternative embodiments.

[0195] <<Supplement>>

[0196] Summarize the communication method and others related to the present invention.

[0197] (1) The first time interleaver is a time interleaver that performs time interleaving including convolutional interleaving on multiple data units. The convolutional interleaver that performs the above-mentioned convolutional interleaving includes: a first switch that switches the connection destination of the input of the convolutional interleaver to one end of a certain branch among multiple branches equal in number to the number of interleaving units in which the data units to be interleaved are arranged; FIFO (first in, first out) memories provided in some of the multiple branches except for one branch, with different numbers among the branches in this part; a second switch that switches the connection destination of the output of the convolutional interleaver to the other end of a certain branch among the multiple branches; the first switch switches the connection destination when multiple data units equal in number to the number of codewords in each frame have passed, and the switching of the connection destination is performed by sequentially repeating the multiple branches to connect to the destination branch; the second switch switches the connection destination when multiple data units equal in number to the number of codewords in each frame have passed, and the switching of the connection destination is performed by sequentially repeating the multiple branches to connect to the destination branch.

[0198] (2) The first time deinterleaver is a time deinterleaver that performs time deinterleaving including convolutional deinterleaving on multiple data units. The convolutional deinterleaver that performs the above-mentioned convolutional deinterleaving includes: a first switch that switches the connection destination of the input of the convolutional deinterleaver to one end of a certain branch among multiple branches equal in number to the number of interleaving units in which the data units to be deinterleaved are arranged; FIFO (first in, first out) memories provided in some of the multiple branches except for one branch, with different numbers among the branches in this part; a second switch that switches the connection destination of the output of the convolutional deinterleaver to the other end of a certain branch among the multiple branches; the first switch switches the connection destination when multiple data units equal in number to the number of codewords in each frame have passed, and the switching of the connection destination is performed by sequentially repeating the multiple branches to connect to the destination branch; the second switch switches the connection destination when multiple data units equal in number to the number of codewords in each frame have passed, and the switching of the connection destination is performed by sequentially repeating the multiple branches to connect to the destination branch.

[0199] (3) The first time interleaving method is a time interleaving method for performing time interleaving including convolutional interleaving on multiple data units. The time interleaver for performing the above time interleaving method includes a convolutional interleaver for performing the above convolutional interleaving. The above convolutional interleaver includes: a first switch for switching the connection destination of the input of the convolutional interleaver to one end of a certain branch among a plurality of branches equal in number to the number of interleaving units in which the data units to be interleaved are arranged; FIFO (first in, first out) memories provided in some of the plurality of branches except for one branch, with different numbers among these some branches; a second switch for switching the connection destination of the output of the convolutional interleaver to the other end of a certain branch among the plurality of branches; the first switch switches the connection destination when a plurality of data units equal in number to the number of codewords per frame have passed, and the switching of the connection destination is performed by sequentially repeating the plurality of branches to connect to the destination branch; the second switch switches the connection destination when a plurality of data units equal in number to the number of codewords per frame have passed, and the switching of the connection destination is performed by sequentially repeating the plurality of branches to connect to the destination branch.

[0200] (4) The first time deinterleaving method is a time deinterleaving method for performing time deinterleaving including convolutional deinterleaving on multiple data units. The time deinterleaver for performing the above time deinterleaving method includes a convolutional deinterleaver for performing the above convolutional deinterleaving. The above convolutional deinterleaver includes: a first switch for switching the connection destination of the input of the convolutional deinterleaver to one end of a certain branch among a plurality of branches equal in number to the number of interleaving units in which the data units to be deinterleaved are arranged; FIFO (first in, first out) memories provided in some of the plurality of branches except for one branch, with different numbers among these some branches; a second switch for switching the connection destination of the output of the convolutional deinterleaver to the other end of a certain branch among the plurality of branches; the first switch switches the connection destination when a plurality of data units equal in number to the number of codewords per frame have passed, and the switching of the connection destination is performed by sequentially repeating the plurality of branches to connect to the destination branch; the second switch switches the connection destination when a plurality of data units equal in number to the number of codewords per frame have passed, and the switching of the connection destination is performed by sequentially repeating the plurality of branches to connect to the destination branch.

[0201] Industrial applicability

[0202] The present invention can be used in a time interleaver for time interleaving multiple data units and a corresponding time deinterleaver.

[0203] Description of Reference Numerals

[0204] 100 Transmitter

[0205] 110 Input Processing Unit

[0206] 120 BICM Encoder

[0207] 130 Time Interleaver

[0208] 140 Modulator

[0209] 150 RF Front End

[0210] 160 Antenna

[0211] 310 Delay Unit

[0212] 320 Stacking Unit

[0213] 330 Reading Unit

[0214] 410 Separation Unit

[0215] 420 Depiling Unit

[0216] 430 Delay Unit

[0217] 500 Time Interleaver

[0218] 510 Row-Column Block Interleaver

[0219] 520, 520A, 520B Block Interleaver

[0220] 530 Convolutional Interleaver

[0221] 540 Switch

[0222] 545-11, 545-21, 545-22 Memory Unit

[0223] 550 Switch

[0224] 700 Time Deinterleaver

[0225] 710 Row-Column Block Deinterleaver

[0226] 720 Block Deinterleaver

[0227] 730 Convolutional Deinterleaver

[0228] 740 Switch

[0229] 745-01, 745-02, 745-11 Memory Unit

[0230] 750 Switch

[0231] 1000 Time Interleaver

[0232] 1020 Block Interleaver

[0233] 1030 Convolutional Interleaver

[0234] 1040 Switch

[0235] 1045 FIFO Register

[0236] 1050 Switch

[0237] 1100 Time De - Interleaver

[0238] 1120 Block De - Interleaver

[0239] 1130 Convolutional De - Interleaver

[0240] 1140 Switch

[0241] 1145 FIFO Register

[0242] 1150 Switch

Claims

1. A convolutional interleaver, which is a convolutional interleaver for performing convolutional interleaving, wherein, it includes: A first switch that switches the first connection destination of the input end of the convolutional interleaver to one end of a certain branch among multiple branches whose number is equal to the number of interleaving units configured with the data units to be interleaved; Multiple FIFO registers, which are arranged in a part of the branches among the multiple branches except for one branch, and the number is different among the multiple branches, and additional FIFO registers are added to each lower branch. The FIFO register is a first-in first-out register; and A second switch that switches the second connection destination of the output end of the convolutional interleaver to the other end of a certain branch among the multiple branches, The uppermost branch does not include a FIFO register, the branches lower than the uppermost branch include FIFO registers, and each branch that is one bit lower has one more FIFO register, When the number of data units equal to the number of codewords of each frame has passed, the first switch switches the first connection destination of the input end by sequentially switching the branch corresponding to the first connection destination among the multiple branches; When the number of data units equal to the number of codewords of each frame has passed, the second switch switches the second connection destination of the output end by sequentially switching the branch corresponding to the second connection destination among the multiple branches; The first switch and the second switch always point to the same branch.

2. A convolutional deinterleaver, which is a convolutional deinterleaver for performing convolutional deinterleaving, wherein, it includes: A first switch that switches the first connection destination of the input end of the convolutional deinterleaver to one end of a certain branch among multiple branches whose number is equal to the number of interleaving units configured with the data units to be deinterleaved; Multiple FIFO registers, which are arranged in a part of the branches among the multiple branches except for one branch, and the number is different among the multiple branches, and additional FIFO registers are added to each upper branch. The FIFO register is a first-in first-out register; and A second switch that switches the second connection destination of the output end of the convolutional deinterleaver to the other end of a certain branch among the multiple branches, The lowermost branch does not include a FIFO register, the branches higher than the lowermost branch include FIFO registers, and each branch that is one bit higher has one more FIFO register, When the number of data units equal to the number of codewords of each frame has passed, the first switch switches the first connection destination of the input end by sequentially switching the branch corresponding to the first connection destination among the multiple branches; When the number of data units equal to the number of codewords of each frame has passed, the second switch switches the second connection destination of the output end by sequentially switching the branch corresponding to the second connection destination among the multiple branches; The first switch and the second switch always point to the same branch.

3. A convolutional interleaving method, wherein, it includes: a step of switching the first connection destination at the input end of a convolutional interleaver to one end of a certain branch among a plurality of branches equal in number to the number of interleaving units configuring the data units to be interleaved through a first switch; a step of setting a plurality of FIFO registers in the plurality of branches except for one branch, the number of the plurality of FIFO registers being different from each other among the plurality of branches, and additional FIFO registers being added to the lower-positioned branches, the FIFO register being a first-in first-out register; and a step of switching the second connection destination at the output end of the convolutional interleaver to the other end of a certain branch among the plurality of branches through a second switch, the uppermost branch does not include a FIFO register, the branches lower than the uppermost branch include FIFO registers, and each branch lower by one position has one more FIFO register, in the switching performed by the first switch, when a plurality of data units equal in number to the number of codewords of each frame have passed, the first switch switches the first connection destination at the input end by sequentially switching the branch corresponding to the first connection destination among the plurality of branches; in the switching performed by the second switch, when a plurality of data units equal in number to the number of codewords of each frame have passed, the second switch switches the second connection destination at the output end by sequentially switching the branch corresponding to the second connection destination among the plurality of branches, the first switch and the second switch always point to the same branch.

4. A convolutional deinterleaving method, wherein, it includes: a step of switching the first connection destination at the input end of a convolutional deinterleaver to one end of a certain branch among a plurality of branches equal in number to the number of interleaving units configuring the data units to be deinterleaved through a first switch; a step of setting a plurality of FIFO registers in the plurality of branches except for one branch, the number of the plurality of FIFO registers being different from each other among the plurality of branches, and additional FIFO registers being added to the upper-positioned branches, the FIFO register being a first-in first-out register; and a step of switching the second connection destination at the output end of the convolutional deinterleaver to the other end of a certain branch among the plurality of branches through a second switch, the lowermost branch does not include a FIFO register, the branches higher than the lowermost branch include FIFO registers, and each branch higher by one position has one more FIFO register, in the switching performed by the first switch, when a plurality of data units equal in number to the number of codewords of each frame have passed, the first switch switches the first connection destination at the input end by sequentially switching the branch corresponding to the first connection destination among the plurality of branches, In the switching performed by the second switch, when a plurality of data units equal in number to the number of codewords per frame have passed, the second switch switches the second connection destination of the output terminal by sequentially switching the branches corresponding to the second connection destination among the plurality of branches. The first switch and the second switch always point to the same branch.

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