Sub-clock current pulse generator

Abstract

Embodiments of the present disclosure relate to a sub-clock current pulse generator. A delay-locked loop includes a control loop that receives reference and feedback clock signals and generates a bias voltage based on the reference and feedback clock signals. A delay chain receives the reference clock signal and generates N consecutive delayed versions of the reference clock signal, each at consecutive taps of the delay chain. The Nth delayed version is the feedback clock signal. The control loop has a phase detector that asserts an up signal when the phase of the feedback clock signal lags the phase of the reference clock signal and asserts a down signal when the phase of the feedback clock signal leads the phase of the reference clock signal. A digital filter block compares the number of assertions of the up signal during a reference clock signal period with the number of assertions of the down signal and, based thereon, asserts an up or down command signal. A bias voltage generation circuit receives the up and down command signals and generates a bias voltage based thereon.

Description

Technical Field

[0001] This application relates to the field of pulse generation, and more particularly, to the generation of pulses having a fraction of the reference clock pulse width. Background Art

[0002] Augmented reality technology is a technology that uses superimposed computer-generated images to enhance the real-time direct or indirect view of the physical real world. For example, augmented reality technology can be incorporated into a head-mounted headset worn by a user, such that the computer-generated images are superimposed on the user's view of the real world. The computer-generated images can be information about the real world (e.g., the name of a landmark), information related to the user's own life (e.g., a reminder of an upcoming appointment), etc.

[0003] Some augmented reality head-mounted headsets involve the use of such a micro-projector that scans RGB lasers across a separate screen for each eye in a scanning mode at a rate sufficient to form a visible image. For this type of augmented reality head-mounted headset, precise control of the laser power and pulse width is of concern to ensure proper functionality and that the images appear as expected.

[0004] Other augmented reality head-mounted headsets involve the use of such a micro-projector that scans RGB lasers across each eye in a scanning mode at a rate sufficient for the eyes to perceive the image. For this type of augmented reality head-mounted headset, precise control of the laser power and pulse width is of particular concern to avoid causing discomfort to the user's eyes.

[0005] Although there are technologies for precisely controlling the laser power, there is still a need for technologies for precisely controlling the laser pulse width. Therefore, there is a need for further development in this field. Summary of the Invention

[0006] The delay-locked loop disclosed herein includes a control loop configured to receive a reference clock signal and a feedback clock signal and generate a first bias voltage and a second bias voltage based on the reference clock signal and the feedback clock signal. The delay-locked loop further includes a delay chain configured to receive the reference clock signal and generate N successively delayed versions of the reference clock signal, each of the N successively delayed versions of the reference clock signal being at a successive tap of the delay chain. The delay-locked loop further includes a pulse decoder configured to generate a pulse output signal having a pulse width equal to a desired fraction of the pulse width of the reference clock signal by selecting taps (e.g., two taps) of the delay chain to be used as inputs. The delay chain has N delay units.

[0007] Each nth delay unit (where n is an integer between 1 and N) of the N delay units has: a delay block configured to receive the (n-1)th delayed output signal and generate the nth delayed signal, the nth delayed signal being equal to the reference clock signal delayed as follows: n / N of the reference clock signal minus an additional delay, but if (n-1) equals zero, the delay block is instead configured to receive the reference clock signal; and a virtual block having circuitry and virtual logic, the circuitry being configured to receive the nth delayed signal and output the nth delayed signal at the nth tap of the delay chain, the virtual logic being configured to receive the nth delayed signal from the circuitry and add an additional delay to the nth delayed signal, the additional delay being a function of the delay time in the pulse decoder, the virtual logic also being configured to generate the nth delayed output signal, the nth delayed output signal being equal to the nth delayed signal delayed by the additional delay. The feedback clock signal is the Nth delayed output signal.

[0008] The pulse decoder can also be configured to receive an input integer m, and the desired fraction can be m / N.

[0009] The circuitry configured to receive the nth delayed signal and output the nth delayed signal at the nth tap of the delay chain can be a buffer circuit configured to receive the nth delayed signal, buffer the nth delayed signal, and output the nth delayed signal at the nth tap of the delay chain.

[0010] The delay block of each n-th delay unit may include: a first current source transistor configured to be biased by a first bias voltage and configured to generate a first bias current; and a second current source transistor configured to be biased by a second bias voltage and configured to generate a second bias current. The delay block of each n-th delay unit may further include an inverter having an inverter PMOS transistor and an inverter NMOS transistor. The source of the inverter PMOS transistor is coupled to the first current source transistor to receive the first bias current, and the gate of the inverter PMOS transistor is configured to receive the (n-1)-th delayed output signal. The drain of the inverter NMOS transistor is coupled to the drain of the inverter PMOS transistor, the source of the inverter NMOS transistor is coupled to the second current source transistor to receive the second bias current, and the gate of the inverter NMOS transistor is configured to receive the (n-1)-th delayed output signal. The inverter may be configured to generate an n-th delayed signal at the drain of the inverter PMOS transistor and the drain of the inverter NMOS transistor. The delay block of each n-th delay unit may further include a pseudo-inverter having a pseudo-inverter PMOS transistor including a source coupled to the source of the first current source transistor to receive the first bias current, a drain coupled to ground, and a gate configured to receive the complement of the (n-1)-th delayed output signal. The delay block of each n-th delay unit may further include a pseudo-inverter NMOS transistor having a drain coupled to a supply voltage, a source coupled to the source of the second current source transistor to receive the second bias current, and a gate configured to receive the complement of the (n-1)-th delayed output signal.

[0011] Another aspect disclosed herein is a delay locked loop including: a control loop configured to receive a reference clock signal and a feedback clock signal and generate a first bias voltage based on the reference clock signal and the feedback clock signal; a delay chain configured to receive the reference clock signal and generate N consecutive delayed versions of the reference clock signal, each of the N consecutive delayed versions of the reference clock signal being at a consecutive tap of the delay chain; and a pulse decoder configured to generate a pulse output signal having a pulse width equal to a desired fraction of the pulse width of the reference clock signal by selecting taps (e.g., two taps) of the delay chain to be used as inputs. The delay chain includes N delay units.

[0012] Each nth delay unit (where n is an integer between 1 and N) among the N delay units includes: a delay circuit biased by a first bias voltage, configured to receive a (n - 1)th delayed output signal and generate an nth delayed signal, the nth delayed signal being equal to the reference clock signal delayed by: n / N of the reference clock signal minus an additional delay, but if (n - 1) equals zero, the delay circuit is instead configured to receive the reference clock signal, the delay circuit is further configured to output the nth delayed signal at the nth tap of the delay chain and add the additional delay to the nth delayed signal, the additional delay being a function of the delay time in the pulse decoder. The delay circuit is further configured to generate an nth delayed output, the nth delayed output being equal to the nth delayed signal delayed by the additional delay. The feedback clock signal is the Nth delayed output signal.

[0013] The delay circuit of each nth delay unit may include: a first current source transistor configured to be biased by a first bias voltage and configured to generate a first bias current; a second current source transistor configured to be biased by the first bias voltage and configured to generate a second bias current; and a first inverter. The first inverter may include a first inverter PMOS transistor and a first inverter NMOS transistor. The source of the first inverter PMOS transistor is coupled to a supply voltage, the gate of the first inverter PMOS transistor is configured to receive the (n-1)th delay output signal, the drain of the first inverter NMOS transistor is coupled to the drain of the first inverter PMOS transistor, the source of the first inverter NMOS transistor is coupled to the first current source transistor to receive the first bias current, and the gate of the first inverter NMOS transistor is configured to receive the (n-1)th delay output signal. The first inverter is configured to generate a first attenuation ramp signal in response to an assertion of the (n-1)th delay output signal. The delay circuit of each nth delay unit may further include a second inverter. The second inverter may include a second inverter PMOS transistor and a second inverter NMOS transistor. The second inverter PMOS transistor has a source coupled to the supply voltage and a gate configured to receive the complement of the (n-1)th delay output signal. The drain of the second inverter NMOS transistor is coupled to the drain of the first inverter PMOS transistor, the source of the second inverter NMOS transistor is coupled to the second current source transistor to receive the second bias current, and the gate of the second inverter NMOS transistor is configured to receive the complement of the (n-1)th delay output signal. The second inverter may be configured to generate a second attenuation ramp signal in response to an assertion of the complement of the (n-1)th delay output signal. The delay circuit of each nth delay unit may further include circuitry configured to start generation of a rising edge of the nth delay output signal when the first attenuation ramp signal falls below a threshold voltage and to start generation of a falling edge of the nth delay output signal when the second attenuation ramp signal falls below the threshold voltage.

[0014] The first bias current and the second bias current may be equal and may have an amplitude such that when the (n-1)th delay output signal is asserted, the first inverter generates a first attenuation ramp signal while the second inverter generates a first rising edge, and when the (n-t)th delay output signal is deasserted, the second inverter generates a second attenuation ramp signal while the first inverter generates a second rising edge, the amplitude of the slope of the first attenuation ramp signal being less than the amplitude of the slope of the first rising edge, and the amplitude of the slope of the second attenuation ramp signal being less than the amplitude of the slope of the second rising edge.

[0015] The circuit system may include a first set PMOS transistor having a source coupled to a supply voltage, a gate coupled to the drains of a first inverter PMOS transistor and a first inverter NMOS transistor, and a drain coupled to a first common node. The circuit system may further include a first reset NMOS transistor having a drain coupled to a second common node, a gate coupled through an inverter to the drains of the first inverter PMOS transistor and the first inverter NMOS transistor, and a source coupled to ground. The circuit system may also include a second set PMOS transistor having a source coupled to the supply voltage, a gate coupled to the drains of a second inverter PMOS transistor and a second inverter NMOS transistor, and a drain coupled to the second common node. The circuit system may further include a second reset NMOS transistor having a source coupled to the first common node, a gate coupled through an inverter to the drains of the second inverter PMOS transistor and the second inverter NMOS transistor, and a source coupled to ground. The nth delayed output signal may be generated at the first common node, the complement of the nth delayed output signal may be generated at the second common node, and the SR latch may have a set input coupled to the first common node and a reset input coupled to the second common node.

[0016] The delay circuit of each nth delay unit may further include an OR gate having a first input coupled to the drains of the first inverter PMOS transistor and the first inverter NMOS transistor, a second input coupled to the select signal through an inverter, a third input coupled to the first common node, and an output. The delay circuit of each nth delay unit may further include a PMOS transistor having a source coupled to the supply voltage, a gate coupled to the output of the OR gate, and a drain at which the nth delayed signal is generated. The delay circuit of each nth delay unit may further include an NMOS transistor having a source coupled to ground, a gate coupled through an inverter to the output of the OR gate, and a drain at which the complement of the nth delayed signal is generated.

[0017] By generating rising edges and falling edges, a pulse output signal can be generated to have a pulse width equal to a desired fraction of the pulse width of a reference clock signal. Each of the N delay cells can be used to generate a rising edge or a falling edge, where the total number of the N delay cells used to generate rising edges indicates the delay between the start of a period of the reference clock signal and the rising edge, and the total number of the N delay cells used to generate falling edges indicates the delay between the falling edge and the end of a period of the reference clock signal. Additionally, the pulse decoder can include circuitry configured to perform the following operations: select a first series of taps, the first series of taps representing the delayed signals respectively generated by each of the N delay cells that are used to generate the rising edge of the pulse output signal; select a second series of taps, the second series of taps representing the complements of the delayed signals respectively generated by each of the N delay cells that are used to generate the rising edge of the pulse output signal; select a third series of taps, the third series of taps representing the delayed signals respectively generated by each of the N delay cells that are used to generate the falling edge of the pulse output signal; and select a fourth series of taps, the fourth series of taps representing the complements of the delayed signals respectively generated by each of the N delay cells that are used to generate the falling edge of the pulse output signal. The pulse decoder can further include an SR latch having a set input, a reset input, and an output that generates the pulse output signal through a buffer, the set input being coupled to the first series of taps and the fourth series of taps, and the reset input being coupled to the second series of taps and the third series of taps.

[0018] The delay cell among the N delay cells associated with the last tap of the first series of taps can receive an asserted version of the select signal, and the delay cell among the N delay cells associated with the first tap of the third series of taps can receive an asserted version of the select signal. The remaining delay cells among the N delay cells can receive a deasserted version of the select signal.

[0019] The control loop may include a phase detector configured to: receive a reference clock signal and a feedback clock signal; assert an up signal in response to the phase of the feedback clock signal lagging behind the phase of the reference clock signal; and assert a down signal in response to the phase of the feedback clock signal leading the phase of the reference clock signal. The control loop may further include a digital filter block configured to: receive the up signal and the down signal; count the number of assertions of the up signal during a plurality of cycles of the reference clock signal; count the number of assertions of the down signal during a plurality of cycles of the reference clock signal; compare the number of assertions of the up signal during a plurality of cycles of the reference clock signal with the number of assertions of the down signal during a plurality of cycles of the reference clock signal; and then assert an up command signal or a down command signal based on the comparison result. The control loop may further include a bias voltage generation circuit configured to receive the up command signal and the down command signal and generate a first bias voltage based on the up command signal and the down command signal.

[0020] The control loop may include a phase detector configured to: receive a reference clock signal and a feedback clock signal; assert an up signal in response to the phase of the feedback clock signal lagging behind the phase of the reference clock signal; and assert a down signal in response to the phase of the feedback clock signal leading the phase of the reference clock signal. The control loop may further include a digital filter block configured to: receive the up signal and the down signal; count the number of assertions of the up signal during a plurality of cycles of the reference clock signal; count the number of assertions of the down signal during a plurality of cycles of the reference clock signal; compare the number of assertions of the up signal during a plurality of cycles of the reference clock signal with the number of assertions of the down signal during a plurality of cycles of the reference clock signal; and then assert an up command signal or a down command signal according to the comparison result. The digital filter block may be further configured to assert a trigger signal substantially simultaneously with asserting the up command signal or the down command signal.

[0021] The control loop may further include a monostable configured to receive the trigger signal and assert the output of the monostable as a pulse based on receiving the trigger signal. A first AND gate may be configured to receive the up command signal and the output of the monostable and generate a first switch control signal as a result of a logical AND operation between the up command signal and the output of the monostable. A second AND gate is configured to receive the down command signal and the output of the monostable and generate a second switch control signal as a result of a logical AND operation between the down command signal and the output of the monostable.

[0022] An integrating capacitor can be coupled between a node and ground. A first switch can be configured to selectively couple the integrating capacitor to a current source in response to an assertion of a first switch control signal. A second switch can be configured to selectively couple the integrating capacitor to a current sink in response to an assertion of a second switch control signal. An operational transconductance amplifier can have an inverting terminal coupled to the node, a non-inverting terminal coupled to a second node, and an output. A resistor can be coupled between the second node and ground. A first PMOS transistor can have a source coupled to a supply voltage, a drain coupled to the second node, and a gate coupled to the output of the operational transconductance amplifier. A second PMOS transistor can have a source coupled to the supply voltage, a drain coupled to a diode-coupled NMOS transistor to generate a first bias voltage, and a gate coupled to the output of the operational transconductance amplifier.

[0023] The digital filtering block can be further configured to generate a current source control signal for the current source based on a comparison of the number of assertions of the upper signal during a plurality of cycles of a reference clock signal with the number of assertions of the lower signal during the plurality of cycles of the reference clock signal; and generate a current sink control signal for the current sink based on a comparison of the number of assertions of the upper signal during the plurality of cycles of the reference clock signal with the number of assertions of the lower signal during the plurality of cycles of the reference clock signal.

[0024] Another aspect disclosed herein is a delay-locked loop including a control loop configured to receive a reference clock signal and a feedback clock signal and generate at least one bias voltage based on the reference clock signal and the feedback clock signal. The delay-locked loop further includes a delay chain configured to receive the reference clock signal and generate N consecutive delayed versions of the reference clock signal, each of the N consecutive delayed versions of the reference clock signal being at consecutive taps of the delay chain, wherein the Nth delayed version of the reference clock signal is the feedback clock signal. The control loop further includes a phase detector configured to: receive the reference clock signal and the feedback clock signal; assert an up signal in response to the phase of the feedback clock signal lagging behind the phase of the reference clock signal; and assert a down signal in response to the phase of the feedback clock signal leading the phase of the reference clock signal. The control loop may further include a digital filtering block configured to: receive the up signal and the down signal; count the number of assertions of the up signal during a plurality of cycles of the reference clock signal; count the number of assertions of the down signal during a plurality of cycles of the reference clock signal; compare the number of assertions of the up signal during a plurality of cycles of the reference clock signal with the number of assertions of the down signal during a plurality of cycles of the reference clock signal; and then assert an up command signal or a down command signal based on the comparison result. The control loop further includes a bias voltage generation circuit configured to receive the up command signal and the down command signal and generate at least one bias voltage based on the up command signal and the down command signal.

[0025] The digital filtering block may be further configured to assert a trigger signal substantially simultaneously with the assertion of the up command signal or the down command signal.

[0026] The bias voltage generation circuit may include a monostable configured to receive the trigger signal and assert the output of the monostable as a pulse based on the received trigger signal. The bias voltage generation circuit may further include a first AND gate configured to receive the up command signal and the output of the monostable and generate a first switch control signal as a result of a logical AND operation between the up command signal and the output of the monostable. The bias voltage generation circuit may further include a second AND gate configured to receive the down command signal and the output of the monostable and generate a second switch control signal as a result of a logical AND operation between the down command signal and the monostable.

[0027] The bias voltage generating circuit may further include: an integrating capacitor coupled between the node and ground; a current source; a first switch configured to selectively couple the integrating capacitor to the current source in response to the assertion of a first switch control signal; a current sink; a second switch configured to selectively couple the integrating capacitor to the current sink in response to the assertion of a second switch control signal; and an operational transconductance amplifier having an inverting terminal coupled to the node, a non-inverting terminal coupled to a second node, and an output. The bias voltage generating circuit may further include a resistor coupled between the second node and ground; and a first PMOS transistor having a source coupled to a supply voltage, a drain coupled to the second node, and a gate coupled to the output of the operational transconductance amplifier. The bias voltage generating circuit may further include a second PMOS transistor having a source coupled to the supply voltage, a drain coupled to the drain of a diode-coupled NMOS transistor to generate at least one bias voltage, and a gate coupled to the output of the operational transconductance amplifier.

[0028] The digital filter block may be further configured to generate a current source control signal for the current source and a current sink control signal for the current sink based on a comparison of the number of assertions of the upper signal during a plurality of cycles of the reference clock signal with the number of assertions of the lower signal during the plurality of cycles of the reference clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1A is a block diagram of a first embodiment of a circuit for generating a pulse signal having a pulse width equal to a desired fraction of the pulse width of a reference clock signal.

[0030] Figure 1B is a diagram showing a reference clock (CKref), and delayed versions (CK1...CKN) of the reference clock generated by Figure 1A a delay locked loop.

[0031] Figure 2 is Figure 1A a block diagram of a delay cell of

[0032] Figure 3 is Figure 2 a schematic diagram of a delay block of

[0033] Figure 4 is Figure 2 a schematic diagram of details of a dummy block of

[0034] Figure 5Block diagram of a second embodiment of a circuit for generating a pulse signal having a pulse width equal to a desired fraction of the pulse width of a reference clock signal.

[0035] Figure 6 Is Figure 5 Schematic block diagram of a pulse decoder of Figure 5 Block diagram of a delay chain of

[0036] Figure 7 Is Figures 5 - 6 Schematic diagram of a sample delay cell in a delay cell of

[0037] Figure 8 Is a timing diagram showing Figure 7 The operation of a delay cell of

[0038] Figure 9 Schematic block diagram of an alternative design of a circuit for generating a pulse signal having a pulse width equal to a desired fraction of the pulse width of a reference clock signal. Detailed Description

[0039] The following disclosure enables one of ordinary skill in the art to make and use the subject matter disclosed herein. Without departing from the spirit and scope of this disclosure, the general principles described herein can be applied to embodiments and applications other than those detailed above. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

[0040] First, referring to Figure 1A , the delay locked loop (DLL) 5 is now described. The delay locked loop (DLL) 5 includes a control loop 9, a delay chain 14, and a pulse decoder 15. For ease of understanding, the delay chain 14 will first be described as a whole; later, specific implementation details and specific operation details will be given.

[0041] The delay chain 14 includes N delay cells 14A... 14N, where N is any integer. The first delay cell 14A receives the reference clock CKref as an input, is controlled by control signals VCTRLn and VCTRLp, and outputs a delayed version CK1 of the reference clock CKref along with the complement CKb1 of the delayed version, which is suitable for use by the control loop 9 in locking the delay provided by the delay chain 14 to generate a final delayed version CKN of the reference clock CKref (representing a one-cycle delay compared to CKref).

[0042] Each remaining delay unit 14B...14N receives the output of the immediately preceding delay unit as input and is similarly controlled by control signals VCTRLn and VCTRLp. Accordingly, each remaining delay unit 14B...14N outputs a corresponding increased delay version of the reference clock CKref - CK1 and CKb1 are delayed from CKref by 1 / N of the period of CKref, while CK2 and CKb2 are delayed from CKref by 2 / N of the period, and so on, until CKN is delayed from CKref by the entire period of CKref.

[0043] In Figure 1B are illustrated N delayed versions of the reference clock CKref produced by the delay chain 14, Figure 1B showing the reference clock CKref, and the N delayed versions CK1...CKN of the reference clock produced by the delay chain 14. N defines the sub-order, into which the DLL 5 divides the entire period of the reference clock CKref. For this example, N is 8, and it can be seen that the entire period of the reference clock CKref is divided into 8 sub-steps. Accordingly, it can be seen that CK1 is delayed from the reference clock CKref by 1 / 8 of the period, CK2 is delayed from the reference clock CKref by 2 / 8 of the period, and so on, until CKN (here CK8) is delayed by the full period of CKref.

[0044] The control loop 9 receives the reference clock CKref and CKN and generates the control signals VCTRLn and VCTRLp in a manner that maintains the phase alignment between CKref and CKN (also as Figure 1B shown, where CKref and CKN are in phase alignment). More specifically, the control loop 9 includes a phase detector 11 that receives CKN and the reference clock CKref, the phase detector 11 generating a control signal Up / Dn for a charge pump 12, the charge pump 12 generating the control signals VCTRLn and VCTRLp so as to maintain the phase alignment between CKN and CKref. The loop filter 13 for the control loop 9 is a low-pass filter as shown (and can be, for example, a capacitor coupled between the output of the charge pump 12 and ground), but other filtering techniques can be used.

[0045] The function and purpose of the pulse decoder 15 will be explained below, but, generally speaking, the pulse decoder produces a pulse output signal Pulse m , the pulse output signal Pulse ma pulse width of m / N of the pulse width of the reference clock CKref and having a fixed position within the period of the reference clock CKref (e.g., occurring during the fourth sub-stage of the period of the reference clock CKref), where m is the input to the pulse decoder 15. Note that the problem introduced by the pulse decoder 15 is that it introduces its own delay, meaning that the Pulse m pulse will not occur during the desired portion of the CKref pulse. Since this is undesirable, the delay chain 14 has been designed to compensate for the delay introduced by the pulse decoder 15.

[0046] Accordingly, the first delay unit 14A also outputs a version CK1dec of CK1 and its complement CKb1dec, and the complement CKb1dec is suitable for use by the pulse decoder 15 in generating the pulse output signal Pulse m . Compared with CK1 and CK1b, CK1dec and CKb1dec lack the additional delay expected in the pulse decoder 15 at this tap position. Thus, CK1 and CKb1 are delayed from CKref by 1 / N of the period of CKref, while CK1dec and CKb1dec are delayed from CKref as follows: 1 / N of the period of CKref minus the additional delay expected in the pulse decoder 15.

[0047] Each of the remaining delay units 14B...14N also outputs a version of its delayed signal for use by the pulse decoder 15 - the delay unit 14B outputs a version CK2dec of CK2 (and its complement CKb2dec), and so on until the delay unit 14N outputs a version CKNdec of CKN (and its complement CKbNdec). Here, CK2dec and CKb2dec are delayed from CKref as follows: 2 / N of the period of CKref minus the additional delay expected in the pulse decoder 15, and so on until CKNdec and CKbNdec are delayed from CKref as follows: the entire period of CKref minus the additional delay expected in the pulse decoder 15.

[0048] The pulse decoder 15 receives as inputs the delayed versions CK1dec...CKNdec of the reference clock CKref from the delay chain 14 (in addition to their complements), and the input code m. By using CK1dec...CKNdec and CKb1dec...CKbNdec instead of CK1...CKN in the pulse decoder 15, the pulse decoder 15 generates the pulse output signal Pulse m such that the pulse output signal Pulse m appropriately has a pulse width of m / N and a fixed position within the period of the reference clock CKref. Thus, by selecting the value of m, the pulse output signal Pulsem The pulse width thereof, and its position within the period of the reference clock CKref, are selected. The output Pulse m can be used, for example, as an input to a laser driver used in a micro-projector, although other uses can be envisioned.

[0049] Typically, in a laser driver, during each period of CKref, a current (appropriately modulated in amplitude) is output. However, designers typically desire to output this current within less than the entire period of CKref (e.g., within a fraction N of the entire period of CKref). As will be understood by those skilled in the art, this helps to provide brightness control and also reduces so-called speckle noise. However, Pulse m 's position within the CKref period must be well-defined and fixed. The pulse decoder is outside the loop of the DLL, so in prior art designs, the errors (e.g., delays) introduced by the pulse decoder cannot be well-controlled. However, using the DLL 5 disclosed herein allows this delay (at the first order) to be eliminated, resulting in Pulse m 's position being preferably defined within the period of CKref.

[0050] To achieve this functionality, the pulse decoder 15 (depending on the value of m) combines the outputs or "taps" (e.g., two taps) of the delay chain 14 to produce a Pulse with a desired rising edge and a desired falling edge m .

[0051] To compensate for the delay in the pulse decoder 15, as explained, the delayed versions CK1dec...CKNdec and CKb1dec...CKbNdec of the reference clock used by the pulse decoder 15 (compared to the delayed versions CK1...CKN and CKb1...CKbN of the reference clock CKref) have removed the expected delay in the pulse decoder 15 from it. This "expected" delay in the pulse decoder 15 is intended to simulate the delay experienced in a virtual path using the current tap selection derived from the current value of m. In Figure 1B the example shown, m is, for example, 1, and N is, for example, 8, resulting in Pulse m having a pulse width of 1 / 8 of the period of CKref as shown.

[0052] To state the above operation in another way, if the DLL 5 is properly locked and the delay units 14A...14N are matched, the purpose of the control loop 9 is to make the edges of CKref and CKN coincide. As a result, each delay unit 14A...14N will occupy exactly 1 / N of the entire CKref period, so the output of each delay unit 14A...14N represents a timing point located at n / N [1, 2,... N] of the period of CKref. The taps of the delay units 14A...14N that have been combined to generate Pulse m The delay introduced by the pulse decoder 15 will shift the effective edge relative to their exact n / N positions. Taking taps before the dummy unit introduces more or less the same delay as the pulse decoder path to allow compensation for this delay, thereby re-aligning the Pulse m edge back to the n / N timing position.

[0053] Figure 2 The block diagram of a single delay unit 14' is shown in

[0054] The delay block 16 is controlled by the control signals VCTRLp and VCTRLn and receives as inputs a delayed version of the reference clock CKref generated by the previous delay unit in the delay chain 14, and the complement of this delayed version - here, these are represented as CK(n - 1) and CKb(n - 1) (where n is any positive integer up to N). Note that if the delay unit 14' is the first delay unit in the delay chain 14, the delay block 16 will receive CKref as an input instead of CK(n - 1) and CKb(n - 1). The delay block 16 produces an intermediate signal labeled nCK(n - 1) as an output.

[0055] The dummy block 17 receives the intermediate signal nCK(n - 1) as an input, delays this intermediate signal by an amount intended to simulate the delay in the pulse decoder 15, and produces from the dummy block a delayed version CKn of the clock signal CKref and its complement CKbn. The dummy block 17 also produces versions CKndec and CKbndec of CKn and CKbn for use by the pulse decoder 15.

[0056] Details of the delay block 16 are in Figure 3is shown. The delay block 16 includes a CMOS inverter arrangement that is created by a series connection of a PMOS transistor MP2 and an NMOS transistor MN1 (receiving CK(n-1) as an input and generating nCK(n-1) as an output), where the source of the PMOS transistor MP2 is biased by a current that is sourced from the power supply VDD through the PMOS transistor MP1, while the source current bias of the NMOS transistor MN1 is biased by a current that is sunk to ground through the NMOS transistor MN2. The PMOS transistor MP1 is controlled by the VCTRLp signal generated by the charge pump 12 of the control loop 9 (since VCTRLp controls the magnitude of the source current generated by MP1), while the NMOS transistor MN2 is biased by the VCTRLn signal generated by the charge pump 12 of the control loop 9 (since VCTRLn controls the magnitude of the sink current generated by MN2). The delay capacitor Cc is coupled between the drain of MP2 / drain of MN1 and ground. The purpose of the PMOS transistor MP1 and the NMOS transistor MN2 is to provide a stable current to the CMOS inverter arrangement without turning off, thus allowing the problems that would occur when these transistors switch to be avoided. Therefore, it should be understood that although the control loop 9 adjusts VCTRLp and VCTRLn, the control loop 9 does not reduce them to such an extent that the PMOS transistor MP1 and the NMOS transistor MN2 fall out of saturation and turn off. Instead, any adjustment will change the rise and / or fall slope of the output nCK(n-1).

[0057] To understand Figure 3 the operation of the delay block 16, consider Figure 3 (ignoring the PMOS transistor MP3 and the NMOS transistor MN3, which will be described below) shows a delay cell in which the PMOS transistor MP1 and the NMOS transistor MN2 are (identical) current generators that are always biased on by the signals VCTRLp and VCTRLn. Those voltages are modulated by the control loop 9 to adjust the delay of the delay cell.

[0058] When CK(n-1) goes high, the NMOS transistor MN1 turns on, and the current through the NMOS transistor MN2 discharges the output capacitance (which includes the capacitor Cc). The time required for this current to discharge nCK(n-1) below the threshold voltage of the next gate (not shown in the figure) defines the delay of the rising edge of CK(n-1).

[0059] Similarly, when CK(n-1) goes low, the PMOS transistor MP2 turns on and the NMOS transistor MN1 turns off, and the current through the PMOS transistor MP1 charges the output capacitance (including the capacitor Cc).

[0060] Thus, although NMOS transistor MN2 and PMOS transistor MP1 are always on (with their VGS greater than their threshold voltages), they can only source / sink current to the output when NMOS transistor MN1 or PMOS transistor MP2 is turned on respectively. The control loop 9 that changes the VCTRLn and VCTRLp voltages will change the slope of charging and / or discharging the output capacitance (and thus change the time for charging and / or discharging the output capacitance).

[0061] Conventionally (where PMOS transistor MP3 and NMOS transistor MN3 do not exist), during the time when PMOS transistor MP1 and NMOS transistor MN2 are blocked by PMOS transistor MP2 or NMOS transistor MN1 respectively, PMOS transistor MP1 and NMOS transistor MN2 will have a drain-to-source voltage of 0. When PMOS transistor MP2 or NMOS transistor MN1 becomes active, since PMOS transistor MP2 or NMOS transistor MN1 has a drain-to-source voltage of 0 at the beginning, PMOS transistor MP2 or NMOS transistor MN1 cannot immediately provide an appropriate current. Also, conventionally, the switching of PMOS transistor MP2 or NMOS transistor MN1 also adds a charge contribution to the output node. Therefore, these two real-world effects will result in operating characteristics different from those when PMOS transistor MP1 and NMOS transistor MN2 act as ideal (controlled) current generators.

[0062] To address these real-world effects caused by the lack of ideal behavior of PMOS transistor MP1 and NMOS transistor MN2, PMOS transistor MP3 and NMOS transistor MN3 have been added.

[0063] The delay block 16 also includes a pseudo-inverter formed by PMOS transistor MP3 and NMOS transistor MN3. Here, the source of PMOS transistor MP3 is connected to the drain of PMOS transistor MP1 and the source of PMOS transistor MP2, the drain of PMOS transistor MP3 is connected to ground, and the gate of PMOS transistor MP3 is biased by CKb(n - 1). Additionally, the drain of NMOS transistor MN3 is connected to VDD, the source of NMOS transistor MN3 is connected to the source of NMOS transistor MN1 and the drain of NMOS transistor MN2, and the gate of NMOS transistor MN3 is also biased by CKb(n - 1) and thus connected to the gate of PMOS transistor MP3.

[0064] Consider the case where the PMOS transistor MP2 is turned off. In this case, the PMOS transistor MP3 is turned on, and the PMOS transistor MP1 is allowed to continue providing current. During this period, nCK(n - 1) is grounded through the NMOS transistor MN2. When CK(n - 1) goes low, the PMOS transistor MP2 is turned on, and the PMOS transistor MP3 is turned off. Thus, the PMOS transistor MP1 can continue to provide current; the drain - to - source voltage of the PMOS transistor MP1 hardly changes. Additionally, the PMOS transistors MP2 and MP3 (and the NMOS transistors MN3 and MN1) will switch such that one transistor is turned on while the other is turned off. Since they are designed to be the same size, the charge injection associated with the switching cancels out (to the first order).

[0065] Now consider the case where the NMOS transistor NM1 is turned off. In this case, the NMOS transistor MN3 is turned on, and the NMOS transistor MN2 is allowed to continue sinking current. During this period, nCK(n - 1) is pulled high by the PMOS transistor MP1. When CK(n - 1) goes high, the NMOS transistor MN1 is turned on and the NMOS transistor MN3 is turned off. Thus, the NMOS transistor MN2 can continue to sink current.

[0066] Details of the virtual block 17 are shown in Figure 4 The virtual block 17 includes a buffer 18 that receives the intermediate signal nCK(n - 1) and generates CKndec and CKbndec (by means of an inverter 20) from the intermediate signal for use by the pulse decoder 15. The virtual logic 19 is designed to replicate the delay of the current tap selection used in the pulse decoder 15 that is derived from the current value of m. Since it is CKndec and CKbndec that are used by the pulse decoder 15 to generate Pulse m , but it is CKN that is used by the control loop 9 of the DLL 5, thus, CKndec and CKbndec actually pre - compensate for the delay introduced by the current tap selection used by the pulse decoder 15 that is derived from the current value of m.

[0067] Therefore, this design of the DLL 5 using the delay chain 14 has compensated for and solved the delay problem introduced by the pulse decoder 15.

[0068] Now refer to Figure 5 to describe another embodiment of the DLL 5’. The delay - locked loop (DLL) 5’ includes a control loop 9’, a delay chain 14”, and a pulse decoder 15’. The overall functions of the control loop 9, the delay chain 14”, and the pulse decoder 15’ are the same as those in FIG. 1. However, the implementation details of the delay chain 14” and the pulse decoder 15’ are different.

[0069] The pulse decoder 15’ is shown in detail in Figure 6 . The pulse decoder 15’ includes a circuit 40 that receives an input m and connects each of CK1dec, CKb1dec...CKNdec, CKbNdec to either node N1 or node N2 based on a hardware definition. An SR latch formed by inverters 41 and 42 is coupled between node N1 and node N2. In particular, inverter 41 has an input of inverter 41 coupled to node N2 and an output of inverter 41 coupled to node N1, while inverter 42 has an input of inverter 42 coupled to node N1 and an output of inverter 42 coupled to node N2. Node N1 is tapped to provide the output Pulse of the pulse decoder 15’ through buffer 43 m .

[0070] Due to how the CK1dec, CKb1dec...CKNdec, CKbNdec signals are generated (as shown in Figure 7 and described in detail below), nodes N1 and N2 are for the major part of the CKref cycle and are not forced by any delay cells of the delay chain 14” (because, except for possible short pulses, Figure 7 M7 and M8 are off). Once a particular delay cell of the delay chain 14” sets or resets them in the SR latch, the logic states of N1 and N2 are maintained in the hold mode by the SR latch formed by inverters 41 and 42. The tap selection for creating the rising and falling times of the output pulse Pulse m is defined by the way in which the corresponding ones of CK1dec, CKb1dec...CKNdec, CKbNdec of a given delay cell of the delay chain 14” are connected to N1 and N2, and the value of the signal SEL (e.g., SEL1...SELN, which is based on the value of m) for each delay cell of the delay chain 14” itself.

[0071] This operation may be best understood with reference to a specific example. For this example, assume that Figure 6 the delay chain 14” and the pulse decoder 15’ are designed to generate an output pulse Pulse m , where the rising edge can occur at 1 / 8, 2 / 8, 3 / 8, or 4 / 8 of the CKref cycle and the falling edge can occur at 5 / 8, 6 / 8, 7 / 8, or 8 / 8 of the CKref cycle.

[0072] Thus, first, the first four delay units (14A’, 14B’, 14C’ and 14D’) will have CK1dec, CK2dec, CK3dec and CK4dec connected to N1, and CKb1dec, CKb2dec, CKb3dec and CKb4dec connected to node N2; similarly, the last four delay units (14E’, 14F’, 14G’ and 14H’, where 14H’ is 14N’ here) will have CK5dec, CK6dec, CK7dec and CK8dec connected to node N2, and CKb5dec, CKb6dec, CKb7dec, CKb8dec connected to node N1.

[0073] Now, if for example it is desired to generate a pulse Pulse m having a pulse width equal to 4 / 8 (so, m = 4, N = 8), where the rising edge is at 2 / 4 of the CKref period and the falling edge is at 6 / 8 of Ckref, then the delay units 14B’ and 14F’ are selected (where SEL is high). Thus, it is understood that the delay units (where SEL is high) for generating the rising edge are selected, the delay units (where SEL is high) for generating the falling edge are selected, and for the other delay units, SEL is low.

[0074] As will be understood by those skilled in the art, this arrangement can be generalized to place the pulse Pulse m at any desired position within the CKref period.

[0075] Now turning to Figure 7 , the sample delay unit 14”’ of the delay chain 14” is shown, where it is noted that this example is an example of the first delay unit in the delay chain 14”. The delay unit 14”’ includes a first CMOS inverter 51 formed by a PMOS transistor M1 and an NMOS transistor M2. Specifically, the PMOS transistor M1 has a source coupled to the supply voltage VDD, a drain coupled to the drain of the NMOS transistor M2 at node A, and a gate coupled to the gate of the NMOS transistor M2 to receive the reference clock signal CKref. The NMOS transistor M2 has a drain coupled to the drain of the PMOS transistor M1, a source coupled to the drain of the NMOS transistor M3, and a gate coupled to the gate of the PMOS transistor M1 to receive the reference clock signal CKref. The NMOS transistor M3 has a drain coupled to the source of the NMOS transistor M2, a source coupled to ground, and a gate biased by the VCTRLn signal, and the NMOS transistor M3 acts as a low-side current sink for the first CMOS inverter 51.

[0076] Here, note the following fact. The first CMOS inverter 51 is directly supplied by the power supply node VDD on its high side, but is supplied by the NMOS transistor M3 on its low side. Therefore, the rise of the output of the first CMOS inverter 51 will be basically a step, but the fall of the output of the first CMOS inverter 51 can be tuned by the amplitude of VCTRLn. Therefore, the control loop 9' of the DLL 5' tunes the amplitude of VCTRLn such that the fall of the output of the first CMOS inverter 51 is an attenuation relative to a step down (which can be seen in traces A and B as shown in Figure 8 as will be described below).

[0077] The delay unit 14''' also includes a second CMOS inverter 52 formed by a PMOS transistor M4 and an NMOS transistor M5. Specifically, the source of the PMOS transistor M4 is coupled to the supply voltage VDD, the drain of the PMOS transistor M4 is coupled to the drain of the NMOS transistor M5 at node B, and the gate of the PMOS transistor M4 is coupled to the gate of the NMOS transistor M5 to receive the reference clock signal CKref through the inverter 22. The drain of the NMOS transistor M5 is coupled to the drain of the PMOS transistor M4, the source of the NMOS transistor M5 is coupled to the drain of the NMOS transistor M6, and the gate of the NMOS transistor M5 is coupled to the gate of the PMOS transistor M4 to receive the reference clock signal CKref through the inverter. The drain of the NMOS transistor M6 is coupled to the source of the NMOS transistor M5, the source of the NMOS transistor M6 is coupled to ground, and the gate of the NMOS transistor M6 is biased by the VCTRLn signal, and the NMOS transistor M6 acts as the low-side current sink of the second CMOS inverter 52.

[0078] Here, note the following fact. The second CMOS inverter 52 is directly supplied by the power supply node VDD on its high side, but is supplied by the NMOS transistor M6 on its low side. Therefore, the rise of the output of the second CMOS inverter 52 will be basically a step, but the fall of the output of the second CMOS inverter 52 can be tuned by the amplitude of VCTRLn. The control loop 9' of the DLL 5' therefore tunes the amplitude of VCTRLn such that the fall of the output of the second CMOS inverter 52 is an attenuation relative to a step down (which can be seen in traces A and B as shown in Figure 8 as will be described below).

[0079] The source of the PMOS transistor MSET1 is coupled to the supply voltage VDD, the drain of the PMOS transistor MSET1 is coupled to node C, and the gate of the PMOS transistor MSET1 is coupled to node A. The source of the NMOS transistor MRESET1 is coupled to ground, the drain of the NMOS transistor MRESET1 is coupled to node D, and the gate of the NMOS transistor MRESET1 is coupled to node A through inverter 24. The source of the PMOS transistor MSET2 is coupled to the supply voltage VDD, the drain of the PMOS transistor MSET2 is coupled to node D, and the gate of the PMOS transistor MSET2 is coupled to node B. The source of the NMOS transistor MRESET2 is coupled to ground, the drain of the NMOS transistor MRESET2 is coupled to node C, and the gate of the NMOS transistor MRESET2 is coupled to node B through inverter 25.

[0080] The SR latch is formed by inverters 27 and 28 and is coupled between nodes C and D. Specifically, the input of inverter 27 is coupled to node C, and the output of inverter 27 is coupled to node D, while the input of inverter 28 is coupled to node D, and the output of inverter 28 is coupled to node C.

[0081] The OR gate 26 has: a first input coupled to node A, a second input for receiving the selection signal SEL through inverter 30, a third input coupled to node C, and an output coupled to node E. The source of the PMOS transistor M7 is coupled to VDD, the drain of the PMOS transistor M7 provides the CKbdec1 signal to the circuit 40 of the pulse decoder 15’, and the gate of the PMOS transistor M7 is coupled to node E. The source of the NMOS transistor M8 is coupled to ground, the drain of the NMOS transistor M8 provides the CKbdec1 signal to the circuit 40 of the pulse decoder 15’, and the gate of the NMOS transistor M8 is coupled to node E through inverter 29.

[0082] Now refer to Figure 7 and 8 to describe the operation of the delay unit 14”’. When starting this description, the generation of CKdec1 and CKbdec1 is not considered initially. When CKref goes high at time T0 ( Figure 8 ), node A will fall within a time defined by: the current provided by the NMOS transistor M3, the capacitance on node A itself, and the threshold for activating the PMOS transistor MSET1 and the NMOS transistor MRESET1. Additionally, node B is quickly pulled high, and both the PMOS transistor MSET2 and the NMOS transistor MRESET2 are turned off.

[0083] When node A descends, CK1 is pulled high by PMOS transistor MSET1 at time T3. Accordingly, the previously described delay (plus the delay to flip the SR flip-flop formed by inverters 27 and 28) will occur between the rising edges of CKref and CK1 (represented as the interval between times T0 and T3).

[0084] When CKref goes low at node T4, node B will descend within the time defined as follows: the current provided by NMOS transistor M6, the capacitance on node B itself, and the threshold to activate PMOS transistor MSET2 and NMOS transistor MRESET2. Additionally, node A is quickly pulled high, and both PMOS transistor MSET1 and NMOS transistor MRESET1 are turned off.

[0085] When node B goes low, CK1 is pulled low by NMOS transistor MRESET2 at time T7. Accordingly, the previously described delay (plus the delay to flip the SR flip-flop formed by inverters 27 and 28) will occur between the falling edges of CKref and CK1 (represented as the interval between T4 and T7).

[0086] The operation of delay cell 14”’ has now been described. Consider Figure 6 the operation of pulse decoder 15’. As previously described regarding the rising edge of CKref, when node A goes low between times T0 and T3, a certain time (the time between T0 and T3) is required to pull CK1 high. During this time, if SEL is high, the input to OR gate 26 will be low, and node E will go low to turn on PMOS transistor M7 and NMOS transistor M8.

[0087] CKdec1 and CKbdec1 are connected to Figure 6 nodes N1 and N2 of. When CKdec1 goes high at time T2 and CKbdec1 goes low, the SR flip-flop formed by inverters 41 and 42 will flip, whereupon node N1 goes high, and thus Pulse m goes low. As a result, when N1 goes high, Pulse m goes high. This completes the generation of the rising edge of Pulse m .

[0088] Another delay will be selected in the delay cell (via Figure 7the selection signal SEL in it). For this delay, CKndec will be connected to node N2, and CKbndec will be connected to N1. When CK(n - 1) goes high, the rising edge starting from CKref moves across the delay chain 14”’. Using the same behavior described previously, CKndec will go high (while CKbndec will go low). Due to the relative connection of nodes N1 and N2, node N2 is pulled high, and thus nodes N1 and Pulse m are pulled low. This completes the generation of the falling edge of Pulse m .

[0089] It can be seen that the generation of Pulse m depends on how CKndec and CKbdec are connected to node N1 or N2. Note that for most operations, the flip - flop formed by inverters 41 and 42 is in the hold mode. Only during a very short interval (when the OR gate 26 drives node E low), depending on the connection of CKndec and CKbndec to node N1 or N2, the flip - flop is forced into the set or reset state.

[0090] Therefore, in practice, the connection of the delay units 14A...14N, 14A’...14N’, and their selection via the associated selection SEL signal (where it can be understood that each delay unit has its own SEL value, and only two of the delay units in the delay unit group will have their selection signal SEL asserted) allows the shaping of Pulse m (in terms of pulse width and position within the CKref period). Note that in the Figure 6 and Figure 7 described topology, Figure 4 the basic idea is implemented. In fact, the delay path between CKref and CK1 includes more or less the same logic gates as the path between CKref and Pulse m (and is thus approximately equal). Specifically, the SR flip - flop formed by inverters 27 and 28 is simulated by the SR flip - flop formed by inverters 41 and 42, and the PMOS transistor M7 and NMOS transistor M8 simulate the PMOS transistors MSET1, MSET2 and NMOS transistors MRESET1, MRESET2. Again, the edges of Pulse m well represent the valid CKn edges (and thus the valid n / N division of the clock period).

[0091] Since the rising and falling edges of CK1 (as well as the rising and falling edges of CKb1) are already generated by the falling ramps of the corresponding NMOS transistors M3 and M6 in CMOS inverters 52 and 52, the delays generated between time T0 and T3, and between time T4 and T7 are 1 / N as expected. This avoids the possible mismatch problems in operations that rely on the PMOS to trigger the generation of one edge of CK1 and the NMOS to trigger the next edge of CK1. This provides the additional benefit that delay cell 14”’ is insensitive to the duty cycle, meaning the delay cell can operate at a duty cycle up to and including (1-(1 / N))*100%.

[0092] Now referring to Figure 9 Another alternative DLL 5” is described. This DLL 5” is similar to DLL5’, except for the structure and operation of control loop 9”. Thus, since the other components of DLL 5” remain unchanged compared to DLL 5’, this description will focus on control loop 9”.

[0093] Control loop 9 receives reference clock CKref and CKN, and generates control signal VCTRLn in a manner that maintains the phase alignment between CKref and CKN. More specifically, control loop 9 includes phase detector 11 that receives CKN and reference clock CKref. Phase detector 11 generates control signal U / D for digital filter block 61. Digital filter block 61 generates control signals Up and Dn, as well as select signal Select and trigger signal Trigger. Monostable 62 receives select signal Select and trigger signal Trigger, and provides an output to AND gates 63, 64. Digital filter block 61 provides control signal Up to AND gate 63, and control signal Dn to AND gate 64. Digital filter block 61 also provides control signal Ctrl1 to current source 65, and control signal Ctrl2 to current source 66 to control the amplitude of the current outputs of these current sources 65, 66.

[0094] Current source 65 is arranged as a current source and is selectively coupled to integration capacitor Cinteg through switch S1, which is controlled by the output of AND gate 63. Similarly, current source 66 is arranged as a current sink and is selectively coupled to integration capacitor Cinteg through switch S2, which is controlled by the output of AND gate 64. Integration capacitor Cinteg is coupled between the center tap N between switches S1 and S2 and ground.

[0095] An operational transconductance amplifier (OTA) 67 has an inverting terminal coupled to node N, a non-inverting terminal coupled to node Nn, and an output. A PMOS transistor Tr1 has a source coupled to the supply voltage VDD, a drain coupled to node Nn, and a gate coupled to receive the output of the OTA 67. A resistor R is coupled between node Nn and ground. Another PMOS transistor Tr2 has a source coupled to the supply voltage VDD, a drain coupled at node Nn1 to the drain of a diode-coupled transistor Tr3, and a gate also coupled to the output of the OTA 67. A control signal VCTRLn is generated at node Nn1.

[0096] In operation, the phase detector 11 compares the phases of the delayed clock signal CKN and the reference clock CKref. If the phase of the delayed clock signal CKN lags the phase of the reference clock CKref, the phase detector 11 asserts the control signal U, and if the phase of the delayed clock signal CKN leads the phase of the reference clock, the phase detector 11 asserts the control signal D. If the control loop 9 has not been locked, the digital filter block 61 asserts the select signal and the trigger signals Select, Trigger, causing the monostable 62 to generate an asserted pulse for a given period of time. This asserted pulse, together with the control signal Up or the control signal Dn asserted by the digital filter block 61, causes the AND gates 63, 64 to receive the asserted control signal Up or Dn to appropriately close the switches S1 or S2.

[0097] Thus, if the phase of the delayed clock signal CKN lags the phase of the reference clock CKref, the control signal U will be asserted by the phase detector 11 and the control signal Up will be asserted by the digital filter block 61, and thus when the monostable 62 asserts its output, the AND gate 63 will cause the switch S1 to close, supplying current from the current source 65 to the integration capacitor Cinteg to increase the voltage across the integration capacitor Cinteg. As the voltage across the integration capacitor Cinteg at node N increases, the magnitude of the output current of the OTA 67 increases, ultimately increasing the current supplied to node Nn1 by the drain of the PMOS transistor Tr2, and thus increasing the voltage VCTRLn. When the outputs of the CMOS inverters 51, 52 are pulled low at nodes A and B, this ultimately increases the magnitude of the decay slope of the CMOS inverters 51, 52 ( Figure 7 ).

[0098] As a result, if the phase of the delayed clock signal CKN is ahead of the phase of the reference clock CKref, the control signal D will be asserted by the phase detector 11 and the control signal Dn will be asserted by the digital filter block 61, and thus when the monostable 62 asserts its output, the AND gate 64 will cause the switch S2 to close, thereby sinking current from the current source 66 from the integrating capacitor Cinteg to reduce the voltage across the integrating capacitor Cinteg. As the voltage across the integrating capacitor Cinteg at the node N decreases, the magnitude of the output current of the OTA 67 decreases, ultimately reducing the current supplied to the node Nn1 by the drain of the PMOS transistor Tr2, and thus reducing the voltage VCTRLn. When the outputs of the CMOS inverters 51, 52 at the nodes A and B are pulled low, this ultimately reduces the magnitude of the attenuation slope of the CMOS inverters 51, 52 ( Figure 7 ).

[0099] When these operations bring the control loop 9 close to lock, the phase difference between the delayed clock signal CKN and the reference clock CKref becomes low. Due to the noise, the phase detector 11 will eventually issue a rapid sequence of assertions of the U and D control signals, the end result of which is that the control loop 9 oscillates around lock.

[0100] To filter out the above-mentioned noise, the digital filter block 61 accumulates the total assertions of the control signals U, D received over K cycles of the reference clock CKref and decides how to perform the corresponding processing depending on the total assertion of U and the total assertion of D. For example, this can be performed depending on the ratio of the total assertion of U and the total assertion of D over K cycles of CKref. It can also be performed depending on the comparison between these total numbers in order to determine whether to assert the control signal Up to the AND gate 63 or the control signal Dn to the AND gate 64. For example, if (the number of assertions of D) - (the number of assertions of U) > 32, the digital filter block 61 asserts the down (Dn) signal to the AND gate 64, and if (the number of assertions of U) - (the number of assertions of D) > 32, the digital filter block 61 asserts the up (Up) signal to the AND gate 63. If these differences are less than this value, the digital filter block 61 asserts neither Up nor Dn. In this case, the digital filter block 61 can change the control signals Ctrl1 and / or Ctrl2 that control the current sources 65 and 66, thereby changing the magnitude of the current generated by the current sources 65 and 66, thereby changing the voltage step generated on Cinteg when the switches S1 and S2 are closed, and thus changing VCTRLn. This operation can be performed until an acceptable lock is achieved. This comparison can be performed for a suitable value other than 32.

[0101] Although the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from the present disclosure will understand that other embodiments can be conceived without departing from the scope of the present disclosure as disclosed herein. Accordingly, the scope of the present disclosure should be limited only by the appended claims.

Claims

1. A delay - locked loop, comprising: A control loop, configured to receive a reference clock signal and a feedback clock signal, and generate a first bias voltage and a second bias voltage based on the reference clock signal and the feedback clock signal; A delay chain, configured to receive the reference clock signal and generate N consecutive delayed versions of the reference clock signal, each of the N consecutive delayed versions of the reference clock signal being at a consecutive tap of the delay chain; and A pulse decoder, configured to generate a pulse output signal having a pulse width equal to a desired fraction of the pulse width of the reference clock signal by selecting a tap of the delay chain as an input; Wherein the delay chain includes N delay units; Where n is an integer between 1 and N, and each n - th delay unit of the N delay units includes: A delay block, configured to receive an (n - 1)-th delayed output signal and generate an n - th delayed signal, the n - th delayed signal being equal to the reference clock signal delayed by: n / N of the reference clock signal minus an additional delay, wherein if n - 1 equals zero, the delay block is instead configured to receive the reference clock signal; A dummy block, comprising: A circuit configured to receive the n - th delayed signal and output the n - th delayed signal at the n - th tap of the delay chain; and Dummy logic, configured to receive the n - th delayed signal from the circuit and add the additional delay to the n - th delayed signal, the additional delay being a function of the delay time in the pulse decoder, and the dummy logic being configured to generate an n - th delayed output signal, the n - th delayed output signal being equal to the n - th delayed signal delayed by the additional delay; and Wherein the feedback clock signal is the N - th delayed output signal.

2. The delay - locked loop according to claim 1, wherein the pulse decoder is further configured to receive an input integer m; and wherein the desired fraction is m / N.

3. The delay - locked loop according to claim 1, wherein the circuit configured to receive the n - th delayed signal and output the n - th delayed signal at the n - th tap of the delay chain is a buffer circuit, the buffer circuit being configured to receive the n - th delayed signal, buffer the n - th delayed signal, and output the n - th delayed signal at the n - th tap of the delay chain.

4. The delay - locked loop according to claim 1, wherein the delay block of each n - th delay unit includes: A first current - source transistor, configured to be biased by the first bias voltage and configured to generate a first bias current; A second current - source transistor, configured to be biased by the second bias voltage and configured to generate a second bias current; An inverter, comprising an inverter PMOS transistor and an inverter NMOS transistor, wherein the inverter PMOS transistor has a source coupled to the source of the first current source transistor to receive the first bias current and has a gate configured to receive the (n-1)-th delayed output signal, and the inverter NMOS transistor has a drain coupled to the drain of the inverter PMOS transistor, has a source coupled to the source of the second current source transistor to receive the second bias current, and has a gate configured to receive the (n-1)-th delayed output signal, and the inverter is configured to generate the n-th delayed signal at the drain of the inverter PMOS transistor and at the drain of the inverter NMOS transistor; and A pseudo-inverter, comprising a pseudo-inverter PMOS transistor and a pseudo-inverter NMOS transistor, wherein the pseudo-inverter PMOS transistor has a source coupled to the source of the first current source transistor to receive the first bias current, has a drain coupled to ground, and has a gate configured to receive the complement of the (n-1)-th delayed output signal, and the pseudo-inverter NMOS transistor has a drain coupled to the supply voltage, has a source coupled to the source of the second current source transistor to receive the second bias current, and has a gate configured to receive the complement of the (n-1)-th delayed output signal.

5. A delay locked loop, comprising: A control loop configured to receive a reference clock signal and a feedback clock signal and to generate a first bias voltage based on the reference clock signal and the feedback clock signal; A delay chain configured to receive the reference clock signal and to generate N consecutive delayed versions of the reference clock signal, each of the N consecutive delayed versions of the reference clock signal being at a consecutive tap of the delay chain; and A pulse decoder configured to generate a pulse output signal having a pulse width equal to a desired fraction of the pulse width of the reference clock signal by selecting a tap of the delay chain to be used as an input; wherein the delay chain includes N delay units; where n is an integer between 1 and N, and each n-th delay unit of the N delay units includes: A delay circuit biased by the first bias voltage, the delay circuit being configured to: Receive the (n-1)-th delayed output signal and generate an n-th delayed signal, the n-th delayed signal being equal to the reference clock signal delayed by: n / N of the reference clock signal minus an additional delay, wherein if n-1 equals zero, the delay circuit is instead configured to receive the reference clock signal, Output the n-th delayed signal at the n-th tap of the delay chain, and Add the additional delay to the n-th delayed signal, the additional delay being a function of the delay time in the pulse decoder, and generate an n-th delayed output equal to the n-th delayed signal delayed by the additional delay; and wherein the feedback clock signal is the Nth delayed output signal.

6. The delay locked loop according to claim 5, wherein the delay circuit of each nth delay unit comprises: a first current source transistor configured to be biased by the first bias voltage and configured to generate a first bias current; a second current source transistor configured to be biased by the first bias voltage and configured to generate a second bias current; a first inverter comprising: a first inverter PMOS transistor having a source coupled to the supply voltage and a gate configured to receive the (n - 1)th delayed output signal; and a first inverter NMOS transistor having a drain coupled to the drain of the first inverter PMOS transistor, a source coupled to the source of the first current source transistor to receive the first bias current, and a gate configured to receive the (n - 1)th delayed output signal; wherein the first inverter is configured to generate a first decaying ramp signal in response to an assertion of the (n - 1)th delayed output signal; a second inverter comprising: a second inverter PMOS transistor having a source coupled to the supply voltage and a gate configured to receive the complement of the (n - 1)th delayed output signal; and a second inverter NMOS transistor having a drain coupled to the drain of the first inverter PMOS transistor, a source coupled to the source of the second current source transistor to receive the second bias current, and a gate configured to receive the complement of the (n - 1)th delayed output signal; wherein the second inverter is configured to generate a second decaying ramp signal in response to an assertion of the complement of the (n - 1)th delayed output signal; and a circuit system configured to start generation of a rising edge of the nth delayed output signal when the first decaying ramp signal falls below a threshold voltage, and to start generation of a falling edge of the nth delayed output signal when the second decaying ramp signal falls below the threshold voltage.

7. The delay locked loop according to claim 6, wherein the first bias current and the second bias current are equal and have an amplitude such that when the (n - 1)th delayed output signal is asserted, the first inverter generates the first decaying ramp signal while the second inverter generates a first rising edge, and when the (n - 1)th delayed output signal is de-asserted, the second inverter generates the second decaying ramp signal while the first inverter generates a second rising edge, the amplitude of the slope of the first decaying ramp signal being less than the amplitude of the slope of the first rising edge, and the amplitude of the slope of the second decaying ramp signal being less than the amplitude of the slope of the second rising edge.

8. The delay locked loop according to claim 6, wherein the circuit system comprises: A first set PMOS transistor having a source coupled to the supply voltage, a gate coupled to the drain of the first inverter PMOS transistor and the drain of the first inverter NMOS transistor, and a drain coupled to a first common node; A first reset NMOS transistor having a drain coupled to a second common node, a gate coupled to the drain of the first inverter PMOS transistor and the drain of the first inverter NMOS transistor through an inverter, and a source coupled to ground; A second set PMOS transistor having a source coupled to the supply voltage, a gate coupled to the drain of the second inverter PMOS transistor and the drain of the second inverter NMOS transistor, and a drain coupled to the second common node; A second reset NMOS transistor having a source coupled to the first common node, a gate coupled to the drain of the second inverter PMOS transistor and the drain of the second inverter NMOS transistor through an inverter, and a source coupled to ground; wherein the n-th delayed output signal is generated at the first common node; wherein the complement of the n-th delayed output signal is generated at the second common node, and an SR latch having a set input coupled to the first common node and a reset input coupled to the second common node.

9. The delay locked loop according to claim 8, wherein the delay circuit of each n-th delay unit further comprises: an OR gate having a first input, a second input coupled to the select signal through an inverter, a third input coupled to the first common node, and an output, the first input being coupled to the drain of the first inverter PMOS transistor and the drain of the first inverter NMOS transistor; a PMOS transistor having a source coupled to the supply voltage, a gate coupled to the output of the OR gate, and a drain at which the n-th delayed signal is generated; and an NMOS transistor having a source coupled to ground, a gate coupled to the output of the OR gate through an inverter, and a drain at which the complement of the n-th delayed signal is generated.

10. The delay-locked loop according to claim 9, wherein the pulse output signal is generated to have a pulse width that is equal to a desired fraction of the pulse width of the reference clock signal by generating a rising edge and a falling edge; wherein each of the N delay units is used to generate the rising edge or is used to generate the falling edge, wherein the total number of the N delay units that are used to generate the rising edge indicates a delay between a start of a period of the reference clock signal and the rising edge, and the total number of the N delay units that are used to generate the falling edge indicates a delay between the falling edge and an end of the period of the reference clock signal; And wherein the pulse decoder comprises: a circuit configured to: select a first series of taps representing the delayed signals respectively generated by each of the delay units among the N delay units that are used to generate the rising edge of the pulse output signal; select a second series of taps representing the complements of the delayed signals respectively generated by each of the delay units among the N delay units that are used to generate the rising edge of the pulse output signal; Select a third series of taps, where the third series of taps represent the delayed signals respectively generated by each of the N delay units that are used to generate the falling edge of the pulse output signal; and Select a fourth series of taps, where the fourth series of taps represent the complements of the delayed signals respectively generated by each of the N delay units that are used to generate the falling edge of the pulse output signal; and An SR latch having a set input, a reset input, and an output that generates the pulse output signal through a buffer, where the set input is coupled to the set inputs of the first series of taps and the fourth series of taps, and the reset input is coupled to the second series of taps and the third series of taps.

11. The delay locked loop according to claim 10, wherein the delay unit among the N delay units associated with the last tap of the first series of taps receives an asserted version of the selection signal; the delay unit among the N delay units associated with the first tap of the third series of taps receives an asserted version of the selection signal; and the remaining delay units among the N delay units receive a deasserted version of the selection signal.

12. The delay locked loop according to claim 5, wherein the control loop includes:[[]] A phase detector configured to: receive the reference clock signal and the feedback clock signal; Assert an up signal in response to the phase of the feedback clock signal lagging behind the phase of the reference clock signal; And assert a down signal in response to the phase of the feedback clock signal leading the phase of the reference clock signal; A digital filter block configured to: receive the up signal and the down signal; count the number of assertions of the up signal during a plurality of cycles of the reference clock signal; Count the number of assertions of the down signal during the plurality of cycles of the reference clock signal; Compare the number of assertions of the up signal during the plurality of cycles of the reference clock signal with the number of assertions of the down signal during the plurality of cycles of the reference clock signal; And then assert an up command signal or a down command signal based on the comparison; and And A bias voltage generation circuit configured to receive the up command signal and the down command signal and generate the first bias voltage based on the up command signal and the down command signal.

13. The delay locked loop according to claim 5, wherein the control loop includes:[[]] A phase detector configured to: receive the reference clock signal and the feedback clock signal; Assert an up signal in response to the phase of the feedback clock signal lagging behind the phase of the reference clock signal; And assert a down signal in response to the phase of the feedback clock signal leading the phase of the reference clock signal; A digital filter block, configured to: receive the upper signal and the lower signal; count the number of assertions of the upper signal during multiple cycles of the reference clock signal; count the number of assertions of the lower signal during the multiple cycles of the reference clock signal; compare the number of assertions of the upper signal during the multiple cycles of the reference clock signal with the number of assertions of the lower signal during the multiple cycles of the reference clock signal; and then assert an upper command signal or a lower command signal according to the comparison; wherein the digital filter block is further configured to: assert a trigger signal substantially simultaneously with the assertion of the upper command signal or the lower command signal; A monostable, configured to receive the trigger signal and, based on receiving the trigger signal, assert the output of the monostable as a pulse; A first AND gate, configured to receive the upper command signal and the output of the monostable and generate a first switch control signal as a result of a logical AND operation between the upper command signal and the output of the monostable; A second AND gate, configured to receive the lower command signal and the output of the monostable and generate a second switch control signal as a result of a logical AND operation between the lower command signal and the output of the monostable; An integrating capacitor, coupled between a node and ground; A current source; A first switch, configured to selectively couple the integrating capacitor to the current source in response to the assertion of the first switch control signal; A current sink; A second switch, configured to selectively couple the integrating capacitor to the current sink in response to the assertion of the second switch control signal; An operational transconductance amplifier, having an inverting terminal coupled to the node, a non-inverting terminal coupled to a second node, and an output; A resistor, coupled between the second node and ground; A first PMOS transistor, having a source coupled to a supply voltage, a drain coupled to the second node, and a gate coupled to the output of the operational transconductance amplifier; and A second PMOS transistor, having a source coupled to the supply voltage, a drain coupled to the drain of a diode-coupled NMOS transistor to generate the first bias voltage, and a gate coupled to the output of the operational transconductance amplifier.

14. The delay locked loop according to claim 13, wherein the digital filter block is further configured to: generate a current source control signal for the current source based on the comparison of the number of assertions of the upper signal during the multiple cycles of the reference clock signal with the number of assertions of the lower signal during the multiple cycles of the reference clock signal; and generate a current sink control signal for the current sink based on the comparison of the number of assertions of the upper signal during the multiple cycles of the reference clock signal with the number of assertions of the lower signal during the multiple cycles of the reference clock signal.

15. A delay locked loop, comprising: A control loop configured to receive a reference clock signal and a feedback clock signal, and generate at least one bias voltage based on the reference clock signal and the feedback clock signal; A delay chain configured to receive the reference clock signal and generate N consecutive delayed versions of the reference clock signal, each of the N consecutive delayed versions of the reference clock signal being at consecutive taps of the delay chain, wherein the Nth delayed version of the reference clock signal is the feedback clock signal; And Wherein the control loop comprises: A phase detector configured to: receive the reference clock signal and the feedback clock signal; assert an up signal in response to the phase of the feedback clock signal lagging behind the phase of the reference clock signal; and assert a down signal in response to the phase of the feedback clock signal leading ahead of the phase of the reference clock signal; A digital filter block configured to: receive the up signal and the down signal; count the number of assertions of the up signal during a plurality of cycles of the reference clock signal; count the number of assertions of the down signal during a plurality of cycles of the reference clock signal; compare the number of assertions of the up signal during the plurality of cycles of the reference clock signal with the number of assertions of the down signal during the plurality of cycles of the reference clock signal; and then assert an up command signal or a down command signal based on the comparison; and A bias voltage generation circuit configured to receive the up command signal and the down command signal and generate at least one bias voltage based on the up command signal and the down command signal.

16. The delay locked loop according to claim 15, wherein the digital filter block is further configured to assert a trigger signal substantially simultaneously with the assertion of the up command signal or the down command signal; And Wherein the bias voltage generation circuit comprises: A monostable configured to receive the trigger signal and assert the output of the monostable with a pulse based on receiving the trigger signal; A first AND gate configured to receive the up command signal and the output of the monostable and generate a first switch control signal as a result of a logical AND operation between the up command signal and the output of the monostable; A second AND gate configured to receive the down command signal and the output of the monostable and generate a second switch control signal as a result of a logical AND operation between the down command signal and the output of the monostable; An integrating capacitor coupled between a node and ground; A current source; A first switch configured to selectively couple the integrating capacitor to the current source in response to the assertion of the first switch control signal; A current sink; A second switch configured to selectively couple the integrating capacitor to the current sink in response to the assertion of the second switch control signal; An operational transconductance amplifier having an inverting terminal coupled to the node, a non-inverting terminal coupled to a second node, and an output; A resistor coupled between the second node and ground; A first PMOS transistor having a source coupled to a supply voltage, a drain coupled to the second node, and a gate coupled to the output of the operational transconductance amplifier; and A second PMOS transistor having a source coupled to the supply voltage, a drain coupled to the drain of the diode-coupled NMOS transistor to generate the at least one bias voltage, and a gate coupled to the output of the operational transconductance amplifier.

17. The delay locked loop of claim 16, wherein the digital filter block is further configured to generate a current source control signal for the current source and a current sink control signal for the current sink based on a comparison of the number of assertions of the up signal during the plurality of cycles of the reference clock signal with the number of assertions of the down signal during the plurality of cycles of the reference clock signal, and based on a comparison of the number of assertions of the up signal during the plurality of cycles of the reference clock signal with the number of assertions of the down signal during the plurality of cycles of the reference clock signal.

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