Semiconductor device including a stacked structure having a gate region and an insulating region

Abstract

A semiconductor device including a stacked structure having a gate region and an insulating region is provided. The semiconductor device includes a lower structure and a stacked structure extending from the lower structure into a connection region, wherein the stacked structure includes a gate pad and a molded pad. The molded pad includes an intermediate molded pad, the intermediate molded pad includes a first intermediate molded pad and a second intermediate molded pad located between a pair of first intermediate molded pads, each first intermediate molded pad having a first length in a first direction, the second intermediate molded pad having a second length in the first direction that is greater than the first length, one intermediate molded pad including a molded pad portion and an insulating protrusion portion located on the molded pad portion, one first intermediate molded pad including the molded pad portion and the insulating protrusion portion, and a central region of the second intermediate molded pad does not include the insulating protrusion portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0086900, filed on July 18, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the inventive concepts relate to semiconductor devices, and more particularly, to a semiconductor device including a stack structure having a gate region and an insulating region. Background Art

[0004] Semiconductor devices including gate electrodes stacked in a direction perpendicular to the surface of a semiconductor substrate have been developed. To increase the integration density of semiconductor devices, the number of stacked gate electrodes has increased. As the number of gate electrodes stacked in a direction perpendicular to the surface of the semiconductor substrate increases, difficulties in electrically connecting the gate electrodes to peripheral circuits increase, and unexpected defects may occur. Summary of the Invention

[0005] Example embodiments of the inventive concepts provide semiconductor devices that may have improved integration density.

[0006] According to an example embodiment of the present invention, a semiconductor device includes: a lower structure including a lower substrate, an upper substrate located on the lower substrate, a peripheral circuit region located between the lower substrate and the upper substrate and including peripheral wiring, and a gap-filling insulating layer penetrating the upper substrate; a stacked structure located in a memory cell array region on the lower structure and extending to a connection region on the lower structure, wherein the stacked structure has a stepped structure in the connection region, the stacked structure including a gate region and a first insulating region, the gate region being located in the memory cell array region and extending into the connection region, and the first insulating region being located in the connection region; a capping insulating layer located on the stacked structure; and a memory cell vertical structure located in the gate region in the memory cell array region, the stacked structure including a plurality of first layers and a plurality of second layers alternately stacked on the lower structure, the plurality of second layers including a plurality of gate layers located in the gate region, a plurality of mold layers located in the first insulating region, a plurality of gate pads extending from the plurality of gate layers, and a plurality of mold pads extending from at least one of the mold layers, the plurality of gate layers each including a conductive material, the plurality of mold layers The layers each include an insulating material, the multiple mold layers include one or more lower mold layers, a plurality of intermediate mold layers located on the one or more lower mold layers, and one or more floating mold layers located on the multiple intermediate mold layers, the multiple mold pads include a plurality of intermediate mold pads extending from at least one of the multiple intermediate mold layers, the multiple intermediate mold pads include a stepped structure descending along a first direction, the first direction extending from the memory cell array region to the connection region, the multiple intermediate mold pads include a plurality of first intermediate mold pads and a plurality of intermediate mold pads located among the plurality of first intermediate mold pads. a second intermediate molded pad between a pair of first intermediate molded pads, the plurality of first intermediate molded pads each having a first length in the first direction, the second intermediate molded pad having a second length in the first direction that is greater than the first length, at least one of the plurality of intermediate molded pads having a molded pad portion and an insulating protrusion portion located on the molded pad portion, at least one of the plurality of first intermediate molded pads including the molded pad portion and the insulating protrusion portion, and at least a central area of ​​the second intermediate molded pad excluding the insulating protrusion portion.

[0007] According to an example embodiment of the present invention, a semiconductor device includes: a lower structure; a stacked structure located in a memory cell array region on the lower structure and extending into a connection region on the lower structure, wherein the stacked structure includes a gate region and an insulating region, the gate region includes a plurality of gate pads, and the insulating region includes a plurality of mold pads; and a memory cell vertical structure penetrating the gate region in the memory cell array region, the plurality of mold pads including a plurality of middle mold pads, the plurality of middle mold pads including a plurality of first middle mold pads and a plurality of middle mold pads located among the plurality of first middle mold pads. a second intermediate molded pad between the pairs of first intermediate molded pads, the plurality of first intermediate molded pads each having a first length in a first direction, the second intermediate molded pad having a second length in the first direction greater than the first length, at least one of the plurality of intermediate molded pads including a molded pad portion and an insulating protrusion portion located on the molded pad portion, at least one of the plurality of first intermediate molded pads including the molded pad portion and the insulating protrusion portion, and at least a central area of ​​the second intermediate molded pad excluding the insulating protrusion portion.

[0008] According to an example embodiment of the present invention, a semiconductor device includes: a lower structure including a lower substrate, an upper substrate located on the lower substrate, a peripheral circuit region located between the lower substrate and the upper substrate and including peripheral wiring, and a gap-filling insulating layer penetrating the upper substrate; a stacked structure located in a memory cell array region on the lower structure and extending into a connection region on the lower structure, wherein the stacked structure includes a gate region and an insulating region, the gate region being located in the memory cell array region and extending into the connection region, and the insulating region being located in the connection region; a memory cell vertical structure penetrating the gate region in the memory cell array region; and a covering insulating layer located on the stacked structure, the stacked structure including a plurality of first layers and a plurality of second layers alternately stacked on the lower structure, the plurality of first layers including an interlayer insulating layer, and the plurality of second layers including a plurality of layers located in the gate region. a gate layer, a plurality of mold layers located in the insulating region, a plurality of gate pads extending from the gate layer, and a plurality of mold pads extending from at least some of the mold layers, the plurality of mold pads including a plurality of intermediate mold pads, the plurality of intermediate mold pads including a plurality of first intermediate mold pads and second intermediate mold pads located between pairs of first intermediate mold pads among the plurality of first intermediate mold pads, the plurality of first intermediate mold pads each having a first length in a first direction, the second intermediate mold pads having a second length greater than the first length in the first direction, the first direction extending from the memory cell array region to the connection region, at least one first intermediate mold pad among the plurality of first intermediate mold pads having a first thickness, and a central region of the second intermediate mold pad including an insulating material layer having a second thickness less than the first thickness, or the central region of the second intermediate mold pad includes the covering insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present invention will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a top view illustrating a semiconductor device according to an example embodiment of the inventive concept;

[0011] Figure 2 It shows Figure 1 an enlarged top view of portion "A" shown;

[0012] Figures 3 to 12 is a cross-sectional view illustrating an example of a semiconductor device according to an example embodiment of the inventive concept;

[0013] Figure 13A and Figure 13B is an enlarged cross-sectional view illustrating a modified example of a semiconductor device according to an example embodiment of the inventive concept;

[0014] Figure 14 and Figure 15 is an enlarged cross-sectional view illustrating another modified example of the semiconductor device according to an example embodiment of the inventive concept;

[0015] Figure 16 is an enlarged cross-sectional view illustrating another modified example of the semiconductor device according to an example embodiment of the inventive concept;

[0016] Figure 17 is an enlarged cross-sectional view illustrating another modified example of the semiconductor device according to an example embodiment of the inventive concept;

[0017] Figure 18 is an enlarged cross-sectional view illustrating another modified example of the semiconductor device according to an example embodiment of the inventive concept;

[0018] Figure 19 is an enlarged cross-sectional view illustrating another modified example of the semiconductor device according to an example embodiment of the inventive concept;

[0019] 20A to 20C is a cross-sectional view illustrating a modified example of a semiconductor device according to an example embodiment of the inventive concept;

[0020] Figure 21 is a flowchart illustrating an example of a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept; and

[0021] Figures 22A to 23B is a cross-sectional view illustrating an example of a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0023] Will refer to Figures 1 to 12 An example of a semiconductor device according to an exemplary embodiment of the present invention is described. In the following description, reference will be made to Figures 1 to 12 Describe each element and refer to Figures 1 to 12 An example of each element is described in part of the drawings. Figures 1 to 12 , Figure 1 is a top view illustrating a semiconductor device according to an example embodiment of the inventive concept, Figure 2 yes Figure 1 An enlarged top view of portion "A" is shown, Figure 3 It is along Figure 2 A cross-sectional view taken along line II' in FIG. Figure 4 It shows Figure 3 An enlarged top view of portion "B" is shown, Figure 5 It is along Figure 2 A cross-sectional view taken along line II-II' in FIG. Figure 6 It shows Figure 5 An enlarged top view of portion "C" is shown, Figure 7 It is along Figure 2 A cross-sectional view taken along line III-III' in FIG. Figure 8 It shows Figure 7 An enlarged top view of portion "D" is shown, Figure 9 It is along Figure 2 A cross-sectional view taken along line IV-IV' in FIG. Figure 10 It shows Figure 9 An enlarged top view of portion "E" is shown, Figure 11 It is along Figure 10 The cross-sectional view taken along line V-V' in FIG. Figure 12 It shows Figure 11 Enlarged views of parts "F1" and "F2" are shown.

[0024] Reference Figures 1 to 12 , the semiconductor device 1 in example embodiments may include a lower structure 3, a memory cell array region MA, and a connection region EA on the lower structure 3. The memory cell array region MA and the connection region EA may be adjacent to each other.

[0025] The lower structure 3 may include a lower substrate 5 , an upper substrate 12 located on the lower substrate 5 , and a peripheral circuit region 7 located between the lower substrate 5 and the upper substrate 12 .

[0026] The lower structure 3 may further include a gap-filling insulating layer 13 penetrating the upper substrate 12 and an intermediate insulating layer 14 located on the upper substrate 12 and, in some embodiments, surrounding the upper substrate 12. The peripheral circuit region 7 may include a peripheral wiring 8 and a lower insulating layer 9 located on the peripheral wiring 8 and, in some embodiments, covering the peripheral wiring 8.

[0027] The semiconductor device 1 in example embodiments may include a stacked structure ST on a lower structure 3 .

[0028] The stack structure ST may be disposed in the memory cell array area MA and may extend into the connection area EA.

[0029] The stacked structure ST may include a gate area GA including a conductive material and an insulating area IA not including a conductive material.

[0030] The gate region GA may be disposed in the memory cell array region MA and may be partially disposed in the connection region EA. The insulating region IA may be disposed in the connection region EA and may be adjacent to the gate region GA.

[0031] The stacked structure ST may include first layers 20 and second layers 23 alternately stacked on the lower structure 3 .

[0032] The first layer 20 may be disposed in the gate area GA and the insulating area IA. The first layer 20 may be configured as an interlayer insulating layer.

[0033] The second layer 23 may include gate layers 29G, 31G, 33G, and 35G disposed in the gate area GA and mold layers 29M, 31M, and 35M disposed in the insulating area IA.

[0034] In example embodiments, the mold layers 29M, 31M, and 35M may be formed of an insulating material having an etch selectivity different from that of the first layer 20. For example, the first layer 20 may be formed of silicon oxide, and the mold layers 29M, 31M, and 35M may be formed of silicon nitride.

[0035] In example embodiments, the gate layers 29G, 31G, 33G, and 35G may each include a conductive material. For example, the gate layers 29G, 31G, 33G, and 35G may each be configured as a gate electrode.

[0036] The gate layers 29G, 31G, 33G, and 35G may include one or more lower gate layers 29G, a plurality of intermediate gate layers 31G on the one or more lower gate layers 29G, and a plurality of upper gate layers 33G on the plurality of intermediate gate layers 31G. The term "plurality" used herein means two or more.

[0037] The molding layers 29M, 31M, and 35M may include one or more lower molding layers 29M, a plurality of middle molding layers 31M on the one or more lower molding layers 29M, and a plurality of upper molding layers 35M on the plurality of middle molding layers 31M.

[0038] The lower and intermediate gate layers 29G and 31G and the lower and intermediate mold layers 29M and 31M located at the same level in a boundary region between the gate area GA and the insulating area IA may be located at opposite sides of each other and may contact each other.

[0039] The gate layers 29G, 31G, 33G, and 35G may further include a floating gate layer 35G, and the mold layers 29M, 31M, and 35M may further include a floating mold layer 35M.

[0040] The floating gate layer 35G may be disposed on the plurality of intermediate mold layers 31M in the connection area EA and may be spaced apart from the plurality of upper gate layers 33G. The floating mold layer 35M may be disposed on the plurality of intermediate mold layers 31M in the connection area EA and may be spaced apart from the plurality of upper gate layers 33G.

[0041] The gate layers 29G, 31G, 33G, and 35G may include a plurality of gate pads arranged in a stepped form, and the mold layers 29M, 31M, and 35M may include a plurality of mold pads arranged in a stepped form. As used herein, "stepped form" or "stepped structure" refers to a plurality of layers in which the outermost edge of a first layer extends laterally beyond the outermost edge of a second layer immediately above the first layer.

[0042] One or more lower gate layers 29G may include one or more lower gate pads 29GP, multiple intermediate gate layers 31G may include intermediate gate pads 31GP, multiple upper gate layers 33G may include upper gate pads 33GP, and floating gate layer 35G may include floating gate pads 35GP.

[0043] The one or more lower mold layers 29M may include one or more lower mold pads 29MP, the plurality of middle mold layers 31M may include middle mold pads 31MP, and the floating mold layer 35M may include floating mold pads 35MP.

[0044] The semiconductor device 1 in the example embodiment of the present inventive concepts may further include a memory cell vertical structure 46 in the memory cell array region MA. The memory cell vertical structure 46 may penetrate the gate region GA of the stack structure ST.

[0045] The semiconductor device 1 in example embodiments may further include a plurality of separation structures 69 a , 69 b , and 69 c .

[0046] The multiple separation structures 69a, 69b and 69c may include multiple first separation structures 69a passing through the memory cell array area MA and the connection area EA, multiple second separation structures 69b passing through the memory cell array area MA and extending into a partial area of ​​the connection area EA, and multiple third separation structures 69c arranged in the connection area EA.

[0047] A plurality of second partition structures 69b may be disposed between the plurality of first partition structures 69a. A plurality of third partition structures 69c may be disposed between the plurality of first partition structures 69a.

[0048] The stack structure ST may be divided into a plurality of regions by a plurality of first separation structures 69a. Figure 2As shown, in the connection area EA, the stack structure ST may include a first stack region ST1, a second stack region ST2 located on a first side of the first stack region ST1, and a third stack region ST3 located on a second side of the first stack region ST1 opposite to the first side. Therefore, in the connection area EA, the first stack region ST1 may be disposed between the second stack region ST2 and the third stack region ST3. The first stack region ST1, the second stack region ST2, and the third stack region ST3 may be separated from each other by a first separation structure 69a among a plurality of first separation structures 69a.

[0049] The plurality of third separation structures 69 c may be provided in the first stack region ST1 , and may not be provided in the second and third stack regions ST2 and ST3 .

[0050] In the first stack region ST1 , the plurality of third separation structures 69 c and the plurality of second separation structures 69 b may have ends opposite to each other.

[0051] In the stack structure ST, the gate area GA may be disposed through the memory cell array area MA and the first stack area ST1 , and may be disposed in a portion of the second stack area ST2 and a portion of the third stack area ST3 .

[0052] In the stack structure ST, the insulating region IA may include a first insulating region IA1 disposed in a portion of the second stack region ST2 and a second insulating region IA2 disposed in a portion of the third stack region ST3 .

[0053] In the connection area EA, the upper gate layer 33G may include a portion descending to a first height in the first direction X (eg, at Figure 3 In other words, as each upper gate pad 33GP extends along the first direction X, the corresponding upper gate pad 33GP becomes lower in the Z direction. The first direction X can be directed from the memory cell array area MA to the connection area EA.

[0054] In the connection area EA, the intermediate gate layer 31G and the intermediate mold layer 31M may each include a second height (eg, at a position between the first and second gate layers) descending in the first direction X to a second height higher than the first height. Figure 3 and Figure 5 In other words, the distance in the Z direction between each adjacent middle pad in the middle pads 31GP and 31MP is greater than the distance in the Z direction between each adjacent upper gate pad in the upper gate pad 33GP.

[0055] The intermediate pads 31GP and 31MP may include an intermediate gate pad 31GP of the intermediate gate layer 31G and an intermediate mold pad 31MP of the intermediate mold layer 31M. In the second stack region ST2 and the third stack region ST3, the corresponding intermediate pads 31GP and 31MP may be arranged at a constant horizontal height in the second direction Y. In the first stack region ST1, the corresponding intermediate pads 31GP and 31MP may be lowered to a first height in a direction from the second stack region ST2 to the third stack region ST3.

[0056] In the connection area EA, the lower gate layer 29G and the lower mold layer 29M may include lower pads 29GP and 29MP that are lowered from a step having a certain height in the second stack region ST2 along the first direction X to a first height and in the first stack region ST1 from the second stack region ST2 along a direction toward the third stack region ST3 to the first height. The lower pads 29GP and 29MP may include a lower gate pad 29GP of the lower gate layer 29G and a lower mold pad 29MP of the lower mold layer 29M.

[0057] The first direction X may be directed from the memory cell array area MA to the connection area EA, and the second direction Y may be perpendicular to the first direction X.

[0058] In the connection area EA, the floating gate layer 35G and the floating mold layer 35M may include floating pads 35GP and 35MP that are lowered from a step having a certain height in the second stacking area ST2 in a direction toward the upper gate pad 33GP and that are lowered from the second stacking area ST2 in the direction toward the third stacking area ST3 in the first stacking area ST1.

[0059] The floating pads 35GP and 35MP may include a floating gate pad 35GP of the floating gate layer 35G and a floating mold pad 35MP of the floating mold layer 35M.

[0060] In example embodiments, the first height may refer to a distance between upper surfaces of the second layers 23 adjacent to each other in the vertical direction Z.

[0061] In example embodiments, the second height may be greater than the first height. For example, the second height may refer to a distance between an upper surface of a lowermost second layer and an upper surface of an uppermost second layer among four second layers 23 arranged in the vertical direction Z.

[0062] A first cover insulating layer 40 and a second cover insulating layer 43 may be disposed on the stacked structure ST. The first cover insulating layer 40 may be located on the uppermost second layer of the second layers 23 and, in some embodiments, cover the uppermost second layer. The second cover insulating layer 43 may have an upper surface coplanar with an upper surface of the first cover insulating layer 40. The second cover insulating layer 43 may be located on the rest of the stacked structure ST and, in some embodiments, cover the rest of the stacked structure ST.

[0063] The first upper insulating layer 66 and the second upper insulating layer 72 stacked in sequence may be disposed on the first cover insulating layer 40 and the second cover insulating layer 43. The first to third separation structures 69a, 69b, and 69c may penetrate the stacked structure ST, may extend upward, and may penetrate the first cover insulating layer 40, the second cover insulating layer 43, and the first upper insulating layer 66.

[0064] A bit line contact plug 78 penetrating the first and second upper insulating layers 66 and 72 and electrically connected to the memory cell vertical structure 46 may be provided.

[0065] In the connection area EA, a gate contact structure 75 penetrating the first and second upper insulating layers 66 and 72 , extending downward, and electrically connected to the lower, middle, and upper gate pads 29GP, 31GP, and 33GP may be provided.

[0066] A peripheral contact structure 81 that contacts the peripheral pad portion 8P of the peripheral wiring 8 , extends upward, and penetrates the gap-fill insulating layer 13 and the insulating area IA of the stack structure ST may be provided.

[0067] The gate connection wiring 85 may be disposed on the gate contact structure 75 and the peripheral contact structure 81 .

[0068] In example embodiments, a dummy contact plug 75d may be provided in the connection area EA, penetrating the first and second upper insulating layers 66 and 72, extending downward, and electrically connected to the floating gate pad 35GP. The dummy contact plug 75d may be electrically insulated from the gate connection wiring 85. The bit line 84 may be provided on the bit line contact plug 78.

[0069] In the following description, reference will be made to Figure 3 and Figure 4 The middle mold pad 31MP of the middle mold layer 31M is described in more detail.

[0070] Reference Figure 3 and Figure 4The middle mold pads 31MP of the middle mold layer 31M may include first middle mold pads 31MPa and second middle mold pads 31MPb disposed between the first middle mold pads 31MPa. The second middle mold pads 31MPb may be disposed between some of the plurality of first middle mold pads 31MPa and other first middle mold pads 31MPa.

[0071] The first intermediate mold pads 31 MPa may respectively have the same or similar structures, and the second intermediate mold pads 31 MPb may have a structure different from that of each of the first intermediate mold pads 31 MPa.

[0072] In example embodiments, each of the first intermediate mold pads 31 MPa may have a first length in the first direction X, and the second intermediate mold pads 31 MPb may have a second length in the first direction X that is greater than the first length.

[0073] In example embodiments, the first and second middle mold pads 31 MPa and 31 MPb may each include a mold pad portion 24 a and an insulating protrusion portion 24 b on the mold pad portion 24 a .

[0074] The insulating protrusion portion 24b can be formed of a material having an etch selectivity different from that of the mold pad portion 24a. For example, the mold pad portion 24a can be formed of a first insulating material based on (e.g., including) silicon nitride, and the insulating protrusion portion 24b can be formed of a second insulating material based on (e.g., including) silicon nitride, the etching rate of the second insulating material being higher than the etching rate of the first insulating material, but the present invention is not limited thereto. For example, the mold pad portion 24a can be formed of a first silicon nitride, and the insulating protrusion portion 24b can be formed of a second silicon nitride that is configured to be more porous than the first silicon nitride. The etching rate of the second silicon nitride can be higher than the etching rate of the first silicon nitride relative to an etchant including phosphate.

[0075] In example embodiments, the second middle mold pad 31MPb may include a first portion 31Mb1 and a second portion 31Mb2 spaced apart from each other in the first direction X. The first portion 31Mb1 and the second portion 31Mb2 may be sequentially spaced apart from the memory cell array area MA. For example, the first portion 31Mb1 may be located between the second portion 31Mb2 and the memory cell array area MA in the first direction X.

[0076] The first portion 31Mb1 and the second portion 31Mb2 may each include the mold pad portion 24a and the insulating protrusion portion 24b described above.

[0077] The length of the first portion 31Mb1 in the first direction X may be substantially the same as the length of each first middle mold pad 31MPa in the first direction X. The length of the second portion 31Mb2 in the first direction X may be smaller than the length of each first middle mold pad 31MPa in the first direction X.

[0078] In example embodiments, one or more second intermediate mold pads 31MPb may be provided. When a plurality of second intermediate mold pads 31MPb are provided, each of the plurality of second intermediate mold pads 31MPb may be provided between one of the plurality of first intermediate mold pads 31MPa and another of the plurality of first intermediate mold pads 31MPa. When a plurality of second intermediate mold pads 31MPb are provided, each of the plurality of second intermediate mold pads 31MPb may have a first portion 31Mb1 and a second portion 31Mb2.

[0079] A plurality of second middle mold pads 31MPb may be provided in each of the first insulating area IA1 and the second insulating area IA2. Figure 2 , a portion "CTa" overlapping the first and second insulating areas IA1 and IA2 may refer to a central region of the second middle mold pad 31MPb disposed between the first portion 31Mb1 and the second portion 31Mb2 of each of the plurality of second middle mold pads 31MPb. At least the central region of the second middle mold pad 31MPb may not include the insulating protrusion portion 24b.

[0080] The center region of the second intermediate mold pad 31MPb may include a second cover insulating layer 43 and, in some embodiments, be filled with the second cover insulating layer 43. The second cover insulating layer 43 may include an insulating material different from the insulating material of the intermediate mold layer 31M. For example, when the second cover insulating layer 43 is formed of a single material such as silicon oxide, the region between the first portion 31Mb1 and the second portion 31Mb2 of the second intermediate mold pad 31MPb may be filled with the silicon oxide of the second cover insulating layer 43. Unlike the above-described example embodiments, when the second cover insulating layer 43 is formed of at least two materials, a blocking insulating layer and a cover insulating layer, the region between the first portion 31Mb1 and the second portion 31Mb2 of the second intermediate mold pad 31MPb may be filled with the blocking insulating layer of the second cover insulating layer 43. The blocking insulating layer of the second cover insulating layer 43 may be formed of a material different from, for example, silicon nitride (e.g., aluminum oxide), and the cover insulating layer of the second cover insulating layer 43 may be formed of silicon oxide.

[0081] Return to reference Figure 3 The lower mold pads 29MP of the lower mold layer 29M may include a first lower mold pad 29MPa and a second lower mold pad 29MPb. The second lower mold pad 29MPb may be disposed between the first lower mold pad 29MPa and the first middle mold pad 31MPa.

[0082] The length of the second lower mold pad 29MPb in the first direction X may be greater than the length of each first lower mold pad 29MPa in the first direction X. The second lower mold pad 29MPb may have a structure that is the same as or similar to that of the second middle mold pad 31MPb and may be formed of a material that is the same as or similar to that of the second middle mold pad 31MPb.

[0083] exist Figure 2 , a portion “CTb” overlapping the first and second insulating areas IA1 and IA2 may refer to a central area of ​​each second lower mold pad 29MPb.

[0084] In the following description, reference will be made to Figure 5 and Figure 6 The intermediate gate pads 31GP of the intermediate gate layer 31G arranged along the first direction X are described in more detail.

[0085] Reference Figure 5 and Figure 6 , the intermediate gate layer 31G may include intermediate gate pads 31GP each having an increased thickness.

[0086] The intermediate gate pads 31GP may include first intermediate gate pads 31GPa and second intermediate gate pads 31GPb disposed between adjacent first intermediate gate pads 31GPa. For example, the second intermediate gate pad 31GPb may be disposed between one of the plurality of first intermediate gate pads 31GPa and another of the plurality of first intermediate gate pads 31GPa.

[0087] The second intermediate gate pad 31GPb may have a structure different from that of each first intermediate gate pad 31GPa.

[0088] In example embodiments, each of the first intermediate gate pads 31GPa may have a first length in the first direction X, and the second intermediate gate pads 31GPb may have a second length in the first direction X that is greater than the first length.

[0089] In example embodiments, the second intermediate gate pad 31GPb may include a first portion 31GPb1 and a second portion 31GPb2 spaced apart from each other in the first direction X. A length of the first portion 31GPb1 in the first direction X may be greater than a length of the second portion 31GPb2 in the first direction X.

[0090] The length of the first portion 31GPb1 in the first direction X may be substantially the same as the length of each first intermediate gate pad 31GPa in the first direction X. The length of the second portion 31GPb2 in the first direction X may be smaller than the length of each first intermediate gate pad 31GPa in the first direction X.

[0091] In example embodiments, one or more second intermediate gate pads 31GPb may be provided. When a plurality of second intermediate gate pads 31GPb are provided, each of the plurality of second intermediate gate pads 31GPb may be provided between one of the plurality of first intermediate gate pads 31GPa and another of the plurality of first intermediate gate pads 31GPa.

[0092] Similar to the second middle mold pad 31MPb, the center area of ​​the second middle gate pad 31GPb may include a second cover insulating layer 43, and in some embodiments, is filled with the second cover insulating layer 43. For example, the center area between the first portion 31GPb1 and the second portion 31GPb2 of the second middle gate pad 31GPb may include a second cover insulating layer 43, and in some embodiments, is filled with the second cover insulating layer 43. Figure 2 , a portion “CTa” overlapping the gate area GA may refer to a central area of ​​each second intermediate gate pad 31GPb.

[0093] The lower gate pads 29GP of the lower gate layer 29G may include a first lower gate pad 29GPa and a second lower gate pad 29GPb. The second lower gate pad 29GPb may be disposed between the first lower gate pad 29GPa and the first intermediate gate pad 31GPa.

[0094] The length of the second lower gate pad 29GPb in the first direction X may be greater than the length of each first lower gate pad 29GPa in the first direction X. The second lower gate pad 29GPb may have a structure substantially the same as that of the second intermediate gate pad 31GPb and may be formed of a material that is the same as or similar to that of the second intermediate gate pad 31GPb. Figure 2 , a portion “CTb” overlapping the gate area GA may refer to a central area of ​​each second lower gate pad 29GPb.

[0095] In the following description, reference will be made to Figure 7 、 Figure 8 、 Figure 9 and Figure 10 The insulating area IA and the gate area GA are described in more detail. Figure 7 and Figure 8 It can be seen that the first portion 31Mb1 and the second portion 31Mb2 of the second middle mold pad 31MPb are spaced apart from each other in the first direction X (eg, Figure 4 A cross-sectional view of the area between ). Figure 9 and Figure 10 A cross-sectional structure of a central area of ​​one first middle mold pad 31 MPa in the second direction Y may be shown.

[0096] Reference Figure 7 and Figure 8 , in the first part 31Mb1( Figure 4 ) and the second part 31Mb2( Figure 4 In the cross-sectional structure of the region between the uppermost second layer 23, the second middle mold layer 31M, and the second middle gate layer 31G in the second direction Y, the uppermost second layer 23 may not include a portion having an increased thickness.

[0097] In the first part 31Mb1( Figure 4 ) and the second part 31Mb2( Figure 4 In the cross-sectional structure of the region between the insulating region IA and the second middle mold layer 31M in the second direction Y, the width of the insulating region IA in the second direction Y may be determined by the width of the second middle mold layer 31M in the second direction Y.

[0098] Reference Figure 9 and Figure 10 In the second stacking region ST2 ( Figure 2 In the first stacking region ST1 ( Figure 2 In the middle pads 31GP and 31MP, the middle gate pad 31GP may be formed from the second stacking region ST2 to the third stacking region ST3 ( Figure 2 In the third stacking area ST3 ( Figure 2 In FIG. 3 , the middle pads 31GP and 31MP may be arranged at a constant level.

[0099] As in reference Figure 3 and Figure 4 As described in the example embodiment of FIG, each first intermediate mold pad 31MPa may include a mold pad portion 24a and an insulating protrusion portion 24b located on the mold pad portion 24a. The length of the insulating protrusion portion 24b in the second direction Y may be smaller than the length of the mold pad portion 24a in the second direction Y.

[0100] Each of the intermediate gate pads 31GP adjacent to the first intermediate mold pad 31MPa may include a gate extension portion 31GPe extending from the upper region of the portion having the increased thickness to the upper surface of the mold pad portion 24a and adjacent to the side surface of the insulating protrusion portion 24b. The gate extension portion 31GPe may contact the upper surface of the mold pad portion 24a and may contact the side surface of the insulating protrusion portion 24b. Therefore, each of the intermediate gate pads 31GP adjacent to the first intermediate mold pad 31MPa may include a gate extension portion 31GPe overlapping the upper surface of the mold pad portion 24a of the adjacent first intermediate mold pad 31MPa. The width of the insulating region 1A in the second direction Y may be determined by the length of the insulating protrusion portion 24b in the second direction Y. The length of the insulating protrusion portion 24b in the second direction Y may be less than the length of each intermediate mold layer 31M in the second direction Y. The length of the mold pad portion 24 a in the second direction Y may be the same as the length of each middle mold layer 31M in the second direction Y.

[0101] As in Figure 7 and Figure 8 In the illustrated exemplary embodiment, in the first portion 31MPb1 ( Figure 4 Middle) and the second part 31MPb2( Figure 4 In the cross-sectional structure of the region between the insulating region IA and the insulating region IA in the second direction Y, the insulating region IA may have a first length L1 in the second direction Y. Figure 9 and Figure 10In the illustrated example embodiment, in a cross-sectional structure of a central region of one first intermediate mold pad 31 MPa in the second direction Y, the insulating region IA may further have a second length L2 in the second direction Y. The first length L1 may be greater than the second length L2.

[0102] In the following description, reference will be made to Figure 11 and Figure 12 The gate layers 29G, 31G, 33G, and 35G, the memory cell vertical structure 46, and the separation structures 69a, 69b, and 69c are described in more detail.

[0103] Reference Figure 11 and Figure 12 The gate layers 29G, 31G, 33G, and 35G may each include a first gate layer 27a and a second gate layer 27b. The first gate layer 27a may cover the lower and upper surfaces of the second gate layer 27b and may extend to the region between the second gate layer 27b and the memory cell vertical structure 46.

[0104] In example embodiments, the first gate layer 27a may include a first conductive material (eg, tungsten (W), etc.), and the second gate layer 27b may include a second conductive material (eg, titanium nitride (TiN), tungsten nitride (WN), etc.) different from the first conductive material.

[0105] In another example embodiment, the first gate layer 27a may include a dielectric material, and the second gate layer 27b may include a conductive material (eg, TiN, W, etc.) The dielectric material of the first gate layer 27a may include a high-k dielectric such as aluminum oxide (AlO).

[0106] The memory cell vertical structure 46 may include a dielectric structure 48, a channel layer 57, a core layer 60, and a pad layer 63. The channel layer 57 may be disposed on a side surface of the core layer 60, the pad layer 63 may be disposed on the core layer 60, and the dielectric structure 48 may be disposed on an outer side surface of the channel layer 57.

[0107] The dielectric structure 48 may include a first dielectric layer 50, a second dielectric layer 54, and a data storage layer 52 disposed between the first dielectric layer 50 and the second dielectric layer 54. The second dielectric layer 54 may be disposed between the channel layer 57 and the data storage layer 52.

[0108] The bit line contact plug 78 may be in contact with the pad layer 63 .

[0109] In example embodiments, the intermediate gate layer 31G may include a word line. A region of the data storage layer 52 opposite the intermediate gate layer 31G, which may be configured as a word line, may be configured as a data storage region that may store data in the flash memory device.

[0110] In example embodiments, at least one lower gate layer 29G or at least one of the plurality of lower gate layers 29G may be configured as a lower selection gate electrode, and at least one of the plurality of upper gate layers 33G may be configured as an upper selection gate electrode.

[0111] In another example embodiment, when multiple lower gate layers 29G are provided, one of the multiple lower gate layers 29G may be configured as a lower select gate electrode, while another may be configured as a lower erase gate electrode used in an erase operation of the flash memory device. One of the multiple upper gate layers 33G may be configured as an upper select gate electrode, while another may be configured as an upper erase gate electrode used in an erase operation of the flash memory device.

[0112] In example embodiments, the first to third separation structures 69a, 69b, and 69c may each include a separation spacer 70a and a separation core pattern 70b. The separation spacer 70a may be formed of an insulating material, and the separation core pattern 70b may be formed of a conductive material.

[0113] In another example embodiment, the first to third separation structures 69 a , 69 b , and 69 c may each be formed of an insulating material such as silicon oxide.

[0114] In the following description, reference will be made to Figure 13A describe Figure 4 The second middle mold pad 31MPb ( Figure 4 ) is a modified example. Figure 13A It shows Figure 4 The second middle mold pad 31MPb ( Figure 4 (middle) is an enlarged view of a modified example.

[0115] In the modified example, refer to Figure 13A The second middle mold pad 31MPb' may include a mold pad portion 24a' and a first insulating protrusion portion 24b1 and a second insulating protrusion portion 24b2 disposed on the mold pad portion 24a' and spaced apart from each other. The first insulating protrusion portion 24b1 and the second insulating protrusion portion 24b2 may be spaced apart from the memory cell array area MA in sequence. The length of the first insulating protrusion portion 24b1 in the first direction X may be greater than the length of the second insulating protrusion portion 24b2 in the first direction X.

[0116] In the following description, reference will be made to Figure 13B describe Figure 6 The second intermediate gate pad 31GPb ( Figure 6 ) is a modified example. Figure 13B It shows Figure 6The second intermediate gate pad 31GPb ( Figure 6 (middle) is an enlarged view of a modified example.

[0117] In the modified example, refer to Figure 13B The second intermediate gate pad 31GPb' may include a first portion 31GPb1' and a second portion 31GPb2' arranged sequentially in the first direction X and each having an increasing thickness, and a third portion 31GPb3' connecting the first portion 31GPb1' to the second portion 31GPb2'. The thickness of the third portion 31GPb3' (for example, in the vertical direction Z) may be less than the thickness of each of the first portion 31GPb1' and the second portion 31GPb2'. The third portion 31GPb3' may be the central region of the second intermediate gate pad 31GPb'. The central region 31GPb3' of the second intermediate gate pad 31GPb' may include a conductive material layer. The first portion 31GPb1', the second portion 31GPb2', and the central region 31GPb3' may include a conductive material layer.

[0118] In the following description, reference will be made to Figure 14 describe Figure 4 The second middle mold pad 31MPb ( Figure 4 ) is a modified example. Figure 14 It shows Figure 4 The second middle mold pad 31MPb ( Figure 4 (middle) is an enlarged view of a modified example.

[0119] In an exemplary embodiment, referring to Figure 14 The second middle mold pad 31Mb″ may include a mold pad portion 24a″ and a first insulating protrusion portion 24b1′ and a second insulating protrusion portion 24b2′ provided on the mold pad portion 24a″ and spaced apart from each other. The length of each of the first insulating protrusion portion 24b1′ and the second insulating protrusion portion 24b2′ in the first direction X may be smaller than the length of each first middle mold pad 31MPa in the first direction X.

[0120] In the following description, we will describe Figure 6 The second intermediate gate pad 31GPb ( Figure 6 ) is a modified example. Figure 15 It shows Figure 6 The second intermediate gate pad 31GPb ( Figure 6 (middle) is an enlarged view of a modified example.

[0121] In the modified example, refer to Figure 15The second intermediate gate pad 31GPb″ may have a thickness substantially the same as that of each first intermediate gate pad 31GPa, and a length in the first direction X may be greater than a length in the first direction X of each first intermediate gate pad 31GPa.

[0122] In the following description, reference will be made to Figure 16 Describe the second middle mold pad 31MPb ( Figure 4 ) is a modified example. Figure 16 It shows Figure 4 FIG. 1 is an enlarged view of another modified example of the second middle mold pad 31MPb.

[0123] In the modified example, refer to Figure 16 , the second middle mold pad 31MPbb may include a first portion 31MPb1′ and a second portion 31MPb2′ spaced apart from each other in the first direction X. The first portion 31MPb1′ and the second portion 31MPb2′ may each include the mold pad portion 24a ( Figure 4 ) and the insulating protrusion 24b ( Figure 4 ).

[0124] A length of each of the first portion 31MPb1 ′ and the second portion 31MPb2 ′ in the first direction X may be smaller than a length of each of the first middle mold pads 31MPa in the first direction X.

[0125] In the following description, reference will be made to Figure 17 and Figure 18 Describe the first intermediate mold pad 31MPa ( Figure 4 middle) and the second middle mold pad 31MPb ( Figure 4 ) is a modified example. Figure 17 and Figure 18 is a graph showing the first intermediate mold pad 31MPa ( Figure 4 middle) and the second middle mold pad 31MPb ( Figure 4 (middle) is an enlarged view of a modified example.

[0126] In the modified example, refer to Figure 17, the second intermediate mold pad 31MPbb' may not have an increased thickness. The first intermediate mold pad 31MPa1 of the first intermediate mold pad 31MPaa adjacent to the second intermediate mold pad 31MPbb' may not have an increased thickness, while the other first intermediate mold pads 31MPa2 may have an increased thickness. For example, the first intermediate mold pads 31MPa2 of the first intermediate mold pads 31MPaa that have an increased thickness may include the mold pad portion 24a and the insulating protrusion portion 24b described in the above example embodiment, and the first intermediate mold pads 31MPa1 of the first intermediate mold pads 31MPaa that do not have an increased thickness may include only the mold pad portion 24a and may not include the insulating protrusion portion 24b.

[0127] In the modified example, refer to Figure 18 , the second middle mold pad 31MPbb' may not have an increased thickness, each partial first middle mold pad 31MPa1' of the first middle mold pad 31MPaa' adjacent to the second middle mold pad 31MPbb' may not have an increased thickness, and each other first middle mold pad 31MPa2' may have an increased thickness.

[0128] The first intermediate mold pads 31 MPa1 ′ each having no increased thickness may be referred to as a first thin intermediate mold pad, and the first intermediate mold pads 31 MPa2 ′ each having an increased thickness may be referred to as a first thick intermediate mold pad.

[0129] A height difference between a first thin intermediate mold pad 31MPaa' and a second intermediate mold pad 31MPbb' adjacent to the second intermediate mold pad 31MPbb', which are disposed at a level higher than that of the second intermediate mold pad 31MPaa', of the first intermediate mold pad 31MPaa' may be smaller than a height difference between the first thin intermediate mold pad 31MPa1' and the first thick intermediate mold pad 31MPa2'.

[0130] A height difference between a first thin intermediate mold pad 31MPaa' and a second intermediate mold pad 31MPbb' adjacent to the second intermediate mold pad 31MPaa', which are disposed at a level lower than that of the second intermediate mold pad 31MPbb', of the first intermediate mold pad 31MPaa' may be greater than a height difference between the first thin intermediate mold pad 31MPa1' and the first thick intermediate mold pad 31MPa2'.

[0131] In some of the aforementioned example embodiments, some of the plurality of intermediate mold pads 31MP may each include a mold pad portion 24a and an insulating protrusion portion 24b located on the mold pad portion 24a, and at least some of the plurality of first intermediate mold pads 31MPa may each include a mold pad portion 24a and an insulating protrusion portion 24b.

[0132] In some of the aforementioned example embodiments, at least the central region of the second middle mold pad 31MPb may not include the insulating protrusion portion 24b. Figure 4 As shown, a central region of the second middle mold pad 31MPb may include the second cover insulating layer 43 , and in some embodiments, be filled with the second cover insulating layer 43 .

[0133] In some example embodiments, a first intermediate mold pad including the mold pad portion 24a and the insulating protrusion portion 24b among the plurality of first intermediate mold pads 31 MPa may have a first thickness, and in some example embodiments, a central portion of the second intermediate mold pad may have a second thickness less than the first thickness. For example, Figure 13A As shown, the central area (in 13A) of the second middle mold pad 31MPb' may include an insulating material layer having a second thickness less than the first thickness. Figure 13A The insulating material layer in the central area of ​​​​the mold pad portion 24a can be part of the mold pad portion 24a.

[0134] In example embodiments, by providing a stack structure ST including the gate area GA and the insulating area IA, the integration density of a semiconductor device may be improved.

[0135] In the following description, reference will be made to Figures 19 to 20C A modified example of the semiconductor device 1a is described. Figures 19 to 20C , Figure 19 is a top view showing a modified example of the semiconductor device. Figure 20A is shown along Figure 19 A cross-sectional view of the area taken along line VI-VI'. Figure 20B is shown along Figure 19 A cross-sectional view of the region taken along line VII-VII' in FIG. Figure 20C 2 is a cross-sectional view showing regions taken along line VIII-VIII' and line IX-IX'.

[0136] Reference Figures 19 to 20C, a lower structure 3 substantially the same as that in the above-described exemplary embodiment may be provided. The lower structure 3 may include a lower substrate 5, an upper substrate 12 located on the lower substrate 5, a peripheral circuit region 7 located between the lower substrate 5 and the upper substrate 12, a gap-filling insulating layer 13 penetrating the lower substrate 5, and an intermediate insulating layer 14 located on a side surface of the lower substrate 5 and surrounding the side surface of the lower substrate 5 in some embodiments.

[0137] The stack structure ST' may be disposed on the lower structure 3. The stack structure ST' may be disposed on the lower structure 3 in the memory cell array area MA and the connection area EA. The stack structure ST' may include a gate area GA' and an insulating area IA' not including a conductive material.

[0138] The gate region GA′ may be disposed in the memory cell array region MA, and may be disposed in a portion of the connection region EA.

[0139] The stacked structure ST' may include first layers 120 and second layers 123 alternately stacked on the lower structure 3. The first layer 120 may be disposed in the gate area GA' and the insulating area IA'. The first layer 120 may be configured as an interlayer insulating layer.

[0140] A first cover insulating layer 140 and a second cover insulating layer 143 may be disposed on the stack structure ST'. The first cover insulating layer 140 may be located on the uppermost second layer of the second layers 123, and in some embodiments, covers the uppermost second layer. The upper surface of the second cover insulating layer 143 may be coplanar with the upper surface of the first cover insulating layer 140, and the second cover insulating layer 143 may be located on the rest of the stack structure ST', and in some embodiments, covers the rest of the stack structure ST'.

[0141] A plurality of separation structures 169a, 169b, and 169c penetrating the stack structure ST' may be disposed on the lower structure 3. The plurality of separation structures 169a, 169b, and 169c may include a first separation structure 169a passing through the memory cell array region MA and the connection region EA, a second separation structure 169b passing through the memory cell array region MA and extending into a portion of the connection region EA, and a third separation structure 169c disposed in a portion of the connection region EA.

[0142] Each first separation structure 169a may include a pair of first portions 169a1 passing through the memory cell array area MA and extending into a portion of the connection area EA, and a second portion 169a2 connected to the pair of first portions 169a1 and extending in the first direction X in the connection area EA.

[0143] The third partition structure 169c may be disposed between the second portions 169a2 of the first partition structures 169a. The second partition structure 169b may be disposed between the first portions 169a1 of the first partition structures 169a.

[0144] The distance between the side surface of the third separator structure 169c and the side surface of the second portion 169a2 of each first separator structure 169a adjacent to the third separator structure 169c may be greater than the distance between the side surfaces of the second separator structures 169b adjacent to each other. The distance between the side surface of the third separator structure 169c and the side surface of the second portion 169a2 of each first separator structure 169a adjacent to the third separator structure 169c may be greater than the distance between the side surfaces of the second separator structures 169b adjacent to each other and the side surfaces of the first portion 169a1 of the first separator structure 169a.

[0145] The second layer 123 may include gate layers 129G, 131G, 133G, and 135G disposed in the gate region GA′ and mold layers 129M, 131M, and 135M disposed in the insulating region IA′. Therefore, the corresponding lower gate layer 129G and the intermediate gate layer 131G disposed at the same level in the boundary region between the gate region GA′ and the insulating region IA′ and the corresponding lower mold layer 129M and the intermediate mold layer 131M may be opposite to each other (e.g., the corresponding ends of the lower mold layer 129M and the intermediate mold layer 131M may face the corresponding ends of the lower gate layer 129G and the intermediate gate layer 131G).

[0146] In example embodiments, the mold layers 129M, 131M, and 135M may be made of Figures 1 to 12 The mold layers 29M, 31M, and 35M are shown to be formed of the same material.

[0147] In example embodiments, the gate layers 129G, 131G, 133G, and 135G may each include a conductive material. For example, the gate layers 129G, 131G, 133G, and 135G may each be configured as a gate electrode.

[0148] The gate layers 129G, 131G, 133G, and 135G may include one or more lower gate layers 129G, a plurality of intermediate gate layers 131G on the one or more lower gate layers 129G, an upper gate layer 133G on the plurality of intermediate gate layers 131G, and a floating gate layer 135G on the plurality of intermediate gate layers 131G.

[0149] The mold layers 129M, 131M, and 135M may include one or more lower mold layers 129M, a plurality of middle mold layers 131M on the one or more lower mold layers 129M, and a floating mold layer 135M on the plurality of middle mold layers 131M.

[0150] The gate layers 129G, 131G, 133G, and 135G may include multiple gate pads arranged in a staircase structure, and the mold layers 129M, 131M, and 135M may include multiple mold pads arranged in a staircase structure. For example, one or more lower gate layers 129G may include one or more lower gate pads 129GP, multiple intermediate gate layers 131G may include intermediate gate pads 131GP, and multiple upper gate layers 133G may include upper gate pads 133GP. One or more lower mold layers 129M may include one or more lower mold pads 129MP, and the intermediate mold layer 131M may include an intermediate mold pad 131MP.

[0151] The thickness of at least one of lower gate pad 129GP, middle gate pad 131GP, and upper gate pad 133GP may be greater than the thickness of each of gate layers 129G, 131G, and 133G. The thickness of each of gate layers 129G, 131G, and 133G may refer to the thickness of a region of each of gate layers 129G, 131G, and 133G where lower gate pad 129GP, middle gate pad 131GP, and upper gate pad 133GP are not provided.

[0152] A thickness of at least one of the lower mold pad 129MP and the middle mold pad 131MP may be greater than a thickness of each of the gate layers 129G, 131G, and 133G.

[0153] In some embodiments, the thickness of at least one of the lower mold pad 129MP and the middle mold pad 131MP may be greater than the thickness of each of the mold layers 129M and 133M. The thickness of each of the mold layers 129M and 133M may refer to the thickness of the region of each of the mold layers 129M and 133M where the lower mold pad 129MP and the middle mold pad 133MP are not provided.

[0154] The intermediate gate pad 131GP may include a first intermediate gate pad 131GPa. The first intermediate gate pad 131GPa is formed by Figure 6 The first intermediate gate pad 31GPa ( Figure 6The intermediate gate pad 131GP may include a second intermediate gate pad 31GPb formed of the same material as the material of the intermediate gate pad 31Gpa and having the same structure as the structure of each first intermediate gate pad 31Gpa. Figure 6 The second intermediate gate pad 31GPb ( Figure 6 The material of the second intermediate gate pad 31GPb is the same as that of the material of the second intermediate gate pad 31GPb. Figure 6 In the example embodiment shown, the second intermediate gate pad 131GPb may include a first portion 131GPb1 and a second portion 131GPb2 spaced apart from each other, and a central area of ​​the second intermediate gate pad 131GPb located between the first portion 131GPb1 and the second portion 131GPb2 may be filled with the second capping insulating layer 143 .

[0155] The lower gate pad 129GP may include a first lower gate pad 129GPa. The first lower gate pad 129GPa is formed by Figure 5 The first lower gate pad 29GPa ( Figure 5 The lower gate pad 129GP may include a second lower gate pad 129GPb having the same material as the material of the first lower gate pad 29GPa and the lower gate pad 129GP may include a second lower gate pad 129GPb having the same material as the material of the first lower gate pad 29GPa. Figure 5 The second lower gate pad 29GPb ( Figure 5 The material of the second lower gate pad 29GPb is the same as that of the material of the second lower gate pad 29GPb. Figure 5 In the example embodiment shown, the second lower gate pad 129GPb may include a first portion 129GPb1 and a second portion 129GPb2 spaced apart from each other, and a central area of ​​the second lower gate pad 129GPb located between the first portion 129GPb1 and the second portion 129GPb2 may be filled with the second capping insulating layer 143 .

[0156] The middle mold pad 131MP may include a first middle mold pad 131MPa. The first middle mold pad 131MPa is formed by Figure 4 The first intermediate mold pad shown is 31 MPa ( Figure 4 The intermediate mold pad 131MP may include a second intermediate mold pad 131MPb made of the same material as the first intermediate mold pad 31MPa. Figure 4 The second middle mold pad 31MPb ( Figure 4The first intermediate mold pad 131MPa may be formed of the same material as the material of the first intermediate mold pad 131MPa and have the same structure as the second intermediate mold pad 31MPb. For example, each first intermediate mold pad 131MPa may include a mold pad portion 124a and an insulating protrusion portion 124b located on the mold pad portion 124a. Figure 4 In the example embodiment shown, the second middle mold pad 131MPb may include a first portion 131MPb1 and a second portion 131MPb2 spaced apart from each other. The central region of the second middle mold pad 131MPb may not include the insulating protrusion 124b. For example, the central region of the second middle mold pad 131MPb between the first portion 131MPb1 and the second portion 131MPb2 may be filled with the second cover insulating layer 143.

[0157] The lower mold pad 129MP may include a first lower mold pad 129MPa and a second lower mold pad 129MPb. The second lower mold pad 129MPb may be adjacent to the middle mold pad 131MP and may include a first portion 129MPb1 and a second portion 129MPb2 spaced apart from each other. The central region of the second lower mold pad 129MPb may not include the insulating protrusion 124b. For example, the central region of the second lower mold pad 129MPb between the first portion 129MPb1 and the second portion 129MPb2 may be filled with the second capping insulating layer 143.

[0158] exist Figure 19 , the reference symbol “CT” may refer to a central area of ​​the second middle mold pad 131MPb, a central area of ​​the second middle gate pad 131GPb, a central area of ​​the second lower mold pad 129MPb, and a central area of ​​the second lower gate pad 129MPb.

[0159] A first upper insulating layer 166 and a second upper insulating layer 172 may be sequentially stacked on the first cover insulating layer 140 and the second cover insulating layer 143. The first to third separation structures 169a, 169b, and 169c may penetrate the stacked structure ST', may extend upward, and may penetrate the first and second cover insulating layers 140 and 143 and the first upper insulating layer 166.

[0160] A bit line contact plug 178 penetrating the first and second upper insulating layers 166 and 172 and electrically connected to the memory cell vertical structure 146 may be provided.

[0161] In the connection area EA, a gate contact structure 175 penetrating the first and second upper insulating layers 166 and 172 , extending downward, and electrically connected to the lower, middle, and upper gate pads 129GP, 131GP, and 133GP may be provided.

[0162] A peripheral contact structure 181 that contacts the peripheral pad portion 8P of the peripheral wiring 8 , extends upward, and penetrates the gap-fill insulating layer 113 and the insulating region IA′ of the stack structure ST′ may be provided.

[0163] A gate connection wiring 185 may be disposed on the gate contact structure 175 and the peripheral contact structure 181 .

[0164] The bit line 184 may be disposed on the bit line contact plug 178 .

[0165] In the following description, reference will be made to Figure 21 and Figures 22A to 23B An example of a method of manufacturing a semiconductor device is described. Figure 21 is a flowchart illustrating a method of fabricating a semiconductor device according to example embodiments of the inventive concepts. Figures 22A to 23B is a cross-sectional view illustrating an example of a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts. Figure 22A and Figure 23A is shown along Figure 19 A cross-sectional view of the region cut along line VII-VII' in FIG. Figure 22B and Figure 23B is shown along Figure 19 A cross-sectional view of the region taken along line VIII-VIII' and line IX-IX' in FIG.

[0166] Reference Figure 19 、 Figure 21 、 Figure 22A and Figure 22B , a mold structure 119 including an insulating layer 120 and a mold layer 121 may be formed on the lower structure 3 (S10). The insulating layer 120 may be formed of silicon oxide, and the mold layer 121 may be formed of silicon nitride. The insulating layer 120 and the mold layer 121 may be alternately stacked.

[0167] The lower structure 3 may include a lower substrate 5, an upper substrate 12 located on the lower substrate 5, a peripheral circuit area 7 located between the lower substrate 5 and the upper substrate 12, a gap-filling insulating layer 13 penetrating the lower substrate 5, and an intermediate insulating layer 14 located on the side surface of the lower substrate 5 and surrounding the side surface of the lower substrate 5 in some embodiments.

[0168] A molding structure 119 may be formed on the lower structure 3 in the memory cell array area MA and the connection area EA.

[0169] In the connection area EA, a step structure exposing the mold layer 121 may be formed (S20). For example, the step structure may be formed by patterning the insulating layer 120 and the mold layer 121, and the mold layer 121 may be exposed through the step structure. The form of the step structure may not be limited to the example shown in the figure and may be changed. For example, the step structure may be configured as Figures 1 to 12 The stacked structure ST shown has a staircase structure.

[0170] In the connection area EA, pad areas 121P each having an increased thickness may be formed by forming an additional mold layer 124 b on the exposed mold layer 121 ( S30 ).

[0171] By performing a photolithography process and an etching process, a portion of the pad region 121P may be etched ( S40 ).

[0172] In example embodiments, a length of each of the etched partial pad regions in the first direction X may be greater than a length of each other pad region in the first direction X. The etched partial pad region may be divided into a first portion 121P1 and a second portion 121P2 .

[0173] In example embodiments, etching a portion of the pad region 121P may include removing the additional mold layer and the mold layer of the etched pad region.

[0174] In another example embodiment, etching a portion of the pad region 121P may include removing only the additional mold layer while retaining the mold layer of the etched pad region.

[0175] A cover insulating layer 140 and 143 may be formed on the mold structure 119 and, in some embodiments, cover the mold structure 119. The cover insulating layers 140 and 143 may include a first cover insulating layer 140 formed before forming the stepped structure and a second cover insulating layer 143 formed after forming the stepped structure. A memory cell vertical structure 146 may be formed penetrating the first cover insulating layer 140 and the mold structure 119. The memory cell vertical structure 146 may have the same Figure 12 The vertical structure 46 of the memory cell shown ( Figure 12 The structure of the same structure as in the above example.

[0176] Reference 20A to 20C Together Figure 19 、 Figure 21 、 Figure 23A and Figure 23B, an insulating layer 166 may be formed (S50). For example, a first upper insulating layer 166 may be formed on the first cover insulating layer 140 and the second cover insulating layer 143. A mold structure 119 ( Figure 22A ) separation groove 165.

[0177] The gate layers 129G, 131G, 133G and 135G (in 20A to 20C ) replaces a portion of the mold layer 121 and a portion of the additional mold layer 124b.

[0178] With gate layers 129G, 131G, 133G and 135G ( Figures 20A to 20C Replacing a portion of the mold layer 121 and a portion of the additional mold layer 124b may include: forming an empty space 167 by partially etching the mold layer 121 and the additional mold layer 124b exposed by the separation trench 165; and forming gate layers 129G, 131G, 133G, and 135G in the empty space 167. Figures 20A to 20C middle).

[0179] The remaining molded layers 121 ( Figure 23A and Figure 23B ) and the remaining first upper insulating layer 166 may be included in the reference Figure 20A and Figure 20B In the mold layers 129M, 131M and 135M described in the aforementioned example embodiments.

[0180] Reference Figure 19 as well as 20A to 20C , a filling separation trench 165 ( Figure 23B The partition structures 169a, 169b and 169c ( Figure 20C A second upper insulating layer 172 may be formed on the first upper insulating layer 166.

[0181] A bit line contact plug 178 penetrating the first and second upper insulating layers 166 and 172 and electrically connected to the memory cell vertical structure 146 may be formed.

[0182] A gate contact structure 175 ( ) penetrating the first and second upper insulating layers 166 and 172, extending downward, and electrically connected to the gate pads 129GP, 131GP, and 133GP of the gate layers 129G, 131G, 133G, and 135G may be formed. 20A to 20C middle).

[0183] An insulating region IA′ ( ) may be formed penetrating the mold layers 129M, 131M, and 135M. Figure 19 ) and is electrically connected to the peripheral contact structure 181 of the peripheral pad portion 8P of the peripheral wiring 8 of the peripheral circuit region 7 of the lower structure 3.

[0184] A bit line 184 may be formed on the bit line contact plug 178 .

[0185] A gate connection wiring 185 may be formed on the gate contact structure 175 and the peripheral contact structure 181 .

[0186] According to the aforementioned example embodiments, by providing a stack structure including a gate region and an insulating region on a lower structure including a peripheral circuit region, the integration density of a semiconductor may be improved.

[0187] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: a lower structure comprising a lower substrate, an upper substrate located on the lower substrate, a peripheral circuit region located between the lower substrate and the upper substrate and comprising peripheral wiring, and a gap-filling insulating layer penetrating the upper substrate; a stacked structure located in a memory cell array region on the lower structure and extending into a connection region on the lower structure, wherein the stacked structure has a stepped structure in the connection region, wherein the stacked structure includes a gate region and a first insulating region, wherein the gate region is located in the memory cell array region and extends into the connection region, and wherein the first insulating region is located in the connection region; a covering insulating layer, located on the stacked structure; and A vertical structure of a memory cell is located in the gate region in the memory cell array region, The stacked structure includes a plurality of first layers and a plurality of second layers alternately stacked on the lower structure. The plurality of second layers include a plurality of gate layers located in the gate region, a plurality of mold layers located in the first insulating region, a plurality of gate pads extending from the plurality of gate layers, and a plurality of mold pads extending from at least one of the mold layers. Wherein, the plurality of gate layers all comprise conductive materials, Wherein, the plurality of molding layers each comprise insulating material, The plurality of molding layers include one or more lower molding layers, a plurality of intermediate molding layers located on the one or more lower molding layers, and one or more floating molding layers located on the plurality of intermediate molding layers. wherein the plurality of mold pads include a plurality of intermediate mold pads extending from at least one of the plurality of intermediate mold layers, wherein the plurality of intermediate mold pads comprise a stepped structure descending along a first direction, wherein the first direction extends from the memory cell array region to the connection region, wherein the plurality of intermediate mold pads include a plurality of first intermediate mold pads and a second intermediate mold pad located between pairs of the first intermediate mold pads in the plurality of first intermediate mold pads; wherein the plurality of first intermediate mold pads each have a first length in the first direction, wherein the second middle mold pad has a second length in the first direction that is greater than the first length, wherein at least one of the plurality of intermediate mold pads comprises a mold pad portion and an insulating protrusion portion located on the mold pad portion; wherein at least one first intermediate mold pad of the plurality of first intermediate mold pads comprises the mold pad portion and the insulating protrusion portion, and Wherein, at least a central area of ​​the second middle mold pad does not include the insulating protrusion portion.

2. The semiconductor device according to claim 1, wherein the second intermediate mold pad includes a first portion and a second portion spaced apart from each other in the first direction, wherein the first portion and the second portion of the second intermediate mold pad each include the mold pad portion and the insulating protrusion portion, wherein the length of the first portion of the second middle mold pad in the first direction is greater than the length of the second portion of the second middle mold pad in the first direction, wherein the mold pad portion comprises the same material as that of the plurality of intermediate mold layers and has the same thickness as that of each of the plurality of intermediate mold layers, wherein the mold pad portion comprises a first insulating material based on silicon nitride, and The insulating protrusion portion includes a second insulating material based on silicon nitride, and an etching rate of the second insulating material is higher than an etching rate of the first insulating material.

3. The semiconductor device according to claim 1 , further comprising: a plurality of peripheral contact structures penetrating the first insulating region and electrically connected to peripheral contact pads of the peripheral wiring; a plurality of gate contact structures located on the plurality of gate pads; as well as a plurality of gate connection wirings located on the plurality of peripheral contact structures and the plurality of gate contact structures, The plurality of gate layers include one or more lower gate layers, a plurality of intermediate gate layers located on the one or more lower gate layers, and a plurality of upper gate layers located on the plurality of intermediate gate layers. The plurality of gate pads include a plurality of upper gate pads extending from the plurality of upper gate layers, a plurality of intermediate gate pads extending from the plurality of intermediate gate layers, and one or more lower gate pads extending from the one or more lower gate layers. wherein the plurality of intermediate gate pads comprise a stepped structure descending in the first direction and descending in a second direction perpendicular to the first direction, The plurality of intermediate gate pads include a plurality of first intermediate gate pads and a second intermediate gate pad located between pairs of the plurality of first intermediate gate pads. wherein a first thickness of each of the plurality of first intermediate gate pads is greater than a second thickness of each of the plurality of gate layers; wherein each of the plurality of first intermediate gate pads has the first length in the first direction, wherein the second intermediate gate pad has a second length in the first direction that is greater than the first length, and One of the plurality of gate connection wirings is electrically connected to one of the plurality of peripheral contact structures and is electrically connected to one of the plurality of gate contact structures.

4. The semiconductor device according to claim 3, in, The second intermediate gate pad includes a first portion, a second portion, and a central area between the first portion of the second intermediate gate pad and the second portion of the second intermediate gate pad. The central area of ​​the second intermediate gate pad includes a conductive material layer having a thickness less than the first thickness or includes the covering insulating layer. wherein the first portion of the second intermediate gate pad extends from one of the plurality of intermediate gate layers, and One of the plurality of gate contact structures is in contact with the first portion of the second intermediate gate pad.

5. The semiconductor device according to claim 4, in, The second intermediate mold pad is one of a plurality of second intermediate mold pads, wherein each of the plurality of second intermediate mold pads is located between a pair of first intermediate mold pads of the plurality of first intermediate mold pads, wherein the second intermediate gate pad is one of a plurality of second intermediate gate pads, Each of the plurality of second intermediate gate pads is located between a pair of first intermediate gate pads among the plurality of first intermediate gate pads. wherein the one or more lower molding layers are a plurality of lower molding layers, The plurality of molding pads further include a plurality of lower molding pads, and the plurality of lower molding pads extend from the plurality of lower molding layers respectively. wherein the plurality of lower mold pads include a first lower mold pad and a second lower mold pad, wherein the length of the second lower mold pad in the first direction is greater than the length of the first lower mold pad in the first direction, wherein the second lower mold pad is adjacent to the plurality of first middle mold pads, and The second lower mold pad has the same structure as that of a corresponding second middle mold pad among the plurality of second middle mold pads, and includes the same material as that of a corresponding second middle mold pad among the plurality of second middle mold pads.

6. The semiconductor device according to claim 5, further comprising: A plurality of partition structures penetrate the stacking structure, Wherein, the stacked structure further includes a second insulating region, Part of the gate region is located between the first insulating region and the second insulating region. The plurality of first intermediate gate pads are located between the first insulating region and the second insulating region. The plurality of first intermediate gate pads include a structure in which an outermost edge of a first intermediate gate pad among the plurality of first intermediate gate pads extends laterally beyond an outermost edge of a second first intermediate gate pad among the plurality of first intermediate gate pads, and the second first intermediate gate pad is immediately above the first intermediate gate pad. The plurality of separation structures penetrate the gate region between the first insulating region and the second insulating region. The first portion of the gate region is located between a side surface of a separation structure adjacent to the first insulating region among the plurality of separation structures and a side surface of the first insulating region, and The second portion of the gate region is located between a side surface of a separation structure adjacent to the second insulating region among the plurality of separation structures and a side surface of the second insulating region.

7. A semiconductor device, comprising: Substructure; a stacked structure located in a memory cell array region on the lower structure and extending into a connection region on the lower structure, wherein the stacked structure includes a gate region and an insulating region, the gate region includes a plurality of gate pads, and the insulating region includes a plurality of mold pads; and A vertical structure of a memory cell penetrates the gate region in the memory cell array region, wherein the plurality of mold pads include a plurality of middle mold pads, wherein the plurality of intermediate mold pads include a plurality of first intermediate mold pads and a second intermediate mold pad located between pairs of the first intermediate mold pads in the plurality of first intermediate mold pads; wherein the plurality of first intermediate mold pads each have a first length in a first direction, wherein the second middle mold pad has a second length in the first direction that is greater than the first length, wherein at least one of the plurality of intermediate mold pads comprises a mold pad portion and an insulating protrusion portion located on the mold pad portion; wherein at least one first intermediate mold pad of the plurality of first intermediate mold pads comprises the mold pad portion and the insulating protrusion portion, and Wherein, at least a central area of ​​the second middle mold pad does not include the insulating protrusion portion.

8. The semiconductor device according to claim 7, in, the width of the mold pad portion in the second direction is greater than the width of the insulating protrusion portion of the at least one first intermediate mold pad including the mold pad portion and the insulating protrusion portion in the second direction, wherein the first direction extends from the memory cell array region to the connection region, and The second direction is perpendicular to the first direction.

9. The semiconductor device according to claim 8, in, The plurality of gate pads include a plurality of intermediate gate pads, The plurality of intermediate gate pads include a plurality of first intermediate gate pads and a second intermediate gate pad located between pairs of the first intermediate gate pads in the plurality of first intermediate gate pads. The plurality of first intermediate gate pads each have the first length in the first direction, wherein the second intermediate gate pad has the second length in the first direction, Wherein, the plurality of first intermediate gate pads each have a first thickness, and In which, a first intermediate gate pad among the multiple first intermediate gate pads that is adjacent to the at least one first intermediate molded pad including the molded pad portion and the insulating protrusion portion includes a gate extension portion, and the gate extension portion overlaps with the upper surface of the molded pad portion of the at least one first intermediate molded pad and is adjacent to the side surface of the insulating protrusion portion.

10. The semiconductor device according to claim 7, in, The stacked structure includes a plurality of first layers and a plurality of second layers alternately stacked on the lower structure. Wherein, the first layer includes an interlayer insulating layer, The plurality of second layers include a plurality of gate layers located in the gate region and a plurality of molding layers located in the insulating region. wherein the plurality of gate pads extend from the plurality of gate layers respectively, wherein the plurality of molding pads extend from the plurality of molding layers respectively, The plurality of molding layers include one or more lower molding layers, a plurality of intermediate molding layers located on the one or more lower molding layers, and one or more floating molding layers located on the plurality of intermediate molding layers. The plurality of gate layers include one or more lower gate layers, a plurality of intermediate gate layers located on the one or more lower gate layers, a plurality of upper gate layers located on the plurality of intermediate gate layers, and one or more floating gate layers located on the plurality of intermediate gate layers and spaced apart from the plurality of upper gate layers. wherein the plurality of gate pads include a plurality of intermediate gate pads extending from the plurality of intermediate gate layers, wherein the plurality of intermediate gate pads comprise a stepped structure that descends in the first direction and descends in a second direction perpendicular to the first direction, and Each of the plurality of first intermediate mold pads has a constant height in the second direction.

11. The semiconductor device according to claim 7, further comprising: a plurality of peripheral contact structures penetrating the insulating region; a plurality of gate contact structures located on the plurality of gate pads; as well as a plurality of gate connection wirings located on the plurality of peripheral contact structures and the plurality of gate contact structures, The lower structure includes a lower substrate, an upper substrate located on the lower substrate, a peripheral circuit region located between the lower substrate and the upper substrate and including peripheral wiring, and a gap-filling insulating layer penetrating the upper substrate. wherein each of the plurality of peripheral contact structures penetrates the insulating region, extends downward, penetrates the gap-filling insulating layer, and is electrically connected to a peripheral pad of the peripheral wiring, and One of the plurality of gate connection wirings is electrically connected to one of the plurality of peripheral contact structures and one of the plurality of gate contact structures.

12. The semiconductor device according to claim 11, wherein At least one peripheral contact structure of the plurality of peripheral contact structures penetrates a portion of the central region of the second intermediate mold pad.

13. The semiconductor device according to claim 7, further comprising: a plurality of partition structures, each of the plurality of partition structures penetrating the stacked structure, wherein the plurality of separation structures are spaced apart from the insulating region, and Part of the gate region is arranged between the insulating region and a separation structure adjacent to a side surface of the insulating region among the plurality of separation structures.

14. The semiconductor device according to claim 13, wherein The plurality of partition structures include a first partition structure, a second partition structure and a third partition structure, wherein the first separation structure passes through the memory cell array region and the connection region; wherein the second separation structure passes through the memory cell array region and extends into a portion of the connection region, and The third separation structure is located in the connection region and is spaced apart from the memory cell array region.

15. A semiconductor device, comprising: a lower structure comprising a lower substrate, an upper substrate located on the lower substrate, a peripheral circuit region located between the lower substrate and the upper substrate and including peripheral wiring, and a gap-filling insulating layer penetrating the upper substrate, a stacked structure located in a memory cell array region on the lower structure and extending into a connection region on the lower structure, wherein the stacked structure includes a gate region and an insulating region, wherein the gate region is located in the memory cell array region and extends into the connection region, and wherein the insulating region is located in the connection region; A vertical structure of a memory cell penetrates the gate region in the memory cell array region; and a covering insulating layer, located on the stacked structure, The stacked structure includes a plurality of first layers and a plurality of second layers alternately stacked on the lower structure. wherein the plurality of first layers include an interlayer insulating layer, The plurality of second layers include a plurality of gate layers located in the gate region, a plurality of mold layers located in the insulating region, a plurality of gate pads extending from the gate layers, and a plurality of mold pads extending from at least some of the mold layers. wherein the plurality of mold pads include a plurality of middle mold pads, wherein the plurality of intermediate mold pads include a plurality of first intermediate mold pads and a second intermediate mold pad located between pairs of the first intermediate mold pads in the plurality of first intermediate mold pads; wherein the plurality of first intermediate mold pads each have a first length in a first direction, wherein the second middle mold pad has a second length in the first direction that is greater than the first length, wherein the first direction extends from the memory cell array region to the connection region, and wherein at least one of the plurality of first intermediate mold pads has a first thickness, and The central area of ​​the second intermediate mold pad includes an insulating material layer having a second thickness less than the first thickness, or the central area of ​​the second intermediate mold pad includes the cover insulating layer.

16. The semiconductor device according to claim 15, wherein The second intermediate mold pad and at least one first intermediate mold pad of the plurality of first intermediate mold pads each include a mold pad portion and an insulating protrusion portion located on the mold pad portion, and The central area of ​​the second middle mold pad located between the first portion and the second portion of the second middle mold pad does not include the insulating protrusion.

17. The semiconductor device according to claim 16, wherein The first portion and the second portion of the second intermediate mold pad include the mold pad portion and the insulating protrusion portion.

18. The semiconductor device according to claim 16, in, The plurality of gate pads include a plurality of intermediate gate pads, The plurality of intermediate gate pads include a plurality of first intermediate gate pads and a second intermediate gate pad located between pairs of the first intermediate gate pads in the plurality of first intermediate gate pads. The plurality of first intermediate gate pads each have the first length in the first direction, wherein the second intermediate gate pad has the second length in the first direction, In which, a first intermediate gate pad among the multiple first intermediate gate pads that is adjacent to the at least one first intermediate molded pad including the molded pad portion and the insulating protrusion portion is in contact with the upper surface of the molded pad portion of the at least one first intermediate molded pad and is in contact with the side surface of the insulating protrusion portion.

19. The semiconductor device according to claim 15, further comprising: a plurality of peripheral contact structures penetrating the insulating region and the gap-filling insulating layer and electrically connected to peripheral contact pads of the peripheral wiring; a plurality of gate contact structures electrically connected to the plurality of gate pads; as well as a plurality of gate connection wirings located on the plurality of peripheral contact structures and the plurality of gate contact structures, One of the plurality of gate connection wirings is electrically connected to one of the plurality of peripheral contact structures and one of the plurality of gate contact structures.

20. The semiconductor device according to claim 19, wherein At least one peripheral contact structure of the plurality of peripheral contact structures penetrates a portion of the central region of the second intermediate mold pad.

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