A hardware reuse method and system for transformer integrated tester

Abstract

The present invention discloses a hardware reuse method and system for an integrated transformer tester. The system operates on all circuit boards within the tester and includes a hardware layer, an abstract function layer, a connection layer, a control layer, a task scheduling layer, and a main control layer. Given that an integrated transformer tester includes a large number of analog ICs, digital ICs, and peripheral circuits, the performance of these ICs is determined by these peripheral circuits. The present invention reuses the peripheral circuits of these analog and digital ICs, achieving a single chip with multiple functions and multiple application scenarios. Circuit switching is primarily controlled and coordinated using digital switches.

Description

Technical Field

[0001] The present invention relates to the technical field of transformer testing, and in particular to a hardware reuse method and system applied to an integrated transformer tester. Background Art

[0002] Most existing transformer testers are split-body devices. An integrated transformer tester contains numerous analog and digital ICs, as well as peripheral circuits. These peripheral circuits determine the performance of these ICs. This inconvenience necessitates instrument changes and constant wiring during testing. This is primarily due to the extensive nature of transformer testing, which requires a wide range of hardware. Traditional transformer testers are built with separate hardware components, resulting in significant hardware redundancy. A hardware reuse system is needed to streamline and reuse existing hardware, reducing the complexity of multiple instruments into a single instrument. This allows for hardware reuse, minimizes test size, and reduces the number of test steps.

[0003] Furthermore, there are currently no hardware programming systems. Most systems program digital ICs or simulate hardware circuits through logic gates to achieve hardware reuse. A hardware abstraction system is needed to abstract existing hardware circuits and achieve reuse. Summary of the Invention

[0004] One of the technical problems to be solved by this invention is to address the problem of hardware redundancy in traditional transformer testers, which are all separate hardware. This invention provides a hardware reuse method for integrated transformer testers. This hardware reuse system for integrated transformer testers primarily reuses the peripheral circuits of the analog and digital integrated circuits of the integrated transformer tester, achieving a single chip with multiple functions and multiple application scenarios. The switching of these circuits is primarily controlled by digital switches.

[0005] The second technical problem to be solved by this invention is to provide a hardware reuse system for integrated transformer testers, addressing the problem of traditional transformer testers, which have single-chip hardware and thus suffer from a high degree of hardware redundancy. This hardware reuse system for integrated transformer testers primarily reuses the peripheral circuits of the analog and digital ICs of the integrated transformer tester, thereby achieving a single chip with multiple functions and multiple application scenarios. The switching of these circuits is primarily controlled by digital switches.

[0006] As a first aspect of the present invention, a hardware multiplexing method for an integrated transformer tester is characterized in that: during a measurement process, the main control module first sends a measurement start instruction for measurement content A to the task switching module. After receiving the instruction, the task switching module obtains the corresponding task information of task A from the task database and transmits the encoded method to the hardware connection codec system in the control layer;

[0007] After receiving the connection code, the hardware connection codec system decodes the code to obtain specific hardware connection information, and transmits the specific hardware connection information to the hardware connection verification system for connection verification;

[0008] After receiving the connection information, the hardware connection verification system verifies whether there are any errors or omissions in the connection method by querying the specific hardware information and hardware connection rules in the hardware connection verification database; after passing the verification, the hardware connection encoding and decoding system passes the decoded specific hardware connection information through the connection layer, and schedules the abstract function layer to complete the setting of the peripheral circuit abstract class - that is, the peripheral circuit setting of the physical hardware, and the connection of the functional module abstract class. At this point, the hardware layer has also completed the connection and started to execute the hardware task.

[0009] As a second aspect of the present invention, a hardware reuse system for an integrated transformer tester runs on all circuit boards in the integrated transformer tester, including:

[0010] The hardware layer is composed of hardware IC modules and digital IC modules and their peripheral circuits, which constitute the hardware modules, ADC modules and DAC modules in the hardware multiplexing system to connect the digital control system and functional hardware system in the hardware multiplexing system;

[0011] An abstract function layer, the abstract function layer is composed of hardware abstract classes. Each hardware abstract class represents a hardware circuit model. The hardware abstract class abstracts the modules composed of hardware IC modules, digital IC modules and their peripheral circuits in the hardware layer.

[0012] A connection layer, which is composed of a hardware connection system and a communication system. The hardware connection system switches the connection sequence and connection structure of the hardware circuits in the hardware layer, and the communication system is responsible for the communication work of the hardware multiplexing system;

[0013] The control layer is composed of a hardware connection encoding and decoding system, a hardware connection verification system, and a hardware connection database, wherein:

[0014] The hardware connection encoding and decoding system is responsible for encoding the hardware IC module abstracted by the hardware abstract class in the abstract function layer to store it in the hardware connection verification database for identification, and at the same time decodes the task issued by the upper task scheduling layer to obtain the hardware connection content, and sends the decoded content to the hardware connection verification system for verification. After passing the verification, it is sent to the hardware connection system to connect the hardware device;

[0015] The hardware connection verification system compares the hardware connection content decoded by the hardware connection codec system with the hardware entity information in the hardware connection verification database and the hardware connection rules recorded in the hardware connection verification database to prevent hardware connection errors or misconnections that may cause circuit unusability or even safety accidents.

[0016] The hardware connection verification database stores the hardware entity information and coding information of all hardware IC modules involved in the hardware multiplexing system, as well as the connection rules of the hardware ICs involved in the hardware multiplexing system, for providing to the hardware connection verification system for query; the hardware connection verification database has two input ports and one output port, the two input ports are respectively connected to the hardware connection codec system and the main control layer, the hardware connection codec system provides the hardware connection verification database with the coding information of the abstracted hardware IC device, and the main control layer provides the hardware IC module entity hardware information and hardware connection rules to the hardware connection verification database, and the output port is connected to the hardware connection verification system;

[0017] The task scheduling layer is composed of a task registration module, a task switching module and a task database; the task registration module is used to register the test tasks running in the transformer integrated tester. After receiving the registered task, the task registration module formats the task information and outputs it to the task database for storage; after receiving the task switching instruction or task start instruction of the main control layer, the task switching module reads the corresponding task information from the task database and sends it to the hardware connection codec system to drive the hardware multiplexing system to execute the corresponding hardware task. At the same time, the task switching module is also responsible for receiving the test results calculated by the subordinate calculation IC and uploading them to the main control layer;

[0018] The main control layer includes a main control module, which is responsible for the user interface. The user registers the corresponding task information and the corresponding hardware device entity information through the main control module and obtains the final measurement results through the main control module.

[0019] In a preferred embodiment of the present invention, the hardware abstract class is divided into a functional module abstract class and a peripheral circuit abstract class; the functional module abstract class represents the abstraction of a hardware circuit module, the functional module abstract class is functional, and after being abstracted into a function, it exists as a functional function module. After the functional module abstract class is called, it can directly process the signal and produce corresponding processing effects; the peripheral circuit abstract class is mainly a subsidiary substructure of the functional module abstract class, which mainly abstracts the peripheral circuit of a functional module and adjusts its peripheral circuit structure to have different performance and parameters to meet the needs of the corresponding instrument functions.

[0020] In a preferred embodiment of the present invention, the functional module abstract class includes the peripheral circuit abstract class, and the peripheral circuit abstract class exists as a subclass of the functional module abstract class; in the actual calling process, it is necessary to first call the peripheral circuit abstract class to set the performance parameters of the functional module, and then call the functional module abstract class to achieve the corresponding effect.

[0021] In a preferred embodiment of the present invention, after the abstraction is completed, the peripheral circuit abstract class exists as an implicit structure. The user only needs to call the functional module abstract class and set relevant parameters through the interface of the functional module abstract class. Then, the user can call the corresponding internal function in the functional module abstract class, that is, the corresponding peripheral circuit abstract class to complete the corresponding module parameters and performance settings.

[0022] In a preferred embodiment of the present invention, the hardware connection system is mainly composed of digitally controlled switches.

[0023] Due to the adoption of the above technical solution, given that an integrated transformer tester includes a large number of analog ICs, digital ICs, and peripheral circuits, the performance of which is determined by these peripheral circuits. This invention reuses the peripheral circuits of these analog and digital ICs, thereby achieving a single chip with multiple functions and multiple application scenarios. The switching of these circuits is primarily controlled by digital switches. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The figure is a schematic diagram of the architecture of the hardware multiplexing system applied to the transformer integrated tester according to the present invention.

[0025] Figure 2 The figure is a schematic diagram of the architecture of the hardware abstract class in the hardware reuse system of the transformer integrated tester applied in the present invention. DETAILED DESCRIPTION

[0026] The present invention is further described below with reference to the accompanying drawings and specific embodiments.

[0027] Given that an integrated transformer tester includes numerous analog ICs, digital ICs, and peripheral circuits, the performance of these ICs is determined by these peripheral circuits. The hardware reuse system for this integrated transformer tester, as described in the present invention, primarily reuses the peripheral circuits of these analog and digital ICs, achieving a single chip with multiple functions and multiple application scenarios. Circuit switching is primarily controlled and coordinated using digital switches.

[0028] The hardware multiplexing system applied to the transformer integrated tester of the present invention runs on all circuit boards in the system.

[0029] See also Figure 1 The hardware reuse system for the transformer integrated tester shown in the figure is divided into six layers, namely hardware layer 10, abstract function layer 20, connection layer 30, control layer 40, task scheduling layer 50 and main control layer 60.

[0030] The hardware layer 10 is composed of the hardware IC module 11 and the digital IC module 12 and their peripheral circuits in this hardware multiplexing system, which constitute the hardware module, ADC module and DAC module in this hardware multiplexing system to connect the digital control system and functional hardware system in this hardware multiplexing system.

[0031] The abstract function layer 20 mainly abstracts the hardware IC module 11, the digital IC module 12 and the modules they constitute in the hardware layer 10. This layer is composed of hardware abstract classes 21, each of which represents a hardware circuit model.

[0032] See also Figure 2 The hardware abstract class 21 is mainly divided into the functional module abstract class 21a and the peripheral circuit abstract class 21b. Among them, the functional module abstract class 21a represents the abstraction of a hardware circuit module, such as the abstraction of ADC, DAC, amplifier circuit, attenuator circuit, etc. The functional module abstract class 21a is functional. After being abstracted into a function, it exists as a functional function module. After the functional module abstract class 21a is called, it can directly process the signal and produce corresponding processing effects.

[0033] The peripheral circuit abstract class 21b is mainly a subsidiary substructure of the functional module abstract class 21a. It mainly abstracts the peripheral circuit of a functional module and adjusts its peripheral circuit structure to have different performance and parameters to meet the needs of the corresponding instrument functions.

[0034] In practice, the functional module abstract class 21a includes the peripheral circuit abstract class 21b, which exists as a subclass of the functional module abstract class 21a. In practice, the peripheral circuit abstract class 21b must be called first to set the performance parameters of the functional module, and then the functional module abstract class 21a must be called to achieve the desired effect.

[0035] After the abstraction is completed, the peripheral circuit abstract class 21b exists as an implicit structure. The user only needs to call the functional module abstract class 21a and set relevant parameters through the interface of the peripheral circuit abstract class 21b. Then, the user can call the corresponding internal function in the functional module abstract class 21a, that is, the corresponding peripheral circuit abstract class 21b to complete the corresponding module parameters and performance settings.

[0036] The connection layer 30 is mainly composed of a hardware connection system 31 and a communication system 32. The hardware connection system 31 is mainly composed of digital switches, and its main function is to switch the connection sequence of the hardware circuit and the connection structure. In the peripheral circuit abstract class 21b, specifically in the embodiment, it is the resistor structure (such as T-type structure, voltage divider structure, etc.), the capacitor structure, the inductor structure, etc., as well as the programming switching of the connection method of the above-mentioned various devices. In the functional module abstract class 21a, it is mainly the switching of the connection sequence of the functional modules. Specifically in the embodiment, for example, after the amplifier, the connection is either an ADC, a DAC, an attenuator, or a computing chip, etc.

[0037] The communication system 32 is mainly responsible for the communication work of the entire system.

[0038] The control layer 40 is mainly composed of a hardware connection encoding and decoding system 40, a hardware connection verification system 42, and a hardware connection database 43.

[0039] The hardware connection encoding and decoding system 41 is mainly responsible for encoding the hardware IC device abstracted by the hardware abstract class 21 and storing it in the hardware connection verification database 43 for identification. At the same time, it decodes the tasks issued by the upper task scheduling layer 50 to obtain the hardware connection content, and sends the decoded content to the hardware connection verification system 42 for verification. After verification, it is sent to the hardware connection system 31 to connect the hardware device.

[0040] The hardware connection verification system 42 mainly compares the hardware connection content decoded by the hardware connection encoding and decoding system 41 with the hardware entity information in the hardware connection verification database 43 and the hardware connection rules recorded in the hardware connection verification database 43 to prevent errors or omissions in the hardware connection, or incorrect connections, which may cause the circuit to be unusable or even cause safety accidents.

[0041] The hardware connection verification database 43 stores the physical hardware information and encoding information of all hardware ICs involved in this disclosure, as well as the connection rules for the hardware ICs involved in this hardware reuse system. This database is primarily used to provide information to the hardware connection verification system 42 for query. The database 43 has only two input ports and one output port, with the two input ports connected to the hardware connection codec system 41 and the main control layer 60, respectively. The hardware connection codec system 41 provides the database 43 with the encoding information of the abstracted hardware IC devices. The main control layer 60 primarily provides the database 43 with the physical hardware information and hardware connection rules of the hardware IC devices. The output port is connected to the hardware connection verification system 42.

[0042] The task scheduling layer 50 is mainly composed of a task registration module 51 , a task switching module 52 and a task database 53 .

[0043] The task registration module 51 is primarily used to register test tasks running in the transformer integrated tester. The registration content includes the task content, task output interface and specifications, hardware connection methods, etc. After receiving a registered task, the task registration module 51 formats the task information and outputs it to the task database 53 for storage.

[0044] After receiving a task switch instruction or task start instruction from the main control layer 60, the task switching module 52 reads the corresponding task information, particularly the hardware connection method, from the task database 53 and sends it to the hardware connection codec system 41 to drive the hardware multiplexing system to execute the corresponding hardware task. The task switching module 52 is also responsible for receiving test results calculated by the subordinate computing ICs and uploading them to the main control layer 60.

[0045] The main control layer 60 includes a main control module 61, which is the core module of this hardware reuse system and is typically located on the main control board. This module primarily handles the user interface. Users register task information and hardware device entity information through this module. The final measurement results are also obtained through this module.

[0046] In a specific measurement process, it is assumed that the measurement content is A, B, and C. In a measurement process, the main control module 61 first sends a measurement start instruction for measurement content A to the task switching module 52. After receiving the instruction, the task switching module 52 obtains the corresponding task information of task A (especially the hardware connection method) from the task database 53, and transmits the encoded method to the hardware connection codec system 41 in the control layer 40.

[0047] After receiving the connection code, the hardware connection codec system 41 decodes the code to obtain specific hardware connection information, such as the connection mode of hardware a(x,y,z)-b(x,yz,z)-c(x,y,z), where a,b,c represent the function module abstract class 21a, and x,y,z represent the parameters and performance of the function module abstract class 21a, and passes the information to the hardware connection verification system 42 for connection verification.

[0048] After receiving the connection information, the hardware connection verification system 42 verifies the connection scheme for errors and omissions by querying the hardware connection verification database 43 for specific hardware information and hardware connection rules. Once verified, the hardware connection codec system 41 passes the decoded hardware connection information through the connection layer 30, dispatching the abstract function layer 20 to complete the configuration of the peripheral circuit abstract class 21b—that is, the peripheral circuit configuration of the physical hardware—and the connection of the functional module abstract class 21a. At this point, the hardware layer 10 has completed the connection and begins executing the hardware task.

Claims

1. A hardware reuse method for a transformer integrated tester, characterized by During a measurement, the main control module first sends a measurement start instruction for measurement content A to the task switching module. After receiving the instruction, the task switching module obtains the corresponding task information of task A from the task database and transmits the hardware IC device abstracted by the encoded hardware abstract class to the hardware connection codec system in the control layer. After receiving the connection code in the hardware IC device abstracted by the encoded hardware abstract class, the hardware connection encoding and decoding system decodes the connection code to obtain specific hardware connection information, and transmits the specific hardware connection information to the hardware connection verification system for connection verification; After receiving the connection information, the hardware connection verification system verifies whether there are any errors or omissions in the specific hardware connection information by querying the specific hardware information and hardware connection rules in the hardware connection verification database; after passing the verification, the hardware connection encoding and decoding system passes the decoded specific hardware connection information through the connection layer and the scheduling abstract function layer to complete the setting of the peripheral circuit abstract class, that is, the peripheral circuit setting of the physical hardware, and the connection of the functional module abstract class. At this point, the hardware layer has also completed the connection and started to execute the hardware task.

2. A hardware reuse system for a transformer integrated tester, running on all circuit boards in the transformer integrated tester, characterized in that: include: The hardware layer is composed of hardware IC modules and digital IC modules and their peripheral circuits, which constitute the hardware modules, ADC modules and DAC modules in the hardware multiplexing system to connect the digital control system and functional hardware system in the hardware multiplexing system; An abstract function layer, the abstract function layer is composed of hardware abstract classes. Each hardware abstract class represents a hardware circuit model. The hardware abstract class abstracts the modules composed of hardware IC modules, digital IC modules and their peripheral circuits in the hardware layer. A connection layer, which is composed of a hardware connection system and a communication system. The hardware connection system switches the connection sequence and connection structure of the hardware circuits in the hardware layer, and the communication system is responsible for the communication work of the hardware multiplexing system; The control layer is composed of a hardware connection encoding and decoding system, a hardware connection verification system, and a hardware connection verification database, wherein: The hardware connection encoding and decoding system is responsible for encoding the hardware IC module abstracted by the hardware abstract class in the abstract function layer to store it in the hardware connection verification database for identification, and at the same time decodes the task issued by the upper task scheduling layer to obtain the hardware connection content, and sends the decoded content to the hardware connection verification system for verification. After passing the verification, it is sent to the hardware connection system to connect the hardware device; The hardware connection verification system compares the hardware connection content decoded by the hardware connection codec system with the hardware entity information in the hardware connection verification database and the hardware connection rules recorded in the hardware connection verification database to prevent hardware connection errors or misconnections that may cause circuit unusability or even safety accidents. The hardware connection verification database stores the hardware entity information and coding information of all hardware IC modules involved in the hardware multiplexing system, as well as the connection rules of the hardware ICs involved in the hardware multiplexing system, for providing to the hardware connection verification system for query; the hardware connection verification database has two input ports and one output port, the two input ports are respectively connected to the hardware connection codec system and the main control layer, the hardware connection codec system provides the hardware connection verification database with the coding information of the abstracted hardware IC device, and the main control layer provides the hardware IC module entity hardware information and hardware connection rules to the hardware connection verification database, and the output port is connected to the hardware connection verification system; The task scheduling layer is composed of a task registration module, a task switching module and a task database; the task registration module is used to register the test tasks running in the transformer integrated tester. After receiving the registered task, the task registration module formats the task information and outputs it to the task database for storage; after receiving the task switching instruction or task start instruction of the main control layer, the task switching module reads the corresponding task information from the task database and sends it to the hardware connection codec system to drive the hardware multiplexing system to execute the corresponding hardware task. At the same time, the task switching module is also responsible for receiving the test results calculated by the subordinate calculation IC and uploading them to the main control layer; The main control layer includes a main control module, which is responsible for the user interface. The user registers the corresponding task information and the corresponding hardware device entity information through the main control module and obtains the final measurement results through the main control module.

3. A hardware multiplexing system for a transformer integrated tester according to claim 2, characterized in that: The hardware abstract class is divided into a functional module abstract class and a peripheral circuit abstract class; The functional module abstract class represents an abstraction of a hardware circuit module. The functional module abstract class is functional and exists as a functional function module after being abstracted into a function. After being called, the functional module abstract class can directly process the signal and produce the corresponding processing effect; the peripheral circuit abstract class is a subsidiary substructure of the functional module abstract class, which abstracts the peripheral circuit of a functional module and adjusts its peripheral circuit structure to have different performance and parameters to meet the needs of the corresponding instrument function.

4. A hardware multiplexing system for a transformer integrated tester according to claim 3, characterized in that: The functional module abstract class includes the peripheral circuit abstract class, and the peripheral circuit abstract class exists as a subclass of the functional module abstract class. In the actual calling process, it is necessary to first call the peripheral circuit abstract class to set the performance parameters of the functional module, and then call the functional module abstract class to achieve the corresponding effect.

5. A hardware multiplexing system for a transformer integrated tester according to claim 4, characterized in that: After the abstraction is completed, the peripheral circuit abstract class exists as an implicit structure. The user only needs to call the functional module abstract class and set relevant parameters through the interface of the functional module abstract class. Then, the corresponding internal function can be called in the functional module abstract class, that is, the corresponding peripheral circuit abstract class to complete the corresponding module parameters and performance settings.

6. A hardware multiplexing system for a transformer integrated tester according to claim 2, characterized in that: The hardware connection system is composed of digitally controlled switches.

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