Array substrate, display panel and display device

Abstract

The present application discloses an array substrate, a display panel and a display device, which are used to avoid short circuit between a gate line and a common electrode lead caused by electrostatic breakdown of a gate insulating layer. The array substrate provided in the embodiment of the present application includes: a gate line and a data line, and a pixel unit, wherein the gate line and the data line are arranged between at least some adjacent pixel units; and further includes: a common electrode lead, and a common electrode layer; the common electrode lead is arranged in the same layer as the data line and extends in the same direction and is located between at least some adjacent pixel units; the common electrode layer and the common electrode lead are insulated by an insulating layer and connected by a via hole on the insulating layer; the via hole is located in the area where the gate line and the common electrode lead intersect; the gate line includes a straight line portion extending in a first direction away from the via hole; the gate line also includes a curved portion surrounded by a curve along the edge of the via hole near the via hole, and the curved portion is a evacuation portion for evading the via hole.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Static electricity will accumulate in display panels due to various reasons during manufacturing and use. When the static electricity accumulates to a certain extent, it will be released at the place where the anti-static ability of the panel is relatively weak, causing a series of display abnormalities. The current mainstream anti-static measure is to design an electrostatic discharge (ESD) unit around the panel. The ESD unit is grounded to conduct static electricity. However, before the ESD unit is formed, for example, static electricity accumulated during the preparation of the array substrate due to substrate transportation, thin film deposition, etching, etc. cannot be conducted. When it accumulates to a certain extent, it will be released at the via position with relatively weak anti-static ability, causing static electricity breakdown, causing a series of short circuit defects, and resulting in yield loss. Summary of the invention

[0003] The embodiments of the present application provide an array substrate, a display panel and a display device, which are used to prevent the gate line and the common electrode lead from being short-circuited due to electrostatic breakdown of the gate insulation layer.

[0004] An array substrate provided in an embodiment of the present application includes: a plurality of gate lines and a plurality of data lines arranged crosswise, and a plurality of pixel units, wherein the gate lines and the data lines are arranged between at least some adjacent pixel units;

[0005] The array substrate further comprises: a common electrode lead, and a common electrode layer located on the common electrode lead;

[0006] The common electrode lead is arranged in the same layer as the data line, extends in the same direction, and is located between at least part of the adjacent pixel units;

[0007] The common electrode layer and the common electrode lead are insulated by an insulating layer and connected through a via hole on the insulating layer; the via hole is located in a region where the gate line and the common electrode lead intersect;

[0008] The gate line includes a straight line portion extending along a first direction away from the via hole; the gate line also includes a curved portion close to the via hole and surrounding along an edge of the via hole, and the curved portion is a avoiding portion avoiding the via hole.

[0009] In some embodiments, the orthographic projection of the via hole on the base substrate is circular or elliptical, and the orthographic projection of the avoidance portion on the base substrate is arc-shaped.

[0010] In some embodiments, the gate line includes: a first gate line, and a second gate line;

[0011] The first gate line is located above each row of the pixel units extending along the first direction, and the second gate line is located below each row of the pixel units extending along the first direction;

[0012] The first gate line and the second gate line have the same extending direction and are between two adjacent rows of pixel units;

[0013] The first gate line includes a first avoidance portion connected to the straight line portion, and the second gate line includes a second avoidance portion connected to the straight line portion;

[0014] The first avoidance portion and the second avoidance portion respectively surround two opposite edges of the via hole;

[0015] The plurality of pixel units include: first pixel units and second pixel units arranged alternately; the first pixel units include first thin film transistors, and the second pixel units include second thin film transistors;

[0016] The first gate line is electrically connected to the first thin film transistor, and the second gate line is electrically connected to the second thin film transistor.

[0017] In some embodiments, the array substrate further comprises: a base substrate; the first thin film transistor and the second thin film transistor comprise: a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode sequentially arranged on the base substrate;

[0018] The gate line is arranged in the same layer as the gate electrode, the common electrode lead is arranged in the same layer as the source electrode and the drain electrode, and the insulating layer includes a passivation layer located on the source electrode and the drain electrode.

[0019] In some embodiments, each of the common electrode leads comprises: a plurality of connection portions located at the region where the gate lines and the common electrode leads intersect, and a first connection lead extending along the second direction and connecting the connection portions;

[0020] The common electrode layer is connected to the connecting portion through the via hole;

[0021] In the first direction, the width of the connecting portion is greater than the width of the first connecting lead;

[0022] The orthographic projection of the via hole on the base substrate falls within the orthographic projection of the connecting portion on the base substrate, and in the first direction and the second direction, the width of the via hole is smaller than the width of the connecting portion.

[0023] In some embodiments, an orthographic projection of the avoiding portion on the base substrate overlaps with an orthographic projection of the connecting portion on the base substrate.

[0024] In some embodiments, in the first direction, a width of the connecting portion in at least a portion of the area is greater than a width of the avoiding portion.

[0025] In some embodiments, a distance between an orthographic projection of the avoidance portion on the base substrate and an orthographic projection of the via hole on the base substrate is greater than 0 and less than or equal to 2 micrometers.

[0026] An embodiment of the present application provides a display panel, which includes: an array substrate provided in the embodiment of the present application, an opposite substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the array substrate.

[0027] An embodiment of the present application provides a display device, which includes the display panel provided by the embodiment of the present application.

[0028] In the array substrate, display panel and display device provided in the embodiments of the present application, the gate line includes a avoidance portion for avoiding the area where the via hole is located, that is, the avoidance portion has an orthographic projection on the base substrate located outside the orthographic projection area of ​​the via hole on the base substrate, and the avoidance portion bypasses the area corresponding to the via hole. Therefore, in the area corresponding to the via hole, the distance between the avoidance portion and the common electrode lead is increased. Even after the process of forming the via hole, charge accumulation is generated at the common electrode lead exposed by the via hole. Compared with the related art, the electric field strength between the gate line and the common electrode lead is reduced, and the gate insulating layer will not be broken down, thereby avoiding the short circuit between the gate line and the common electrode lead caused by electrostatic breakdown of the gate insulating layer, thereby avoiding poor display. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A schematic diagram of the structure of an array substrate of the related art;

[0031] Figure 2 A schematic diagram of the structure of an array substrate provided in an embodiment of the present application;

[0032] Figure 3 The embodiment of the present application provides Figure 2 Cross-sectional view of AA';

[0033] Figure 4 Provided in the embodiments of this application Figure 2 A top view of the grid lines in the middle area B;

[0034] Figure 5 A top view of the structure of another array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. And in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in the field without creative work belong to the scope of protection of this application.

[0036] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. "First", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and other similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0037] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present application. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0038] In the related art, the cross-sectional view of the via hole of the array substrate is as follows: Figure 1 As shown, the passivation layer 5 has a via hole 7 exposing the common electrode lead 4 in the intersection area of ​​the gate line 2 and the common electrode lead 4, and the common electrode layer 6 is electrically connected to the common electrode lead 4 through the via hole 7. Since the via hole 7 is overlapped above the gate line 2, a step edge between the gate line 2 and the common electrode lead 4 is formed in the area of ​​the via hole 7, and the gate line 2 and the common electrode lead 4 are closest at the tip of the step, and the distance between the gate line 2 and the common electrode lead 4 at the tip of the step is b. A gate insulating layer 3 is included between the gate line 2 and the common electrode lead 4, and the thickness of the gate insulating layer 3 is a, the slope angle of the gate line 2 is θ, the thickness of the gate line 2 is c, and the distance between the gate line 2 and the common electrode lead 4 at the tip of the step is b=(ac) / sinθ.

[0039] When etching to form a via, the gas continuously etches the passivation layer film at the via until the common electrode lead is exposed. The gas ionizes the common electrode lead at the via to generate charge accumulation. The gate line and the common electrode lead form a capacitor. When there is a voltage difference between the gate line and the common electrode lead, an electric field is formed between the two. According to the electric field strength formula E=U / d, U is the voltage difference between the two electrodes, d is the distance between the two electrodes, and E is the electric field strength. The smaller the distance d between the two electrodes, the greater the electric field strength E. At the same time, according to the tip discharge principle, under the action of a strong electric field, the equipotential density is large where the surface curvature of the object is large. The higher the surface charge density, the greater the electric field strength. The covalent bonds in the insulating layer are destroyed in the strong electric field, resulting in ionization. When the number of ionizations reaches a certain level, the insulating layer is broken down, causing a short circuit between the gate line and the common electrode lead.

[0040] Based on the above problems existing in the related art, the present application embodiment provides an array substrate, such as Figure 2 , Figure 3 , Figure 4 As shown, the array substrate includes: a plurality of gate lines 2 and a plurality of data lines 23 arranged crosswise, and a plurality of pixel units 18, wherein the gate lines 2 and the data lines 23 are arranged between at least some of the adjacent pixel units 18;

[0041] The array substrate further comprises: a common electrode lead 4, and a common electrode layer 6 located on the common electrode lead 4;

[0042] The common electrode lead 4 is disposed in the same layer as the data line 23 and extends in the same direction and is located between at least a portion of the adjacent pixel units 18;

[0043] The common electrode layer 6 is insulated from the common electrode lead 4 by an insulating layer 25 and connected via a via hole 7 on the insulating layer 25; the via hole 7 is located in a region B where the gate line 2 and the common electrode lead 4 intersect;

[0044] The gate line 2 includes a straight line portion 11 extending along the first direction X away from the via hole 7 ; the gate line 2 also includes a curved portion close to the via hole 7 and surrounding the edge of the via hole 7 , and the curved portion is a avoiding portion 10 avoiding the via hole.

[0045] It should be noted that Figure 3 for Figure 2 The cross-sectional view along AA', Figure 4 for Figure 2 Top view of the grid lines in area B. Figure 2 The common electrode layer is not shown in the figure. In a specific implementation, a common voltage signal can be provided to the common electrode layer through a common electrode lead.

[0046] In the array substrate provided in the embodiment of the present application, the gate line includes a avoidance portion for avoiding the area where the via hole is located, that is, the avoidance portion has an orthographic projection on the base substrate located outside the orthographic projection area of ​​the via hole on the base substrate, and the avoidance portion bypasses the area corresponding to the via hole. Therefore, in the area corresponding to the via hole, the distance between the avoidance portion and the common electrode lead is increased. Even after the process of forming the via hole, charge accumulation is generated at the common electrode lead exposed by the via hole. Compared with the related art, the electric field strength between the gate line and the common electrode lead is reduced, which will not cause the gate insulating layer to be broken down, thereby avoiding the short circuit between the gate line and the common electrode lead caused by electrostatic breakdown of the gate insulating layer, thereby avoiding poor display.

[0047] In some embodiments, Figure 2 As shown, the common electrode lead 4 extends along the second direction Y; Figure 2 As shown, the first direction X and the second direction Y are perpendicular.

[0048] In some embodiments, Figure 4 As shown, the shape of the orthographic projection of the via hole 7 on the base substrate is circular or elliptical, and the shape of the orthographic projection of the avoidance portion 10 on the base substrate is arc-shaped.

[0049] In the array substrate provided by the embodiment of the present application, the shape of the orthographic projection of the via hole on the base substrate is circular, and the shape of the orthographic projection of the avoidance portion on the base substrate is arc-shaped. Therefore, without changing the setting position of the straight portion of the gate line, the space in the intersection area of ​​the gate line and the common electrode lead can be reasonably utilized to achieve the avoidance portion avoiding the area corresponding to the via hole, avoiding increasing the non-display area between the pixel units, and ensuring the aperture ratio of the display product.

[0050] In some embodiments, Figure 2 , Figure 3 , Figure 4 As shown, the gate line 2 includes: a first gate line 12 and a second gate line 13;

[0051] The first gate line 12 is located above each row of pixel units 18, and the second gate line 13 is located below each row of pixel units 18;

[0052] The first gate line 12 and the second gate line 13 have the same extending direction and are between two adjacent rows of pixel units 18;

[0053] The first gate line 12 includes a first avoidance portion 14 connected to the straight line portion 11, and the second gate line 13 includes a second avoidance portion 15 connected to the straight line portion 11;

[0054] The first avoidance portion 14 and the second avoidance portion 15 respectively surround two opposite edges of the via hole 7;

[0055] The plurality of pixel units 18 include: first pixel units 19 and second pixel units 20 arranged alternately;

[0056] The first pixel unit 19 further includes a first thin film transistor 21, and the second pixel unit 19 further includes a second thin film transistor 22;

[0057] The first gate line 12 is electrically connected to the first thin film transistor 21 , and the second gate line 13 is electrically connected to the second thin film transistor 22 .

[0058] The array substrate provided in the embodiment of the present application adopts a dual gate design. In specific implementation, Figure 2 As shown, the first gate line 12 is used to drive the first pixel unit 19, and the second gate line 13 is used to drive the second pixel unit 20. The first pixel unit 19 and the second pixel unit 20 adjacent to each other in the first direction X are electrically connected to the same data line 23, so that the number of data lines can be reduced, and the number of driving chips can be reduced, thereby saving the cost of the driving chip.

[0059] The array substrate is divided into a display area and a peripheral area outside the display area. Figure 2 An example is given for explanation by taking the case where the via hole in the insulating layer that connects the common electrode layer and the common electrode lead is located in the display area.

[0060] In a specific implementation, the common electrode layer and the common electrode lead extend to the peripheral area, and the insulating layer in the peripheral area has a via hole that connects the common electrode layer and the common electrode lead, so that a common voltage signal can be provided to the common electrode layer through the common electrode lead. However, in order to ensure the uniformity of the common voltage signal of the common electrode layer, a via hole is also required to be provided in the display area to connect the common electrode layer and the common electrode lead.

[0061] In some embodiments, the array substrate provided by the embodiment of the present application is applied to liquid crystal display, and two layers of indium tin oxide (ITO) need to be sequentially arranged on the metal layer where the common electrode lead is located, and the two layers of ITO are respectively the common electrode layer and the pixel electrode layer. For the liquid crystal display product of the HADS mode, the second layer of ITO is used as the common electrode layer, so a via must be arranged to make the common electrode layer contact with the common electrode lead, so that a common voltage signal can be provided to the common electrode layer through the common electrode lead. Due to the use of the Dual Gate design, the common electrode lead is arranged in the same layer as the data line and the source and drain of the thin film transistor, and the gate line and the common electrode lead must overlap with each other. The area where the gate line and the common electrode lead overlap corresponds to the area where the black matrix of the opposite substrate is set, that is, the non-display area between the pixel units, so that the via connecting the common electrode layer and the common electrode lead is arranged in the area where the gate line and the common electrode lead overlap, so that the area between the pixel units can be reasonably utilized, avoiding increasing the area of ​​the non-display area between the pixel units, thereby avoiding the loss of the aperture ratio and contrast of the display product.

[0062] In some embodiments, Figure 2 , Figure 3 As shown, the array substrate further includes: a base substrate 1; a first thin film transistor 21 and a second thin film transistor 22 include: a gate G, a gate insulating layer 3, an active layer 24, a source S and a drain D sequentially arranged on the base substrate 1;

[0063] The gate line 2 is disposed in the same layer as the gate electrode G, the common electrode lead 4 is disposed in the same layer as the source electrode S and the drain electrode D, and the insulating layer 25 includes a passivation layer 5 located on the source electrode and the drain electrode.

[0064] That is, in the array substrate provided in the embodiment of the present application, the first thin film transistor and the second thin film transistor are of bottom gate structure. Of course, the first thin film transistor and the second thin film transistor may also be of top gate structure.

[0065] In specific implementation, Figure 2 As shown, the gate of the first thin film transistor 21 is electrically connected to the first gate line 12 , and the gate of the second thin film transistor 22 is electrically connected to the second gate line 13 .

[0066] In specific implementation, Figure 2 As shown, the data line 23 is electrically connected to the source electrodes S of the first thin film transistor 19 and the second thin film transistor 20 .

[0067] In a specific implementation, the pixel electrode is electrically connected to the drain electrode, and the pixel electrode overlaps with the common electrode.

[0068] In some embodiments, Figure 2As shown, two columns of pixel units 18 are included between two adjacent common electrode leads 4 .

[0069] In some embodiments, Figure 2 , Figure 3 As shown, each of the common electrode leads 4 includes: a plurality of connection portions 8 located at the intersection of the gate lines 2 and the common electrode leads 4, and a first connection lead 9 electrically connected to the connection portions 8;

[0070] The common electrode layer 6 is connected to the connecting portion 8 through the via hole 7;

[0071] In the first direction X, the width of the connecting portion 8 is greater than the width of the first connecting lead 9;

[0072] The orthographic projection of the via hole 7 on the base substrate 1 falls within the orthographic projection of the connecting portion 8 on the base substrate 1 , and in the first direction X and the second direction Y, the width of the via hole 7 is smaller than the width of the connecting portion 8 .

[0073] In the array substrate provided by the embodiment of the present application, the width of the via hole is smaller than the width of the connecting portion in the first direction and the second direction, thereby ensuring that the common electrode and the connecting portion are completely overlapped in the via hole and avoiding poor overlap between the common electrode and the connecting portion.

[0074] In some embodiments, the connection portion is formed integrally with the first connection lead.

[0075] In some embodiments, Figure 2 , Figure 3 As shown, the orthographic projection of the avoidance portion 10 on the base substrate 1 overlaps with the orthographic projection of the connection portion 8 on the base substrate 1 .

[0076] It should be noted that, in the array substrate provided in the embodiment of the present application, the orthographic projection of the avoidance portion on the base substrate overlaps with the orthographic projection of the connection portion on the base substrate, thereby making reasonable use of the space in the intersection area of ​​the gate line and the common electrode lead, avoiding increasing the non-display area and ensuring the aperture ratio of the display product.

[0077] In some embodiments, Figure 2 As shown, in the first direction X, the width of the connecting portion 8 in at least a partial area is greater than the width of the avoiding portion.

[0078] Of course, in some embodiments, it can also be as follows Figure 5 As shown, the orthographic projection of the avoidance portion 10 on the base substrate and the orthographic projection of the connection portion 8 on the base substrate do not overlap each other.

[0079] In specific implementation, Figure 2As shown, the pattern of the orthographic projection of the connection portion of the common electrode lead 4 on the substrate is an island shape. Of course, in specific implementation, the pattern of the connection portion can also be other shapes such as a circle or a rectangle, and this application does not limit this.

[0080] In some embodiments, Figure 3 As shown, the distance h between the orthographic projection of the avoidance portion 10 on the base substrate and the orthographic projection of the via hole 7 on the base substrate is greater than 0 and less than or equal to 2 micrometers.

[0081] In the array substrate provided by the embodiment of the present application, the distance between the orthographic projection of the avoidance portion on the base substrate and the orthographic projection of the via on the base substrate is greater than 0 and less than or equal to 2 microns, so that the interval between the orthographic projection of the via and the orthographic projection of the gate line can be ensured, and the distance between the edge of the via and the gate line can be further increased, thereby increasing the distance between the gate line and the common electrode lead in the area corresponding to the via, avoiding the gate insulation layer from being broken down, and avoiding the gate insulation layer from being electrostatically broken down and causing the gate line and the common electrode lead to short-circuit. At the same time, it can also avoid the size of the intersection area between the gate line and the common electrode lead being too large, avoid increasing the non-display area between the pixel units of the display product, and ensure the aperture ratio of the display product.

[0082] An embodiment of the present application further provides a display panel, which includes: an array substrate provided in the embodiment of the present application, an opposite substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the array substrate.

[0083] That is, the display panel provided in the embodiment of the present application is a liquid crystal display panel.

[0084] An embodiment of the present application provides a display device, which includes a display panel provided by an embodiment of the present application.

[0085] The display device provided in the embodiment of the present application is any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by a person skilled in the art, and will not be described in detail here, nor should they be used as a limitation to the present application. The implementation of the display device can refer to the embodiment of the array substrate described above, and the repeated parts will not be described in detail.

[0086] To summarize, in the array substrate, display panel and display device provided by the embodiments of the present application, the gate line includes a avoidance portion that avoids the area where the via is located, that is, the avoidance portion has an orthographic projection on the base substrate located outside the orthographic projection area of ​​the via on the base substrate, and the avoidance portion bypasses the area corresponding to the via. Therefore, in the area corresponding to the via, the distance between the avoidance portion and the common electrode lead is increased. Even after the process of forming the via, charge accumulation is generated at the common electrode lead exposed by the via. Compared with the related art, the electric field strength between the gate line and the common electrode lead is reduced, and the gate insulating layer will not be broken down, thereby avoiding the short circuit between the gate line and the common electrode lead caused by electrostatic breakdown of the gate insulating layer, thereby avoiding poor display.

[0087] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An array substrate, characterized in that: The array substrate comprises: a plurality of gate lines and a plurality of data lines arranged in a cross manner, and a plurality of pixel units, wherein the gate lines and the data lines are arranged between at least some adjacent pixel units; The array substrate further comprises: a common electrode lead, and a common electrode layer located on the common electrode lead; The common electrode lead is arranged in the same layer as the data line, extends in the same direction, and is located between at least part of the adjacent pixel units; The common electrode layer and the common electrode lead are insulated by an insulating layer and connected through a via hole on the insulating layer; the via hole is located in a region where the gate line and the common electrode lead intersect; The gate line includes a straight line portion extending along a first direction away from the via hole; the gate line also includes a curved portion close to the via hole and surrounding the edge of the via hole, the curved portion being a avoiding portion avoiding the via hole; The array substrate further comprises: a base substrate; the common electrode lead extends along a second direction; and the first direction is perpendicular to the second direction.

2. The array substrate according to claim 1, characterized in that: The orthographic projection of the via hole on the base substrate is circular or elliptical, and the orthographic projection of the avoidance portion on the base substrate is arc-shaped.

3. The array substrate according to claim 1, characterized in that: The gate lines include: a first gate line and a second gate line; The first gate line is located above each row of the pixel units extending along the first direction, and the second gate line is located below each row of the pixel units extending along the first direction; The first gate line and the second gate line have the same extending direction and are between two adjacent rows of pixel units; The first gate line includes a first avoidance portion connected to the straight line portion, and the second gate line includes a second avoidance portion connected to the straight line portion; The first avoidance portion and the second avoidance portion respectively surround two opposite edges of the via hole; The plurality of pixel units include: first pixel units and second pixel units arranged alternately; the first pixel units include first thin film transistors, and the second pixel units include second thin film transistors; The first gate line is electrically connected to the first thin film transistor, and the second gate line is electrically connected to the second thin film transistor.

4. The array substrate according to claim 3, characterized in that: The first thin film transistor and the second thin film transistor include: a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode sequentially arranged on the base substrate; The gate line is arranged in the same layer as the gate electrode, the common electrode lead is arranged in the same layer as the source electrode and the drain electrode, and the insulating layer includes a passivation layer located on the source electrode and the drain electrode.

5. The array substrate according to claim 1, characterized in that: Each of the common electrode leads comprises: a plurality of connection portions located at the region where the gate lines and the common electrode leads intersect, and a first connection lead extending along the second direction and connecting the connection portions; The common electrode layer is connected to the connecting portion through the via hole; In the first direction, the width of the connecting portion is greater than the width of the first connecting lead; The orthographic projection of the via hole on the base substrate falls within the orthographic projection of the connecting portion on the base substrate, and in the first direction and the second direction, the width of the via hole is smaller than the width of the connecting portion.

6. The array substrate according to claim 5, characterized in that: The orthographic projection of the avoiding portion on the base substrate overlaps with the orthographic projection of the connecting portion on the base substrate.

7. The array substrate according to claim 6, characterized in that: In the first direction, the width of the connecting portion in at least a partial area is greater than the width of the avoiding portion.

8. The array substrate according to claim 1, characterized in that: A distance between an orthographic projection of the avoidance portion on the base substrate and an orthographic projection of the via hole on the base substrate is greater than 0 and less than or equal to 2 micrometers.

9. A display panel, characterized in that: The display panel comprises: the array substrate according to any one of claims 1 to 8, an opposite substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the array substrate.

10. A display device, characterized in that: The display device comprises the display panel according to claim 9.

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