Overcurrent protection circuit, method, clock signal generation circuit and display device

Abstract

The present invention provides an overcurrent protection circuit, method, clock signal generating circuit and display device. The overcurrent protection circuit includes N first overcurrent detection circuits, N second overcurrent detection circuits, a first signal generating circuit, a second signal generating circuit, a first level conversion circuit, a second level conversion circuit and a control circuit; the first signal generating circuit is used to output a first control signal to the first level conversion circuit when receiving a first overcurrent indication signal; the second signal generating circuit outputs a second control signal to the second level conversion circuit when receiving the second overcurrent indication signal; the control circuit is used to provide a shutdown control signal to the nth output control module within a predetermined time after receiving a third control signal and / or a fourth control signal; N is a positive integer, and n is a positive integer less than or equal to N. The present invention only needs to use two level conversion circuits to realize overcurrent protection of the clock signal generating circuit.

Description

Technical Field

[0001] The present invention relates to the field of overcurrent protection technology, and in particular to an overcurrent protection circuit, method, clock signal generating circuit and display device. Background Art

[0002] In the gate drive circuit included in the display device, several clock signal generation circuits are needed to convert low-voltage clock signals into high-voltage clock signals for powering the gate of the transistor; in order to prevent the clock signal generation circuit output from short-circuiting and causing chip failure, overcurrent protection needs to be added to disconnect the output power tube during protection. In the prior art, a large number of level conversion circuits are required when performing overcurrent protection on the clock signal generation circuit, which is not conducive to saving area. Summary of the invention

[0003] The main purpose of the present invention is to provide an overcurrent protection circuit, method, clock signal generating circuit and display device to solve the problem in the prior art that a large number of level conversion circuits are required when performing overcurrent protection on the clock signal generating circuit, which is not conducive to saving area.

[0004] In order to achieve the above-mentioned object, the present invention provides an overcurrent protection circuit, which is applied to a clock signal generating circuit, wherein the clock signal generating circuit includes N clock signal generating units, where N is a positive integer; the nth clock signal generating unit includes an nth clock signal output terminal, an nth output control module, an nth first output control terminal, an nth first output module, an nth second output control terminal and an nth second output module, wherein the nth output control module is used to provide an nth first output control signal to the nth first output control terminal and to provide an nth second output control signal to the nth second output control terminal. ; The nth first output module is used to control whether to output the first voltage signal through the nth clock signal output terminal under the control of the nth first output control signal; the nth second output module is used to control whether to output the second voltage signal through the nth clock signal output terminal under the control of the nth second output control signal; n is a positive integer less than or equal to N; the overcurrent protection circuit includes N first overcurrent detection circuits, N second overcurrent detection circuits, a first signal generating circuit, a second signal generating circuit, a first level conversion circuit, a second level conversion circuit and a control circuit; wherein,

[0005] The nth first overcurrent detection circuit is used for providing a first overcurrent indication signal to the first signal generating circuit through the output end of the nth first overcurrent detection circuit when detecting that the output current of the nth first output module is greater than a predetermined current;

[0006] The nth second overcurrent detection circuit is used for providing a second overcurrent indication signal to the second signal generating circuit through the output end of the nth second overcurrent detection circuit when detecting that the output current of the nth second output module is greater than a predetermined current;

[0007] The first signal generating circuit is used for outputting a first control signal to the first level conversion circuit through an output terminal of the first signal generating circuit when receiving the first over-current indication signal;

[0008] The second signal generating circuit is used for outputting a second control signal to the second level conversion circuit through an output terminal of the second signal generating circuit when receiving the second over-current indication signal;

[0009] The first level conversion circuit is used to perform level conversion on the first control signal to obtain a third control signal, and provide the third control signal to the control circuit;

[0010] The second level conversion circuit is used to perform level conversion on the second control signal to obtain a fourth control signal, and provide the fourth control signal to the control circuit;

[0011] The control circuit is used to provide a shutdown control signal to the nth output control module within a predetermined time after receiving the third control signal and / or the fourth control signal;

[0012] The nth output control module is used to control the nth first output module to stop outputting the first voltage signal through the nth clock signal output terminal, and to control the nth second output module to stop outputting the second voltage signal through the nth clock signal output terminal when receiving the shutdown control signal.

[0013] Optionally, the control circuit is further configured to provide a normal working control signal to the nth output control module after receiving the third control signal and / or the fourth control signal and after a predetermined time has passed;

[0014] The nth output control module is used to control the provision of the nth first output control signal to the nth first output module and the provision of the nth second output control signal to the nth second output module under the control of the input clock signal provided by the input clock signal end when the normal working control signal is received.

[0015] Optionally, the control circuit includes a first OR gate, an RS trigger and a timer;

[0016] The first input terminal of the first OR gate is connected to the third control signal, the second input terminal of the first OR gate is connected to the fourth control signal, and the output terminal of the first OR gate is electrically connected to the set terminal of the RS flip-flop;

[0017] The positive phase output terminal of the RS trigger is electrically connected to the nth output control module;

[0018] The timer is electrically connected to the positive phase output terminal, and is used to start timing when the positive phase output terminal outputs a shutdown control signal, and after a predetermined time, provide a reset signal to the reset terminal of the RS trigger, so that the RS trigger provides a normal working control signal through the positive phase output terminal.

[0019] Optionally, the first signal generating circuit includes a second OR gate; the second OR gate includes N input terminals;

[0020] The nth input terminal of the second OR gate is electrically connected to the output terminal of the nth first over-current detection circuit;

[0021] An output terminal of the second OR gate is electrically connected to an output terminal of the first signal generating circuit.

[0022] Optionally, the second signal generating circuit includes a third OR gate; the third OR gate includes N input terminals;

[0023] The nth input terminal of the third OR gate is electrically connected to the output terminal of the nth second overcurrent detection circuit, and the output terminal of the third OR gate is electrically connected to the output terminal of the second signal generating circuit.

[0024] The present invention also provides an overcurrent protection method, which is applied to the above-mentioned overcurrent protection circuit. The overcurrent protection method comprises:

[0025] When the nth first overcurrent detection circuit detects that the output current of the nth first output module is greater than a predetermined current, the nth first overcurrent detection circuit provides a first overcurrent indication signal to the first signal generating circuit through the output terminal of the nth first overcurrent detection circuit;

[0026] When the nth second overcurrent detection circuit detects that the output current of the nth second output module is greater than a predetermined current, the nth second overcurrent detection circuit provides a second overcurrent indication signal to the second signal generating circuit through the output terminal of the nth second overcurrent detection circuit;

[0027] When the first signal generating circuit receives the first over-current indication signal, the first signal generating circuit outputs a first control signal to the first level conversion circuit through its output terminal;

[0028] When the second signal generating circuit receives the second over-current indication signal, the second signal generating circuit outputs a second control signal to the second level conversion circuit through its output terminal;

[0029] The first level conversion circuit performs level conversion on the first control signal to obtain a third control signal, and provides the third control signal to the control circuit;

[0030] The second level conversion circuit performs level conversion on the second control signal to obtain a fourth control signal, and provides the fourth control signal to the control circuit;

[0031] The control circuit provides a shutdown control signal to the nth output control module within a predetermined time after the control circuit receives the third control signal and / or the fourth control signal;

[0032] When the nth output control module receives the shutdown control signal, the nth output control module controls the nth first output module to stop outputting the first voltage signal through the nth clock signal output terminal, and controls the nth second output module to stop outputting the second voltage signal through the nth clock signal output terminal.

[0033] Optionally, the clock signal generating method according to the embodiment of the present invention further includes:

[0034] After the control circuit receives the third control signal and / or the fourth control signal and a predetermined time has passed, the control circuit provides a normal working control signal to the nth output control module;

[0035] When the nth output control module receives the normal working control signal, under the control of the input clock signal provided by the input clock signal end, the nth output control module controls providing the nth first output control signal to the nth first output module, and controls providing the nth second output control signal to the nth second output module.

[0036] The present invention also provides a clock signal generating circuit, comprising the above-mentioned overcurrent protection circuit and N clock signal generating units, where N is a positive integer;

[0037] The nth clock signal generating unit comprises an nth clock signal output terminal, an nth output control module, an nth first output control terminal, an nth first output module, an nth second output control terminal and an nth second output module;

[0038] The nth output control module is used to provide the nth first output control signal to the nth first output control terminal, and provide the nth second output control signal to the nth second output control terminal;

[0039] The nth first output module is used for controlling whether to output the first voltage signal through the nth clock signal output terminal under the control of the nth first output control signal;

[0040] The nth second output module is used for controlling whether to output the second voltage signal through the nth clock signal output terminal under the control of the nth second output control signal;

[0041] n is a positive integer less than or equal to N.

[0042] Optionally, the nth output control module includes a first inverter, a fourth OR gate, a fifth OR gate, a second inverter, a third inverter, a third level conversion circuit, a fourth level conversion circuit, a p-type drive circuit and an n-type drive circuit; the control circuit in the overcurrent protection circuit includes an RS trigger;

[0043] The input end of the first inverter is electrically connected to the input clock signal end, the output end of the first inverter is electrically connected to the first input end of the fourth OR gate; the second input end of the fourth OR gate is electrically connected to the positive phase output end of the RS trigger;

[0044] The first input terminal of the fifth OR gate is electrically connected to the positive phase output terminal of the RS flip-flop, and the second input terminal of the fifth OR gate is electrically connected to the input clock signal terminal;

[0045] The input end of the second inverter is electrically connected to the output end of the fourth OR gate, and the input end of the third inverter is electrically connected to the output end of the fifth OR gate;

[0046] The third level conversion circuit is electrically connected to the output end of the second inverter, and is used to perform level conversion on the signal outputted from the output end of the second inverter to obtain a first output control signal, and provide the first output control signal to the p-type driving circuit;

[0047] The p-type driving circuit is used to provide the first output control signal to the nth first output control terminal;

[0048] The fourth level conversion circuit is electrically connected to the output end of the third inverter, and is used to perform level conversion on the signal outputted from the output end of the third inverter to obtain a second output control signal, and provide the second output control signal to the n-type driving circuit;

[0049] The n-type driving circuit is used to provide the second output control signal to the nth second output control terminal.

[0050] Optionally, the first output module includes a first output transistor, and the second output module includes a second output transistor;

[0051] The control electrode of the first output transistor is electrically connected to the nth first output control terminal, the first electrode of the first output transistor is electrically connected to the high voltage terminal through a first resistor, and the second electrode of the first output transistor is electrically connected to the nth clock signal output terminal;

[0052] The control electrode of the second output transistor is electrically connected to the nth second output control terminal, the first electrode of the second output transistor is electrically connected to the nth clock signal output terminal, and the second electrode of the second output transistor is electrically connected to the low voltage terminal through a second resistor.

[0053] The present invention also provides a display device, comprising the above-mentioned clock signal generating circuit.

[0054] The overcurrent protection circuit, method, clock signal generating circuit and display device described in the embodiments of the present invention only need to use two level conversion circuits to achieve overcurrent protection for the clock signal generating circuit. When it is detected that the output current of at least one first output module and / or the output current of at least one second output module exceeds the predetermined current, overcurrent protection can be performed, and a small area is occupied. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 is a structural diagram of an overcurrent protection circuit according to an embodiment of the present invention;

[0056] Figure 2 is a structural diagram of an overcurrent protection circuit according to another embodiment of the present invention;

[0057] Figure 3 is a structural diagram of an overcurrent protection circuit according to another embodiment of the present invention;

[0058] Figure 4 is a structural diagram of a clock signal generating circuit according to an embodiment of the present invention;

[0059] Figure 5 is a circuit diagram of a clock signal generating circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0061] The transistors used in all embodiments of the present invention may be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0062] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0063] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0064] The overcurrent protection circuit described in the embodiment of the present invention is applied to a clock signal generating circuit, wherein the clock signal generating circuit includes N clock signal generating units, where N is a positive integer; Figure 1 As shown, the nth clock signal generating unit includes an nth clock signal output terminal CLK_LS, an nth output control module 10, an nth first output control terminal C1, an nth first output module 11, an nth second output control terminal C2 and an nth second output module 12;

[0065] The nth output control module 10 is electrically connected to the nth first output control terminal C1 and the nth second output control terminal C2, respectively, and is used to provide the nth first output control signal to the nth first output control terminal C1, and provide the nth second output control signal to the nth second output control terminal C2;

[0066] The nth first output module 11 is electrically connected to the nth first output control terminal C1 and the nth clock signal output terminal CLK_LS respectively, and is used to control whether to output the first voltage signal through the nth clock signal output terminal CLK_LS under the control of the nth first output control signal provided by C1;

[0067] The nth second output module 12 is electrically connected to the nth second output control terminal C2 and the nth clock signal output terminal CLK_LS respectively, and is used to control whether to output the second voltage signal through the nth clock signal output terminal CLK_LS under the control of the nth second output control signal provided by C2;

[0068] n is a positive integer less than or equal to N;

[0069] The overcurrent protection circuit includes N first overcurrent detection circuits, N second overcurrent detection circuits, a first signal generating circuit 21, a second signal generating circuit 22, a first level conversion circuit 23, a second level conversion circuit 24 and a control circuit 25; wherein,

[0070] like Figure 1 As shown, the nth first overcurrent detection circuit 13 is electrically connected to the nth first output module 11 and the first signal generating circuit 21 respectively, and is used to provide a first overcurrent indication signal to the first signal generating circuit 21 through the output end of the nth first overcurrent detection circuit 13 when it is detected that the output current of the nth first output module 11 is greater than the predetermined current;

[0071] The nth second overcurrent detection circuit 14 is electrically connected to the nth second output module 12 and the second signal generating circuit 22, respectively, and is used to provide a second overcurrent indication signal to the second signal generating circuit 22 through the output end of the nth second overcurrent detection circuit 14 when it is detected that the output current of the nth second output module 12 is greater than a predetermined current;

[0072] The first signal generating circuit 21 is electrically connected to the first level conversion circuit 23, and is configured to output a first control signal to the first level conversion circuit 23 through an output terminal of the first signal generating circuit 21 when receiving the first over-current indication signal;

[0073] The second signal generating circuit 22 is electrically connected to the second level conversion circuit 24, and is configured to output a second control signal to the second level conversion circuit 24 through the output terminal of the second signal generating circuit 22 when receiving the second over-current indication signal;

[0074] The first level conversion circuit 23 is electrically connected to the control circuit 25, and is used for performing level conversion on the first control signal to obtain a third control signal, and providing the third control signal to the control circuit 25;

[0075] The second level conversion circuit 24 is electrically connected to the control circuit 25, and is used for performing level conversion on the second control signal to obtain a fourth control signal, and providing the fourth control signal to the control circuit 25;

[0076] The control circuit 25 is electrically connected to the nth output control module 10, and is used to provide a shutdown control signal to the nth output control module 10 within a predetermined time after receiving the third control signal and / or the fourth control signal;

[0077] The nth output control module 10 is used to control the nth first output module 11 to stop outputting the first voltage signal through the nth clock signal output terminal, and control the nth second output module 12 to stop outputting the second voltage signal through the nth clock signal output terminal when receiving the shutdown control signal.

[0078] In the embodiment of the present invention, the predetermined current can be selected according to actual conditions, and the predetermined time can also be selected according to actual conditions.

[0079] The present invention Figure 1 When the embodiment of the overcurrent protection circuit shown is in operation, when the nth first overcurrent detection circuit 13 detects that the output current of the nth first output module 11 is greater than the predetermined current, the first overcurrent indication signal is provided to the first signal generating circuit 21; when the nth second overcurrent detection circuit 14 detects that the output current of the nth second output module 12 is greater than the predetermined current, the second overcurrent indication signal is provided to the second signal generating circuit 22;

[0080] When the first signal generating circuit 21 receives the first over-current indication signal, it outputs a first control signal to the first level conversion circuit 23; when the second signal generating circuit 22 receives the second over-current indication signal, it outputs a second control signal to the second level conversion circuit 24;

[0081] The first overcurrent indication signal is an overcurrent indication signal of a P-type transistor, the first overcurrent indication signal is in a high voltage domain, and the first control signal is also in a high voltage domain; the second overcurrent indication signal is an overcurrent indication signal of an N-type transistor, the second overcurrent indication signal is in a negative voltage domain, and the second control signal is also in a negative voltage domain;

[0082] The first level conversion circuit 23 performs level conversion on the first control signal to obtain a third control signal, and provides the third control signal to the control circuit 25; wherein the third control signal is in the ground voltage domain;

[0083] The second level conversion circuit is electrically connected to the control circuit 25, and is used to perform level conversion on the second control signal to obtain a fourth control signal, and provide the fourth control signal to the control circuit 25; wherein the fourth control signal is in the ground voltage domain;

[0084] The first control signal in the high voltage domain may refer to: the potential of the first control signal is switched between 25V and 30V, but is not limited thereto; that is, when the first control signal corresponds to logic "1", the potential of the first control signal is 30V, and when the first control signal corresponds to logic "0", the potential of the first control signal is 25V;

[0085] The second control signal in the negative voltage domain may refer to: the potential of the second control signal is switched between -10V and -5V, but is not limited thereto; that is, when the second control signal corresponds to logic "1", the potential of the second control signal is -5V, and when the second control signal corresponds to logic "0", the potential of the first control signal is -10V;

[0086] The third control signal in the ground voltage domain may refer to: the potential of the third control signal switching between 0V and 5V, but is not limited thereto; that is, when the third control signal corresponds to logic "1", the potential of the third control signal is 5V, and when the third control signal corresponds to logic "0", the potential of the third control signal is 0V;

[0087] The fourth control signal in the ground voltage domain may refer to: the potential of the fourth control signal switching between 0V and 5V, but is not limited thereto; that is, when the fourth control signal corresponds to logic "1", the potential of the fourth control signal is 5V, and when the fourth control signal corresponds to logic "0", the potential of the fourth control signal is 0V;

[0088] The first level conversion circuit 23 performs level conversion on the first control signal to obtain the third control signal, which means: converting the first control signal in the high voltage domain into the third control signal in the ground voltage domain;

[0089] The second level conversion circuit 24 performs level conversion on the second control signal to obtain the fourth control signal, which means: converting the second control signal in the negative voltage domain into the fourth control signal in the ground voltage domain;

[0090] providing a shutdown control signal to the nth output control module 10 within a predetermined time after the control circuit 25 receives the third control signal and / or the fourth control signal;

[0091] The nth output control module 10 is used to control the nth first output module 11 to stop outputting the first voltage signal through the nth clock signal output terminal, and to control the nth second output module 12 to stop outputting the second voltage signal through the nth clock signal output terminal when receiving the shutdown control signal, that is, to control the first output transistor included in the nth first output module 11 and the second output transistor included in the nth second output module 12 to be turned off.

[0092] The overcurrent protection circuit described in the embodiment of the present invention only needs to use two level conversion circuits to achieve overcurrent protection for the clock signal generating circuit. When it is detected that the output current of at least one first output module and / or the output current of at least one second output module exceeds the predetermined current, overcurrent protection is performed.

[0093] exist Figure 1 In the illustrated embodiment, the nth first output module 11 is also electrically connected to a high voltage terminal, and the high voltage terminal is used to provide a high voltage signal VGH, and VGH may be a 30V voltage signal, but is not limited thereto;

[0094] The nth second output module 12 is also electrically connected to a low voltage terminal, and the low voltage terminal is used to provide a low voltage signal VGL. VGL may be a -10V voltage signal, but is not limited thereto.

[0095] In a specific implementation, the nth first output module may include a first output transistor, and the second output module may include a second output transistor;

[0096] The control electrode of the first output transistor is electrically connected to the nth first output control terminal, the first electrode of the first output transistor is electrically connected to the high voltage terminal through a first resistor, and the second electrode of the first output transistor is electrically connected to the nth clock signal output terminal;

[0097] The control electrode of the second output transistor is electrically connected to the nth second output control terminal, the first electrode of the second output transistor is electrically connected to the nth clock signal output terminal, and the second electrode of the second output transistor is electrically connected to the low voltage terminal through a second resistor;

[0098] The output current of the nth first output module 11 may be the current flowing through the first electrode of the first output transistor, and the output current of the nth second output module 12 may be the current flowing through the second electrode of the second output transistor, but the present invention is not limited thereto.

[0099] In the embodiment of the present invention, the control circuit may also be configured to provide a normal working control signal to the nth output control module after receiving the third control signal and / or the fourth control signal and after a predetermined time has passed;

[0100] The nth output control module is used to control the provision of the nth first output control signal to the nth first output module and the provision of the nth second output control signal to the nth second output module under the control of the input clock signal provided by the input clock signal end when the normal working control signal is received.

[0101] In a specific implementation, after the control circuit receives the third control signal and / or the fourth control signal and a predetermined time has passed, the control circuit provides a normal operating control signal to the nth output control module, so that the nth output control module controls the nth first output module and the nth second output module to operate normally under the control of the input clock signal.

[0102] Optionally, the control circuit may include a first OR gate, an RS trigger and a timer;

[0103] The first input terminal of the first OR gate is connected to the third control signal, the second input terminal of the first OR gate is connected to the fourth control signal, and the output terminal of the first OR gate is electrically connected to the set terminal of the RS flip-flop;

[0104] The positive phase output terminal of the RS trigger is electrically connected to the nth output control module;

[0105] The timer is electrically connected to the positive phase output terminal, and is used to start timing when the positive phase output terminal outputs a shutdown control signal, and after a predetermined time, provide a reset signal to the reset terminal of the RS trigger, so that the RS trigger provides a normal working control signal through the positive phase output terminal.

[0106] When the output current of at least one first output module is greater than the predetermined current, the third control signal corresponds to logic "1", and when the output current of at least one second output module is greater than the predetermined current, the fourth control signal corresponds to logic "0". At this time, the voltage signal output by the first OR gate corresponds to logic "1", and the set end of the RS trigger is connected to logic "1", then the voltage signal output by the positive phase output end of the RS trigger corresponds to logic "1", and at this time, the nth output control module controls the nth first output module to stop working, and the nth output control module controls the nth second output module to stop working; and when the voltage signal output by the first OR gate corresponds to logic "1", the timer starts timing, and after a predetermined time, the timer provides a voltage signal corresponding to logic "1" to the reset end of the RS trigger, so that the voltage signal output by the RS trigger through its output end corresponds to logic "0", so that the operation of the nth output control module is not affected, and the nth output control module, the nth first output module and the nth second output module work normally.

[0107] like Figure 2 As shown, in Figure 1 Based on the embodiment of the overcurrent protection circuit shown, the control circuit 25 may include a first OR gate OR1, an RS trigger 31 and a timer 32;

[0108] The first input terminal of the first OR gate OR1 is connected to the third control signal, the second input terminal of the first OR gate OR2 is connected to the fourth control signal, and the output terminal of the first OR gate OR1 is electrically connected to the set terminal S of the RS flip-flop 31;

[0109] The positive phase output terminal Q of the RS trigger 31 is electrically connected to the nth output control module 10;

[0110] The timer 32 is electrically connected to the positive phase output terminal Q, and is used to start timing when the positive phase output terminal Q outputs a shutdown control signal, and after a predetermined time, provide a reset signal to the reset terminal R of the RS trigger 31, so that the RS trigger 31 provides a normal working control signal through the positive phase output terminal Q.

[0111] In a specific implementation, the first signal generating circuit may include a second OR gate; the second OR gate may include N input terminals;

[0112] The nth input terminal of the second OR gate is electrically connected to the output terminal of the nth first over-current detection circuit;

[0113] An output terminal of the second OR gate is electrically connected to an output terminal of the first signal generating circuit.

[0114] Optionally, the second signal generating circuit includes a third OR gate; the third OR gate includes N input terminals;

[0115] The nth input terminal of the third OR gate is electrically connected to the output terminal of the nth second overcurrent detection circuit, and the output terminal of the third OR gate is electrically connected to the output terminal of the second signal generating circuit.

[0116] like Figure 3 As shown, in Figure 2 Based on the embodiment of the overcurrent protection circuit shown, the first signal generating circuit includes a second OR gate OR2, and the second signal generating circuit includes a third OR gate OR3;

[0117] The nth input terminal of OR2 is electrically connected to the output terminal of the nth first overcurrent detection circuit 13;

[0118] The nth input terminal of OR3 is electrically connected to the output terminal of the nth second overcurrent detection circuit 14;

[0119] The output end of OR2 is electrically connected to the first level conversion circuit 23 , and the output end of OR2 is electrically connected to the second level conversion circuit 24 .

[0120] The overcurrent protection method described in the embodiment of the present invention is applied to the above-mentioned overcurrent protection circuit, and the overcurrent protection method includes:

[0121] When the nth first overcurrent detection circuit detects that the output current of the nth first output module is greater than a predetermined current, the nth first overcurrent detection circuit provides a first overcurrent indication signal to the first signal generating circuit through the output terminal of the nth first overcurrent detection circuit;

[0122] When the nth second overcurrent detection circuit detects that the output current of the nth second output module is greater than a predetermined current, the nth second overcurrent detection circuit provides a second overcurrent indication signal to the second signal generating circuit through the output terminal of the nth second overcurrent detection circuit;

[0123] When the first signal generating circuit receives the first over-current indication signal, the first signal generating circuit outputs a first control signal to the first level conversion circuit through its output terminal;

[0124] When the second signal generating circuit receives the second over-current indication signal, the second signal generating circuit outputs a second control signal to the second level conversion circuit through its output terminal;

[0125] The first level conversion circuit performs level conversion on the first control signal to obtain a third control signal, and provides the third control signal to the control circuit;

[0126] The second level conversion circuit performs level conversion on the second control signal to obtain a fourth control signal, and provides the fourth control signal to the control circuit;

[0127] The control circuit provides a shutdown control signal to the nth output control module within a predetermined time after the control circuit receives the third control signal and / or the fourth control signal;

[0128] When the nth output control module receives the shutdown control signal, the nth output control module controls the nth first output module to stop outputting the first voltage signal through the nth clock signal output terminal, and controls the nth second output module to stop outputting the second voltage signal through the nth clock signal output terminal.

[0129] In the overcurrent protection method described in the embodiment of the present invention, when it is detected that the output current of at least one first output module and / or the output current of at least one second output module exceeds a predetermined current, overcurrent protection may be performed.

[0130] In a specific implementation, the clock signal generation method described in the embodiment of the present invention may further include:

[0131] After the control circuit receives the third control signal and / or the fourth control signal and a predetermined time has passed, the control circuit provides a normal working control signal to the nth output control module;

[0132] When the nth output control module receives the normal working control signal, under the control of the input clock signal provided by the input clock signal end, the nth output control module controls providing the nth first output control signal to the nth first output module, and controls providing the nth second output control signal to the nth second output module.

[0133] The clock signal generating circuit described in the embodiment of the present invention comprises the above-mentioned overcurrent protection circuit and N clock signal generating units, where N is a positive integer;

[0134] The nth clock signal generating unit comprises an nth clock signal output terminal, an nth output control module, an nth first output control terminal, an nth first output module, an nth second output control terminal and an nth second output module;

[0135] The nth output control module is used to provide the nth first output control signal to the nth first output control terminal, and provide the nth second output control signal to the nth second output control terminal;

[0136] The nth first output module is used for controlling whether to output the first voltage signal through the nth clock signal output terminal under the control of the nth first output control signal;

[0137] The nth second output module is used for controlling whether to output the second voltage signal through the nth clock signal output terminal under the control of the nth second output control signal;

[0138] n is a positive integer less than or equal to N;

[0139] The clock signal generating circuit described in the embodiment of the present invention can perform overcurrent protection on N clock signal generating units.

[0140] Optionally, the nth output control module includes a first inverter, a fourth OR gate, a fifth OR gate, a second inverter, a third inverter, a third level conversion circuit, a fourth level conversion circuit, a p-type drive circuit and an n-type drive circuit; the control circuit in the overcurrent protection circuit includes an RS trigger;

[0141] The input end of the first inverter is electrically connected to the input clock signal end, the output end of the first inverter is electrically connected to the first input end of the fourth OR gate; the second input end of the fourth OR gate is electrically connected to the positive phase output end of the RS trigger;

[0142] The first input terminal of the fifth OR gate is electrically connected to the positive phase output terminal of the RS flip-flop, and the second input terminal of the fifth OR gate is electrically connected to the input clock signal terminal;

[0143] The input end of the second inverter is electrically connected to the output end of the fourth OR gate, and the input end of the third inverter is electrically connected to the output end of the fifth OR gate;

[0144] The third level conversion circuit is electrically connected to the output end of the second inverter, and is used to perform level conversion on the signal outputted from the output end of the second inverter to obtain a first output control signal, and provide the first output control signal to the p-type driving circuit;

[0145] The p-type driving circuit is used to provide the first output control signal to the nth first output control terminal;

[0146] The fourth level conversion circuit is electrically connected to the output end of the third inverter, and is used to perform level conversion on the signal outputted from the output end of the third inverter to obtain a second output control signal, and provide the second output control signal to the n-type driving circuit;

[0147] The n-type driving circuit is used to provide the second output control signal to the nth second output control terminal.

[0148] like Figure 4 As shown, in Figure 3 Based on the embodiment shown, the nth output control module 10 includes a first inverter F1, a fourth OR gate OR4, a fifth OR gate OR5, a second inverter F2, a third inverter F3, a third level conversion circuit 41, a fourth level conversion circuit 42, a p-type drive circuit 43 and an n-type drive circuit 44;

[0149] The input end of the first inverter F1 is electrically connected to the input clock signal end, and the output end of the first inverter F1 is electrically connected to the first input end of the fourth OR gate OR4; the second input end of the fourth OR gate OR4 is electrically connected to the positive phase output end Q of the RS trigger 31; the input clock signal end is used to provide an input clock signal CLK_IN;

[0150] The first input terminal of the fifth OR gate OR5 is electrically connected to the positive phase output terminal Q of the RS trigger 31, and the second input terminal of the fifth OR gate OR5 is electrically connected to the input clock signal terminal;

[0151] The input end of the second inverter F2 is electrically connected to the output end of the fourth OR gate OR4, and the input end of the third inverter F3 is electrically connected to the output end of the fifth OR gate OR5;

[0152] The third level conversion circuit 41 is electrically connected to the output end of the second inverter F2, and is used to perform level conversion on the signal outputted from the output end of the second inverter F2 to obtain a first output control signal, and provide the first output control signal to the p-type driving circuit 43;

[0153] The p-type driving circuit 43 is used to provide the first output control signal to the n-th first output control terminal C1 and enhance the driving capability of the n-th first output control terminal C1;

[0154] The fourth level conversion circuit 42 is electrically connected to the output end of the third inverter F3, and is used to perform level conversion on the signal outputted from the output end of the third inverter F3 to obtain a second output control signal, and provide the second output control signal to the n-type driving circuit 44;

[0155] The n-type driving circuit 44 is used to provide the second output control signal to the n-th second output control terminal C2 and enhance the driving capability of the n-th second output control terminal C2.

[0156] In an embodiment of the present invention, the first output module includes a first output transistor, and the second output module includes a second output transistor;

[0157] The control electrode of the first output transistor is electrically connected to the nth first output control terminal, the first electrode of the first output transistor is electrically connected to the high voltage terminal through a first resistor, and the second electrode of the first output transistor is electrically connected to the nth clock signal output terminal;

[0158] The control electrode of the second output transistor is electrically connected to the nth second output control terminal, the first electrode of the second output transistor is electrically connected to the nth clock signal output terminal, and the second electrode of the second output transistor is electrically connected to the low voltage terminal through a second resistor.

[0159] like Figure 5 As shown, in Figure 4 Based on the embodiment shown, the first output module includes a first output transistor P1, and the second output module includes a second output transistor N1;

[0160] The gate of the first output transistor P1 is electrically connected to the nth first output control terminal C1, the source of the first output transistor P1 is electrically connected to the high voltage terminal through the first resistor R1, and the drain of the first output transistor P1 is electrically connected to the nth clock signal output terminal CLK_LS; the high voltage terminal is used to provide a high voltage signal VGH;

[0161] The gate of the second output transistor N1 is electrically connected to the nth second output control terminal C2, the drain of the second output transistor N1 is electrically connected to the nth clock signal output terminal CLK_LS, and the source of the second output transistor N1 is electrically connected to a low voltage terminal through a second resistor R2; the low voltage terminal is used to provide a low voltage signal VGL.

[0162] exist Figure 5 In the illustrated embodiment, P1 is a PMOS transistor (P-type metal-oxide-semiconductor transistor), and N1 is an NMOS transistor (N-type metal-oxide-semiconductor transistor), but the present invention is not limited thereto.

[0163] The present invention Figure 5 When the embodiment of the clock signal generating circuit shown is working, when the current flowing through the source of P1 and / or the current flowing through the source of N1 (or the output current of other first output modules and / or the output current of other second output modules) exceeds the predetermined current, the overcurrent indication signal is latched in the RS trigger 31, and the timer is controlled to start timing, and the RS trigger 31 outputs a voltage signal corresponding to logic "1" through its positive phase output terminal Q, then OR4 and OR5 both output voltage signals corresponding to logic "1", F2 and F3 output voltage signals corresponding to logic "0", the voltage signal output by F2 and the voltage signal output by F3 are both in the ground voltage domain, the third level conversion circuit 41 converts the voltage signal output by F2 into a first output control signal, the first output control signal is in the high voltage domain, and the fourth level conversion circuit 42 converts the voltage signal output by F3 into a second output control signal, the second output control signal is in the negative voltage domain, so as to control both P1 and N1 to be turned off;

[0164] When the timer starts timing and after a predetermined time has passed, the timer provides a voltage signal corresponding to logic "1" to the reset terminal R of the RS trigger 31, so that the RS trigger 31 outputs a voltage signal corresponding to logic "0" through its positive phase output terminal Q, which will not affect the operation of OR4 and OR5.

[0165] The display device described in the embodiment of the present invention includes the above-mentioned clock signal generating circuit.

[0166] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0167] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An overcurrent protection circuit, applied to a clock signal generating circuit, the clock signal generating circuit comprising N clock signal generating units, N being a positive integer; the nth clock signal generating unit comprising an nth clock signal output terminal, an nth output control module, an nth first output control terminal, an nth first output module, an nth second output control terminal and an nth second output module, the nth output control module being used to provide an nth first output control signal to the nth first output control terminal and to provide an nth second output control signal to the nth second output control terminal; the nth first output module being used to control whether to output a first voltage signal through the nth clock signal output terminal under the control of the nth first output control signal; the nth second output module being used to control whether to output a second voltage signal through the nth clock signal output terminal under the control of the nth second output control signal; n being a positive integer less than or equal to N; characterized in that, The overcurrent protection circuit includes N first overcurrent detection circuits, N second overcurrent detection circuits, a first signal generating circuit, a second signal generating circuit, a first level conversion circuit, a second level conversion circuit and a control circuit; wherein, The nth first overcurrent detection circuit is used for providing a first overcurrent indication signal to the first signal generating circuit through the output end of the nth first overcurrent detection circuit when detecting that the output current of the nth first output module is greater than a predetermined current; The nth second overcurrent detection circuit is used for providing a second overcurrent indication signal to the second signal generating circuit through the output end of the nth second overcurrent detection circuit when detecting that the output current of the nth second output module is greater than a predetermined current; The first signal generating circuit is used for outputting a first control signal to the first level conversion circuit through an output terminal of the first signal generating circuit when receiving the first over-current indication signal; The second signal generating circuit is used for outputting a second control signal to the second level conversion circuit through an output terminal of the second signal generating circuit when receiving the second over-current indication signal; The first level conversion circuit is used to perform level conversion on the first control signal to obtain a third control signal, and provide the third control signal to the control circuit; The second level conversion circuit is used for performing level conversion on the second control signal to obtain a fourth control signal, and providing the fourth control signal to the control circuit; The control circuit is used to provide a shutdown control signal to the nth output control module within a predetermined time after receiving the third control signal and / or the fourth control signal; The nth output control module is used to control the nth first output module to stop outputting the first voltage signal through the nth clock signal output terminal, and control the nth second output module to stop outputting the second voltage signal through the nth clock signal output terminal when receiving the shutdown control signal; The first signal generating circuit comprises N input terminals; the nth input terminal of the first signal generating circuit is electrically connected to the output terminal of the nth first overcurrent detection circuit; The second signal generating circuit includes N input terminals; the nth input terminal of the second signal generating circuit is electrically connected to the output terminal of the nth second overcurrent detection circuit.

2. The overcurrent protection circuit according to claim 1, characterized in that: The control circuit is further configured to provide a normal working control signal to the nth output control module after receiving the third control signal and / or the fourth control signal and after a predetermined time has passed; The nth output control module is used to control the provision of the nth first output control signal to the nth first output module and the provision of the nth second output control signal to the nth second output module under the control of the input clock signal provided by the input clock signal end when the normal working control signal is received.

3. The overcurrent protection circuit according to claim 2, characterized in that: The control circuit includes a first OR gate, an RS trigger and a timer; The first input terminal of the first OR gate is connected to the third control signal, the second input terminal of the first OR gate is connected to the fourth control signal, and the output terminal of the first OR gate is electrically connected to the set terminal of the RS flip-flop; The positive phase output terminal of the RS trigger is electrically connected to the nth output control module; The timer is electrically connected to the positive phase output terminal, and is used to start timing when the positive phase output terminal outputs a shutdown control signal, and after a predetermined time, provide a reset signal to the reset terminal of the RS trigger, so that the RS trigger provides a normal working control signal through the positive phase output terminal.

4. The overcurrent protection circuit according to claim 1 or 2, characterized in that: The first signal generating circuit includes a second OR gate; the second OR gate includes N input terminals; The nth input terminal of the second OR gate is electrically connected to the output terminal of the nth first over-current detection circuit; An output terminal of the second OR gate is electrically connected to an output terminal of the first signal generating circuit.

5. The overcurrent protection circuit according to claim 1 or 2, characterized in that: The second signal generating circuit includes a third OR gate; the third OR gate includes N input terminals; The nth input terminal of the third OR gate is electrically connected to the output terminal of the nth second overcurrent detection circuit, and the output terminal of the third OR gate is electrically connected to the output terminal of the second signal generating circuit.

6. An overcurrent protection method, applied to the overcurrent protection circuit as claimed in any one of claims 1 to 5, characterized in that: The overcurrent protection method comprises: When the nth first overcurrent detection circuit detects that the output current of the nth first output module is greater than a predetermined current, the nth first overcurrent detection circuit provides a first overcurrent indication signal to the first signal generating circuit through the output terminal of the nth first overcurrent detection circuit; When the nth second overcurrent detection circuit detects that the output current of the nth second output module is greater than a predetermined current, the nth second overcurrent detection circuit provides a second overcurrent indication signal to the second signal generating circuit through the output terminal of the nth second overcurrent detection circuit; When the first signal generating circuit receives the first over-current indication signal, the first signal generating circuit outputs a first control signal to the first level conversion circuit through its output terminal; When the second signal generating circuit receives the second over-current indication signal, the second signal generating circuit outputs a second control signal to the second level conversion circuit through its output terminal; The first level conversion circuit performs level conversion on the first control signal to obtain a third control signal, and provides the third control signal to the control circuit; The second level conversion circuit performs level conversion on the second control signal to obtain a fourth control signal, and provides the fourth control signal to the control circuit; The control circuit provides a shutdown control signal to the nth output control module within a predetermined time after the control circuit receives the third control signal and / or the fourth control signal; When the nth output control module receives the shutdown control signal, the nth output control module controls the nth first output module to stop outputting the first voltage signal through the nth clock signal output terminal, and controls the nth second output module to stop outputting the second voltage signal through the nth clock signal output terminal.

7. The overcurrent protection method according to claim 6, characterized in that: Also includes: After the control circuit receives the third control signal and / or the fourth control signal and a predetermined time has passed, the control circuit provides a normal working control signal to the nth output control module; When the nth output control module receives the normal working control signal, under the control of the input clock signal provided by the input clock signal end, the nth output control module controls providing the nth first output control signal to the nth first output module, and controls providing the nth second output control signal to the nth second output module.

8. A clock signal generating circuit, characterized in that: The device comprises an overcurrent protection circuit as claimed in any one of claims 1 to 5 and N clock signal generating units, wherein N is a positive integer; The nth clock signal generating unit comprises an nth clock signal output terminal, an nth output control module, an nth first output control terminal, an nth first output module, an nth second output control terminal and an nth second output module; The nth output control module is used to provide the nth first output control signal to the nth first output control terminal, and provide the nth second output control signal to the nth second output control terminal; The nth first output module is used for controlling whether to output the first voltage signal through the nth clock signal output terminal under the control of the nth first output control signal; The nth second output module is used for controlling whether to output the second voltage signal through the nth clock signal output terminal under the control of the nth second output control signal; n is a positive integer less than or equal to N.

9. The clock signal generating circuit according to claim 8, wherein: The nth output control module includes a first inverter, a fourth OR gate, a fifth OR gate, a second inverter, a third inverter, a third level conversion circuit, a fourth level conversion circuit, a p-type drive circuit and an n-type drive circuit; the control circuit in the overcurrent protection circuit includes an RS trigger; The input end of the first inverter is electrically connected to the input clock signal end, the output end of the first inverter is electrically connected to the first input end of the fourth OR gate; the second input end of the fourth OR gate is electrically connected to the positive phase output end of the RS trigger; The first input terminal of the fifth OR gate is electrically connected to the positive phase output terminal of the RS trigger, and the second input terminal of the fifth OR gate is electrically connected to the input clock signal terminal; The input end of the second inverter is electrically connected to the output end of the fourth OR gate, and the input end of the third inverter is electrically connected to the output end of the fifth OR gate; The third level conversion circuit is electrically connected to the output end of the second inverter, and is used to perform level conversion on the signal outputted from the output end of the second inverter to obtain a first output control signal, and provide the first output control signal to the p-type driving circuit; The p-type driving circuit is used to provide the first output control signal to the nth first output control terminal; The fourth level conversion circuit is electrically connected to the output end of the third inverter, and is used to perform level conversion on the signal outputted from the output end of the third inverter to obtain a second output control signal, and provide the second output control signal to the n-type driving circuit; The n-type driving circuit is used for providing the second output control signal to the nth second output control terminal.

10. The clock signal generating circuit according to claim 8, wherein: The first output module includes a first output transistor, and the second output module includes a second output transistor; The control electrode of the first output transistor is electrically connected to the nth first output control terminal, the first electrode of the first output transistor is electrically connected to the high voltage terminal through a first resistor, and the second electrode of the first output transistor is electrically connected to the nth clock signal output terminal; The control electrode of the second output transistor is electrically connected to the nth second output control terminal, the first electrode of the second output transistor is electrically connected to the nth clock signal output terminal, and the second electrode of the second output transistor is electrically connected to the low voltage terminal through a second resistor.

11. A display device, characterized in that: The method comprises a clock signal generating circuit as claimed in any one of claims 8 to 10.

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