Method for manufacturing a plurality of contact plugs

Abstract

A manufacturing method of multiple contact plugs. The manufacturing method of multiple contact plugs includes forming a transistor, which includes forming source / drain regions on one side of a dummy gate stack, forming a first interlayer dielectric layer covering the source / drain regions, and replacing the dummy gate stack with a replacement gate stack. The method includes forming a second interlayer dielectric layer above the first interlayer dielectric layer and the replacement gate stack, and forming lower source / drain contact plugs electrically coupled to the source / drain regions. A third interlayer dielectric layer is formed above the second interlayer dielectric layer. Gate contact plugs are formed in the second interlayer dielectric layer and the third interlayer dielectric layer. Upper source / drain contact plugs are formed to overlap and contact the lower source / drain contact plugs. The upper source / drain contact plugs and the gate contact plugs are formed of different materials.

Description

[0001] This application is a divisional application of the patent application with the application date of June 14, 2017, the application number of 201710447702.8, and the invention title of "Device with Multiple Contact Plugs and Method for Manufacturing the Same". Technical Field

[0002] This disclosure relates to a method for manufacturing multiple contact plugs, and more particularly to a method for manufacturing multiple contact plugs according to the requirements of each contact plug, such as aspect ratio or resistivity. Background Art

[0003] In transistor manufacturing, metal is used to form contact plugs and metal gates. The contact plugs are used to connect to the source and drain regions and the gate of the transistor.

[0004] In a general manufacturing process for forming contact plugs, a first source / drain contact plug is formed in a first interlayer dielectric layer, and the first source / drain contact plug is electrically connected to the source / drain region. Then, a contact etch stop layer and a second interlayer dielectric layer are formed, and a gate contact opening is formed and extends into the second interlayer dielectric layer, the contact etch stop layer, and the first interlayer dielectric layer to expose the underlying metal gate. A source / drain contact opening is also formed and extends into the second interlayer dielectric layer and the contact etch stop layer to expose the first source / drain contact plug. Then, the gate contact opening and the source / drain contact opening are filled with a conductive material to form a gate contact plug and a second source / drain contact plug. The contact plugs formed in this process may suffer from the problem of voids formed therein, especially for gate contact plugs with a high aspect ratio. Summary of the Invention

[0005] According to some embodiments of the present disclosure, the method includes forming a transistor, which includes forming source / drain regions on one side of a dummy gate stack, forming a first interlayer dielectric layer covering the source / drain regions, and replacing the dummy gate stack with a replacement gate stack. The above method further includes forming a second interlayer dielectric layer above the first interlayer dielectric layer and the replacement gate stack, and forming a lower source / drain contact plug, the lower source / drain contact plug being electrically coupled to the source / drain region. The lower source / drain contact plug passes through the first interlayer dielectric layer and the second interlayer dielectric layer. A third interlayer dielectric layer is formed above the second interlayer dielectric layer. A gate contact plug is formed in the second interlayer dielectric layer and the third interlayer dielectric layer. An upper source / drain contact plug is formed to overlap and contact the lower source / drain contact plug. The upper source / drain contact plug passes through the third interlayer dielectric layer. The upper source / drain contact plug and the gate contact plug are formed of different materials.

[0006] According to some embodiments of the present disclosure, a method includes forming a transistor having a gate stack and source / drain regions located on one side of the gate stack, wherein the gate stack is located in a first interlayer dielectric layer; and forming a lower source / drain contact plug electrically coupled to the source / drain regions. In a first process operation, a gate contact plug is formed above and in contact with the gate stack. In a second process operation, an upper source / drain contact plug is formed to overlap and contact the lower source / drain contact plug, the aspect ratio of the gate contact plug is greater than the aspect ratio of the upper source / drain contact plug, and the gate contact plug has a resistivity higher than that of the upper source / drain contact plug. An etch stop layer is formed above and in contact with the upper source / drain contact plug and the gate contact plug.

[0007] According to some embodiments of the present disclosure, a device includes a first interlayer dielectric layer, a gate stack in the first interlayer dielectric layer, a second interlayer dielectric layer above the first interlayer dielectric layer, source / drain regions adjacent to the gate stack, and a lower source / drain contact plug located above and coupled to the source / drain regions. The lower source / drain contact plug penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer. An upper source / drain contact plug is located above and in contact with the lower source / drain contact plug. A gate contact plug is located above and in contact with the gate stack. The upper source / drain contact plug and the gate contact plug are formed of different materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure can be more easily understood by reading the following detailed description in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clear discussion, the dimensions of various features may be arbitrarily enlarged or reduced.

[0009] Figures 1 to 26 A perspective view and a cross-sectional view of an intermediate process for forming a transistor according to some embodiments;

[0010] Figure 27 A process flow diagram showing the process of forming a transistor and contact plugs according to some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or illustrations for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the disclosure of the present disclosure. Of course, these are merely illustrations and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features of the first feature, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in various illustrations. Such repetition is for the purpose of simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations being discussed.

[0012] In addition, spatial relative terms, such as "beneath", "below", "lower", "above", "upper", etc., may be used herein to simply describe the relationship of an element or feature shown in the figures to another element(s) or feature(s). In addition to the orientation depicted in the figures, spatial relative terms are intended to encompass different orientations of the element when in use or operation. The element may be otherwise oriented (rotated 90 degrees or in other orientations), and the relative spatial descriptions used herein may be interpreted accordingly.

[0013] A transistor and a method of manufacturing the same are provided according to many exemplary embodiments. Intermediate processes of manufacturing a transistor are illustrated according to many embodiments. Some variations of some embodiments will be discussed below. In many of the figures and illustrated embodiments, like element symbols are used to designate like elements. In the illustrated exemplary embodiments, the formation of a fin field-effect transistor (FinFET) is used to illustrate the concepts of the present disclosure. However, the concepts of the present disclosure may also be applied to planar transistors.

[0014] Figures 1 to 26 A perspective view and a cross-sectional view of an intermediate process of forming a fin field-effect transistor are illustrated according to some embodiments of the present disclosure. Figures 1 to 26 The operation of may also be schematically reflected in Figure 27 the process flow diagram of.

[0015] Figure 1 A perspective view of an initial structure is illustrated. The initial structure includes a wafer 10, which further includes a substrate 20. The substrate 20 may be a semiconductor substrate, which may be a substrate formed of a silicon substrate, a silicon germanium substrate, or other semiconductor materials. The substrate 20 may be doped with p-type impurities or n-type impurities. An isolation region 22, such as a shallow trench isolation (STI), may be formed and extend from the top surface of the substrate 20 into the substrate 20. A portion of the substrate 20 between adjacent shallow trench isolation regions 22 may be regarded as a semiconductor strip 24. In some exemplary embodiments, the top surface of the semiconductor strip 24 and the top surface of the shallow trench isolation region 22 may be substantially flush with each other.

[0016] The shallow trench isolation region 22 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer, which is formed, for example, by atomic layer deposition, high density plasma chemical vapor deposition, or chemical vapor deposition. The shallow trench isolation region 22 may also include a dielectric material located above the liner oxide, and the dielectric material may be formed by a process such as flowable chemical vapor deposition, spin coating, or the like.

[0017] Please refer to Figure 2 , the shallow trench isolation region 22 is recessed such that the upper portion of the semiconductor strip 24 protrudes and is higher than the top surface of the shallow trench isolation region 22 to form a protruding fin 24'. A portion of the semiconductor strip 24 located in the shallow trench isolation region 22 is still regarded as the semiconductor strip. The above etching may be performed using a dry etching process, where hydrogen fluoride (HF3) and ammonia (NH3) may be used as etching gases. During the etching process, plasma may be generated. Argon may also be included therein. According to some other embodiments of the present disclosure, the recessing of the shallow trench isolation region 22 may be performed using a wet etching process. And the etching chemical may include, for example, hydrofluoric acid (HF).

[0018] Please refer to Figure 3 , a dummy gate stack 30 is formed on the top surface and sidewalls of the protruding fin 24'. It should be understood that although two dummy gate stacks 30 are shown for clarity, a single or more than two dummy gate stacks may be formed, each dummy gate stack being parallel to each other, and the multiple dummy gate stacks intersecting the same one or more semiconductor fins 24'. The dummy gate stack 30 may include a dummy gate dielectric layer 32 and a dummy gate electrode 34 located above the dummy gate dielectric layer 32. The dummy gate electrode 34 may be formed of, for example, polysilicon, and other materials may also be used to form it. Each dummy gate stack 30 may also include one (or more) hard mask layers 36, and the hard mask layer 36 is located above the respective dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon carbo-nitride, or the like. The dummy gate stack 30 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fin 24'.

[0019] Next, gate spacer walls 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacer walls 38 are formed of a dielectric material such as silicon carbonitride (SiCN), silicon nitride, or the like, and the gate spacer walls 38 may have a single-layer structure or a multi-layer structure including multiple dielectric layers.

[0020] According to some embodiments, each gate spacer 38 includes a low dielectric constant dielectric layer 38A and a non-low dielectric constant dielectric layer 38B. Each of the low dielectric constant dielectric layer 38A and the non-low dielectric constant dielectric layer 38B is formed through a blanket deposition operation followed by an anisotropic etching operation. The low dielectric constant dielectric layer 38A can be formed of a low dielectric constant material having a dielectric constant (k value) below about 3.5, and the k value of the low dielectric constant dielectric layer 38A can be reduced by forming silicon oxynitride (SiON) or silicon oxycarbonitride (SiOCN) having holes formed therein to achieve a predetermined low dielectric constant value. The non-low dielectric constant dielectric layer 38B can be formed of, for example, silicon nitride.

[0021] Next, an etching operation (equivalent to the operation of forming the recessed source / drain described later) is performed to etch a portion of the protruding fin 24' that is not covered by the dummy gate stack 30 and the gate spacer 38, resulting in a structure as Figure 4 shown. The recess can be anisotropic, so that a portion of the protruding fin 24' directly under the dummy gate stack 30 and the gate spacer 38 is protected from etching. According to some embodiments, the top surface of the recessed semiconductor strip 24 can be lower than the top surface 22A of the shallow trench isolation region 22. The recess 40 is thus formed between the shallow trench isolation regions 22. The recess 40 is located on opposite sides of the dummy gate stack 30.

[0022] Next, in an epitaxial operation, a source / drain region is formed by selectively growing a semiconductor material in the recess 40, resulting in a structure as Figure 5A shown. According to some exemplary embodiments, the source / drain region 42 includes silicon germanium or silicon. Depending on whether the resulting fin field effect transistor is a p-type fin field effect transistor or an n-type fin field effect transistor, a p-type impurity or an n-type impurity can be doped in-situ during the epitaxial operation. For example, when the resulting fin field effect transistor is a p-type fin field effect transistor, silicon germanium boron (SiGeB) can be grown. Conversely, when the resulting fin field effect transistor is an n-type fin field effect transistor, silicon phosphide (SiP) or silicon carbon phosphide (SiCP) can be grown. According to other embodiments of the present disclosure, the epitaxial region 42 can be formed of a group III-V compound semiconductor, such as gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium antimonide (GaSb), aluminum antimonide (AlSb), aluminum arsenide (AlAs), aluminum phosphide (AlP), gallium phosphide (GaP), combinations of the above, or multiple layers. After the source / drain region 42 fills the recess 40, the source / drain region 42 begins to expand horizontally, thereby forming multiple facets.

[0023] After the epitaxial operation, the source / drain region 42 can be further implanted with p-type or n-type impurities to increase the impurity concentration of the source / drain region 42. According to some other embodiments of the present disclosure, when the source / drain region 42 is in-situ doped with p-type or n-type impurities during the epitaxial process, the implantation operation can be skipped. The source / drain region 42 can include a lower portion formed in the shallow trench isolation region 22 and an upper portion formed above the top surface 22A of the shallow trench isolation region 22.

[0024] Figure 5B According to other embodiments, the formation of the source / drain region 42 is illustrated, where the protruding fin 24' is not recessed, and the epitaxial region 41 grows epitaxially on the exposed protruding fin 24'. Therefore, the source / drain region (which is also represented by the element symbol 42) includes the epitaxial region 41 and a part of the corresponding protruding fin 24', and both the epitaxial region 41 and the part of the protruding fin 24' are implanted to increase their impurity concentrations.

[0025] Figure 6A A perspective view showing the structure when the Contact Etch Stop Layer (CESL) 47 and the Inter-Layer Dielectric (ILD) 46 are formed. According to some embodiments of the present disclosure, a buffer oxide layer (not shown) and the contact etch stop layer 47 are formed on the source / drain region 42. The buffer oxide layer can be formed of silicon oxide, and the contact etch stop layer 47 can be formed of silicon nitride, silicon carbonitride, or the like. The buffer oxide layer and the contact etch stop layer 47 can be formed, for example, using a conformal deposition method of atomic layer deposition. The inter-layer dielectric layer 46 can include a dielectric material formed using a deposition method such as flowable chemical vapor deposition, spin coating, chemical vapor deposition, or other suitable deposition methods. The inter-layer dielectric layer 46 can be formed of tetraethyl orthosilicate (TEOS) oxide, plasma-enhanced chemical vapor deposition oxide (such as SiO2), phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass (BPSG), or the like. A planarization operation such as Chemical Mechanical Polish (CMP) or Mechanical Grinding can be performed to make the top surfaces of the inter-layer dielectric layer 46, the contact etch stop layer 47, the dummy gate stack 30, and the gate spacer 38 flush with each other.

[0026] Figure 6A The cross-sectional view of the shown structure is illustrated in Figure 6B where the cross-sectional view is taken from a plane containing Figure 6Aobtained from a vertical plane of line segment A-A. In the cross-sectional view, two of the plurality of dummy gate stacks 30 are shown, and source / drain regions 42 formed between adjacent dummy gate stacks 30 are shown. It should be noted that more dummy gate stacks 30 and source / drain regions 42 can be formed. In addition, according to some embodiments, the top surface of the source / drain region 42 can be higher than the bottom surface of the dummy gate stack 30.

[0027] Next, the dummy gate stack 30 is replaced with a replacement gate stack, and the replacement gate stack includes a metal gate and a replacement gate dielectric layer, as Figures 7 to 10 shown. Figures 7 to 10 and as described later Figures 11 to 26 The cross-sectional views shown are all obtained from the same vertical plane containing line segment A-A in Figure 6A . In Figures 7 to 26 , a contour line 22A of the top surface of the shallow trench isolation region 22 is shown, and the semiconductor fin 24' is located above the contour line 22A.

[0028] When Figure 6A and Figure 6B the replacement gate stack, hard mask layer 36, dummy gate electrode 34, and dummy gate dielectric layer 32 shown are first removed in one or more etching operations, resulting in Figure 7 a trench / openings 48 in. The individual operations are shown as operation 202 of the process flow diagram as Figure 27 . The top surface and sidewalls of the protruding semiconductor fin 24' (not in the plane shown) are exposed to the trench 48.

[0029] Figure 8 The formation of the gate spacer 50 is shown according to some embodiments. The individual operations are shown as operation 204 of the process flow diagram as Figure 27 . According to other embodiments, the gate spacer 50 is not formed. To form the gate spacer 50, for example: a deposition method such as atomic layer deposition or chemical vapor deposition is used to form one or more blanket gate spacer layers. The blanket gate spacer layer is conformal. According to some embodiments of the present disclosure, the gate spacer is formed of silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), oxycarbide nitride, or other dielectric materials. The blanket gate spacer layer is etched in an anisotropic etch to remove the horizontal portions, and the remaining vertical portions form the gate spacer 50. The gate spacer 50 further separates the subsequently formed metal gate and the source / drain region, reducing the possibility of leakage and electrical short circuit between the metal gate and the source / drain region.

[0030] According to some embodiments, the gate spacer wall 50 is formed of a low dielectric constant material, which may have a dielectric constant (k value) lower than about 3.5 or 3.0. In this specification, silicon dioxide (SiO2) with a k value of about 3.9 is used to distinguish low k values and high k values. Therefore, a k value lower than 3.8 is regarded as a low k value, and an individual dielectric material is regarded as a low dielectric constant material. Conversely, a k value higher than 3.9 is regarded as a high k value, and an individual dielectric material is regarded as a high dielectric constant material. For example, the gate spacer wall 50 can be formed by forming porous silicon oxynitride (SiON) or silicon oxycarbonitride (SiOCN) to have a predetermined low k value. The formation of the low dielectric constant material spacer wall 50 is beneficial to reducing the parasitic capacitance between the subsequently formed metal gate and the source / drain regions 42.

[0031] Each gate spacer wall 50 can be formed of a single layer having a homogeneous dielectric material, or formed of multiple dielectric layers of different dielectric materials. For example, the gate spacer wall 50 can include a sub-layer 50A formed of a low dielectric constant material and a sub-layer 50B formed of silicon dioxide or a high dielectric constant material. The formation process includes depositing a conformal dielectric layer and performing anisotropic etching to form the sub-layer 50A, and then depositing another conformal dielectric layer and performing another anisotropic etching to form the sub-layer 50B.

[0032] Next, please refer to Figure 9 , to form (replace) the gate dielectric layer 52, which extends into the trench 48 ( Figure 8 ). The individual operations are illustrated as operation 206 of the process flow diagram as Figure 27 . According to some embodiments of the present disclosure, the gate dielectric layer 52 includes an interfacial layer (IL) 54 as the lower part of the gate dielectric layer 52. The interfacial layer 54 is formed on the exposed surface of the protruding fin 24'. The interfacial layer 54 can include an oxide layer such as a silicon dioxide layer, which can be formed by thermally oxidizing the protruding fin 24', a chemical oxidation process, or a deposition process. The gate dielectric layer 52 can also include a high dielectric constant layer 56 formed above the interfacial layer 54. The high dielectric constant layer 56 includes a high dielectric constant material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like. The dielectric constant (k value) of the high dielectric constant material is higher than 3.9, and can be higher than about 7.0. The high dielectric constant layer 56 is located above the interfacial layer 54 and can contact the interfacial layer 54. The high dielectric constant layer 56 can be formed as a conformal layer and extends on the sidewalls of the protruding fin 24' and the top surface and sidewalls of the gate spacer wall 38 / 50. According to some embodiments of the present disclosure, the high dielectric constant layer 56 is formed using atomic layer deposition or chemical vapor deposition.

[0033] Refer again to Figure 9, the stacked layer is deposited. The individual operations are shown as operation 208 in the process flow diagram as Figure 27 . The sub-layers in the stacked layer 58 are not separately shown, however, the above-mentioned sub-layers are distinguishable from each other. A conformal deposition method such as atomic layer deposition or chemical vapor deposition can be used for deposition, so that the thickness of the vertical part and the horizontal part of the stacked layer 58 (and each sub-layer) is substantially the same as each other. The stacked layer 58 extends into the trench 48 ( Figure 8 ), and the stacked layer 58 includes some parts located above the interlayer dielectric layer 46.

[0034] The stacked layer 58 may include a diffusion barrier layer and one (or more) work function layers located above the above-mentioned barrier layer. The diffusion barrier layer can be formed of titanium nitride (TiN), and the titanium nitride may or may not be doped with silicon. The work function layer determines the work function of the gate, and the work function layer includes at least one layer or a plurality of layers formed of different materials. According to whether the individual fin field effect transistor is an n-type fin field effect transistor or a p-type fin field effect transistor, the material of the work function layer is selected. For example: when the fin field effect transistor is an n-type fin field effect transistor, the work function layer may include a tantalum nitride (TaN) layer and a titanium aluminum (TiAl) layer above the tantalum nitride layer. When the fin field effect transistor is a p-type fin field effect transistor, the work function layer may include a tantalum nitride layer, a titanium nitride layer above the tantalum nitride layer, and a titanium aluminum layer above the titanium nitride layer. After depositing one or more work function layers, another barrier layer is formed, and the barrier layer can be another layer of titanium nitride layer.

[0035] Next, the metal material 60 is deposited, which can be formed of tungsten or cobalt, for example. The metal material 60 fills the remaining trench 48 ( Figure 8 ). In the subsequent operations shown in Figure 10 , a planarization operation such as chemical mechanical polishing or mechanical polishing can be performed, so that a part of the high-k layer 56, the stacked layer 58, and the metal material layer 60 located above the interlayer dielectric layer 46 can be removed. The individual operation is shown as operation 210 in the process flow diagram as Figure 27 . Thus, the metal gate electrode 62 is formed, which can include the remaining part of the stacked layer 58 and the metal material layer 60. The remaining part of the gate dielectric layer 52, the stacked layer 58, and the metal material layer 60 are hereafter regarded as the replacement gate stack 64. As shown in Figure 10 , the top surfaces of the metal gate 62, the spacer 38 / 50, the contact etch stop layer 47, and the interlayer dielectric layer 46 can be substantially coplanar at this time.

[0036] According to other embodiments, the recessed gate stack 64 is formed to create a recess between opposite portions of the gate spacer walls 38 / 50, and a dielectric hardmask (such as silicon nitride, not shown) is filled into the recess and then planarized such that the dielectric hardmask, spacer walls 38 / 50, contact etch stop layer 47, and interlayer dielectric layer 46 are substantially coplanar at this time.

[0037] In Figure 10 , the dashed line (labeled 64 / 50) is shown aligned with the outer edge of the gate spacer wall 50 to indicate that the gate spacer wall 50 and replacement gate stack 64 extend under the top surface of the illustrated semiconductor fin 24' and along the sidewalls of the semiconductor fin 24'. The dashed line represents those portions of the gate spacer wall 50 and replacement gate stack 64 that are not in the illustrated plane. Additionally, although not shown, the gate spacer wall 38 may also extend along the sidewalls of the semiconductor fin 24', as Figure 3 shown.

[0038] Figures 11 to 26 The formation of source / drain contact plugs and gate contact plugs is illustrated. In the example shown, three source / drain regions 42 are shown, and the formation of a source / drain contact plug connected to the leftmost source / drain region 42 is disclosed in the illustrated process. In an actual process, source / drain contact plugs connected to the central and rightmost source / drain regions 42 may also be formed. However, these source / drain contact plugs are formed in a plane different from the illustrated plane and are thus not visible. Similarly, although a single gate contact plug located directly above the right gate stack 64 is shown, there may also be a gate contact plug located directly above the left gate stack 64 and connected to the left gate stack 64, which is in a plane different from the illustrated plane and is thus not shown in the figure.

[0039] Please refer to Figure 11 , an interlayer dielectric layer 68 is formed over a dielectric hardmask (not shown). The material of the interlayer dielectric layer 68 may be selected from the same candidate materials (and methods) as those used to form the interlayer dielectric layer 46, and the interlayer dielectric layer 46 and interlayer dielectric layer 68 may be formed of the same or different dielectric materials. For example, the interlayer dielectric layer 68 may be formed using plasma enhanced chemical vapor deposition and may include silicon oxide (SiO2). There may or may not be a distinguishable interface between the interlayer dielectric layer 46 and the interlayer dielectric layer 68. The thickness of the interlayer dielectric layer 68 may be from about to about

[0040] Then, a metal hard mask 70 serving as an etch mask in subsequent etching is formed over the interlayer dielectric layer 68. The metal hard mask 70 can be formed of a metal nitride such as titanium nitride. Thereafter, a pad oxide layer 72 formed of silicon oxide is formed over the hard mask layer 70. Then, photoresist 74 is applied and patterned to form an opening 76.

[0041] Then, the patterned photoresist 74 is used to etch the underlying pad oxide layer 72 and metal hard mask 70 such that the opening 76 extends into the metal hard mask 70. Next, the photoresist 74 is removed, for example, in an ashing process. Then, the remaining pad oxide layer 72 and metal hard mask 70 are used as an etch mask to etch the interlayer dielectric layer 68, the interlayer dielectric layer 46, and the contact etch stop layer 47 to form a source / drain contact opening 78, as Figure 12 shown. The individual operations are illustrated as operation 212 of the process flow diagram as Figure 27 shown. In etching the interlayer dielectric layer 68 and the interlayer dielectric layer 46, the contact etch stop layer 47 is used as an etch stop layer, and the contact etch stop layer 47 is then etched to expose the underlying source / drain region 42.

[0042] Please refer to Figure 13 , a dielectric layer 80 is formed, for example, using a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The dielectric layer 80 can be a high-k dielectric layer having a k value greater than 3.9 such that the dielectric layer 80 has good isolation properties. Candidate materials include aluminum oxide (Al x O y ), hafnium oxide (HfO2), silicon nitride (SiN), and silicon oxycarbonitride (SiOCN) (without holes or substantially no holes inside). The thickness of the dielectric layer 80 can be from about 2 nm to about 4 nm.

[0043] Thereafter, anisotropic etching is performed such that the horizontal portions of the dielectric layer 80 are removed, and the remaining vertical portions on the sidewalls of the opening 78 form contact spacer 82 which forms a ring when viewed from above the wafer 10. The resulting structure is as Figure 14 shown. The individual operations are illustrated as operation 214 of the process flow diagram as Figure 27 shown. According to some other embodiments, the formation of the contact spacer 82 can be skipped.

[0044] Figures 15 to 18 The formation of the lower source / drain contact plug is illustrated. The individual operations are illustrated as operation 216 of the process flow diagram as Figure 27 shown. Please refer to Figure 15, a metal layer 84 (such as a titanium layer or a cobalt layer) is deposited, for example, using physical vapor deposition. Then, a barrier layer 86 is formed over the metal layer 84. The barrier layer 86 can be a metal nitride layer such as a titanium nitride layer or a tantalum nitride layer. The barrier layer 86 can be formed by nitriding the top layer of the metal layer 84 while leaving the lower layer of the metal layer 84 un-nitrided, or the barrier layer 86 can be formed by using a deposition method such as chemical vapor deposition. Both the metal layer 84 and the barrier layer 86 are conformal and extend into the opening 78.

[0045] Then, annealing is performed to form source / drain silicide regions 88 as Figure 16 shown. The above annealing can be performed through rapid thermal annealing, furnace annealing, or similar processes. Thus, the lower portion of the metal layer 84 reacts with the source / drain regions 42 to form the silicide regions 88. After the silicidation process, the sidewall portions of the metal layer 84 remain. According to some embodiments of the present disclosure, the top surface of the silicide region 88 contacts the bottom surface of the barrier layer 86.

[0046] Next, as Figure 17 shown, a metallic material 90 is deposited over and in contact with the barrier layer 86. The metallic material 90 can be selected from the same group as the candidate materials for the metal-containing material 60 and can include tungsten or cobalt. Then, a planarization process such as chemical mechanical polishing or mechanical polishing is performed to remove a portion of the metal layer 84, the barrier layer 86, and the metallic material layer 90 located above the interlayer dielectric layer 68. The resulting structure is as Figure 18 shown, and the structure can include source / drain contact plugs 92.

[0047] Figure 19 Illustrates the formation of an etch stop layer 94 and an interlayer dielectric layer 96. The individual operations are illustrated as the operation 218 of the process flow diagram as Figure 27 shown. The etch stop layer 94 can be formed of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, or the like, and the etch stop layer 94 can be formed using a deposition method such as chemical vapor deposition. The interlayer dielectric layer 96 can include a material selected from phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass, tetraethyl orthosilicate oxide, or plasma-enhanced chemical vapor deposition oxide (silicon oxide (SiO2)). The interlayer dielectric layer 96 can be formed using spin coating, flowable chemical vapor deposition, or similar methods, or the interlayer dielectric layer 96 can be formed using a deposition method such as plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition.

[0048] Please refer to Figure 20, the interlayer dielectric layer 96 and the etch stop layer 94 are etched to form an opening 98. According to some embodiments of the present disclosure, the opening 98 has a high aspect ratio (the ratio of height to width), which may be greater than about 4.0 or higher. The opening may be narrow such that a first portion of the surface of the metal gate electrode 62 is exposed, and a second portion of the metal gate electrode 62 remains covered by the interlayer dielectric layer 68. During the operation of the fabricated transistor, since a voltage is applied to the metal gate electrode 62 but no current flows through it, the contact area between the metal gate electrode 62 and the upper gate contact plug may be small and does not significantly affect the performance of the transistor. Therefore, making the opening 98 narrow is beneficial for reducing the size of the transistor without sacrificing electrical performance.

[0049] In a subsequent operation, the opening 98 is filled with one or more conductive materials 102, such as Figure 21 shown. The conductive material 102 has good void filling ability, so no voids are generated in the conductive material 102. According to some embodiments, the conductive material 102 may be formed of a metal nitride such as titanium nitride, and the forming method may include, for example, physical vapor deposition. Although titanium nitride has a high resistivity (higher than that of metals), the high resistivity does not significantly affect the performance of the transistor because the transistor is used to apply voltage rather than current. According to other embodiments, the conductive material 102 may be formed of other materials such as tungsten.

[0050] The conductive material 102 may be homogeneous, and the entire conductive material 102 has the same composition and may be formed of homogeneous titanium nitride or homogeneous tungsten. In other embodiments, the conductive material 102 has a composite structure, for example, including: a barrier layer 102A and a metallic material 102B. For example: the barrier layer 102A may be formed of titanium nitride, and the metallic material 102B may be formed of tungsten. The conductive material 102 does not contain cobalt because cobalt has insufficient void filling ability, and if cobalt is filled into the opening 98 ( Figure 20 ), voids may be generated therein due to the high aspect ratio of the individual openings.

[0051] According to some embodiments, a planarization operation such as chemical mechanical polishing or mechanical polishing is performed to remove the excess conductive material 102 to form a gate contact plug 104, such as Figure 22 shown. The individual operations are illustrated as Figure 27Operation 220 of the process flow diagram. The top surface of the gate contact plug 104 is thus coplanar with the top surface of the dielectric layer 96. According to some other embodiments, an etch-back process is performed to remove excessive conductive material 102. The resulting top surface of the gate contact plug 104 can thus be higher than, coplanar with, or lower than the top surface of the interlayer dielectric layer 96. The dashed line 106 schematically depicts the position of the top surface of the gate contact plug 104 when the top surface of the gate contact plug 104 is not coplanar with the top surface of the interlayer dielectric layer 96.

[0052] Please refer to Figure 23 , the interlayer dielectric layer 96 and the etch stop layer 94 are etched to form source / drain contact openings 108. The above etching operation is performed by a first stage etch that stops on the etch stop layer 94 and a second stage etch that stops on the source / drain contact plug 92 and the interlayer dielectric layer 68. The opening 108 can have a width W1, and the width W1 is greater than the width W2 of the underlying source / drain contact plug 92. Thus, the entire top surface of the source / drain contact plug 92 is used to contact the upper source / drain contact plug 114 ( Figure 25 ), so the contact resistance between the source / drain contact plug 92 and the source / drain contact plug 114 is reduced. Furthermore, the width W1 is greater than the width W3 of the gate contact plug 104, and the width W1 can be about 1.2 times greater than the width W3. The W1 / W3 ratio can also be about 1.2 to 2.0.

[0053] Next, one or more conductive materials are deposited into the opening 108, as Figure 24 shown. The conductive materials 110 / 112 are different from the material forming the gate contact plug 104. Since the opening 108 has a low aspect ratio, the void filling of the opening 108 is simple, and the conductive materials 110 / 112 do not have to have good void filling ability. However, the resistivity ρ2 of the conductive materials 110 / 112 is preferably low to conduct the source / drain current. The resistivity ρ2 is lower than the resistivity ρ1 of the gate contact plug 104.

[0054] According to some embodiments of forming the conductive materials 110 / 112, a blanket barrier layer 110 is first deposited, and then a metal-containing material 112 is deposited on top of the blanket barrier layer 110. The barrier layer 110 can be formed of a metal nitride such as titanium nitride or tantalum nitride. The metal-containing material 112 is formed of a material selected from tungsten, ruthenium, cobalt, copper, or an alloy thereof. The method of forming the metal-containing material 112 can be selected from chemical vapor deposition, physical vapor deposition, or similar processes. According to some embodiments, where the metal-containing material 112 contains cobalt, the conductive material 102 preferably does not include tungsten, and the conductive material 102 can be formed of homogeneous titanium nitride. This is because in such as Figure 25In the subsequent planarization shown, the gate contact plug 104 is also planarized, for example, using chemical mechanical polishing. The slurry for chemical mechanical polishing of cobalt may cause unintended excessive recess of tungsten (if used in the gate contact plug 104).

[0055] Next, refer to Figure 25 , and perform a planarization operation such as chemical mechanical polishing or mechanical polishing to remove the excessive barrier layer 110 and the metal-containing material 112 to form the source / drain contact plug 114. The individual operations are shown as operation 222 of the process flow diagram in Figure 27 . In this specification, the source / drain contact plug 92 and the source / drain contact plug 114 are regarded as the lower source / drain contact plug and the upper source / drain contact plug, respectively. The fabrication of the fin field effect transistor 120 is thus completed.

[0056] In some embodiments, where the gate contact plug 104 ( Figure 22 ) is recessed, as shown by the dashed line 106, a portion of the barrier layer 110 is filled into the recess of the contact plug 104. The metal-containing material 112 may or may not be filled into the recess of the contact plug 104, where the barrier layer 110 (with or without the metal-containing material 112) is left as part of the fin field effect transistor 120.

[0057] In a subsequent operation, an interconnect structure is formed. For example, as shown in Figure 26 , an etch stop layer 122 and an inter-metal dielectric (IMD) 124 are formed. The inter-metal dielectric layer 124 may be formed of a low dielectric constant material. Metal lines 126 and 130 may be formed in the inter-metal dielectric layer 124, and the metal lines 126 and 130 are connected to the source / drain contact plug 114 and the gate contact plug 104 through contact windows 128 and 132, respectively.

[0058] Embodiments of the present disclosure have some advantageous features. The gate contact plug (104) may have an aspect ratio higher than that of the source / drain contact plug (114), so it is difficult to avoid voids when filling the voids of the gate contact plug 92. Accordingly, the gate contact plug is formed using a material with good void filling ability. However, the resistivity of the gate contact plug is not very restrictive because the gate contact plug is used to apply voltage rather than conduct current. On the contrary, the source / drain contact plug is preferably of low resistivity because it is used to conduct current. However, the void filling ability of the source / drain contact plug does not need to be highly required because the source / drain contact plug according to some embodiments of the present disclosure has a low aspect ratio. Accordingly, a material with a low resistivity value is selected to form the source / drain contact plug, but the void filling ability of the material of the source / drain contact plug is not very restricted. According to some embodiments of the present disclosure, the gate contact plug and the source / drain contact plug are formed in different processes and are formed using different materials to meet their different requirements.

[0059] According to some embodiments of the present disclosure, the method includes forming a transistor, which includes forming source / drain regions on one side of a dummy gate stack, forming a first interlayer dielectric layer covering the source / drain regions, and replacing the dummy gate stack with a replacement gate stack. The above method further includes forming a second interlayer dielectric layer above the first interlayer dielectric layer and the replacement gate stack, and forming a lower source / drain contact plug that is electrically coupled to the source / drain regions. The lower source / drain contact plug passes through the first interlayer dielectric layer and the second interlayer dielectric layer. A third interlayer dielectric layer is formed above the second interlayer dielectric layer. A gate contact plug is formed in the second interlayer dielectric layer and the third interlayer dielectric layer. An upper source / drain contact plug is formed to overlap and contact the lower source / drain contact plug. The upper source / drain contact plug passes through the third interlayer dielectric layer. The upper source / drain contact plug and the gate contact plug are formed of different materials.

[0060] According to an embodiment of the present disclosure, the aspect ratio of the gate contact plug is greater than the aspect ratio of the upper source / drain contact plug, and the gate contact plug has a resistivity higher than that of the upper source / drain contact plug.

[0061] According to an embodiment of the present disclosure, the upper source / drain contact plug and the gate contact plug are formed through separate processes.

[0062] According to an embodiment of the present disclosure, the entire gate contact plug is formed by depositing a homogeneous material, and the upper source / drain contact plug is formed by depositing a composite structure, and the composite structure includes a lower layer and an upper layer located above the lower layer.

[0063] According to an embodiment of the present disclosure, the entirety of the gate contact plug is formed of a metal nitride.

[0064] According to an embodiment of the present disclosure, the entirety of the gate contact plug is formed of titanium nitride.

[0065] According to an embodiment of the present disclosure, the operation of replacing the dummy gate stack with the replacement gate stack includes removing the dummy gate stack to form a trench in the first interlayer dielectric layer; forming gate sidewalls in the trench; and forming the replacement gate stack in the trench.

[0066] According to an embodiment of the present disclosure, the operation of forming the lower source / drain contact plug includes etching the second interlayer dielectric layer and the first interlayer dielectric layer to form a source / drain contact opening; forming contact sidewalls in the source / drain opening; and filling the source / drain opening with a metal material to form the lower source / drain contact plug.

[0067] According to an embodiment of the present disclosure, the operation of forming the contact sidewalls includes forming high-k sidewalls.

[0068] According to some embodiments of the present disclosure, the method includes forming a transistor having a gate stack and source / drain regions located on one side of the gate stack, wherein the gate stack is located in a first interlayer dielectric layer; and forming a lower source / drain contact plug that is electrically coupled to the source / drain regions. In a first process operation, a gate contact plug is formed above and in contact with the gate stack. In a second process operation, an upper source / drain contact plug is formed to overlap and contact the lower source / drain contact plug. An etch stop layer is formed above the upper source / drain contact plug and the gate contact plug and contacts the upper source / drain contact plug and the gate contact plug.

[0069] According to an embodiment of the present disclosure, the above manufacturing method further includes depositing a second interlayer dielectric layer above the first interlayer dielectric layer before forming the upper source / drain contact plug and the gate contact plug; and depositing a third interlayer dielectric layer above the second interlayer dielectric layer, wherein the lower source / drain contact plug passes through the first interlayer dielectric layer and the second interlayer dielectric layer, the gate contact plug passes through the second interlayer dielectric layer and the third interlayer dielectric layer, and the upper source / drain contact plug passes through the third interlayer dielectric layer.

[0070] According to an embodiment of the present disclosure, the aspect ratio of the gate contact plug is greater than the aspect ratio of the upper source / drain contact plug, and the gate contact plug has a higher resistivity than the upper source / drain contact plug.

[0071] According to an embodiment of the present disclosure, the entire gate contact plug is formed of a homogeneous material, the upper source / drain contact plug has a composite structure, and the composite structure includes a lower layer and an upper layer located above the lower layer.

[0072] According to an embodiment of the present disclosure, the entire gate contact plug is formed of a metal nitride.

[0073] According to an embodiment of the present disclosure, the operation of forming the lower source / drain contact plug includes etching the first interlayer dielectric layer to form a source / drain contact opening; forming a contact spacer in the source / drain contact opening; and filling the source / drain contact opening with a metal material.

[0074] According to an embodiment of the present disclosure, the operation of forming the contact spacer includes forming a high-k spacer.

[0075] According to some embodiments of the present disclosure, the device includes a first interlayer dielectric layer, a gate stack in the first interlayer dielectric layer, a second interlayer dielectric layer above the first interlayer dielectric layer, source / drain regions adjacent to the gate stack, and a lower source / drain contact plug located above the source / drain regions and coupled to the source / drain regions. The lower source / drain contact plug penetrates the first interlayer dielectric layer and the second interlayer dielectric layer. The upper source / drain contact plug is located above the lower source / drain contact plug and contacts the lower source / drain contact plug. The gate contact plug is located above the gate stack and contacts the gate stack. The upper source / drain contact plug and the gate contact plug are formed of different materials.

[0076] According to an embodiment of the present disclosure, the upper source / drain contact plug and the gate contact plug have different resistance values.

[0077] According to an embodiment of the present disclosure, the entire gate contact plug is formed of a homogeneous material.

[0078] According to the above embodiments of the present disclosure, the device having a plurality of contact plugs further includes a dielectric contact spacer surrounding the lower source / drain contact plug.

[0079] The foregoing outlines the features of multiple embodiments so that those of ordinary skill in the art can further understand aspects of the present disclosure. Those of ordinary skill in the art should be able to readily use the present disclosure as a basis to design or modify other processes and structures to achieve the same purposes and / or advantages as those described in the embodiments herein. Those of ordinary skill in the art should also understand that the above equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can be modified, substituted, or replaced without departing from the spirit and scope of the present disclosure.

Claims

1. A manufacturing method of a plurality of contact plugs, characterized in that, Comprising: Forming a transistor including a gate stack and a source / drain region located at one side of the gate stack, wherein the gate stack is located in a first interlayer dielectric layer; Forming a lower source / drain contact plug, wherein the lower source / drain contact plug is electrically coupled to the source / drain region; Forming a gate contact plug above the gate stack and contacting the gate stack; Forming an upper source / drain contact plug, wherein the upper source / drain contact plug overlaps and contacts the lower source / drain contact plug, an aspect ratio of the gate contact plug is greater than an aspect ratio of the upper source / drain contact plug, and the gate contact plug has a resistivity higher than that of the upper source / drain contact plug, wherein a width of the upper source / drain contact plug is greater than a width of the lower source / drain contact plug and greater than a width of the gate contact plug; And Forming an etch stop layer above the upper source / drain contact plug and the gate contact plug, wherein the etch stop layer contacts the upper source / drain contact plug and the gate contact plug.

2. The manufacturing method of the plurality of contact plugs according to claim 1, characterized in that, Further comprising: Depositing a second interlayer dielectric layer above the first interlayer dielectric layer before forming the upper source / drain contact plug and the gate contact plug; and Depositing a third interlayer dielectric layer above the second interlayer dielectric layer, wherein the lower source / drain contact plug penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer, the gate contact plug penetrates through the second interlayer dielectric layer and the third interlayer dielectric layer, and the upper source / drain contact plug penetrates through the third interlayer dielectric layer.

3. The manufacturing method of the plurality of contact plugs according to claim 1, characterized in that, The upper source / drain contact plug and the gate contact plug are formed of different materials.

4. The manufacturing method of the plurality of contact plugs according to claim 1, characterized in that, The entirety of the gate contact plug is formed of a homogeneous material, the upper source / drain contact plug has a composite structure, and the composite structure includes a lower layer and an upper layer located above the lower layer.

5. The manufacturing method of the plurality of contact plugs according to claim 4, characterized in that, The entirety of the gate contact plug is formed of a metal nitride.

6. The manufacturing method of the plurality of contact plugs according to claim 5, characterized in that, The entirety of the gate contact plug is formed of titanium nitride.

7. The manufacturing method of the plurality of contact plugs according to claim 1, characterized in that, The operation of forming the lower source / drain contact plug includes: Etching the first interlayer dielectric layer to form a source / drain contact opening; Forming a contact spacer in the source / drain contact opening; and Filling the source / drain contact opening with a metal material.

8. The manufacturing method of the plurality of contact plugs according to claim 7, characterized in that, The operation of forming the contact spacer includes forming a high-k spacer.

9. The manufacturing method of the plurality of contact plugs according to claim 1, characterized in that, The upper source / drain contact plug and the gate contact plug are formed through separate processes.

10. The manufacturing method of the plurality of contact plugs according to claim 1, characterized in that, The transistor is a fin field effect transistor.

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