Wafer with ring for solder bump formation

Abstract

This invention relates to forming solder bumps using a wafer with a ring. At least one circuit element can be formed on the front side of the ring-shaped substrate, and the ring-shaped substrate can be mounted on a mounting chuck. The mounting chuck may have an inner raised portion and a recessed ring surrounding the periphery of the mounting chuck, the inner raised portion being configured to receive a thinned portion of the substrate thereon, and the recessed ring being configured to receive an outer ring of the ring-shaped substrate therein. At least one solder bump can be formed, and when the ring-shaped wafer is placed on the mounting chuck, the at least one solder bump is electrically connected to at least one circuit element.

Description

Technical Field

[0001] This specification relates to forming wafer-level solder bumps on a wafer having rings. Background Technology

[0002] In the integrated circuit (IC) industry, there is a constant effort to make devices more compact while maintaining or improving their operating characteristics. At the same time, there is a desire to improve the speed, reliability, and efficiency of related manufacturing processes.

[0003] For example, when forming integrated circuit devices, it may be desirable to use very thin substrates, such as silicon (Si) substrates. Besides enabling more compact devices, thin substrates offer other advantages, such as facilitating two-sided (e.g., top / bottom or front / back) processing. For instance, backside ion implantation becomes possible.

[0004] In addition, it may be desirable to use wafers with relatively large dimensions (and correspondingly larger surface areas). For example, larger wafer sizes (e.g., eight inches in diameter compared to four-inch or six-inch wafers) typically enable the formation of more devices per wafer and generally provide better wafer area utilization.

[0005] However, large and thin wafers are susceptible to thermal and mechanical stresses. Therefore, such large and thin wafers may be prone to warping, cracking, or breakage.

[0006] While techniques exist to mitigate or eliminate such difficulties, these techniques may limit or hinder other required processing steps. Therefore, in these and similar scenarios, it is difficult or impossible to form the desired device structures and aspects using known techniques. Summary of the Invention

[0007] According to one general aspect, a method of manufacturing a semiconductor device may include: forming at least one circuit element on the front side of an annular substrate, removing an inner portion of the back side of the annular substrate to obtain a thinned portion of the annular substrate, wherein an outer ring of remaining substrate material surrounds a periphery of the back side of the annular substrate. The method may include: mounting the annular substrate on a mounting chuck, wherein the mounting chuck has an inner protrusion and a recessed ring surrounding a periphery of the mounting chuck, the inner protrusion being configured to receive the thinned portion of the substrate thereon, and the recessed ring being configured to receive the outer ring of the annular substrate therein; and forming at least one solder bump when setting an annular wafer on the mounting chuck, the at least one solder bump being electrically connected to at least one circuit element.

[0008] According to another general aspect, a semiconductor device manufacturing assembly includes: a mounting assembly configured to support a wafer on its front side having at least one circuit element formed thereon, the wafer having a back side, wherein a ring is formed around the periphery of the back side and a thinning portion is formed within the ring; and a mounting chuck disposed on the mounting assembly. The mounting chuck may include a raised portion and a recessed portion, the raised portion being configured to receive the thinning portion of the wafer, and the recessed portion being configured to receive the ring of the wafer. The semiconductor device manufacturing assembly may include a mask configured to form at least one solder bump when the wafer is disposed on the mounting chuck, wherein the thinning portion of the wafer is located on the raised portion of the mounting chuck and the ring of the wafer is disposed within the recessed portion of the mounting chuck, the at least one solder bump being for electrical connection to at least one circuit.

[0009] According to another general aspect, the semiconductor device may include at least one integrated circuit formed on a substrate having a thickness of less than about 300 micrometers. The semiconductor device may also include at least one solder bump formed on the integrated circuit having a thickness greater than about 150 micrometers.

[0010] Details of one or more embodiments are set forth in the accompanying drawings and the following description. Other features will be apparent from the specification and drawings, as well as from the claims. Attached Figure Description

[0011] Figure 1A This is a block diagram of an exemplary embodiment of a solder bump mounting assembly.

[0012] Figure 1B It includes multiple circuit elements. Figure 1A A more detailed block diagram of the solder bump mounting assembly.

[0013] Figure 2 Is using Figures 1A to 1B A block diagram of an integrated circuit assembly formed by solder bump mounting components.

[0014] Figure 3 Shown in Figures 1A to 1B The wafer with rings used in the solder bump mounting assembly.

[0015] Figure 4 yes Figures 1A to 1B A more detailed example of an implementation of the solder bump mounting assembly.

[0016] Figure 5 Show Figures 1A to 1B Another exemplary implementation of the solder bump mounting assembly.

[0017] Figure 6 yes Figure 5 A diagram of the mounting chuck for the solder bump mounting assembly.

[0018] Figure 7 yes Figure 7 An enlarged illustration of the installation chuck.

[0019] Figure 8 It shows the use of Figures 1A to 1B To construct the solder bump mounting assembly Figure 2 A flowchart illustrating exemplary operation of the circuit components.

[0020] Figures 9A to 9I Showing the use Figures 1A to 1B An exemplary process flow for constructing a first exemplary circuit component using solder bump mounting components.

[0021] Figure 10 Show Figures 9A to 9I An exemplary result of an exemplary processing flow.

[0022] Figures 11A to 11H Is using Figures 1A to 1B An exemplary process flow for constructing a second exemplary circuit component using solder bump mounting components. Detailed Implementation

[0023] Figures 1A to 11H Exemplary operations and devices are shown for processing large, thin wafers to prevent wafer warping during processing and including the addition of wafer-level solder bumps for power interconnection. Therefore, integrated circuits can be produced quickly, reliably, and efficiently while obtaining the advantages of the included solder bumps (compared to other interconnect methods such as wire bonding and / or solder placement with reflow).

[0024] More specifically, as mentioned above, large, thin semiconductor wafers are susceptible to damage from mechanical and / or thermal stresses, including warping, chipping, or breakage. Such difficulties can be mitigated or eliminated by providing a temporary stabilizing ring around the perimeter of the large, thin wafer.

[0025] For example, a ring-shaped wafer can be obtained by grinding the inner portion of the wafer to a desired thinness while retaining (i.e., not grinding) an outer ring within a defined distance from the edge of the wafer. This ring can then be used to achieve stable handling and provide structural support, thereby preventing the wafer from warping, fracturing, or breaking during subsequent processing. The ring can then be removed before slicing the individual circuits or circuit elements on the wafer.

[0026] However, such ring-shaped wafers are typically formed and / or disposed of by mounting the raw (thicker) wafer on one side (e.g., the top side) using a tape or resin, and then grinding the inner portion of the opposite side (e.g., the bottom side) to form a stable ring around the periphery of the opposite, bottom side. This mounting tape, sometimes referred to as a back-grinding (BG) tape, prevents, hinders, or inhibits further processing steps relative to the top side on which the BG tape is mounted.

[0027] In particular, as detailed below, such BG bands hinder the formation of bonding solder bumps on the wafer top side, especially solder bumps with desired sizes ranging from approximately 100 to 150 micrometers or larger, such as 300 to 500 micrometers. Furthermore, as described in detail below, the option to add solder bumps during associated processing steps may be additionally limited by the temperature and other factors associated with performing those processing steps. In other words, for example, solder bumps may not be properly added during certain processing steps due to high temperatures that cause premature melting of the solder bumps, possible solder contamination from other chemicals used, or other disposal issues.

[0028] In contrast, Figure 1A In the figure, the bump mounting assembly 102 is shown to include a mounting chuck 104, which includes a raised portion 104a and a recessed ring 104b. As shown, the mounting chuck 104 is therefore configured to receive a substrate wafer or wafer 106 having a wafer ring 108 formed around its periphery. That is, the wafer ring 108 may be disposed within the recessed ring 104b, wherein a thinned or recessed portion of the wafer 106 covers the raised portion 104a, thereby fixing the annular wafer 106 relative to the mounting chuck 104.

[0029] Therefore, as shown, the annular wafer 106 can be mounted stably and reliably, thereby facilitating processing operations relative to the circuit elements 110. In the following description, the circuit elements 110 are described as being formed on one side of the annular wafer, referred to herein as the front or top side, which is opposite to the side of the annular wafer that is disposed on and secured by the mounting chuck 104 (referred to herein as the back or bottom side).

[0030] In particular, by using mounting chuck 104 to mount and secure the annular wafer 106, solder bumps 112 can be formed on the circuit element 110 in a flexible, efficient, and reliable manner. As described herein, the solder bump 112 may also be referred to as solder ball, solder ball, or other known or future designations, and can be understood to represent any discrete element of solder material that can be deposited on or otherwise provided to the circuit element 110.

[0031] like Figure 1BAs shown, the plurality of circuit elements shown as 110a, 110b, and 110c may each have corresponding solder bumps 112a, 112b, and 112c formed thereon. Therefore, the substrate 106 can be understood as having such a plurality of circuit elements 110a, 110b, and 110c formed in desired (various) manner over a surface region of the wafer 106. Further examples of forming a plurality of circuit elements on a ring-shaped wafer are described below, for example, with respect to… Figure 3 Show and describe.

[0032] During a later processing stage, wafer ring 108 can be removed, and wafer 106 can be sliced ​​using conventional techniques, thereby... Figure 1A Circuit element 110 or Figure 1B Circuit elements 110a, 110b, and 110c are connected to the remaining, thinned portion of wafer 106. Figure 2 The substrate shown is 202. Figure 2 As further shown, the substrate 202, circuit element 110, and solder bump 112 can be flip-chip mounted onto the circuit board 204. Other conventional techniques can be used to complete the solder joint process, including, for example, adding an adhesive underfill 206.

[0033] therefore, Figure 1A , Figure 1B and Figure 2 Show Figure 1A The mounting chuck 104 can be used to facilitate and enable top-side or front-side processing of annular wafers such as annular wafers 106, and includes forming solder bumps 112. As described above and detailed below, the mounting chuck 104 provides these and other advantages, including, for example, enabling top-side or front-side processing during a processing phase during (or after) that processing phase, and before being flipped to be mounted to circuit board 204, without subjecting the solder bumps 112 to unwanted thermal, chemical, mechanical, or other stresses.

[0034] Furthermore, as mentioned and described, the mounting chuck 104 achieves top-side or front-side processing of the wafer 106 by fixing the wafer 106, including the wafer ring 108, at a processing stage after the removal of the BG tape used to fix the wafer 106 during grinding of the wafer ring 108. Therefore, Figure 1A This method allows for the convenient use of various techniques for forming solder bumps 112, such as those described below relative to... Figure 4 The spherical mask technique shown and described.

[0035] In contrast, conventional techniques typically perform front-side processing before grinding the ring (such as ring 108). Then, during grinding, the BG ribbon is used to hold the wafer in place while the ring is being formed. If needed / desired, the BG ribbon can be held in place while certain back-side processing operations (such as back-side implantation or diffusion) are taking place.

[0036] In these and similar cases, once the BG band is removed, conventional techniques cannot properly secure the ring-shaped wafer for further front-side, wafer-level processing (such as adding solder bumps 112). Instead, conventional techniques attempt to add solder connections after removing the ring and / or after wafer slicing. Such methods are subject to numerous difficulties and challenges, such as the requirement for extremely precise (and error-prone) solder placement / formation for each board to be used with the circuitry of the wafer under consideration. Consequently, such techniques suffer from various difficulties, including potential solder short circuits (e.g., short circuits between two or more solder connections), such as solder short circuits between the source and gate of transistor elements.

[0037] In other words, conventional techniques cannot properly add solder bumps before ring grinding because they may interrupt subsequent processing steps. Such interruptions may include, for example, damage to the solder bumps during subsequent processing (including thermal / chemical / mechanical stresses during such subsequent processing), or reduced reliability of the BG strip. Furthermore, because conventional techniques cannot properly and accurately position the ring-shaped wafer for solder bump addition, they cannot add solder bumps after ring grinding but before wafer slicing.

[0038] certainly, Figure 1A , Figure 1B and Figure 2 Highly simplified views are provided, designed to illustrate the aforementioned and related aspects. More specifically, relative to... Figure 3 Further explanation and examples are provided in Figure 11. It should be understood that... Figure 1A , Figure 1B and Figure 2 It is not intended to be drawn to scale, and many conventional aspects that are obvious to those skilled in the art are omitted.

[0039] For example, (multiple) circuit elements 110 can represent many different examples of various circuit elements. For example, Figure 9 and Figure 10 The circuit elements 110 provided represent examples of fast recovery diodes (FRDs) and / or insulated gate bipolar transistors (IGBTs). Figure 11 provides a more detailed example relative to a wafer-level package (WLP). However, these and other examples provided herein are not intended to be exclusive, limiting, or comprehensive. Therefore, the circuit elements 110 may in fact represent any suitable structure, such as any suitable transistor, diode, or combination thereof.

[0040] Similarly, although wafer 106 may be described herein as being made of silicon (Si), other suitable substrate materials may also be used. Furthermore, various suitable materials may be used to form solder bumps 112, but these are not described in detail herein.

[0041] exist Figure 1A and Figure 1B In this context, exemplary regions of the available wafer area (e.g., chip regions that remain after removing the wafer ring 108 on which the desired circuit elements 110 can be formed) may have diameters ranging from, for example, 188 mm to 196 mm, and depths ranging from, for example, 10 micrometers to 150 micrometers and less than 300 micrometers. Exemplary ranges for the width of the wafer ring 108 may be, for example, 1 mm to 5 mm, and exemplary ranges for the depth / thickness of the wafer ring 108 may be, for example, 200 micrometers to 1000 micrometers.

[0042] In an exemplary embodiment, a suitable handling tool, such as a substantially non-contact pick-up device, can be used to move the substrate wafer 106 onto or remove it from the mounting chuck 104. For example, a variant of a Bernoulli bar or a Bernoulli handling device can be used, which uses a gas jet to create a pressure differential over the annular wafer 106, thereby pulling the wafer upward.

[0043] Figure 1A , Figure 1B and Figure 2 The simplified view shows the cross-section of each of the elements included therein. Figure 3 An exemplary side view of wafer 106 and ring 108 is shown, while Figure 5 and Figure 6 / 7 provides a side angle view of the bump mounting assembly 102 and the mounting chuck 104, respectively.

[0044] Specifically, Figure 3 The diagram shows a front view of wafer 106, which includes a ring 108 surrounding its circumference. In an exemplary embodiment, wafer 106 may be an 8-inch wafer, and the ring may have a width of approximately a few millimeters (e.g., 3 mm). Of course, other sizes and widths may be used, depending on the circumstances.

[0045] exist Figure 3 In the diagram, reference numeral 302 refers to the thinned portion at the center of the wafer 106, which is formed as a groove within the ring 108. In other words, the thinned portion 302 refers to the area of ​​the wafer 106 where back grinding is performed.

[0046] Despite Figure 1A and Figure 2 It is shown in singular form, but Figure 3The circuit elements 110 shown represent multiple circuit elements formed in a grid pattern on wafer 106. Therefore, as is known and as mentioned herein, the circuit elements 110 can be cut by slicing wafer 106.

[0047] Figure 4 This is a cross-section of an exemplary embodiment of the bump mounting assembly 102 in Figure 1. As described above, and as... Figure 4 As shown, a wafer 106 with a ring 108 can be mounted on a mounting chuck 104.

[0048] Then, a ball mask 402 can be used to deposit solder bumps or solder balls 404. That is, consider them together. Figure 3 and Figure 4 It should be understood that the ball mask 402 can be used to form solder bumps 404 at the wafer 106 level over the desired portion of the circuit element 110 in a fast, efficient, flexible and reliable manner. For example, the solder bumps 404 can be of various types (e.g., different sizes or different materials). Of course, other bump or ball deposition techniques can also be used because the wafer 106 is stably and accurately positioned and secured by the mounting chuck 104.

[0049] Figure 5 Show Figure 1A Another exemplary embodiment of the solder bump mounting assembly 102. In Figure 5 In the image, the solder bump mounting assembly 502 is shown as having a wafer 504 disposed therein.

[0050] Figure 6 yes Figure 5 A diagram of the mounting chuck 604 of the solder bump mounting assembly 502. The mounting chuck 604 provides... Figure 1A An exemplary implementation of the installation chuck 104.

[0051] therefore, Figure 6 The installation chuck 604 includes the corresponding Figure 1A The protruding portion 104a and the protruding portion 604a corresponding to Figure 1A The recessed ring 104b and the recessed ring 604b. Therefore, it should be understood that a ring (e.g., ring 108) formed by back grinding of wafer 504 can be disposed within the recessed ring 604b, while the thinned center portion of wafer 504 (e.g., Figure 3 The recessed portion 302 can be provided on the protruding portion 604a of the mounting chuck 602.

[0052] Figure 7 yes Figure 7 An enlarged illustration of the installation chuck. Figure 7 supply Figure 6Enlarged view of the edges of the protruding portion 604a and the recessed ring 604b.

[0053] Figure 8 This is a flowchart illustrating exemplary processing operations in an exemplary embodiment of the system of Figure 1. The following is relative to... Figures 9A to 9I as well as Figures 11A to 11H supply Figure 8 A more detailed example of this operation.

[0054] exist Figure 8 In this process, the wafer (e.g., an 8-inch Si wafer as described above) undergoes a front-side pre-grinding operation (802). For example, such an operation may include forming an insulating layer, openings within the insulating layer for an electrical contact layer, and forming the electrical contact layer.

[0055] Then, back grinding (804) can be performed, including the use of a back grinding belt (BG belt). That is, the wafer that has undergone front-side processing can be mounted / stabilized on the front side using the BG belt, so that the exposed back side of the wafer can undergo grinding, polishing and / or any other operations required to form the aforementioned ring 108.

[0056] Then back-side grinding can be performed (806). For example, back-side diffusion may occur, or as... Figure 9C As shown, backside ion implantation (followed by annealing) can be performed. (As illustrated...) Figure 9E As shown, sputtering or other provisioning of the back contact layer can be performed. Additionally or alternatively, such as... Figure 11C As shown, a backside protection (BSP) strip can be applied within ring 108 over the backside of the thinned portion (302) of wafer 106.

[0057] It should be understood that the BG belt used for performing back-side grinding can be removed in one of several suitable processing stages, depending on which processing operations will be included. For example, the BG belt can be removed after a selected operation in the back-side post-grinding operation mentioned above. Then, as... Figure 9F As shown, two-sided processing can perform certain operations, such as relative to... Figure 9F The aforementioned (multiple) double-sided electroplating operations.

[0058] Then, as described above, relative to Figure 1 and Figures 4 to 7 The annular wafer 106 (or 502) can be mounted on the mounting chuck 104 or 604 (808). In this way, the annular wafer 106 can be mounted stably, securely, and accurately. This positioning enables and facilitates the use of… Figure 4 A spherical mask 402, or other suitable techniques for forming bumps.

[0059] Therefore, solder bumps (810) can be deposited. Specifically, as mentioned above and Figure 4As the example illustrates, it should be understood that solder bumps are deposited at the wafer level. That is, for example, Figure 4 The solder bumps 404 may be deposited together, and / or deposited in a single operation stage, and before the wafer 106 is sawn or sliced ​​into individual circuit elements 110.

[0060] Advantageously, and as detailed below, relative to Figure 10 The wafer-level deposition of solder bumps 404 provides rapid and accurate bump formation. Therefore, the accurately formed solder bumps enable precise electrical contact with circuit boards such as circuit board 104 in Figure 1. Additionally or alternatively, such as relative to... Figures 11A to 11H Further wafer-level processing may then occur.

[0061] Finally, Figure 8 In this context, any back bump processing (812) can be performed. For example, such as Figure 9H and Figure 11G Both demonstrate that sawing or slicing can be performed to remove ring 108 and to individualize circuit element 110. Furthermore, as described above, such as Figure 2 and Figure 9I As shown, flip-chip mounting can be performed.

[0062] Figures 9A to 9I Showing the use Figure 1A and Figure 1B An exemplary process flow for constructing a first exemplary circuit assembly using solder bump mounting components. Figure 9A In the figure, the wafer Si substrate 902 is shown as having contacts 904 mounted thereon and associated circuit elements, wherein the contacts 904 may be made of AlCu or AlSi. That is, although not explicitly shown in FIG. 9 for the sake of simplicity, aspects of the desired circuit elements (e.g., FRD or IGBT) may be included within layers(s) 904.

[0063] Multiple insulating layers, such as oxide-nitride layer 906 and polyimide (PI) layer 908, as well as associated coatings and patterning structures, can be added as shown in the figure. In Figure 9, the surface of the Si substrate 902 having layers 904, 906, and 908 is referred to herein as the top side or front side, while the opposite side is referred to as the bottom side or back side.

[0064] Combine with a suitable BG tape for mounting on the front ( Figure 9B (Not shown in the figure), known preliminary steps and procedures for performing wafer ring grinding can be performed. Therefore, as shown, a thin, central portion 910 of the wafer is formed together with an outer ring 912 surrounding the central portion 910. As mentioned herein, the thickness of the thinned central portion 910 can, for example, be in the range of 100 to 200 micrometers, for example, less than 300 micrometers.

[0065] Therefore, it is possible Figure 9C As shown, 914 ions were implanted onto the back side, and then... Figure 9D Activation annealing 916 in the process. For example... Figure 9E As shown, sputtering of AlCu coating 918 can be performed, along with suitable back metal (BM) annealing and soda ash powder treatment.

[0066] Then, as shown in the figure, known electroless nickel-gold (ENIG) plating techniques can be used and as follows: Figure 9F As shown, a double plating layer 920 is formed on the front and back sides. Therefore, as shown, the double plating layer 920 includes a Ni (nickel) layer 922 and an Au (gold) layer 924 on each side of the front and back sides.

[0067] The aforementioned ENIG process is known to provide various advantages and features. For example, the referenced ENIG process provides a relatively thick Ni layer, which can offset undesirable Ni consumption that may occur during subsequent solder bonding with lead-free solder. While the thicker Ni layer may also lead to undesirable wafer warpage, the bilateral nature of the ENIG process, together with ring 912, provides the desired stability (e.g., avoidance of warpage) of the thinned portion 910.

[0068] Then, the solder bumps 926 can be formed in any desired manner. Specifically, as described above, Figure 1A , Figure 4 , Figure 6 as well as Figure 7 The installation cassette 104 / 604 can be connected with Figure 4 The spherical mask 404 is used together. Still as described above, and as... Figure 9G As shown, the solder bump 926 can be made of any suitable material and has a variety of desired sizes and shapes designed to match the electrical contacts below.

[0069] like Figure 9H As shown, while ring 912 is removed by ring 930, mounting strip 928 can be used to fix the wafer. Then, individual circuits can be sliced ​​using conventional techniques.

[0070] For reference Figure 2 Then, a flip-chip assembly process can be performed relative to a suitable circuit board 932, such as a direct-bonded copper (DBC) board. Figure 9I As shown, the FRD 934 and IGBT 936 can be installed upside down. An exemplary solder bump 938 (corresponding to solder bump 926) and a suitable adhesive underfill 940 are shown.

[0071] therefore, Figures 9A to 9IAn exemplary method for fabricating IGBT / FRD devices is illustrated, utilizing the formation of solder bumps on an ENIG plating layer serving as solder top metal (STM) and the use of ENIG back metal (BM). As shown and described, exemplary aspects of various method implementations include providing a Si substrate and forming (multiple) IGBT / FRD devices, wherein Al (aluminum) wiring is present on the front side of the substrate. Then, thinned portions (e.g., 100-200 μm) and corresponding rings for supporting the wafer are formed on the back side of the wafer using, for example, wafer ring grinding.

[0072] Ion implantation and activation annealing of (multiple) IGBT / FRD devices can be performed on the back side of the wafer, followed by the formation of an Al (e.g., aluminum copper or AlCu) layer on the back side. A double ENIG plating layer can then be formed as a solder top metal (STM) and a back metal using the electroless NiAu plating technique (e.g., at approximately 1.5 micrometers). After solder bump formation on the NiAu STM, the wafer rings can be removed by appropriate circumferential cutting, and the wafer can be slicing (e.g., blade cutting or saw cutting).

[0073] Figure 10 Show Figures 9A to 9I An exemplary result of an exemplary processing flow. Specifically, in

[0074] Figure 10 The left side of the image shows an exemplary conventional processing result, where chips 1002 and 1004 include FRD devices 1006 and 1008. In this type of conventional processing, solder placement is formed on the underlying DBC board for each relevant chip. Therefore, this method is limited by solder placement accuracy, which is controlled by the processing steps of the relevant stages and is often in the range of, for example, 100 micrometers to 200 micrometers. Therefore, as shown in chip 1010, the source 1012 and gate 1014 can be easily short-circuited. Furthermore, although not shown in… Figure 10 As clearly shown, the solder formed in these routine processes is often prone to voids (e.g., bubbles), which can reduce solder reliability even when solder is formed accurately.

[0075] In contrast, using the techniques described herein, device 1016 (e.g., IGFT) may be formed with solder bumps 1018 and adhesive underfill 1020 to obtain chip 1030. Alternatively, device 1022 may include solder bumps 1024 having adhesive underfill 1026 to obtain chip 1028.

[0076] In these examples, all chips on a given wafer can be formed using one-time solder printing / mounting, and ball mounting technology enables relatively small ball formations due to the available processing limitations of such processes, such as 20 microns to 100 microns. In addition to improved accuracy and efficiency, solder voids are avoided, and the isolated bump design reduces solder stress levels relative to the underlying chip.

[0077] Figures 11A to 11H An exemplary process flow is shown for constructing a second exemplary circuit assembly using the solder bump mounting assembly of Figure 1. Figure 11A In the Si substrate 1102, a contact layer 1104 for receiving AlCu or AlSi (and (a plurality of) related circuit elements), a related patterned structure of an oxide-nitride insulating layer 1106, and a PI layer 1108 are provided. Figure 11B After the first PI coating and patterning layer 1110 in the middle is Figure 11C The Cu RDL (redistribution layer) 1112 and the second PI layer 1114 are in the middle.

[0078] Then, as described above, and as... Figure 11D As shown, suitable BG tapes and other suitable grinding techniques can be used to form the thinned portion 1116 and ring 1118 of the original substrate 1102. In this example, a backside protection (BSP) tape 1120 is applied to the thinned portion 1116.

[0079] like Figure 11E As shown, using Figure 1A , Figure 4 , Figure 6 and Figure 7 The mounting chuck 104 / 604 can form an exemplary solder bump 1122. Then, in Figure 11F In the middle, an attachment layer 1124 can be attached to facilitate conventional chip slicing, including Figure 11G The circumferential cut 1126. Thus, it was achieved. Figure 11H 1128 wafer-level bump mounting component.

[0080] Figures 11A to 11H The technology enables wafer-level solder bumps 1122 to be used on substrates thinned to, for example, 200 micrometers or less, even when relatively large solder bumps are desired (e.g., greater than 100 micrometers, such as 300 to 500 micrometers). For example, relatively large solder bumps may be desired based on the characteristics of the underlying circuitry and / or to ensure proper and reliable electrical contact. For instance, in some exemplary applications, larger solder bumps providing correspondingly larger substrate gaps may be associated with improved thermal cycling reliability and / or improved underlayer filler wettability.

[0081] Therefore, thin Si substrates can be used for wafer-level processing using solder bumps, including the methods described and illustrated for manufacturing a wafer-level process (WLP) in which high solder bumps are formed on a Cu redistribution layer (RDL). This method may include providing a Si substrate and forming semiconductor devices / integrated circuits on the Si substrate. After forming a first PI layer below a back metal layer, Cu RDL, and a second PI layer, a thinned portion of the Si wafer and corresponding Si rings for supporting the wafer may be formed, for example, by wafer grinding or a similar process. After forming a back guard strip (BSP) on the back side (ground surface) of the wafer, solder bumps may be formed on the Cu RDL. Finally, the wafer rings may be removed by appropriate circumferential cutting, and slicing (e.g., blade slicing or saw slicing) may be completed.

[0082] In some embodiments, the semiconductor device may include a plurality of integrated circuits formed on the front side of a thinned portion of a ring wafer, the ring wafer including an outer ring surrounding a periphery of a back side of the ring wafer. The semiconductor device may include at least one of the plurality of integrated circuits having a thickness of less than about 300 micrometers, and at least one solder bump formed on and electrically connected to the at least one integrated circuit, the solder bump having a thickness of more than about 150 micrometers.

[0083] In embodiments of such semiconductor devices, the circuit board may be electrically connected to an integrated circuit using at least one solder bump. The at least one integrated circuit may include at least one of a fast recovery diode (FRD) and an insulated gate bipolar transistor (IGBT). The semiconductor device may include a double electroless nickel-gold (ENIG) plating comprising a first layer electrically connected between at least one circuit element and at least one solder bump, and a second layer on opposite sides of a ring-shaped wafer.

[0084] In some embodiments, a method of manufacturing a semiconductor device may include: forming at least one circuit element on the front side of an annular substrate, removing an inner portion of the back side of the annular substrate to obtain a thinned portion of the annular substrate, wherein an outer ring of remaining substrate material surrounds a periphery of the back side of the annular substrate. The method may include: mounting the annular substrate on a mounting chuck, wherein the mounting chuck has an inner protrusion and a recessed ring surrounding a periphery of the mounting chuck, the inner protrusion being configured to receive the thinned portion of the substrate thereon, and the recessed ring being configured to receive an outer ring of the annular substrate therein; and forming at least one solder bump, the at least one solder bump being electrically connected to at least one circuit element, when the annular wafer is placed on the mounting chuck.

[0085] In these and similar embodiments, at least one circuit element may include at least one of a fast recovery diode (FRD) and an insulated gate bipolar transistor (IGBT). The thinning portion may be less than 300 micrometers. The diameter of the at least one solder bump may be greater than 150 micrometers.

[0086] The at least one circuit element may include a plurality of circuit elements formed on the front side of the substrate, and forming at least one solder bump may include forming a plurality of solder bumps across the substrate and electrically connected to each of the plurality of circuit elements. Forming a plurality of solder bumps may include: providing a mask over the front side of the substrate, the mask having openings over the plurality of circuit elements, while mounting the substrate on a mounting chuck; and depositing a plurality of solder bumps through the openings to connect the plurality of solder bumps to the plurality of circuit elements.

[0087] It should be understood that in the foregoing description, when an element such as a layer, region, substrate, or component is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to the other element, or one or more intermediate elements may be present. Conversely, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, no intermediate elements or layers are present. Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used throughout the specific embodiments, elements shown as being directly on, directly connected to, or directly coupled to an element can be referred to in this manner. The claims of this application (if any) may be amended to describe the exemplary relationships described in the specification or shown in the drawings.

[0088] As used in this specification and claims, the singular form may include the plural form unless the context clearly indicates otherwise. In addition to the orientations shown in the figures, spatially relative terms (e.g., above, on, above, below, under, beneath, etc.) are intended to cover different orientations of the device in use or operation. In some embodiments, the relative terms above and below may respectively include vertically above and vertically below. In some embodiments, term proximity may include lateral proximity or horizontal proximity.

[0089] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor processing technologies associated with a semiconductor substrate, including, but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0090] While certain features of the described embodiments have been illustrated herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations falling within the scope of the particular embodiments. It should be understood that these modifications and variations are presented by way of example only and not limitation, and various changes in form and detail are possible. Any parts of the apparatus and / or methods described herein can be combined in any way, except for mutually exclusive combinations. The embodiments described herein can include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A method for manufacturing a semiconductor device, comprising: At least one circuit element is formed on the front side of the annular substrate, and the inner portion of the back side of the annular substrate has been removed to obtain a thinned portion of the annular substrate, wherein the outer ring of the remaining substrate material surrounds the periphery of the back side of the annular substrate. The annular substrate is mounted on a mounting chuck having an inner protrusion and a recessed ring around the periphery of the mounting chuck. The inner protrusion is configured to receive the thinned portion of the substrate thereon, and the recessed ring is configured to receive the outer ring of the annular substrate therein. When the annular wafer is disposed on the mounting chuck, at least one solder bump is formed that is electrically connected to the at least one circuit element; Remove the annular substrate from the mounting chuck; Remove the outer ring from the annular substrate; The substrate is sliced ​​to define individual chips, the chips comprising at least one chip having the at least one circuit element; as well as Mounting the at least one circuit element to at least one circuit board using a flip-chip assembly includes electrically connecting the at least one circuit element to the at least one circuit board using the at least one solder bump.

2. The method according to claim 1, further comprising: Prior to the mounting, a double electroless nickel-gold ENIG plating is formed on the at least one circuit element and on the inner portion of the back side of the substrate and electrically connected to the at least one circuit element; as well as At least one solder bump is formed on the front ENIG plating and electrically connected to the front ENIG plating.

3. The method of claim 1, wherein removing the internal portion comprises: The front side of the substrate is fixed by grinding the BG tape on the back side; Grinding the back side of the substrate to define the thinned portion and the outer ring; as well as Remove the BG band.

4. A semiconductor device manufacturing assembly for flip-chip assemblies, comprising: A mounting assembly configured to support a wafer on which at least one circuit element is formed on its front side, the wafer having a back side, wherein a ring is formed around the periphery of the back side and a thinned portion is formed within the ring. Installation chuck, the installation chuck being disposed on the installation component, and including... The raised portion, configured to receive the thinned portion of the wafer, and A recessed portion, the recessed portion being configured to receive the ring of the wafer; as well as A mask configured to form at least one solder bump when the wafer is placed on the mounting chuck, wherein the thinned portion of the wafer is located on the raised portion of the mounting chuck and the ring of the wafer is disposed within the recessed portion of the mounting chuck, the at least one solder bump being used for electrical connection to the at least one circuit element, wherein the wafer with the ring removed, the at least one circuit element, and the at least one solder bump are flip-chip assembled onto at least one circuit board.

5. The semiconductor device manufacturing assembly of claim 4, wherein the at least one circuit element comprises a plurality of circuit elements formed on the front side of the wafer, and wherein the at least one solder bump comprises a plurality of solder bumps electrically connected to each of the plurality of circuit elements.

6. The semiconductor device manufacturing assembly of claim 4, wherein the thinned portion of the wafer is less than 300 micrometers.

7. The semiconductor device manufacturing assembly of claim 4, wherein the diameter of the at least one solder bump is greater than 150 micrometers.

8. The semiconductor device manufacturing assembly of claim 4, comprising a dual electroless nickel-gold ENIG plating layer located on the at least one circuit element and on the thinned portion located within the ring, and electrically connected to the at least one circuit element, further wherein the at least one solder bump is formed on the front ENIG plating layer and electrically connected to the front ENIG plating layer.

9. A semiconductor device manufactured according to the method of claim 1, The at least one circuit element is at least one integrated circuit, the at least one integrated circuit being formed on a substrate having a thickness of less than 300 micrometers; and The at least one solder bump is formed on the at least one integrated circuit, and the at least one solder bump has a thickness of more than 150 micrometers.

10. The semiconductor device of claim 9, wherein the at least one circuit board is electrically connected to the at least one integrated circuit using the at least one solder bump.

11. The semiconductor device of claim 9, comprising a dual electroless nickel-gold ENIG plating, the dual electroless nickel-gold ENIG plating comprising a first layer electrically connected between the at least one circuit element and the at least one solder bump, and a second layer on opposite sides of the substrate.

12. The semiconductor device of claim 9, wherein the at least one integrated circuit comprises a plurality of integrated circuits formed on the substrate, and the at least one solder bump comprises a plurality of solder bumps, and further, wherein the plurality of integrated circuits are electrically connected to the at least one circuit board through the plurality of solder bumps.

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