semiconductor devices

Abstract

A semiconductor device includes: a substrate having a first surface and a second surface opposite to each other, and having an active area located on the first surface and defined by a first isolation region; a plurality of active fins arranged on the active area, extending along a first direction, and defined by a second isolation region, the second isolation region having a second depth less than the first depth of the first isolation region; a buried conductive wiring located in a trench adjacent to the plurality of active fins and extending along an extension direction of the trench; a filling insulating portion located in the trench and arranged around the buried conductive wiring; an interlayer insulating layer located on the first isolation region and the second isolation region and on the buried conductive wiring; a contact structure penetrating the interlayer insulating layer and contacting the buried conductive wiring; and a conductive through structure extending from the second surface through the substrate to the trench and contacting the buried conductive wiring.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0088905 filed on July 23, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices and methods of manufacturing semiconductor devices. Background Art

[0004] In various semiconductor devices such as logic circuits and memories, active regions such as source and drain regions may be connected to metal wirings of a back-end-of-line (BEOL) process through contact structures.

[0005] However, as semiconductor devices become increasingly integrated, when the size of active elements such as transistors is reduced or the line width and / or pitch of metal wiring is reduced, there may be a problem that undesirable short circuits may occur when interconnecting metal wiring and active regions. Summary of the Invention

[0006] Example embodiments provide a semiconductor device capable of reducing the occurrence of short circuits (or “shorting”) between a conductive through-structure and other components adjacent thereto.

[0007] According to example embodiments, a semiconductor device includes: a substrate having a first surface and a second surface opposite to each other, and having an active region located on the first surface and defined by a first isolation region; a plurality of active fins arranged on the active region, extending in a first direction, and defined by a second isolation region, the second isolation region having a second depth less than the first depth of the first isolation region; a buried conductive wiring formed in a trench adjacent to the plurality of active fins and extending along an extension direction of the trench; a filling insulating portion located in the trench and disposed around the buried conductive wiring; an interlayer insulating layer located on the first isolation region and the second isolation region to cover the buried conductive wiring; a contact structure penetrating the interlayer insulating layer and contacting the buried conductive wiring; and a conductive through structure extending from the second surface through the substrate to the trench and contacting the buried conductive wiring.

[0008] According to example embodiments, a semiconductor device includes: a substrate having an upper surface and a rear surface; a trench in the substrate, the trench having a first width and extending in one direction; a buried conductive wiring in the trench, extending in the one direction, and having a second width narrower than the first width; a filling insulating portion in the trench and disposed around the buried conductive wiring; a device isolation layer in the substrate and defining an active area; an interlayer insulating layer on the device isolation layer, the active area, and the buried conductive wiring; a contact structure penetrating the interlayer insulating layer and contacting the buried conductive wiring; a conductive through-structure extending from the rear surface through the substrate to the trench, having an end adjacent to the trench, and contacting the buried conductive wiring; and a backside wiring portion on the rear surface of the substrate and electrically connected to the conductive through-structure.

[0009] According to example embodiments, a semiconductor device includes: a substrate having an upper surface including an active region; a plurality of active fins located on the active region and extending in one direction; a buried conductive wiring located in a trench adjacent to the plurality of active fins and extending in the one direction; a dielectric barrier located between an inner sidewall of the trench and a side surface of the buried conductive wiring; an interlayer insulating layer located on the upper surface of the substrate and on the buried conductive wiring; and a contact structure penetrating the buried conductive wiring. the interlayer insulating layer and contacting the buried conductive wiring; a through-hole, which penetrates the substrate from the rear surface of the substrate and has a bottom surface exposing an area of ​​the buried conductive wiring and a portion of the substrate; a conductive through-structure, which has a dielectric liner located on the substrate along the inner sidewall and the bottom surface of the through-hole, and a conductive material in the interior of the through-hole and in contact with the area of ​​the buried conductive wiring exposed by the bottom surface; and a back-side wiring portion, which is located on the rear surface of the substrate and electrically connected to the conductive through-structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A layout view or a top view of an upper surface of a semiconductor device according to example embodiments is shown.

[0012] Figure 2 It is taken along line I-I' and line II-II' Figure 1 A cross-sectional view of a semiconductor device is shown.

[0013] Figure 3 It shows Figure 2 An enlarged cross-sectional view of a portion “A1” of a semiconductor device is shown.

[0014] Figure 4A and Figure 4B A layout view or bottom view of a rear surface of a semiconductor device according to example embodiments is shown.

[0015] Figure 5 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0016] Figure 6 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0017] Figure 7 It shows Figure 6 An enlarged cross-sectional view of a portion “ A2 ” of a semiconductor device is shown.

[0018] Figure 8 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0019] Figure 9 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0020] Figures 10A to 10G It shows the manufacturing Figure 1 1 is a cross-sectional view of a process of a method for forming a semiconductor device (a method for forming a device portion and a first wiring portion).

[0021] Figures 11A to 11E It shows the manufacturing Figure 1 1 is a cross-sectional view of a process of a method for forming a semiconductor device (a method for forming a conductive through-structure and a second wiring portion).

[0022] 12A to 12E It shows the manufacturing Figure 6 1 is a cross-sectional view of a process of a method for forming a semiconductor device (a method for forming a device portion and a first wiring portion).

[0023] 13A to 13C It shows the manufacturing Figure 6 1 is a cross-sectional view of a process of a method for forming a semiconductor device (a method for forming a conductive through-structure and a second wiring portion). DETAILED DESCRIPTION

[0024] Hereinafter, various embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 shows a layout diagram or a top view of an upper surface of a semiconductor device according to example embodiments, Figure 2 It is taken along line I-I' and line II-II' Figure 1 A cross-sectional view of a semiconductor device is shown. For ease of description, spatially relative terms such as "below," "beneath," "below," "after," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures, but it will be understood that this is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of "above" and "below."

[0026] Reference Figure 1 and Figure 2 , a semiconductor device 100A according to this embodiment may include a substrate 101 having an active region 102 . A plurality of active fins 105 may be arranged on an upper surface of the active region 102 .

[0027] In some embodiments, the substrate 101 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. In another example, the substrate 101 may have a silicon-on-insulator (SOI) structure. The active region 102 may be a conductive region, such as a well doped with impurities or a structure doped with impurities. For example, the active region 102 may be an n-type well for a PMOS transistor or a p-type well for an NMOS transistor, but the embodiments described herein are not limited thereto.

[0028] Each of the plurality of active fins 105 may have a structure protruding from the upper surface of the active region 102 in an upward direction (eg, z direction). Figure 1 As shown, a plurality of active fins 105 can be arranged side by side on the upper surface of the active region 102 to extend along a first direction (e.g., the y direction). The terms first, second, etc. are used herein only to distinguish one element from another and not for limiting purposes. The active fins 105 can be provided as the active region of each transistor. In this embodiment, the active fins 105 are shown as being provided in a number of two (2) per source / drain region 110, but the embodiments of the present disclosure are not limited thereto. In other embodiments, the active fins 105 can be provided as one (1) per source / drain region 110, three (3) per source / drain region, or more.

[0029] The source / drain region 110 may be formed in a portion of the active fin 105 located on both sides of the gate structure GS. In this embodiment, the source / drain region 110 may be formed by forming a groove in a portion of the active fin 105 and performing a selective epitaxial growth (SEG) process on the groove to have an upper surface higher than the upper surface of the active fin 105. The source / drain region 110 may also be referred to as a raised source / drain (RSD). For example, the source / drain region 110 may include Si, SiGe or Ge and may have N-type or P-type conductivity. When the source / drain region 110 is formed by a p-type source / drain region, the p-type source / drain region 110 may be regrown with SiGe and may be doped with, for example, boron (B), indium (In), gallium (Ga), boron trifluoride (BF3), etc. as p-type impurities. When silicon (Si) is formed in the source / drain region 110 having n-type conductivity, it may be doped with phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb), etc. as n-type impurities. In consideration of the crystallographic stability during the growth process, different shapes may exist. For example, as shown in FIG. Figure 2 As shown by line II-II′ in FIG. 1 , source / drain region 110 may have a pentagonal cross section (in the case of p-type conductivity), but may also have a hexagonal or flat-angled polygonal cross section (in the case of n-type conductivity).

[0030] The semiconductor device 100A according to this embodiment may include a device isolation layer 162 .

[0031] The device isolation layer 162 may include a first isolation region 162a defining the active region 102 and a second isolation region 162b adjacent to the first isolation region 162a defining a plurality of active fins 105. The first isolation region 162a may have a bottom surface that is deeper than a bottom surface of the second isolation region 162b. The first isolation region 162a may be referred to as deep trench isolation (DTI), and the second isolation region 162b may be referred to as shallow trench isolation (STI). The second isolation region 162b may be disposed on the upper surface of the active region 102. The active fin 105 may penetrate (e.g., partially or completely extend through) the second isolation region 162b, and a portion of the active fin 105 may protrude from the second isolation region 162b.

[0032] For example, the device isolation layer 162 may include silicon oxide or a silicon oxide-based insulating material. Specifically, the device isolation layer 162 may be tetraethyl orthosilicate (TEOS), undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), spin-on glass (SOG), or toner silazane (TOSZ), or a combination thereof. The device isolation layer 162 may be formed using a chemical vapor deposition (CVD) process or a spin coating process.

[0033] Figure 3 It shows Figure 2 An enlarged cross-sectional view of a portion “A1” of a semiconductor device is shown.

[0034] Reference Figure 3 as well as Figure 2 , trenches ST for disposing buried conductive wiring 120 may be formed in active region 102 adjacent to the plurality of active fins 105. In this embodiment, trenches ST may be disposed between the plurality of active fins 105 and similarly to the active fins 105 (see Figure 1 ), and may extend along a first direction (eg, y direction). The depth of the trench ST employed in this embodiment may be shallower than that of the first isolation region 162a, but deeper than that of the second isolation region 162b.

[0035] The buried conductive wiring 120 may be provided on the trench ST. The buried conductive wiring 120 may extend in the second direction (eg, y direction) along the bottom surface of the trench ST (see FIG. 2 ). Figure 1 ).

[0036] Reference Figure 3 , the width W1 of the trench ST may be wider than the width W2 of the buried conductive wiring 120. A filling insulating portion 164 may be provided around the buried conductive wiring 120 to fill the trench ST. The filling insulating portion 164 may be provided along the inner sidewall and a portion of the lower surface (e.g., the bottom surface) of the trench ST. In this embodiment, the filling insulating portion 164 may be a portion of the device isolation layer 162, and may be a portion extending from the device isolation layer 162 and filling the trench ST. Therefore, the filling insulating portion 164 may include the same material as the device isolation layer 162.

[0037] The conductive through-structure 250 may extend from the rear surface of the substrate 101 to the trench ST and may be connected (e.g., physically and / or electrically) to the buried conductive wiring 120. For example, the conductive through-structure 250 may be a through-silicon via (TSV). Elements referred to herein as being on, contacting, or connected to other elements may be directly on, directly contacting, or directly connected to other elements, or there may be intermediate elements. Conversely, when an element is referred to as being "directly on" another element, "directly contacting" another element, or "directly connected to" another element, there are no intermediate elements.

[0038] Reference Figure 3As shown in “CT1”, a portion of the conductive through-structure 250 may contact the filling insulating portion 164. In this embodiment, since the filling insulating portion 164 exists around the buried conductive wiring 120, the size of the conductive through-structure 250 may be larger than the width W2 of the buried conductive wiring 120, or, even when the conductive through-structure 250 is not correctly aligned, the conductive material 255 (to be described below) of the conductive through-structure 250 does not contact the adjacent active region (e.g., Si).

[0039] In this way, it is possible to effectively prevent an undesirable short circuit that may occur when the conductive through structure 250 falls on the buried conductive wiring 120 , or reduce the occurrence rate of such an undesirable short circuit.

[0040] The upper end or end portion 250T of the conductive through-via structure 250 may be positioned below the level L1 of the upper surface 102T of the active region 102. In this manner, mutual electrical interference may be suppressed by ensuring a sufficient distance from the active fin 105 where no conductive through-via structure 250 is formed to the upper surface 102T of the active region 102. For example, the conductive through-via structure 250 may have a size (e.g., diameter or width) of 20 nm to 500 nm and a distance (e.g., depth) of 200 nm to 3000 nm.

[0041] The buried conductive wiring 120 may be connected to a contact structure 180 that penetrates the interlayer insulating layer 165. The interlayer insulating layer 165 may be disposed on the device isolation layer 162 to cover the source / drain regions 110 and the buried conductive wiring 120. As used herein, "covering" does not require complete coverage. The portion directly covering the buried conductive wiring 120 in the device isolation layer 162 (particularly the second isolation region 162b) may be an insulating cover layer 130. The insulating cover layer 130 may have an upper surface 130T that may be substantially coplanar with the upper surface 162T of the device isolation layer 162.

[0042] The interlayer insulating layer 165 and / or the insulating cover layer 130 may be formed of a material that is the same as or similar to the material of the device isolation layer. Even when the insulating cover layer 130, the device isolation layer 162, and / or the interlayer insulating layer 165 are formed of the same material (e.g., oxide), they can be visually distinguished. Specifically, since the device isolation layer 162, the interlayer insulating layer 165, and the insulating cover layer 130 have different film qualities when formed by different processes, the layers can be distinguished or differentiated from each other, for example, by the boundaries between them.

[0043] The upper surface of the buried conductive wiring 120 used in this embodiment may be lower than the upper end of the active fin 105. The buried conductive wiring 120 may not be exposed to the outside during the process of forming the source / drain region 110. In addition, the buried conductive wiring 120 may be higher than the upper surface 102T of the active region 102. The buried conductive wiring 120 may be electrically connected to the contact structure 180.

[0044] The buried conductive wiring 120 is not limited thereto, but may be formed to have an aspect ratio of 2 or more. For example, the buried conductive wiring 120 may have a width of 5 nm to 50 nm.

[0045] The contact structure 180 employed in this embodiment can connect the source / drain region 110 and the buried conductive wiring 120 together. Specifically, the contact structure 180 may include a first contact region 180A connected to the source / drain region 110 and a second contact region 180B connected to the first contact region 180A and connected to the buried conductive wiring 120. The second contact region 180B may be formed deeper than the first contact region 180A and may be electrically connected to the buried conductive wiring 120. An example of a planar arrangement of the contact portion CP of the second contact region 180B and the buried conductive wiring 120 can be seen in FIG. Figure 1 .

[0046] The contact structure 180 may be connected to a first wiring portion ML1 constituting a back end of line (BEOL) process. The first wiring portion ML1 may be configured to connect a plurality of elements (eg, transistors) implemented on the upper surface of the substrate 101 to each other.

[0047] The first wiring portion ML1 may include a plurality of low dielectric layers 172 and 175, a plurality of metal wirings M1, and a plurality of metal vias V1. The plurality of low dielectric layers may include a first low dielectric layer 172 and a second low dielectric layer 175 disposed on the interlayer insulating layer 165. The metal wiring M1 may be formed in the second low dielectric layer 175, and the metal vias V1 may be formed in the first low dielectric layer 172. In this case, each metal via V1 may be formed at a contact in the metal wiring M1 to be connected to the contact structure 180 (see FIG. 1 ). Figure 1 and Figure 2 ). For example, the first low dielectric layer 172 and the second low dielectric layer 175 may each include a silicon oxide film, a silicon oxynitride film, a SiOC film, a SiCOH film, or a combination thereof. For example, the metal wiring M1 and the metal via V1 may include copper or a copper-containing alloy. The metal wiring M1 and the metal via V1 may be formed together using a dual damascene process.

[0048] In this embodiment, an etch stop layer 171 may be further provided between the interlayer insulating layer 165 and the first low dielectric layer 172. The etch stop layer 171 may prevent the metal (e.g., Cu) constituting the metal wiring M1 and the metal via V1 from diffusing into the underlying region and may also inhibit etching operations. For example, the etch stop layer 171 may include, but is not limited to, aluminum nitride (AlN).

[0049] In this embodiment, the contact structure 180 connected to multiple elements (e.g., source / drain regions 110, etc.) formed on the substrate 101 can be connected to the second wiring portion ML2 located on the rear surface of the substrate 101 via the buried conductive wiring 120 and the conductive through structure 250.

[0050] The second wiring portion ML2 employed in this embodiment may be a power supply line and a signal line implemented on the rear surface of the substrate 101, and may be understood as a wiring portion that replaces a portion of the required BEOL. In this case, since the second wiring portion ML2 may be located on the rear surface of the substrate 101, the second wiring portion ML2 may also be referred to as a "backside wiring portion."

[0051] The second wiring portion ML2 may provide signal lines and power lines for a plurality of elements (eg, transistors) implemented on the upper surface of the substrate 101 through the buried conductive wiring 120 and the conductive through-structure 250 .

[0052] After forming a back-side insulating layer 210 on the rear surface of substrate 101, conductive through-structure 250 may be formed. Second wiring portion ML2 may be disposed on back-side insulating layer 210. Second wiring portion ML2 may include multiple low-dielectric layers 272 and 275, multiple first and second metal wirings M2 and M3, and multiple metal vias V2. The multiple low-dielectric layers may include first and second low-dielectric layers 272 and 275 sequentially disposed on back-side insulating layer 210. First metal wiring M2 is formed on back-side insulating layer 210, and second metal wiring M3 may be formed in second low-dielectric layer 275. Metal vias V2 connecting first and second metal wirings M2 and M3 may be formed in first low-dielectric layer 272. Second metal wiring M3 and metal vias V2 may be formed using a dual damascene process. In this case, first metal wiring M2 may be formed to connect to conductive through-structure 250.

[0053] Figure 4A 1 shows the layout of the conductive through-structures 250 and the buried conductive wiring 120 when viewed from the rear surface of the substrate 101. A plurality of conductive through-structures 250 may be arranged to be connected to the buried conductive wiring 120 extending along the first direction. Figure 4AAs shown, the cross-section of the conductive through-structure 250 may have a substantially rectangular shape, and may have a shape in which the distance or size in a first direction (e.g., y direction) is greater than the distance or size in a second direction (e.g., x direction) perpendicular to the first direction. The conductive through-structures 250 may be arranged on the same line or aligned in the second direction. The cross-section of the conductive through-structure 250 that may be used in this embodiment may have various shapes (e.g., circular, elliptical) and / or other arrangements. In some embodiments, as Figure 4B As shown, the conductive through-structures 250 may be arranged in a diagonal direction (eg, misaligned) with respect to other conductive through-structures 250 adjacent thereto in the second direction.

[0054] In this way, wiring such as signal lines and power supply lines required for the semiconductor device 100A can also be implemented on the rear surface of the substrate 101 by using the buried conductive wiring 120 and the conductive through-structure 250 .

[0055] The second wiring portion ML2 employed in this embodiment may be illustrated as being implemented together with the first wiring portion ML1 disposed on the upper surface (e.g., in the upper portion of the element region) of the substrate 101. In some embodiments, all required BEOL may be implemented as the second wiring portion ML2 disposed on the rear surface of the substrate 101 using the buried conductive wiring 120 and the conductive through-structure 250, and the first wiring portion ML1 may be minimized or omitted.

[0056] In this embodiment, the conductive through structure 250 may include a conductive material 255 and a dielectric liner 251 disposed between the conductive material 255 and the substrate 101. The buried conductive wiring 120 may include a conductive material 125 and a conductive barrier 122 disposed on the side and lower surfaces of the conductive material 125. Similarly, the contact structure 180 may include a conductive material 185 and a conductive barrier 182 disposed on the side and lower surfaces of the conductive material 185.

[0057] For example, at least one of the conductive material 125 in the buried conductive wiring 120, the conductive material 185 in the contact structure 180, and the conductive material 255 in the conductive through-structure 250 may include Cu, Co, Mo, Ru, W, or alloys thereof. For example, the dielectric liner 251 of the conductive through-structure 250 may include SiO2, SiN, SiCN, SiC, SiCOH, SiON, Al2O3, AlN, or porous materials thereof. For example, at least one of the conductive barrier 122 in the buried conductive wiring 120 and the conductive barrier 182 in the contact structure 180 may include Ta, TaN, Mn, MnN, WN, Ti, TiN, or a combination thereof.

[0058] The contact structure 180 may include a metal silicide layer (not shown) disposed between the conductive barrier 182 and the source / drain region 110. For example, the metal silicide layer may be formed of a material such as CoSi, NiSi, TiSi, or the like.

[0059] The semiconductor device 100A according to this embodiment may include a gate structure GS. Figure 1 As shown, the gate structure GS may have a linear shape extending along a second direction (e.g., x-direction) intersecting the first direction (e.g., y-direction). In this way, the gate structure GS may overlap a region of the active fin 105. The gate structure GS used in this embodiment may include a gate spacer 141, a gate dielectric film 142 and a gate electrode 145 sequentially arranged between the gate spacers 141, and a gate capping layer 147 disposed on the gate electrode 145.

[0060] For example, the gate spacer 141 may include an insulating material such as SiOCN, SiON, SiCN, SiN, etc. For example, the gate dielectric film 142 may be formed of a silicon oxide film, a high dielectric film, or a combination thereof. The high dielectric film may include a material having a relatively high dielectric constant (e.g., about 10 to 25) higher than the dielectric constant of the silicon oxide film. For example, the high dielectric film may be formed of hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, or a combination thereof, but is not limited thereto. The gate dielectric film 142 may be formed by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process.

[0061] In some embodiments, the gate electrode 145 may include a first gate electrode and a second gate electrode made of different materials. The first gate electrode may adjust the work function, and a space formed above the first gate electrode may be filled. For example, the first gate electrode may include a metal nitride such as a titanium nitride film (TiN), a tantalum nitride film (TaN), or a tungsten nitride film (WN), and the second gate electrode may include aluminum (Al), tungsten (W), molybdenum (Mo), or a semiconductor material such as doped polysilicon. For example, the gate cap layer 147 may be formed of an insulating material such as silicon nitride.

[0062] The above embodiments may be modified and implemented in various ways. For example, according to embodiments of the present disclosure, various changes may be made to the width of the trench, the position of the conductive through-structure, and / or the configuration of the buried conductive wiring.

[0063] Figure 5 is a cross-sectional view showing a semiconductor device according to example embodiments, and is to be understood as Figure 2 An enlarged cross-sectional view of a portion "A1" of a semiconductor device is shown, similar to Figure 3 Enlarged view shown.

[0064] Reference Figure 5 It will be understood that, except that the width of the trench ST' is further expanded, and the position of the upper end of the conductive through structure 250 and the configuration of the buried conductive wiring 120 are changed, the semiconductor device 100B has the same Figures 1 to 3 The structure of the semiconductor device 100A is similar to that shown in FIG. Figures 1 to 3 The components of this embodiment will be understood by referring to the description of the same or similar components of the illustrated semiconductor device 100A unless otherwise noted.

[0065] The semiconductor device 100B according to this embodiment may include a trench ST' having an extended width greater than that of the trench ST of the previous embodiment. The extended width of the trench ST' employed in this embodiment may be greater than another width (e.g., a first width) adjacent to the lower ends of the plurality of active fins 105 (e.g., a second width adjacent to the buried conductive wiring 120). In this case, since the filling insulating portion 164 disposed around the buried conductive wiring 120 in the trench ST' may also have a relatively large width, a larger or wider margin than that of the previous embodiment may be provided during the landing process of the conductive through-structure 250. The contact area CT2 between the conductive through-structure 250 and the filling insulating portion 164 may be asymmetric relative to the buried conductive wiring 120 (e.g., on opposite sides of the buried conductive wiring 120).

[0066] The upper end or end of the conductive through structure 250 may be positioned higher than the bottom surface of the buried conductive wiring 120 or extend beyond the bottom surface of the buried conductive wiring 120. The through hole for the conductive through structure 250 may be formed so that a portion of the side surface of the buried conductive wiring 120 is exposed in addition to the bottom surface of the buried conductive wiring 120 for stable connection with the buried conductive wiring 120.

[0067] The buried conductive wiring 120 may include a conductive material 125 and a conductive barrier 122 disposed on the lower surface and side surfaces of the conductive material 125, and may further include a dielectric barrier 121 disposed between the conductive barrier 122 and the filling insulating portion 164. For example, the dielectric barrier 121 may include SiO2, SiN, SiCN, SiC, SiCOH, SiON, Al2O3, AlN, or a porous material thereof.

[0068] In the aforementioned embodiments, a method can be provided for forming a shallow trench insulator (STI) having a trench and a filling insulating portion in an active region adjacent to an active fin, and filling a conductive wiring with the filling insulating portion. Because the filling insulating portion is located around the buried conductive wiring, even when the conductive through-structure is disposed offset from the buried conductive wiring or misaligned with the buried conductive wiring, a short circuit with the active region can be prevented due to contact with the filling insulating portion.

[0069] Although the aforementioned embodiments are illustrated as three-dimensional semiconductor devices having multiple active fins, the present disclosure can also be advantageously implemented in planar semiconductor devices having active regions without active fins. For example, a trench having a larger width than the buried conductive wiring can be formed in the active region, and a filling insulating portion for filling the trench can be formed to be disposed around the buried conductive wiring to suppress or provide an error margin around the active region and reduce the possibility of a conductive through-hole structure short circuit.

[0070] Alternatively, as a modified solution for preventing the conductive through-hole structure and the active area from short-circuiting, a dielectric liner can be formed on the inner surface of the through-hole for the conductive through-hole structure using selective deposition. Selective deposition can not form a dielectric liner on the surface of the buried conductive wiring exposed in the through-hole, but the dielectric liner can be formed only on the surface of the semiconductor (the surface of the substrate and the active area) to contact the conductive material of the conductive through-hole structure. Figures 6 to 9 Various embodiments according to this modification are described in detail.

[0071] Figure 6 is a cross-sectional view illustrating a semiconductor device according to example embodiments, Figure 7 It shows Figure 6 FIG. 1 is an enlarged cross-sectional view of a portion “A2” of a semiconductor device shown. In this case, Figure 6 The cross-sectional view shown is to be understood as Figure 1 A cross-sectional view of the planar layout shown is taken along line II'.

[0072] Reference Figure 6 and Figure 7 , similar to Figure 2 and Figure 3 In the illustrated embodiment, a semiconductor device 100C according to this embodiment may include a substrate 101 having an active region 102. A plurality of active fins 105 may be arranged on an upper surface of the active region 102.

[0073] It will be understood that the semiconductor device 100C has the same structure as the semiconductor device 100C except that the peripheral structure of the buried conductive wiring 120 and the dielectric liner 251 of the conductive through structure 250 are changed. Figures 1 to 3 The structure of the semiconductor device 100A is similar to that shown in FIG. Figures 1 to 3 The components of this embodiment will be understood by referring to the description of the same or similar components of the illustrated semiconductor device 100A unless otherwise noted.

[0074] Each of the plurality of active fins 105 may have a structure protruding from the upper surface of the active region 102 in an upward direction (e.g., z direction). The plurality of active fins 105 may be arranged side by side on the upper surface of the active region 102 to extend in a first direction (e.g., y direction). The source / drain region 110 may be formed in a portion of the active fin 105 located on both sides of the gate structure (not shown). Although the gate structure in this embodiment is not shown, reference may be made to FIG. Figure 2 Shown along Figure 1 The gate structure can be understood by referring to the cross-sectional view taken along line II-II' in FIG.

[0075] The source / drain regions 110 may be formed by forming grooves in a portion of the active fins 105 and performing selective epitaxial growth on the grooves. The upper surface of the source / drain regions 110 may be higher than the upper surface of the active fins 105 .

[0076] Similar to the previous embodiment, the semiconductor device 100C may include a device isolation layer 162 and an interlayer insulating layer 165. The device isolation layer 162 may include a first isolation region 162a defining the active region 102 and a second isolation region 162b defining the active fin 105. The second isolation region 162b may be disposed on the upper surface of the active region 102. The active fin 105 may penetrate the second isolation region 162b, and a portion of the active fin 105 may protrude from the second isolation region 162b.

[0077] Reference Figure 6 and Figure 7 The trench ST″ used in this embodiment can be formed to penetrate the device isolation layer 162, especially the second isolation region 162b, and extend to a partial area of ​​the active area 102 or partially extend into the active area 102. In the final structure, the buried conductive wiring 120 can be disposed in the trench ST″ located in the active area 102 adjacent to the plurality of active fins 105, and the device isolation layer 162 and the insulating capping layer 130 are embedded in the trench ST″.

[0078] In a manner similar to the previous embodiment, the trench ST" can be set between the plurality of active fins 105 and can extend in the first direction similar to the active fins 105. The buried conductive wiring 120 can extend in the first direction along the bottom surface of the trench ST". The trench ST" adopted in this embodiment can be formed to be shallower than the first isolation region 162a but deeper than the second isolation region 162b.

[0079] Reference Figure 6 and Figure 7 , the buried conductive wiring 120 may include a conductive material 125 and a dielectric barrier 121 disposed between the conductive material 125 and the active region 102. The dielectric barrier 121 may be shown at the same height as the conductive material 125, but may also extend further along the inner wall of the trench ST″ of the device isolation layer 162. The conductive through structure 250 may extend from the rear surface of the substrate 101 to the trench ST″ and may be connected to the buried conductive wiring 120. For example, the conductive through structure 250 may be a TSV.

[0080] like Figure 7 As shown, the upper end 250T of the conductive through-structure 250 may be positioned lower than the upper surface 102T of the active region 102. In this embodiment, the conductive through-structure 250 may not be formed to the upper surface 102T of the active region 102 (i.e., it may be limited below the upper surface 102T of the active region 102). Therefore, a sufficient distance from the active region 102 may be ensured to suppress mutual electrical interference.

[0081] The upper end 250T of the conductive through structure 250 may be positioned higher than the bottom surface 120B of the buried conductive wiring 120. In this arrangement, the bottom surface 120B of the buried conductive wiring 120 and a portion of the side surface 120S adjacent thereto may be in contact with the conductive through structure 250. Figure 7 In FIG. 1 , “CA” refers to a contact area between the conductive material 125 of the buried conductive wiring 120 and the conductive material 255 of the conductive through-structure 250 .

[0082] The dielectric liner 251 employed in this embodiment may be disposed on the side surfaces of the conductive through-structure 250 and the surface of the active region 102 adjacent to the upper end 250T. The dielectric liner 251 may be formed using a selective deposition process.

[0083] The selective deposition process employed in this embodiment refers to a process in which the insulating material is deposited only on the surface of a semiconductor such as Si and not on the surface of the conductive material 125 such as metal. The selective deposition process may be a process that can deposit relatively conformally over the entire inner surface of the through hole. For example, the selective deposition process may be performed by an atomic layer deposition (ALD) process.

[0084] In a conventional process for forming a dielectric liner 251 on the entire surface of a through hole for a conductive through structure 250, when the bottom surface of the through hole is exposed to form a contact, the active area 102 on the bottom surface around the contact is exposed (see FIG. Figure 11B and Figure 11C), and the dielectric liner 251 used in this embodiment can be formed using a selective deposition process performed on the semiconductor (the surface of the substrate 101 and the surface of the active region 102) exposed to the inner surface of the through hole (e.g., the side surface of the through hole and the bottom surface of the through hole) but not on the buried conductive wiring 120 (see Figure 13A and 13B The dielectric liner 251 may have a uniform thickness. For example, the dielectric liner 251 may include SiO 2 , SiN, SiCN, SiC, SiCOH, SiON, Al 2 O 3 , AlN, or HfN.

[0085] Even when the size of the conductive through-structure 250 is larger than the width of the buried conductive wiring 120 or the conductive through-structure 250 is not correctly aligned, the conductive through-structure 250 may not contact the adjacent active region (e.g., Si) through the dielectric liner 251 or due to the presence of the dielectric liner 251.

[0086] In this embodiment, the exposed surface of the active region 102 may have a sufficient area to uniformly deposit the dielectric liner 251 on the surface of the active region 102 exposed on or exposed by the bottom surface of the through-hole. In some embodiments, the width of the gap G at the exposed surface of the active region 102 may be greater than twice the thickness (t) of the dielectric liner 251.

[0087] The buried conductive wiring 120 may be connected to a contact structure 180 that penetrates the interlayer insulating layer 165. The interlayer insulating layer 165 may be provided on the device isolation layer 162 to cover the source / drain regions 110 and the buried conductive wiring 120. The insulating capping layer 130 may have an upper surface 130T that may be a substantially flat surface that may be coplanar with the upper surface 162T of the device isolation layer 162.

[0088] The buried conductive wiring 120 employed in this embodiment may have an upper surface higher than the upper surface 102T of the active region 102 and lower than the upper end of the active fin 105. The buried conductive wiring 120 may not be exposed to the outside during the process of forming the source / drain region 110.

[0089] The buried conductive wiring 120 may be electrically connected to a contact structure 180. The contact structure 180 employed in this embodiment may electrically connect the source / drain region 110 and the buried conductive wiring 120. Specifically, the contact structure 180 may include a first contact region 180A connected to the source / drain region 110 and a second contact region 180B connected to the first contact region 180A and to the buried conductive wiring 120.

[0090] In this embodiment, contact structure 180 may be electrically connected to first wiring portion ML1 constituting a back-end of line (BEOL). First wiring portion ML1 may include first and second low-k dielectric layers 172 and 175, a plurality of metal wirings M1, and a plurality of metal vias V1, and may further include an etch stop layer 171 disposed between interlayer insulating layer 165 and first low-k dielectric layer 172.

[0091] The contact structure 180 connected to the plurality of elements (e.g., source / drain regions 110, etc.) formed on the substrate 101 can be connected to the second wiring portion ML2 located on the rear surface of the substrate via the buried conductive wiring 120 and the conductive through-structure 250. In this case, since the second wiring portion ML2 is located on the rear surface of the substrate 101, the second wiring portion ML2 can also be referred to as a "backside wiring portion." The second wiring portion ML2 can provide signal lines and power lines for the plurality of elements (e.g., transistors) implemented on the upper surface of the substrate 101 through the buried conductive wiring 120 and the conductive through-structure 250.

[0092] Figure 8 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0093] Reference Figure 8 It will be understood that the semiconductor device 100D has the same structure as that of the semiconductor device 100D except that the configuration of the buried conductive wiring 120 and the formation area of ​​the dielectric liner 251 are changed accordingly. Figure 6 and Figure 7 The structure of the semiconductor device 100C is similar to that shown in FIG. Figure 6 and Figure 7 The components of this embodiment will be understood by referring to the description of the same or similar components of the illustrated semiconductor device 100C unless otherwise noted.

[0094] With Figure 7 In a manner similar to the illustrated example, since the upper end 250T of the conductive through structure 250 is positioned higher than the bottom surface 120B of the buried conductive wiring 120, the conductive through structure 250 can be formed on the bottom surface 120B of the buried conductive wiring 120 and a portion of the side surface 120S of the buried conductive wiring 120 adjacent to the bottom surface 120B.

[0095] In the previous embodiment ( Figure 7), since the dielectric barrier 121 is removed from the side surface 120S of the buried conductive wiring 120 to expose the side surface of the conductive material 125, the dielectric liner 251 may not be formed on the side surface of the dielectric barrier 121. In this embodiment, since the dielectric barrier 121 at least partially remains on the side surface 120S of the buried conductive wiring 120, the dielectric liner 251 may be formed on the remaining surface of the dielectric barrier 121. In this case, the conductive material 125 of the buried conductive wiring 120 may be exposed at the bottom surface 120B and, therefore, may contact the conductive material 255 of the conductive through structure 250 to provide a contact area CA.

[0096] The first modification (using the filling insulating portion) and the second modification (using the selective deposition process) of the above-described embodiment can be implemented in combination. The semiconductor device according to this embodiment can be shown in FIG. Figure 9 middle.

[0097] Reference Figure 9 It will be understood that the semiconductor device 100E has the same structure as that of the semiconductor device 100E except that the configuration of the buried conductive wiring 120 and the formation area of ​​the dielectric liner 251 are changed accordingly. Figures 1 to 3 The semiconductor device 100A shown and Figure 6 and Figure 7 The structure of the semiconductor device 100C is similar to that shown in FIG. Figures 1 to 3 The semiconductor device 100A shown and Figure 6 and Figure 7 The components of this embodiment will be understood by referring to the description of the same or similar components of the illustrated semiconductor device 100C unless otherwise noted.

[0098] With Figure 2 and Figure 3 In a similar manner to the illustrated example, the width W1 of the trench ST may be wider than the width W2 of the buried conductive wiring 120. The device isolation layer 162 may have a filling insulating portion 164 extending between the trench ST and the buried conductive wiring 120. The filling insulating portion 164 may be provided around the buried conductive wiring 120 in the trench ST.

[0099] Since the upper end 250T of the conductive through structure 250 is positioned higher than the bottom surface 120B of the buried conductive wiring 120, the conductive through structure 250 can be formed on the bottom surface 120B of the buried conductive wiring 120 and the side surface 120S of the buried conductive wiring 120 adjacent to the bottom surface 120B. Figure 6 and Figure 7 In a similar manner to the illustrated example, the dielectric liner 251 may also extend to the upper end 250T of the conductive through-structure 250. The dielectric liner 251 may be formed by a selective deposition process.

[0100] Even when the dielectric liner 251 may not be smoothly formed (e.g., may extend discontinuously) on the bottom surface of the through hole, the filling insulating portion 164 located around the buried conductive wiring 120 in the trench ST can reduce or prevent undesirable short circuiting of the conductive through structure 250 and the active area 102.

[0101] Hereinafter, a method for manufacturing a semiconductor device according to an example embodiment will be described with reference to the accompanying drawings. In describing the manufacturing method, the structural characteristics and advantages of the semiconductor device according to the example embodiment will be understood in more detail.

[0102] manufacture Figure 1 The method of the semiconductor device 100A shown will be divided into processes for forming the device portion and the first wiring portion ( Figures 10A to 10G ) and a process for forming a conductive through-structure and a second wiring portion ( Figures 11A to 11E ), and will be described separately. Figures 10A to 10G It shows the manufacturing Figure 1 1 is a cross-sectional view of a process of a method for forming a semiconductor device (a method for forming a device portion and a first wiring portion).

[0103] First, refer to Figure 10A , trenches ST for burying conductive wirings may be formed in the active region 102 adjacent to the plurality of active fins 105 .

[0104] A fin mask FM may be provided on the upper surface of each of the plurality of active fins 105. The fin mask FM may be a mask that has been used in an operation for forming the plurality of active fins 105 prior to this operation. The trench ST may be formed to extend along a first direction in which the plurality of active fins 105 extend. A formation region of the trench ST may be located between the active fins 105 in the plurality of active fins 105. During the formation of the trench ST, a portion of the active fin 105 a may be removed together with a portion of the active region 102, as indicated by the dotted line.

[0105] Reference Figure 10B , a first insulating layer 162 ′ may be formed, and a hole H for burying the conductive wiring may be formed in the first insulating layer 162 ′.

[0106] A first insulating layer 162' may be formed to cover the plurality of active fins 105 on the substrate 101. After forming the first insulating layer 162' to cover the fin mask FM, the first insulating layer 162' may be planarized using an operation such as CMP to expose the fin mask FM. The first insulating layer 162' may serve as the device isolation layer 162 in the final structure. A hole H may be formed in the first insulating layer 162' to open and expose the bottom surface of the trench ST. The bottom surface of the trench ST exposed by the hole H may be provided by the active region 102.

[0107] Reference Figure 10C , a conductive barrier 122 ′ and a conductive material 125 ′ may be sequentially deposited to fill the hole H.

[0108] A conductive barrier 122' and a conductive material 125' may be formed on the upper surface of the first insulating layer 162' to fill the hole H. In some embodiments, the dielectric barrier may be formed together with the conductive barrier 122' (see FIG. Figure 5 ) or instead of the conductive barrier 122 ′. When forming the dielectric barrier, after the deposition of the dielectric barrier and before the deposition of the conductive material, an operation of removing a portion of the dielectric barrier located on the bottom surface of the trench ST to expose the active region 102 (e.g., an etch-back operation) may be additionally performed.

[0109] Reference Figure 10D , a buried conductive wiring 120 having a predetermined height may be formed in the hole H, and a second insulating layer 130 ′ may be formed to embed the buried conductive wiring 120 in the trench ST.

[0110] Portions of the conductive barrier 122' and the conductive material 125' disposed on the upper surface of the first insulating layer 162' may be removed by applying an etch-back operation or a planarization operation, and portions of the conductive barrier 122' and the conductive material 125' located in the hole H may be lowered to a predetermined depth (d) or lowered to a predetermined depth (d) to form a buried conductive wiring 120. The upper surface level L2 of the buried conductive wiring 120 may be higher than the upper surface level L1 of the active region 102 and lower than the upper end of the active fin 105. A second insulating layer 130' may be formed to fill the hole H defining the buried conductive wiring 120.

[0111] Reference Figure 10E A portion of the second insulating layer 130 ′ and a portion of the first insulating layer 162 ′ may be removed to expose a portion of the plurality of active fins 105 , and source / drain regions 110 may be formed on the exposed portions of the plurality of active fins 105 .

[0112] In this operation, a planarization operation such as CMP may be used to remove a portion of the second insulating layer 130' and a portion of the first insulating layer 162'. This operation may be performed until the fin mask FM is exposed. After removing the fin mask FM, an etch-back operation may be performed to remove a portion of the first insulating layer 162' and a portion of the second insulating layer 130' to expose corresponding portions of the plurality of active fins 105. The first insulating layer 162' obtained through this operation may be provided as a device isolation layer 162, and the second insulating layer 130' may be provided as an insulating cap layer 130. Recesses may be formed in the exposed portions of the plurality of active fins 105, and a selective epitaxial growth operation may be performed in the recesses to form source / drain regions 110.

[0113] Reference Figure 10F , an interlayer insulating layer 165 may be formed, and a contact hole CH for a contact structure may be formed.

[0114] The interlayer insulating layer 165 may be formed to cover the source / drain region 110, and a contact hole CH may be formed. The contact hole CH may include a first hole region CHa connected to the source / drain region 110 and a second hole region CHb connected to the first hole region CHa and connected to the buried conductive wiring 120. The second hole region CHb may be formed deeper than the first hole region CHa and may be connected to the buried conductive wiring 120.

[0115] Reference Figure 10G , a contact structure 180 may be formed, and a first wiring portion ML1 may be formed on the interlayer insulating layer 165 .

[0116] Conductive barrier 182 and conductive material 185 may be sequentially formed to fill contact hole CH, and then a planarization operation such as CMP may be performed to form a substantially coplanar planar surface between upper surfaces of contact structure 180 and interlayer insulating layer 165 .

[0117] A first wiring portion ML1 electrically connected to contact structure 180 may be formed on interlayer insulating layer 165. An etch stop layer 171 may be formed on interlayer insulating layer 165, and first wiring portion ML1 may be formed having a plurality of low dielectric layers 172 and 175, a plurality of metal wirings M1, and a plurality of metal vias V1. The metal wirings M1 and the metal vias V1 may be formed together using a dual damascene operation.

[0118] Figures 11A to 11E It shows the manufacturing Figure 1 1 is a cross-sectional view of a process of a method for forming a semiconductor device (a method for forming a conductive through-structure and a second wiring portion).

[0119] Reference Figure 11A , you can Figure 10GThe resulting structure prepared in FIG. 1 is attached to the support substrate 300 , and through holes TH may be formed in the substrate 101 .

[0120] The support substrate 300 may be attached to Figure 10G The first wiring portion ML1 of the resulting structure is shown so that the rear surface of the substrate 101 is flipped to face upward. A back insulating layer 210 for passivation may be formed on the rear surface of the substrate 101. The through hole TH may be formed to face the trench ST from the rear surface of the substrate 101 or toward the rear surface of the substrate 101. The contact area of ​​the buried conductive wiring 120 may be exposed from the bottom surface of the through hole TH or exposed by the bottom surface of the through hole TH. When the size (e.g., diameter) of the through hole TH is greater than the width of the buried conductive wiring 120 or the through hole TH is not properly aligned, a portion of the filling insulating portion 164 located around the buried conductive wiring 120 may be exposed from the bottom surface of the through hole TH or exposed by the bottom surface of the through hole TH.

[0121] Reference Figure 11B , a dielectric layer 251' for the dielectric liner 251 may be formed. Figure 11C , a portion of the dielectric layer 251 ′ located on the bottom surface THb of the through hole TH may be opened to form a dielectric liner 251 .

[0122] A dielectric layer 251' may be formed on the inner surface of the through hole TH and the upper surface of the back insulating layer 210. In this deposition operation, the dielectric layer 251' may be formed not only on the inner sidewall of the through hole TH but also on the bottom surface THb of the through hole TH. In this case, the exposed contact area CA' of the buried conductive wiring 120 may be covered again by the dielectric layer 251' (see FIG. Figure 11B ). Then, an anisotropic etching operation may be applied to selectively remove the portion of the dielectric layer located on the upper surface of the back insulating layer 210 and the portion of the dielectric layer located on the bottom surface THb of the through hole. Thus, a dielectric liner 251 may be formed by leaving the portion of the dielectric layer located on the inner sidewall of the through hole TH (see FIG. Figure 11C ).

[0123] Reference Figure 11D , a conductive through structure 250 can be formed by depositing a conductive material 255. Figure 11E , a second wiring portion ML2 connected to the conductive through structure 250 may be formed on the rear surface of the substrate 101 .

[0124] A conductive material 255 may be deposited to fill the through hole TH. The conductive material 255 may be connected to the contact area of ​​the buried conductive wiring 120 exposed on the bottom surface THb of the through hole TH. In this operation, when the size (e.g., diameter) of the through hole TH is greater than the width of the buried conductive wiring 120 or the through hole TH is not properly aligned, the conductive material 255 filling the through hole TH may contact the portion of the filling insulating portion 164 located around the buried conductive wiring 120 to prevent an undesirable short circuit with the active area 102. In this deposition operation, the conductive material is also deposited on the upper surface of the back insulating layer 210. A planarization operation such as CMP may be applied to remove the portion of the conductive material 255 located on the upper surface of the back insulating layer 210. Through the planarization operation, the upper surface of the back insulating layer 210 and the upper surface of the conductive through structure 250 may have a substantially flat coplanar surface.

[0125] A second wiring portion ML2 may be formed on the backside insulating layer 210. The second wiring portion ML2 may include a plurality of low dielectric layers 272 and 275, a plurality of first metal wirings M2 and a plurality of second metal wirings M3, and a plurality of metal vias V2. The first metal wirings M2 may be formed to connect to the conductive through-structures 250. The second metal wirings M3 and the metal vias V2 may be formed using a dual damascene operation. The second wiring portion ML2 may provide signal lines and power lines for a plurality of elements (e.g., transistors) implemented on the upper surface of the substrate 101 by burying the conductive wirings 120 and the conductive through-structures 250.

[0126] manufacture Figure 6 The method of the semiconductor device 100C shown can be divided into processes for forming the device portion and the first wiring portion ( 12A to 12E ) and a process for forming a conductive through-structure and a second wiring portion ( 13A to 13C ), and will be described separately. 12A to 12E It shows the manufacturing Figure 6 1 is a cross-sectional view of a process of a method for forming a semiconductor device (a method for forming a device portion and a first wiring portion).

[0127] Reference Figure 12A , a first insulating layer 162 ′ may be formed to cover the plurality of active fins 105 .

[0128] A fin mask FM may be provided on the upper surface of each of the plurality of active fins 105. The fin mask FM may be a mask that has been used in an operation for forming the plurality of active fins 105 prior to this operation. A first insulating layer 162' may be formed on the substrate 101 to cover the plurality of active fins 105. In this operation, after the first insulating layer 162' is formed to cover the fin mask FM, the first insulating layer 162' may be planarized using an operation such as CMP to expose the fin mask FM. In this operation, the active fins ( Figure 10A 105a).

[0129] Reference Figure 12B , trenches ST″ may be formed between the active fins in the plurality of active fins 105 .

[0130] The trench ST” may be formed to extend along a first direction in which the plurality of active fins 105 extend. A formation region of the trench ST” may be located between the plurality of active fins 105. In a manner different from the previous embodiment, the trench ST” according to this embodiment may be formed to penetrate the first insulating layer 162′ (specifically, the device isolation layer 162 in the final structure) and extend to a portion of the active area 102. The bottom surface of the trench ST” may be provided by the active area 102.

[0131] Reference Figure 12C , a buried conductive wiring 120 having a dielectric barrier 121 and a conductive material 125 may be formed in the trench ST″, and the buried conductive wiring 120 may be embedded in the trench ST″ by the second insulating layer 130 ′.

[0132] A dielectric film for the dielectric barrier 121 may be formed on the inner surface of the trench ST″. In this operation, a dielectric film may also be formed on the upper surface of the first insulating layer 162′. The portion of the dielectric film located on the upper surface of the first insulating layer 162′ and the portion of the dielectric film located on the bottom surface of the trench ST″ may be selectively removed. Thus, the dielectric barrier 121 may be formed by leaving the portion of the dielectric film located on the inner sidewall of the trench ST″. The conductive material 125 may be etched back to adjust the height of the buried conductive wiring. Although the dielectric barrier is shown as not being further etched during the etch-back operation, it may be additionally etched in other embodiments (see FIG. 2 ). Figure 7 and Figure 8 ). The second insulating layer 130 ′ may be used to embed the buried conductive wiring 120 in the trench ST″.

[0133] Reference Figure 12DA portion of the second insulating layer 130 ′ and a portion of the first insulating layer 162 ′ may be removed to expose a portion of the active fin 105 , and the source / drain region 110 may be formed on the exposed portion of the active fin 105 .

[0134] In this operation, a portion of the second insulating layer 130' and a portion of the first insulating layer 162' may be removed using a planarization operation such as CMP. This operation may be performed until the fin mask FM is exposed. After the fin mask FM is removed, an etch-back operation may be performed to remove a portion of the first insulating layer 162' and a portion of the second insulating layer 130' to expose a portion of the plurality of active fins 105. The first insulating layer 162' obtained through this operation may be provided as a device isolation layer 162, and the second insulating layer 130' may be provided as an insulating cap layer 130. Recesses may be formed in the exposed portions of the plurality of active fins 105, and a selective epitaxial growth operation may be performed in the recesses to form source / drain regions 110.

[0135] Reference Figure 12E , an interlayer insulating layer 165 may be formed, a contact structure 180 penetrating the interlayer insulating layer 165 may be formed, and a first wiring portion ML1 may be formed on the interlayer insulating layer 165 .

[0136] You can refer to Figure 10F To understand the operation of forming the interlayer insulating layer 165 and the contact structure 180. Figure 10G To understand the operation of forming the first wiring portion ML1 connected to the contact structure 180 on the interlayer insulating layer 165 .

[0137] 13A to 13C It shows the manufacturing Figure 6 1 is a cross-sectional view of a process of a method for forming a semiconductor device (a method for forming a conductive through-structure and a second wiring portion).

[0138] Reference Figure 13A , you can Figure 12E The device manufactured in the embodiment is attached to the support substrate 300 , and through holes TH may be formed in the substrate 101 .

[0139] The support substrate 300 may be attached to Figure 12E The first wiring portion ML1 of the device manufactured in the embodiment of the present invention is formed so that the rear surface of the substrate 101 is turned over to face upward. A back insulating layer 210 for passivation may be formed on the rear surface of the substrate 101. The through hole TH may be formed to face the trench ST from the rear surface of the substrate 101 or toward the rear surface of the substrate 101. The bottom surface of the through hole TH may be formed to be higher than the contact area of ​​the buried conductive wiring 120. For example, the through hole TH may be formed so that the bottom surface and side surfaces of the buried conductive wiring 120 are exposed.

[0140] Reference Figure 13B , a dielectric liner 251 may be formed on the inner surface of the through hole TH using a selective deposition operation.

[0141] In this embodiment, a dielectric liner 251 may be formed on the inner sidewall of the through hole TH using a selective deposition operation. The selective deposition operation employed in this embodiment refers to an operation in which an insulating material may be deposited only on the surface of a semiconductor such as Si and not on the bottom surface of the buried conductive wiring 120. For example, the selective deposition operation may be performed by an atomic layer deposition (ALD) operation. The dielectric liner 251 may not be formed on the conductive material 125 of the buried conductive wiring 120 located at the bottom surface THb of the through hole TH, but may be formed only on the exposed surface of the active region 102. Figure 11B and Figure 11C In a different manner from the operation shown, the dielectric liner 251 used in this embodiment can be formed by selective deposition on the surface of the semiconductor (e.g., the surface of the substrate 101 and the surface of the active area 102) other than the buried conductive wiring 120 exposed on the inner surface of the through hole TH (e.g., the inner sidewall and bottom surface THb of the through hole TH). As described above, in this embodiment, the contact area CA of the buried conductive wiring 120 can be exposed without any additional operation after the dielectric liner is formed. The dielectric liner 251 can have a uniform thickness.

[0142] Reference Figure 13C , a conductive through structure 250 may be formed in the through hole TH, and a second wiring portion ML2 connected to the conductive through structure 250 may be formed on the rear surface of the substrate 101 .

[0143] A conductive material 255 may be deposited to fill the through hole TH. The conductive material 255 may be connected to the contact region of the buried conductive wiring 120 exposed on the bottom surface THb of the through hole TH. During this deposition operation, the conductive material 255 may be deposited on the upper surface of the back insulating layer 210. A planarization operation, such as CMP, may be applied to remove the portion of the conductive material 255 located on the upper surface of the back insulating layer 210. Through the planarization operation, the upper surface of the back insulating layer 210 and the upper surface of the conductive through structure 250 may have a substantially flat coplanar surface. A dielectric liner 251 may also be formed on the upper surface of the back insulating layer 210. After the conductive material 255 filling the conductive through structure 250, the dielectric liner 251 and the portions of the conductive material 255 located on the upper surface of the back insulating layer 210 may be removed using a planarization operation.

[0144] A second wiring portion ML2 may be formed on the backside insulating layer 210. The second wiring portion ML2 may include a plurality of low dielectric layers 272 and 275, a plurality of first metal wirings M2 and a plurality of second metal wirings M3, and a plurality of metal vias V2. The first metal wirings M2 may be formed to be electrically connected to the conductive through-structures 250. The second metal wirings M3 and the metal vias V2 may be formed using a dual damascene operation. The second wiring portion ML2 may provide signal lines and power lines for a plurality of elements (e.g., transistors) implemented on the upper surface of the substrate 101 by burying the conductive wiring 120 and the conductive through-structures 250.

[0145] Therefore, according to some embodiments of the present disclosure, when a conductive through-structure such as a through-silicon via can be formed on a substrate and connected to a buried conductive wiring, short circuits with other adjacent components (e.g., active areas such as Si) can be prevented without reducing the size of the conductive through-structure.

[0146] Various and advantageous advantages and effects of the present disclosure are not limited to the above description, but can be more easily understood in the course of describing specific embodiments of the inventive concept.

[0147] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device comprising: a substrate including a first surface and a second surface opposite to each other, and including an active region located on the first surface and defined by a first isolation region; a plurality of active fins arranged on the active region, extending along a first direction, and defined by a second isolation region, the second isolation region having a second depth less than the first depth of the first isolation region; a buried conductive wiring, the buried conductive wiring being located in a trench adjacent to the plurality of active fins and extending along an extension direction of the trench, wherein a depth of the trench is less than the first depth of the first isolation region and greater than the second depth of the second isolation region; a filling insulating portion, the filling insulating portion being located in the trench and disposed around the buried conductive wiring; an interlayer insulating layer, the interlayer insulating layer being located on the first isolation region and the second isolation region and on the buried conductive wiring; a contact structure penetrating the interlayer insulating layer and contacting the buried conductive wiring; and A conductive through-structure extends from the second surface through the substrate to the trench and contacts the buried conductive wiring.

2. The semiconductor device according to claim 1, wherein A portion of the conductive through-structure contacts the filled insulating portion.

3. The semiconductor device according to claim 2, wherein An upper end of the conductive through structure extends toward the first surface beyond a bottom surface of the buried conductive wiring.

4. The semiconductor device according to claim 1, wherein An upper end of the conductive through structure is confined below an upper surface of the active region. The semiconductor device according to claim 1 , wherein The conductive through-structure includes a conductive material and a dielectric liner located between the conductive material and the substrate. The semiconductor device according to claim 1 , wherein: The trench is located in the active region between active fins of the plurality of active fins.

7. The semiconductor device according to claim 1, wherein A first width of the trench adjacent to lower ends of the plurality of active fins is greater than a second width of the trench adjacent to the buried conductive wiring.

8. The semiconductor device according to claim 1, wherein The level of the upper surface of the buried conductive wiring is between the level of the upper surface of the active region and the level of the upper end of the active fin.

9. The semiconductor device according to claim 1, wherein The buried conductive wiring includes a conductive material and conductive barriers on side surfaces and a lower surface of the conductive material.

10. The semiconductor device according to claim 9, wherein The buried conductive wiring further includes a dielectric barrier located between the conductive barrier and the filled insulating portion.

11. The semiconductor device according to claim 1, further comprising: a first wiring portion located on the interlayer insulating layer and electrically connected to the contact structure; as well as A second wiring portion is located on the second surface of the substrate and is electrically connected to the conductive through structure.

12. The semiconductor device according to claim 1, further comprising: a gate structure, the gate structure being located on the plurality of active fins and extending along a second direction intersecting the first direction; as well as a source / drain region comprising a regrown layer located on opposite sides of the gate structure and on the active region, Wherein, the contact structure is electrically connected to the source / drain region.

13. A semiconductor device comprising: a substrate comprising an upper surface and a rear surface; a trench located in the substrate, the trench having a first width and extending in one direction; a buried conductive wiring located in the trench, extending in the one direction, and having a second width narrower than the first width; a filling insulating portion, the filling insulating portion being located in the trench and disposed around the buried conductive wiring; a device isolation layer located in the substrate and comprising a first isolation region defining an active region and a second isolation region disposed on an upper surface of the active region, the second isolation region having a second depth less than the first depth of the first isolation region, wherein the depth of the trench is less than the first depth of the first isolation region and greater than the second depth of the second isolation region; an interlayer insulating layer, the interlayer insulating layer being located on the device isolation layer, the active area and the buried conductive wiring; a contact structure penetrating the interlayer insulating layer and contacting the buried conductive wiring; a conductive through-structure extending from the rear surface through the substrate to the trench and including an end portion adjacent to the trench and contacting the buried conductive wiring; and A backside wiring portion is located on the back surface of the substrate and is electrically connected to the conductive through-structure.

14. The semiconductor device according to claim 13, further comprising a source / drain region located in the active region, in, The contact structure penetrates the interlayer insulating layer and contacts the source / drain region.

15. The semiconductor device according to claim 13, wherein The end portion of the conductive through structure partially contacts the filling insulating portion and extends beyond a bottom surface of the buried conductive wiring toward the upper surface.

16. The semiconductor device according to claim 13, wherein The buried conductive wiring has an aspect ratio of 2 or greater.

17. The semiconductor device according to claim 16, wherein The buried conductive wiring has a width of 5 nm to 50 nm.

18. A semiconductor device comprising: a substrate, the substrate comprising an upper surface, the upper surface comprising an active area; a plurality of active fins, the plurality of active fins being located on the active area and extending in one direction; a buried conductive wiring located in the trench adjacent to the plurality of active fins and extending along the one direction; a dielectric barrier located between an inner sidewall of the trench and a side surface of the buried conductive wiring; an interlayer insulating layer, the interlayer insulating layer being located on the upper surface of the substrate and on the buried conductive wiring; a contact structure penetrating the interlayer insulating layer and contacting the buried conductive wiring; a through hole penetrating the substrate from a rear surface of the substrate and including a bottom surface exposing a lower surface of the buried conductive wiring and a portion of the substrate; a conductive through-via structure comprising a dielectric liner on the portion of the substrate and on an inner sidewall of the through-hole and a conductive material in the through-hole and in contact with the lower surface of the buried conductive wiring; and A backside wiring portion is located on the back surface of the substrate and is electrically connected to the conductive through-structure.

19. The semiconductor device according to claim 18, wherein An upper end of the conductive through structure extends beyond the lower surface of the buried conductive wiring toward the upper surface of the substrate.

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